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initial commit with v3.6.7
[linux-3.6.7-moxart.git] / drivers / video / omap2 / dss / rfbi.c
blob7c087424b63428d33cd2bbb1560cb476dfefab38
1 /*
2 * linux/drivers/video/omap2/dss/rfbi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "RFBI"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/export.h>
28 #include <linux/vmalloc.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/delay.h>
32 #include <linux/kfifo.h>
33 #include <linux/ktime.h>
34 #include <linux/hrtimer.h>
35 #include <linux/seq_file.h>
36 #include <linux/semaphore.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39
40 #include <video/omapdss.h>
41 #include "dss.h"
42
43 struct rfbi_reg { u16 idx; };
44
45 #define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
46
47 #define RFBI_REVISION RFBI_REG(0x0000)
48 #define RFBI_SYSCONFIG RFBI_REG(0x0010)
49 #define RFBI_SYSSTATUS RFBI_REG(0x0014)
50 #define RFBI_CONTROL RFBI_REG(0x0040)
51 #define RFBI_PIXEL_CNT RFBI_REG(0x0044)
52 #define RFBI_LINE_NUMBER RFBI_REG(0x0048)
53 #define RFBI_CMD RFBI_REG(0x004c)
54 #define RFBI_PARAM RFBI_REG(0x0050)
55 #define RFBI_DATA RFBI_REG(0x0054)
56 #define RFBI_READ RFBI_REG(0x0058)
57 #define RFBI_STATUS RFBI_REG(0x005c)
58
59 #define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
60 #define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
61 #define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
62 #define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
63 #define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
64 #define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
65
66 #define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
67 #define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
68
69 #define REG_FLD_MOD(idx, val, start, end) \
70 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
71
72 enum omap_rfbi_cycleformat {
73 OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
74 OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
75 OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
76 OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
77 };
78
79 enum omap_rfbi_datatype {
80 OMAP_DSS_RFBI_DATATYPE_12 = 0,
81 OMAP_DSS_RFBI_DATATYPE_16 = 1,
82 OMAP_DSS_RFBI_DATATYPE_18 = 2,
83 OMAP_DSS_RFBI_DATATYPE_24 = 3,
84 };
85
86 enum omap_rfbi_parallelmode {
87 OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
88 OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
89 OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
90 OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
91 };
92
93 static int rfbi_convert_timings(struct rfbi_timings *t);
94 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
95
96 static struct {
97 struct platform_device *pdev;
98 void __iomem *base;
99
100 unsigned long l4_khz;
101
102 enum omap_rfbi_datatype datatype;
103 enum omap_rfbi_parallelmode parallelmode;
104
105 enum omap_rfbi_te_mode te_mode;
106 int te_enabled;
107
108 void (*framedone_callback)(void *data);
109 void *framedone_callback_data;
110
111 struct omap_dss_device *dssdev[2];
112
113 struct semaphore bus_lock;
114 } rfbi;
115
116 static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
117 {
118 __raw_writel(val, rfbi.base + idx.idx);
119 }
120
121 static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
122 {
123 return __raw_readl(rfbi.base + idx.idx);
124 }
125
126 static int rfbi_runtime_get(void)
127 {
128 int r;
129
130 DSSDBG("rfbi_runtime_get\n");
131
132 r = pm_runtime_get_sync(&rfbi.pdev->dev);
133 WARN_ON(r < 0);
134 return r < 0 ? r : 0;
135 }
136
137 static void rfbi_runtime_put(void)
138 {
139 int r;
140
141 DSSDBG("rfbi_runtime_put\n");
142
143 r = pm_runtime_put_sync(&rfbi.pdev->dev);
144 WARN_ON(r < 0 && r != -ENOSYS);
145 }
146
147 void rfbi_bus_lock(void)
148 {
149 down(&rfbi.bus_lock);
150 }
151 EXPORT_SYMBOL(rfbi_bus_lock);
152
153 void rfbi_bus_unlock(void)
154 {
155 up(&rfbi.bus_lock);
156 }
157 EXPORT_SYMBOL(rfbi_bus_unlock);
158
159 void omap_rfbi_write_command(const void *buf, u32 len)
160 {
161 switch (rfbi.parallelmode) {
162 case OMAP_DSS_RFBI_PARALLELMODE_8:
163 {
164 const u8 *b = buf;
165 for (; len; len--)
166 rfbi_write_reg(RFBI_CMD, *b++);
167 break;
168 }
169
170 case OMAP_DSS_RFBI_PARALLELMODE_16:
171 {
172 const u16 *w = buf;
173 BUG_ON(len & 1);
174 for (; len; len -= 2)
175 rfbi_write_reg(RFBI_CMD, *w++);
176 break;
177 }
178
179 case OMAP_DSS_RFBI_PARALLELMODE_9:
180 case OMAP_DSS_RFBI_PARALLELMODE_12:
181 default:
182 BUG();
183 }
184 }
185 EXPORT_SYMBOL(omap_rfbi_write_command);
186
187 void omap_rfbi_read_data(void *buf, u32 len)
188 {
189 switch (rfbi.parallelmode) {
190 case OMAP_DSS_RFBI_PARALLELMODE_8:
191 {
192 u8 *b = buf;
193 for (; len; len--) {
194 rfbi_write_reg(RFBI_READ, 0);
195 *b++ = rfbi_read_reg(RFBI_READ);
196 }
197 break;
198 }
199
200 case OMAP_DSS_RFBI_PARALLELMODE_16:
201 {
202 u16 *w = buf;
203 BUG_ON(len & ~1);
204 for (; len; len -= 2) {
205 rfbi_write_reg(RFBI_READ, 0);
206 *w++ = rfbi_read_reg(RFBI_READ);
207 }
208 break;
209 }
210
211 case OMAP_DSS_RFBI_PARALLELMODE_9:
212 case OMAP_DSS_RFBI_PARALLELMODE_12:
213 default:
214 BUG();
215 }
216 }
217 EXPORT_SYMBOL(omap_rfbi_read_data);
218
219 void omap_rfbi_write_data(const void *buf, u32 len)
220 {
221 switch (rfbi.parallelmode) {
222 case OMAP_DSS_RFBI_PARALLELMODE_8:
223 {
224 const u8 *b = buf;
225 for (; len; len--)
226 rfbi_write_reg(RFBI_PARAM, *b++);
227 break;
228 }
229
230 case OMAP_DSS_RFBI_PARALLELMODE_16:
231 {
232 const u16 *w = buf;
233 BUG_ON(len & 1);
234 for (; len; len -= 2)
235 rfbi_write_reg(RFBI_PARAM, *w++);
236 break;
237 }
238
239 case OMAP_DSS_RFBI_PARALLELMODE_9:
240 case OMAP_DSS_RFBI_PARALLELMODE_12:
241 default:
242 BUG();
243
244 }
245 }
246 EXPORT_SYMBOL(omap_rfbi_write_data);
247
248 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
249 u16 x, u16 y,
250 u16 w, u16 h)
251 {
252 int start_offset = scr_width * y + x;
253 int horiz_offset = scr_width - w;
254 int i;
255
256 if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
257 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
258 const u16 __iomem *pd = buf;
259 pd += start_offset;
260
261 for (; h; --h) {
262 for (i = 0; i < w; ++i) {
263 const u8 __iomem *b = (const u8 __iomem *)pd;
264 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
265 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
266 ++pd;
267 }
268 pd += horiz_offset;
269 }
270 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
271 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
272 const u32 __iomem *pd = buf;
273 pd += start_offset;
274
275 for (; h; --h) {
276 for (i = 0; i < w; ++i) {
277 const u8 __iomem *b = (const u8 __iomem *)pd;
278 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
279 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
280 rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
281 ++pd;
282 }
283 pd += horiz_offset;
284 }
285 } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
286 rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
287 const u16 __iomem *pd = buf;
288 pd += start_offset;
289
290 for (; h; --h) {
291 for (i = 0; i < w; ++i) {
292 rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
293 ++pd;
294 }
295 pd += horiz_offset;
296 }
297 } else {
298 BUG();
299 }
300 }
301 EXPORT_SYMBOL(omap_rfbi_write_pixels);
302
303 static int rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
304 u16 height, void (*callback)(void *data), void *data)
305 {
306 u32 l;
307 int r;
308 struct omap_video_timings timings = {
309 .hsw = 1,
310 .hfp = 1,
311 .hbp = 1,
312 .vsw = 1,
313 .vfp = 0,
314 .vbp = 0,
315 .x_res = width,
316 .y_res = height,
317 };
318
319 /*BUG_ON(callback == 0);*/
320 BUG_ON(rfbi.framedone_callback != NULL);
321
322 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
323
324 dss_mgr_set_timings(dssdev->manager, &timings);
325
326 r = dss_mgr_enable(dssdev->manager);
327 if (r)
328 return r;
329
330 rfbi.framedone_callback = callback;
331 rfbi.framedone_callback_data = data;
332
333 rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
334
335 l = rfbi_read_reg(RFBI_CONTROL);
336 l = FLD_MOD(l, 1, 0, 0); /* enable */
337 if (!rfbi.te_enabled)
338 l = FLD_MOD(l, 1, 4, 4); /* ITE */
339
340 rfbi_write_reg(RFBI_CONTROL, l);
341
342 return 0;
343 }
344
345 static void framedone_callback(void *data, u32 mask)
346 {
347 void (*callback)(void *data);
348
349 DSSDBG("FRAMEDONE\n");
350
351 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
352
353 callback = rfbi.framedone_callback;
354 rfbi.framedone_callback = NULL;
355
356 if (callback != NULL)
357 callback(rfbi.framedone_callback_data);
358 }
359
360 #if 1 /* VERBOSE */
361 static void rfbi_print_timings(void)
362 {
363 u32 l;
364 u32 time;
365
366 l = rfbi_read_reg(RFBI_CONFIG(0));
367 time = 1000000000 / rfbi.l4_khz;
368 if (l & (1 << 4))
369 time *= 2;
370
371 DSSDBG("Tick time %u ps\n", time);
372 l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
373 DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
374 "REONTIME %d, REOFFTIME %d\n",
375 l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
376 (l >> 20) & 0x0f, (l >> 24) & 0x3f);
377
378 l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
379 DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
380 "ACCESSTIME %d\n",
381 (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
382 (l >> 22) & 0x3f);
383 }
384 #else
385 static void rfbi_print_timings(void) {}
386 #endif
387
388
389
390
391 static u32 extif_clk_period;
392
393 static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
394 {
395 int bus_tick = extif_clk_period * div;
396 return (ps + bus_tick - 1) / bus_tick * bus_tick;
397 }
398
399 static int calc_reg_timing(struct rfbi_timings *t, int div)
400 {
401 t->clk_div = div;
402
403 t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
404
405 t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
406 t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
407 t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
408
409 t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
410 t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
411 t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
412
413 t->access_time = round_to_extif_ticks(t->access_time, div);
414 t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
415 t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
416
417 DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
418 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
419 DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
420 t->we_on_time, t->we_off_time, t->re_cycle_time,
421 t->we_cycle_time);
422 DSSDBG("[reg]rdaccess %d cspulse %d\n",
423 t->access_time, t->cs_pulse_width);
424
425 return rfbi_convert_timings(t);
426 }
427
428 static int calc_extif_timings(struct rfbi_timings *t)
429 {
430 u32 max_clk_div;
431 int div;
432
433 rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
434 for (div = 1; div <= max_clk_div; div++) {
435 if (calc_reg_timing(t, div) == 0)
436 break;
437 }
438
439 if (div <= max_clk_div)
440 return 0;
441
442 DSSERR("can't setup timings\n");
443 return -1;
444 }
445
446
447 static void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
448 {
449 int r;
450
451 if (!t->converted) {
452 r = calc_extif_timings(t);
453 if (r < 0)
454 DSSERR("Failed to calc timings\n");
455 }
456
457 BUG_ON(!t->converted);
458
459 rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
460 rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
461
462 /* TIMEGRANULARITY */
463 REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
464 (t->tim[2] ? 1 : 0), 4, 4);
465
466 rfbi_print_timings();
467 }
468
469 static int ps_to_rfbi_ticks(int time, int div)
470 {
471 unsigned long tick_ps;
472 int ret;
473
474 /* Calculate in picosecs to yield more exact results */
475 tick_ps = 1000000000 / (rfbi.l4_khz) * div;
476
477 ret = (time + tick_ps - 1) / tick_ps;
478
479 return ret;
480 }
481
482 static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
483 {
484 *clk_period = 1000000000 / rfbi.l4_khz;
485 *max_clk_div = 2;
486 }
487
488 static int rfbi_convert_timings(struct rfbi_timings *t)
489 {
490 u32 l;
491 int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
492 int actim, recyc, wecyc;
493 int div = t->clk_div;
494
495 if (div <= 0 || div > 2)
496 return -1;
497
498 /* Make sure that after conversion it still holds that:
499 * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
500 * csoff > cson, csoff >= max(weoff, reoff), actim > reon
501 */
502 weon = ps_to_rfbi_ticks(t->we_on_time, div);
503 weoff = ps_to_rfbi_ticks(t->we_off_time, div);
504 if (weoff <= weon)
505 weoff = weon + 1;
506 if (weon > 0x0f)
507 return -1;
508 if (weoff > 0x3f)
509 return -1;
510
511 reon = ps_to_rfbi_ticks(t->re_on_time, div);
512 reoff = ps_to_rfbi_ticks(t->re_off_time, div);
513 if (reoff <= reon)
514 reoff = reon + 1;
515 if (reon > 0x0f)
516 return -1;
517 if (reoff > 0x3f)
518 return -1;
519
520 cson = ps_to_rfbi_ticks(t->cs_on_time, div);
521 csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
522 if (csoff <= cson)
523 csoff = cson + 1;
524 if (csoff < max(weoff, reoff))
525 csoff = max(weoff, reoff);
526 if (cson > 0x0f)
527 return -1;
528 if (csoff > 0x3f)
529 return -1;
530
531 l = cson;
532 l |= csoff << 4;
533 l |= weon << 10;
534 l |= weoff << 14;
535 l |= reon << 20;
536 l |= reoff << 24;
537
538 t->tim[0] = l;
539
540 actim = ps_to_rfbi_ticks(t->access_time, div);
541 if (actim <= reon)
542 actim = reon + 1;
543 if (actim > 0x3f)
544 return -1;
545
546 wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
547 if (wecyc < weoff)
548 wecyc = weoff;
549 if (wecyc > 0x3f)
550 return -1;
551
552 recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
553 if (recyc < reoff)
554 recyc = reoff;
555 if (recyc > 0x3f)
556 return -1;
557
558 cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
559 if (cs_pulse > 0x3f)
560 return -1;
561
562 l = wecyc;
563 l |= recyc << 6;
564 l |= cs_pulse << 12;
565 l |= actim << 22;
566
567 t->tim[1] = l;
568
569 t->tim[2] = div - 1;
570
571 t->converted = 1;
572
573 return 0;
574 }
575
576 /* xxx FIX module selection missing */
577 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
578 unsigned hs_pulse_time, unsigned vs_pulse_time,
579 int hs_pol_inv, int vs_pol_inv, int extif_div)
580 {
581 int hs, vs;
582 int min;
583 u32 l;
584
585 hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
586 vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
587 if (hs < 2)
588 return -EDOM;
589 if (mode == OMAP_DSS_RFBI_TE_MODE_2)
590 min = 2;
591 else /* OMAP_DSS_RFBI_TE_MODE_1 */
592 min = 4;
593 if (vs < min)
594 return -EDOM;
595 if (vs == hs)
596 return -EINVAL;
597 rfbi.te_mode = mode;
598 DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
599 mode, hs, vs, hs_pol_inv, vs_pol_inv);
600
601 rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
602 rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
603
604 l = rfbi_read_reg(RFBI_CONFIG(0));
605 if (hs_pol_inv)
606 l &= ~(1 << 21);
607 else
608 l |= 1 << 21;
609 if (vs_pol_inv)
610 l &= ~(1 << 20);
611 else
612 l |= 1 << 20;
613
614 return 0;
615 }
616 EXPORT_SYMBOL(omap_rfbi_setup_te);
617
618 /* xxx FIX module selection missing */
619 int omap_rfbi_enable_te(bool enable, unsigned line)
620 {
621 u32 l;
622
623 DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
624 if (line > (1 << 11) - 1)
625 return -EINVAL;
626
627 l = rfbi_read_reg(RFBI_CONFIG(0));
628 l &= ~(0x3 << 2);
629 if (enable) {
630 rfbi.te_enabled = 1;
631 l |= rfbi.te_mode << 2;
632 } else
633 rfbi.te_enabled = 0;
634 rfbi_write_reg(RFBI_CONFIG(0), l);
635 rfbi_write_reg(RFBI_LINE_NUMBER, line);
636
637 return 0;
638 }
639 EXPORT_SYMBOL(omap_rfbi_enable_te);
640
641 static int rfbi_configure(int rfbi_module, int bpp, int lines)
642 {
643 u32 l;
644 int cycle1 = 0, cycle2 = 0, cycle3 = 0;
645 enum omap_rfbi_cycleformat cycleformat;
646 enum omap_rfbi_datatype datatype;
647 enum omap_rfbi_parallelmode parallelmode;
648
649 switch (bpp) {
650 case 12:
651 datatype = OMAP_DSS_RFBI_DATATYPE_12;
652 break;
653 case 16:
654 datatype = OMAP_DSS_RFBI_DATATYPE_16;
655 break;
656 case 18:
657 datatype = OMAP_DSS_RFBI_DATATYPE_18;
658 break;
659 case 24:
660 datatype = OMAP_DSS_RFBI_DATATYPE_24;
661 break;
662 default:
663 BUG();
664 return 1;
665 }
666 rfbi.datatype = datatype;
667
668 switch (lines) {
669 case 8:
670 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
671 break;
672 case 9:
673 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
674 break;
675 case 12:
676 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
677 break;
678 case 16:
679 parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
680 break;
681 default:
682 BUG();
683 return 1;
684 }
685 rfbi.parallelmode = parallelmode;
686
687 if ((bpp % lines) == 0) {
688 switch (bpp / lines) {
689 case 1:
690 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
691 break;
692 case 2:
693 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
694 break;
695 case 3:
696 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
697 break;
698 default:
699 BUG();
700 return 1;
701 }
702 } else if ((2 * bpp % lines) == 0) {
703 if ((2 * bpp / lines) == 3)
704 cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
705 else {
706 BUG();
707 return 1;
708 }
709 } else {
710 BUG();
711 return 1;
712 }
713
714 switch (cycleformat) {
715 case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
716 cycle1 = lines;
717 break;
718
719 case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
720 cycle1 = lines;
721 cycle2 = lines;
722 break;
723
724 case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
725 cycle1 = lines;
726 cycle2 = lines;
727 cycle3 = lines;
728 break;
729
730 case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
731 cycle1 = lines;
732 cycle2 = (lines / 2) | ((lines / 2) << 16);
733 cycle3 = (lines << 16);
734 break;
735 }
736
737 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
738
739 l = 0;
740 l |= FLD_VAL(parallelmode, 1, 0);
741 l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
742 l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
743 l |= FLD_VAL(datatype, 6, 5);
744 /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
745 l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
746 l |= FLD_VAL(cycleformat, 10, 9);
747 l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
748 l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
749 l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
750 l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
751 l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
752 l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
753 l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
754 rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
755
756 rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
757 rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
758 rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
759
760
761 l = rfbi_read_reg(RFBI_CONTROL);
762 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
763 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
764 rfbi_write_reg(RFBI_CONTROL, l);
765
766
767 DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
768 bpp, lines, cycle1, cycle2, cycle3);
769
770 return 0;
771 }
772
773 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
774 int data_lines)
775 {
776 return rfbi_configure(dssdev->phy.rfbi.channel, pixel_size, data_lines);
777 }
778 EXPORT_SYMBOL(omap_rfbi_configure);
779
780 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
781 u16 *x, u16 *y, u16 *w, u16 *h)
782 {
783 u16 dw, dh;
784 struct omap_video_timings timings = {
785 .hsw = 1,
786 .hfp = 1,
787 .hbp = 1,
788 .vsw = 1,
789 .vfp = 0,
790 .vbp = 0,
791 .x_res = *w,
792 .y_res = *h,
793 };
794
795 dssdev->driver->get_resolution(dssdev, &dw, &dh);
796
797 if (*x > dw || *y > dh)
798 return -EINVAL;
799
800 if (*x + *w > dw)
801 return -EINVAL;
802
803 if (*y + *h > dh)
804 return -EINVAL;
805
806 if (*w == 1)
807 return -EINVAL;
808
809 if (*w == 0 || *h == 0)
810 return -EINVAL;
811
812 dss_mgr_set_timings(dssdev->manager, &timings);
813
814 return 0;
815 }
816 EXPORT_SYMBOL(omap_rfbi_prepare_update);
817
818 int omap_rfbi_update(struct omap_dss_device *dssdev,
819 u16 x, u16 y, u16 w, u16 h,
820 void (*callback)(void *), void *data)
821 {
822 int r;
823
824 r = rfbi_transfer_area(dssdev, w, h, callback, data);
825
826 return r;
827 }
828 EXPORT_SYMBOL(omap_rfbi_update);
829
830 static void rfbi_dump_regs(struct seq_file *s)
831 {
832 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
833
834 if (rfbi_runtime_get())
835 return;
836
837 DUMPREG(RFBI_REVISION);
838 DUMPREG(RFBI_SYSCONFIG);
839 DUMPREG(RFBI_SYSSTATUS);
840 DUMPREG(RFBI_CONTROL);
841 DUMPREG(RFBI_PIXEL_CNT);
842 DUMPREG(RFBI_LINE_NUMBER);
843 DUMPREG(RFBI_CMD);
844 DUMPREG(RFBI_PARAM);
845 DUMPREG(RFBI_DATA);
846 DUMPREG(RFBI_READ);
847 DUMPREG(RFBI_STATUS);
848
849 DUMPREG(RFBI_CONFIG(0));
850 DUMPREG(RFBI_ONOFF_TIME(0));
851 DUMPREG(RFBI_CYCLE_TIME(0));
852 DUMPREG(RFBI_DATA_CYCLE1(0));
853 DUMPREG(RFBI_DATA_CYCLE2(0));
854 DUMPREG(RFBI_DATA_CYCLE3(0));
855
856 DUMPREG(RFBI_CONFIG(1));
857 DUMPREG(RFBI_ONOFF_TIME(1));
858 DUMPREG(RFBI_CYCLE_TIME(1));
859 DUMPREG(RFBI_DATA_CYCLE1(1));
860 DUMPREG(RFBI_DATA_CYCLE2(1));
861 DUMPREG(RFBI_DATA_CYCLE3(1));
862
863 DUMPREG(RFBI_VSYNC_WIDTH);
864 DUMPREG(RFBI_HSYNC_WIDTH);
865
866 rfbi_runtime_put();
867 #undef DUMPREG
868 }
869
870 static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
871 {
872 struct dss_lcd_mgr_config mgr_config;
873
874 mgr_config.io_pad_mode = DSS_IO_PAD_MODE_RFBI;
875
876 mgr_config.stallmode = true;
877 /* Do we need fifohandcheck for RFBI? */
878 mgr_config.fifohandcheck = false;
879
880 mgr_config.video_port_width = dssdev->ctrl.pixel_size;
881 mgr_config.lcden_sig_polarity = 0;
882
883 dss_mgr_set_lcd_config(dssdev->manager, &mgr_config);
884 }
885
886 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
887 {
888 int r;
889
890 if (dssdev->manager == NULL) {
891 DSSERR("failed to enable display: no manager\n");
892 return -ENODEV;
893 }
894
895 r = rfbi_runtime_get();
896 if (r)
897 return r;
898
899 r = omap_dss_start_device(dssdev);
900 if (r) {
901 DSSERR("failed to start device\n");
902 goto err0;
903 }
904
905 r = omap_dispc_register_isr(framedone_callback, NULL,
906 DISPC_IRQ_FRAMEDONE);
907 if (r) {
908 DSSERR("can't get FRAMEDONE irq\n");
909 goto err1;
910 }
911
912 rfbi_config_lcd_manager(dssdev);
913
914 rfbi_configure(dssdev->phy.rfbi.channel,
915 dssdev->ctrl.pixel_size,
916 dssdev->phy.rfbi.data_lines);
917
918 rfbi_set_timings(dssdev->phy.rfbi.channel,
919 &dssdev->ctrl.rfbi_timings);
920
921
922 return 0;
923 err1:
924 omap_dss_stop_device(dssdev);
925 err0:
926 rfbi_runtime_put();
927 return r;
928 }
929 EXPORT_SYMBOL(omapdss_rfbi_display_enable);
930
931 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
932 {
933 omap_dispc_unregister_isr(framedone_callback, NULL,
934 DISPC_IRQ_FRAMEDONE);
935 omap_dss_stop_device(dssdev);
936
937 rfbi_runtime_put();
938 }
939 EXPORT_SYMBOL(omapdss_rfbi_display_disable);
940
941 static int __init rfbi_init_display(struct omap_dss_device *dssdev)
942 {
943 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
944 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
945 return 0;
946 }
947
948 static void __init rfbi_probe_pdata(struct platform_device *pdev)
949 {
950 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
951 int i, r;
952
953 for (i = 0; i < pdata->num_devices; ++i) {
954 struct omap_dss_device *dssdev = pdata->devices[i];
955
956 if (dssdev->type != OMAP_DISPLAY_TYPE_DBI)
957 continue;
958
959 r = rfbi_init_display(dssdev);
960 if (r) {
961 DSSERR("device %s init failed: %d\n", dssdev->name, r);
962 continue;
963 }
964
965 r = omap_dss_register_device(dssdev, &pdev->dev, i);
966 if (r)
967 DSSERR("device %s register failed: %d\n",
968 dssdev->name, r);
969 }
970 }
971
972 /* RFBI HW IP initialisation */
973 static int __init omap_rfbihw_probe(struct platform_device *pdev)
974 {
975 u32 rev;
976 struct resource *rfbi_mem;
977 struct clk *clk;
978 int r;
979
980 rfbi.pdev = pdev;
981
982 sema_init(&rfbi.bus_lock, 1);
983
984 rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
985 if (!rfbi_mem) {
986 DSSERR("can't get IORESOURCE_MEM RFBI\n");
987 return -EINVAL;
988 }
989
990 rfbi.base = devm_ioremap(&pdev->dev, rfbi_mem->start,
991 resource_size(rfbi_mem));
992 if (!rfbi.base) {
993 DSSERR("can't ioremap RFBI\n");
994 return -ENOMEM;
995 }
996
997 clk = clk_get(&pdev->dev, "ick");
998 if (IS_ERR(clk)) {
999 DSSERR("can't get ick\n");
1000 return PTR_ERR(clk);
1001 }
1002
1003 rfbi.l4_khz = clk_get_rate(clk) / 1000;
1004
1005 clk_put(clk);
1006
1007 pm_runtime_enable(&pdev->dev);
1008
1009 r = rfbi_runtime_get();
1010 if (r)
1011 goto err_runtime_get;
1012
1013 msleep(10);
1014
1015 rev = rfbi_read_reg(RFBI_REVISION);
1016 dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n",
1017 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1018
1019 rfbi_runtime_put();
1020
1021 dss_debugfs_create_file("rfbi", rfbi_dump_regs);
1022
1023 rfbi_probe_pdata(pdev);
1024
1025 return 0;
1026
1027 err_runtime_get:
1028 pm_runtime_disable(&pdev->dev);
1029 return r;
1030 }
1031
1032 static int __exit omap_rfbihw_remove(struct platform_device *pdev)
1033 {
1034 omap_dss_unregister_child_devices(&pdev->dev);
1035 pm_runtime_disable(&pdev->dev);
1036 return 0;
1037 }
1038
1039 static int rfbi_runtime_suspend(struct device *dev)
1040 {
1041 dispc_runtime_put();
1042
1043 return 0;
1044 }
1045
1046 static int rfbi_runtime_resume(struct device *dev)
1047 {
1048 int r;
1049
1050 r = dispc_runtime_get();
1051 if (r < 0)
1052 return r;
1053
1054 return 0;
1055 }
1056
1057 static const struct dev_pm_ops rfbi_pm_ops = {
1058 .runtime_suspend = rfbi_runtime_suspend,
1059 .runtime_resume = rfbi_runtime_resume,
1060 };
1061
1062 static struct platform_driver omap_rfbihw_driver = {
1063 .remove = __exit_p(omap_rfbihw_remove),
1064 .driver = {
1065 .name = "omapdss_rfbi",
1066 .owner = THIS_MODULE,
1067 .pm = &rfbi_pm_ops,
1068 },
1069 };
1070
1071 int __init rfbi_init_platform_driver(void)
1072 {
1073 return platform_driver_probe(&omap_rfbihw_driver, omap_rfbihw_probe);
1074 }
1075
1076 void __exit rfbi_uninit_platform_driver(void)
1077 {
1078 platform_driver_unregister(&omap_rfbihw_driver);
1079 }
Linux ARM platform port for MOXA ART SoC