Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523

   1 What:           /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
   2 What:           /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
   3 What:           /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
   4 What:           /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
   5 What:           /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
   6 What:           /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
   7 KernelVersion:  3.4.0
   8 Contact:        linux-iio@vger.kernel.org
   9 Description:
  10                 Reading returns either '1' or '0'.
  11                 '1' means that the clock in question is present.
  12                 '0' means that the clock is missing.
  13
  14 What:           /sys/bus/iio/devices/iio:deviceX/pllY_locked
  15 KernelVersion:  3.4.0
  16 Contact:        linux-iio@vger.kernel.org
  17 Description:
  18                 Reading returns either '1' or '0'. '1' means that the
  19                 pllY is locked.
  20
  21 What:           /sys/bus/iio/devices/iio:deviceX/store_eeprom
  22 KernelVersion:  3.4.0
  23 Contact:        linux-iio@vger.kernel.org
  24 Description:
  25                 Writing '1' stores the current device configuration into
  26                 on-chip EEPROM. After power-up or chip reset the device will
  27                 automatically load the saved configuration.
  28
  29 What:           /sys/bus/iio/devices/iio:deviceX/sync_dividers
  30 KernelVersion:  3.4.0
  31 Contact:        linux-iio@vger.kernel.org
  32 Description:
  33                 Writing '1' triggers the clock distribution synchronization
  34                 functionality. All dividers are reset and the channels start
  35                 with their predefined phase offsets (out_altvoltageY_phase).
  36                 Writing this file has the effect as driving the external
  37                 /SYNC pin low.