arch/arm/boot/dts/highbank.dts

   1 /*
   2  * Copyright 2011-2012 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18
  19 /* First 4KB has pen for secondary cores. */
  20 /memreserve/ 0x00000000 0x0001000;
  21
  22 / {
  23         model = "Calxeda Highbank";
  24         compatible = "calxeda,highbank";
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27         clock-ranges;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         compatible = "arm,cortex-a9";
  35                         reg = <0>;
  36                         next-level-cache = <&L2>;
  37                         clocks = <&a9pll>;
  38                         clock-names = "cpu";
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a9";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                         clocks = <&a9pll>;
  46                         clock-names = "cpu";
  47                 };
  48
  49                 cpu@2 {
  50                         compatible = "arm,cortex-a9";
  51                         reg = <2>;
  52                         next-level-cache = <&L2>;
  53                         clocks = <&a9pll>;
  54                         clock-names = "cpu";
  55                 };
  56
  57                 cpu@3 {
  58                         compatible = "arm,cortex-a9";
  59                         reg = <3>;
  60                         next-level-cache = <&L2>;
  61                         clocks = <&a9pll>;
  62                         clock-names = "cpu";
  63                 };
  64         };
  65
  66         memory {
  67                 name = "memory";
  68                 device_type = "memory";
  69                 reg = <0x00000000 0xff900000>;
  70         };
  71
  72         chosen {
  73                 bootargs = "console=ttyAMA0";
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 interrupt-parent = <&intc>;
  81                 ranges;
  82
  83                 timer@fff10600 {
  84                         compatible = "arm,cortex-a9-twd-timer";
  85                         reg = <0xfff10600 0x20>;
  86                         interrupts = <1 13 0xf01>;
  87                         clocks = <&a9periphclk>;
  88                 };
  89
  90                 watchdog@fff10620 {
  91                         compatible = "arm,cortex-a9-twd-wdt";
  92                         reg = <0xfff10620 0x20>;
  93                         interrupts = <1 14 0xf01>;
  94                         clocks = <&a9periphclk>;
  95                 };
  96
  97                 intc: interrupt-controller@fff11000 {
  98                         compatible = "arm,cortex-a9-gic";
  99                         #interrupt-cells = <3>;
 100                         #size-cells = <0>;
 101                         #address-cells = <1>;
 102                         interrupt-controller;
 103                         reg = <0xfff11000 0x1000>,
 104                               <0xfff10100 0x100>;
 105                 };
 106
 107                 L2: l2-cache {
 108                         compatible = "arm,pl310-cache";
 109                         reg = <0xfff12000 0x1000>;
 110                         interrupts = <0 70 4>;
 111                         cache-unified;
 112                         cache-level = <2>;
 113                 };
 114
 115                 pmu {
 116                         compatible = "arm,cortex-a9-pmu";
 117                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 118                 };
 119
 120                 sata@ffe08000 {
 121                         compatible = "calxeda,hb-ahci";
 122                         reg = <0xffe08000 0x10000>;
 123                         interrupts = <0 83 4>;
 124                 };
 125
 126                 sdhci@ffe0e000 {
 127                         compatible = "calxeda,hb-sdhci";
 128                         reg = <0xffe0e000 0x1000>;
 129                         interrupts = <0 90 4>;
 130                         clocks = <&eclk>;
 131                 };
 132
 133                 memory-controller@fff00000 {
 134                         compatible = "calxeda,hb-ddr-ctrl";
 135                         reg = <0xfff00000 0x1000>;
 136                         interrupts = <0 91 4>;
 137                 };
 138
 139                 ipc@fff20000 {
 140                         compatible = "arm,pl320", "arm,primecell";
 141                         reg = <0xfff20000 0x1000>;
 142                         interrupts = <0 7 4>;
 143                         clocks = <&pclk>;
 144                         clock-names = "apb_pclk";
 145                 };
 146
 147                 gpioe: gpio@fff30000 {
 148                         #gpio-cells = <2>;
 149                         compatible = "arm,pl061", "arm,primecell";
 150                         gpio-controller;
 151                         reg = <0xfff30000 0x1000>;
 152                         interrupts = <0 14 4>;
 153                         clocks = <&pclk>;
 154                         clock-names = "apb_pclk";
 155                 };
 156
 157                 gpiof: gpio@fff31000 {
 158                         #gpio-cells = <2>;
 159                         compatible = "arm,pl061", "arm,primecell";
 160                         gpio-controller;
 161                         reg = <0xfff31000 0x1000>;
 162                         interrupts = <0 15 4>;
 163                         clocks = <&pclk>;
 164                         clock-names = "apb_pclk";
 165                 };
 166
 167                 gpiog: gpio@fff32000 {
 168                         #gpio-cells = <2>;
 169                         compatible = "arm,pl061", "arm,primecell";
 170                         gpio-controller;
 171                         reg = <0xfff32000 0x1000>;
 172                         interrupts = <0 16 4>;
 173                         clocks = <&pclk>;
 174                         clock-names = "apb_pclk";
 175                 };
 176
 177                 gpioh: gpio@fff33000 {
 178                         #gpio-cells = <2>;
 179                         compatible = "arm,pl061", "arm,primecell";
 180                         gpio-controller;
 181                         reg = <0xfff33000 0x1000>;
 182                         interrupts = <0 17 4>;
 183                         clocks = <&pclk>;
 184                         clock-names = "apb_pclk";
 185                 };
 186
 187                 timer {
 188                         compatible = "arm,sp804", "arm,primecell";
 189                         reg = <0xfff34000 0x1000>;
 190                         interrupts = <0 18 4>;
 191                         clocks = <&pclk>;
 192                         clock-names = "apb_pclk";
 193                 };
 194
 195                 rtc@fff35000 {
 196                         compatible = "arm,pl031", "arm,primecell";
 197                         reg = <0xfff35000 0x1000>;
 198                         interrupts = <0 19 4>;
 199                         clocks = <&pclk>;
 200                         clock-names = "apb_pclk";
 201                 };
 202
 203                 serial@fff36000 {
 204                         compatible = "arm,pl011", "arm,primecell";
 205                         reg = <0xfff36000 0x1000>;
 206                         interrupts = <0 20 4>;
 207                         clocks = <&pclk>;
 208                         clock-names = "apb_pclk";
 209                 };
 210
 211                 smic@fff3a000 {
 212                         compatible = "ipmi-smic";
 213                         device_type = "ipmi";
 214                         reg = <0xfff3a000 0x1000>;
 215                         interrupts = <0 24 4>;
 216                         reg-size = <4>;
 217                         reg-spacing = <4>;
 218                 };
 219
 220                 sregs@fff3c000 {
 221                         compatible = "calxeda,hb-sregs";
 222                         reg = <0xfff3c000 0x1000>;
 223
 224                         clocks {
 225                                 #address-cells = <1>;
 226                                 #size-cells = <0>;
 227
 228                                 osc: oscillator {
 229                                         #clock-cells = <0>;
 230                                         compatible = "fixed-clock";
 231                                         clock-frequency = <33333000>;
 232                                 };
 233
 234                                 ddrpll: ddrpll {
 235                                         #clock-cells = <0>;
 236                                         compatible = "calxeda,hb-pll-clock";
 237                                         clocks = <&osc>;
 238                                         reg = <0x108>;
 239                                 };
 240
 241                                 a9pll: a9pll {
 242                                         #clock-cells = <0>;
 243                                         compatible = "calxeda,hb-pll-clock";
 244                                         clocks = <&osc>;
 245                                         reg = <0x100>;
 246                                 };
 247
 248                                 a9periphclk: a9periphclk {
 249                                         #clock-cells = <0>;
 250                                         compatible = "calxeda,hb-a9periph-clock";
 251                                         clocks = <&a9pll>;
 252                                         reg = <0x104>;
 253                                 };
 254
 255                                 a9bclk: a9bclk {
 256                                         #clock-cells = <0>;
 257                                         compatible = "calxeda,hb-a9bus-clock";
 258                                         clocks = <&a9pll>;
 259                                         reg = <0x104>;
 260                                 };
 261
 262                                 emmcpll: emmcpll {
 263                                         #clock-cells = <0>;
 264                                         compatible = "calxeda,hb-pll-clock";
 265                                         clocks = <&osc>;
 266                                         reg = <0x10C>;
 267                                 };
 268
 269                                 eclk: eclk {
 270                                         #clock-cells = <0>;
 271                                         compatible = "calxeda,hb-emmc-clock";
 272                                         clocks = <&emmcpll>;
 273                                         reg = <0x114>;
 274                                 };
 275
 276                                 pclk: pclk {
 277                                         #clock-cells = <0>;
 278                                         compatible = "fixed-clock";
 279                                         clock-frequency = <150000000>;
 280                                 };
 281                         };
 282                 };
 283
 284                 sregs@fff3c200 {
 285                         compatible = "calxeda,hb-sregs-l2-ecc";
 286                         reg = <0xfff3c200 0x100>;
 287                         interrupts = <0 71 4  0 72 4>;
 288                 };
 289
 290                 dma@fff3d000 {
 291                         compatible = "arm,pl330", "arm,primecell";
 292                         reg = <0xfff3d000 0x1000>;
 293                         interrupts = <0 92 4>;
 294                         clocks = <&pclk>;
 295                         clock-names = "apb_pclk";
 296                 };
 297
 298                 ethernet@fff50000 {
 299                         compatible = "calxeda,hb-xgmac";
 300                         reg = <0xfff50000 0x1000>;
 301                         interrupts = <0 77 4  0 78 4  0 79 4>;
 302                 };
 303
 304                 ethernet@fff51000 {
 305                         compatible = "calxeda,hb-xgmac";
 306                         reg = <0xfff51000 0x1000>;
 307                         interrupts = <0 80 4  0 81 4  0 82 4>;
 308                 };
 309         };
 310 };