arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 /*
  11  * Carveout for multimedia usecases
  12  * It should be the last 48MB of the first 512MB memory part
  13  * In theory, it should not even exist. That zone should be reserved
  14  * dynamically during the .reserve callback.
  15  */
  16 /memreserve/ 0x9d000000 0x03000000;
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         compatible = "ti,omap5";
  22         interrupt-parent = <&gic>;
  23
  24         aliases {
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28                 serial3 = &uart4;
  29                 serial4 = &uart5;
  30                 serial5 = &uart6;
  31         };
  32
  33         cpus {
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a15";
  36                 };
  37                 cpu@1 {
  38                         compatible = "arm,cortex-a15";
  39                 };
  40         };
  41
  42         /*
  43          * The soc node represents the soc top level view. It is uses for IPs
  44          * that are not memory mapped in the MPU view or for the MPU itself.
  45          */
  46         soc {
  47                 compatible = "ti,omap-infra";
  48                 mpu {
  49                         compatible = "ti,omap5-mpu";
  50                         ti,hwmods = "mpu";
  51                 };
  52         };
  53
  54         /*
  55          * XXX: Use a flat representation of the OMAP3 interconnect.
  56          * The real OMAP interconnect network is quite complex.
  57          * Since that will not bring real advantage to represent that in DT for
  58          * the moment, just use a fake OCP bus entry to represent the whole bus
  59          * hierarchy.
  60          */
  61         ocp {
  62                 compatible = "ti,omap4-l3-noc", "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  67
  68                 gic: interrupt-controller@48211000 {
  69                         compatible = "arm,cortex-a15-gic";
  70                         interrupt-controller;
  71                         #interrupt-cells = <3>;
  72                         reg = <0x48211000 0x1000>,
  73                               <0x48212000 0x1000>;
  74                 };
  75
  76                 gpio1: gpio@4ae10000 {
  77                         compatible = "ti,omap4-gpio";
  78                         ti,hwmods = "gpio1";
  79                         gpio-controller;
  80                         #gpio-cells = <2>;
  81                         interrupt-controller;
  82                         #interrupt-cells = <1>;
  83                 };
  84
  85                 gpio2: gpio@48055000 {
  86                         compatible = "ti,omap4-gpio";
  87                         ti,hwmods = "gpio2";
  88                         gpio-controller;
  89                         #gpio-cells = <2>;
  90                         interrupt-controller;
  91                         #interrupt-cells = <1>;
  92                 };
  93
  94                 gpio3: gpio@48057000 {
  95                         compatible = "ti,omap4-gpio";
  96                         ti,hwmods = "gpio3";
  97                         gpio-controller;
  98                         #gpio-cells = <2>;
  99                         interrupt-controller;
 100                         #interrupt-cells = <1>;
 101                 };
 102
 103                 gpio4: gpio@48059000 {
 104                         compatible = "ti,omap4-gpio";
 105                         ti,hwmods = "gpio4";
 106                         gpio-controller;
 107                         #gpio-cells = <2>;
 108                         interrupt-controller;
 109                         #interrupt-cells = <1>;
 110                 };
 111
 112                 gpio5: gpio@4805b000 {
 113                         compatible = "ti,omap4-gpio";
 114                         ti,hwmods = "gpio5";
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117                         interrupt-controller;
 118                         #interrupt-cells = <1>;
 119                 };
 120
 121                 gpio6: gpio@4805d000 {
 122                         compatible = "ti,omap4-gpio";
 123                         ti,hwmods = "gpio6";
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                         interrupt-controller;
 127                         #interrupt-cells = <1>;
 128                 };
 129
 130                 gpio7: gpio@48051000 {
 131                         compatible = "ti,omap4-gpio";
 132                         ti,hwmods = "gpio7";
 133                         gpio-controller;
 134                         #gpio-cells = <2>;
 135                         interrupt-controller;
 136                         #interrupt-cells = <1>;
 137                 };
 138
 139                 gpio8: gpio@48053000 {
 140                         compatible = "ti,omap4-gpio";
 141                         ti,hwmods = "gpio8";
 142                         gpio-controller;
 143                         #gpio-cells = <2>;
 144                         interrupt-controller;
 145                         #interrupt-cells = <1>;
 146                 };
 147
 148                 uart1: serial@4806a000 {
 149                         compatible = "ti,omap4-uart";
 150                         ti,hwmods = "uart1";
 151                         clock-frequency = <48000000>;
 152                 };
 153
 154                 uart2: serial@4806c000 {
 155                         compatible = "ti,omap4-uart";
 156                         ti,hwmods = "uart2";
 157                         clock-frequency = <48000000>;
 158                 };
 159
 160                 uart3: serial@48020000 {
 161                         compatible = "ti,omap4-uart";
 162                         ti,hwmods = "uart3";
 163                         clock-frequency = <48000000>;
 164                 };
 165
 166                 uart4: serial@4806e000 {
 167                         compatible = "ti,omap4-uart";
 168                         ti,hwmods = "uart4";
 169                         clock-frequency = <48000000>;
 170                 };
 171
 172                 uart5: serial@48066000 {
 173                         compatible = "ti,omap5-uart";
 174                         ti,hwmods = "uart5";
 175                         clock-frequency = <48000000>;
 176                 };
 177
 178                 uart6: serial@48068000 {
 179                         compatible = "ti,omap6-uart";
 180                         ti,hwmods = "uart6";
 181                         clock-frequency = <48000000>;
 182                 };
 183         };
 184 };