arch/arm/boot/dts/pxa910.dtsi

   1 /*
   2  *  Copyright (C) 2012 Marvell Technology Group Ltd.
   3  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License version 2 as
   7  *  publishhed by the Free Software Foundation.
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         aliases {
  14                 serial0 = &uart1;
  15                 serial1 = &uart2;
  16                 serial2 = &uart3;
  17                 i2c0 = &twsi1;
  18                 i2c1 = &twsi2;
  19         };
  20
  21         soc {
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24                 compatible = "simple-bus";
  25                 interrupt-parent = <&intc>;
  26                 ranges;
  27
  28                 axi@d4200000 {  /* AXI */
  29                         compatible = "mrvl,axi-bus", "simple-bus";
  30                         #address-cells = <1>;
  31                         #size-cells = <1>;
  32                         reg = <0xd4200000 0x00200000>;
  33                         ranges;
  34
  35                         intc: interrupt-controller@d4282000 {
  36                                 compatible = "mrvl,mmp-intc";
  37                                 interrupt-controller;
  38                                 #interrupt-cells = <1>;
  39                                 reg = <0xd4282000 0x1000>;
  40                                 mrvl,intc-nr-irqs = <64>;
  41                         };
  42
  43                 };
  44
  45                 apb@d4000000 {  /* APB */
  46                         compatible = "mrvl,apb-bus", "simple-bus";
  47                         #address-cells = <1>;
  48                         #size-cells = <1>;
  49                         reg = <0xd4000000 0x00200000>;
  50                         ranges;
  51
  52                         timer0: timer@d4014000 {
  53                                 compatible = "mrvl,mmp-timer";
  54                                 reg = <0xd4014000 0x100>;
  55                                 interrupts = <13>;
  56                         };
  57
  58                         timer1: timer@d4016000 {
  59                                 compatible = "mrvl,mmp-timer";
  60                                 reg = <0xd4016000 0x100>;
  61                                 interrupts = <29>;
  62                                 status = "disabled";
  63                         };
  64
  65                         uart1: uart@d4017000 {
  66                                 compatible = "mrvl,mmp-uart";
  67                                 reg = <0xd4017000 0x1000>;
  68                                 interrupts = <27>;
  69                                 status = "disabled";
  70                         };
  71
  72                         uart2: uart@d4018000 {
  73                                 compatible = "mrvl,mmp-uart";
  74                                 reg = <0xd4018000 0x1000>;
  75                                 interrupts = <28>;
  76                                 status = "disabled";
  77                         };
  78
  79                         uart3: uart@d4036000 {
  80                                 compatible = "mrvl,mmp-uart";
  81                                 reg = <0xd4036000 0x1000>;
  82                                 interrupts = <59>;
  83                                 status = "disabled";
  84                         };
  85
  86                         gpio@d4019000 {
  87                                 compatible = "mrvl,mmp-gpio";
  88                                 #address-cells = <1>;
  89                                 #size-cells = <1>;
  90                                 reg = <0xd4019000 0x1000>;
  91                                 gpio-controller;
  92                                 #gpio-cells = <2>;
  93                                 interrupts = <49>;
  94                                 interrupt-names = "gpio_mux";
  95                                 interrupt-controller;
  96                                 #interrupt-cells = <1>;
  97                                 ranges;
  98
  99                                 gcb0: gpio@d4019000 {
 100                                         reg = <0xd4019000 0x4>;
 101                                 };
 102
 103                                 gcb1: gpio@d4019004 {
 104                                         reg = <0xd4019004 0x4>;
 105                                 };
 106
 107                                 gcb2: gpio@d4019008 {
 108                                         reg = <0xd4019008 0x4>;
 109                                 };
 110
 111                                 gcb3: gpio@d4019100 {
 112                                         reg = <0xd4019100 0x4>;
 113                                 };
 114                         };
 115
 116                         twsi1: i2c@d4011000 {
 117                                 compatible = "mrvl,mmp-twsi";
 118                                 reg = <0xd4011000 0x1000>;
 119                                 interrupts = <7>;
 120                                 mrvl,i2c-fast-mode;
 121                                 status = "disabled";
 122                         };
 123
 124                         twsi2: i2c@d4037000 {
 125                                 compatible = "mrvl,mmp-twsi";
 126                                 reg = <0xd4037000 0x1000>;
 127                                 interrupts = <54>;
 128                                 status = "disabled";
 129                         };
 130
 131                         rtc: rtc@d4010000 {
 132                                 compatible = "mrvl,mmp-rtc";
 133                                 reg = <0xd4010000 0x1000>;
 134                                 interrupts = <5 6>;
 135                                 interrupt-names = "rtc 1Hz", "rtc alarm";
 136                                 status = "disabled";
 137                         };
 138                 };
 139         };
 140 };