| blob | d12b34ca05685fd04b0c500088c74740bcacfc84 |
1 /*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 (version with Test Chip 1)
5 * Cortex-A15 MPCore (V2P-CA15)
6 *
7 * HBI-0237A
8 */
10 /dts-v1/;
12 / {
13 model = "V2P-CA15";
14 arm,hbi = <0x237>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 chosen { };
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
41 cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <1>;
45 };
46 };
48 memory@80000000 {
49 device_type = "memory";
50 reg = <0 0x80000000 0 0x40000000>;
51 };
53 hdlcd@2b000000 {
54 compatible = "arm,hdlcd";
55 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>;
57 };
59 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell";
61 reg = <0 0x2b0a0000 0 0x1000>;
62 };
64 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell";
66 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>;
68 };
70 gic: interrupt-controller@2c001000 {
71 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
72 #interrupt-cells = <3>;
73 #address-cells = <0>;
74 interrupt-controller;
75 reg = <0 0x2c001000 0 0x1000>,
76 <0 0x2c002000 0 0x1000>,
77 <0 0x2c004000 0 0x2000>,
78 <0 0x2c006000 0 0x2000>;
79 interrupts = <1 9 0xf04>;
80 };
82 memory-controller@7ffd0000 {
83 compatible = "arm,pl354", "arm,primecell";
84 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>,
86 <0 87 4>;
87 };
89 dma@7ffb0000 {
90 compatible = "arm,pl330", "arm,primecell";
91 reg = <0 0x7ffb0000 0 0x1000>;
92 interrupts = <0 92 4>,
93 <0 88 4>,
94 <0 89 4>,
95 <0 90 4>,
96 <0 91 4>;
97 };
99 timer {
100 compatible = "arm,armv7-timer";
101 interrupts = <1 13 0xf08>,
102 <1 14 0xf08>,
103 <1 11 0xf08>,
104 <1 10 0xf08>;
105 };
107 pmu {
108 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
109 interrupts = <0 68 4>,
110 <0 69 4>;
111 };
113 motherboard {
114 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0 0x14000000 0x04000000>,
116 <2 0 0 0x18000000 0x04000000>,
117 <3 0 0 0x1c000000 0x04000000>,
118 <4 0 0 0x0c000000 0x04000000>,
119 <5 0 0 0x10000000 0x04000000>;
121 interrupt-map-mask = <0 0 63>;
122 interrupt-map = <0 0 0 &gic 0 0 4>,
123 <0 0 1 &gic 0 1 4>,
124 <0 0 2 &gic 0 2 4>,
125 <0 0 3 &gic 0 3 4>,
126 <0 0 4 &gic 0 4 4>,
127 <0 0 5 &gic 0 5 4>,
128 <0 0 6 &gic 0 6 4>,
129 <0 0 7 &gic 0 7 4>,
130 <0 0 8 &gic 0 8 4>,
131 <0 0 9 &gic 0 9 4>,
132 <0 0 10 &gic 0 10 4>,
133 <0 0 11 &gic 0 11 4>,
134 <0 0 12 &gic 0 12 4>,
135 <0 0 13 &gic 0 13 4>,
136 <0 0 14 &gic 0 14 4>,
137 <0 0 15 &gic 0 15 4>,
138 <0 0 16 &gic 0 16 4>,
139 <0 0 17 &gic 0 17 4>,
140 <0 0 18 &gic 0 18 4>,
141 <0 0 19 &gic 0 19 4>,
142 <0 0 20 &gic 0 20 4>,
143 <0 0 21 &gic 0 21 4>,
144 <0 0 22 &gic 0 22 4>,
145 <0 0 23 &gic 0 23 4>,
146 <0 0 24 &gic 0 24 4>,
147 <0 0 25 &gic 0 25 4>,
148 <0 0 26 &gic 0 26 4>,
149 <0 0 27 &gic 0 27 4>,
150 <0 0 28 &gic 0 28 4>,
151 <0 0 29 &gic 0 29 4>,
152 <0 0 30 &gic 0 30 4>,
153 <0 0 31 &gic 0 31 4>,
154 <0 0 32 &gic 0 32 4>,
155 <0 0 33 &gic 0 33 4>,
156 <0 0 34 &gic 0 34 4>,
157 <0 0 35 &gic 0 35 4>,
158 <0 0 36 &gic 0 36 4>,
159 <0 0 37 &gic 0 37 4>,
160 <0 0 38 &gic 0 38 4>,
161 <0 0 39 &gic 0 39 4>,
162 <0 0 40 &gic 0 40 4>,
163 <0 0 41 &gic 0 41 4>,
164 <0 0 42 &gic 0 42 4>;
165 };
166 };
168 /include/ "vexpress-v2m-rs1.dtsi"