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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / arm / mach-ixp4xx / goramo_mlr.c
blobb800a031207c9db0eaaff139fb367b68374420f8
1 /*
2 * Goramo MultiLink router platform code
3 * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
4 */
5
6 #include <linux/delay.h>
7 #include <linux/hdlc.h>
8 #include <linux/i2c-gpio.h>
9 #include <linux/io.h>
10 #include <linux/irq.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/serial_8250.h>
14 #include <asm/mach-types.h>
15 #include <asm/mach/arch.h>
16 #include <asm/mach/flash.h>
17 #include <asm/mach/pci.h>
18
19 #define SLOT_ETHA 0x0B /* IDSEL = AD21 */
20 #define SLOT_ETHB 0x0C /* IDSEL = AD20 */
21 #define SLOT_MPCI 0x0D /* IDSEL = AD19 */
22 #define SLOT_NEC 0x0E /* IDSEL = AD18 */
23
24 /* GPIO lines */
25 #define GPIO_SCL 0
26 #define GPIO_SDA 1
27 #define GPIO_STR 2
28 #define GPIO_IRQ_NEC 3
29 #define GPIO_IRQ_ETHA 4
30 #define GPIO_IRQ_ETHB 5
31 #define GPIO_HSS0_DCD_N 6
32 #define GPIO_HSS1_DCD_N 7
33 #define GPIO_UART0_DCD 8
34 #define GPIO_UART1_DCD 9
35 #define GPIO_HSS0_CTS_N 10
36 #define GPIO_HSS1_CTS_N 11
37 #define GPIO_IRQ_MPCI 12
38 #define GPIO_HSS1_RTS_N 13
39 #define GPIO_HSS0_RTS_N 14
40 /* GPIO15 is not connected */
41
42 /* Control outputs from 74HC4094 */
43 #define CONTROL_HSS0_CLK_INT 0
44 #define CONTROL_HSS1_CLK_INT 1
45 #define CONTROL_HSS0_DTR_N 2
46 #define CONTROL_HSS1_DTR_N 3
47 #define CONTROL_EXT 4
48 #define CONTROL_AUTO_RESET 5
49 #define CONTROL_PCI_RESET_N 6
50 #define CONTROL_EEPROM_WC_N 7
51
52 /* offsets from start of flash ROM = 0x50000000 */
53 #define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */
54 #define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */
55 #define CFG_REV 0x4C /* u32 */
56 #define CFG_SDRAM_SIZE 0x50 /* u32 */
57 #define CFG_SDRAM_CONF 0x54 /* u32 */
58 #define CFG_SDRAM_MODE 0x58 /* u32 */
59 #define CFG_SDRAM_REFRESH 0x5C /* u32 */
60
61 #define CFG_HW_BITS 0x60 /* u32 */
62 #define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
63 #define CFG_HW_HAS_PCI_SLOT 0x00000008
64 #define CFG_HW_HAS_ETH0 0x00000010
65 #define CFG_HW_HAS_ETH1 0x00000020
66 #define CFG_HW_HAS_HSS0 0x00000040
67 #define CFG_HW_HAS_HSS1 0x00000080
68 #define CFG_HW_HAS_UART0 0x00000100
69 #define CFG_HW_HAS_UART1 0x00000200
70 #define CFG_HW_HAS_EEPROM 0x00000400
71
72 #define FLASH_CMD_READ_ARRAY 0xFF
73 #define FLASH_CMD_READ_ID 0x90
74 #define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */
75
76 static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */;
77 static u8 control_value;
78
79 static void set_scl(u8 value)
80 {
81 gpio_line_set(GPIO_SCL, !!value);
82 udelay(3);
83 }
84
85 static void set_sda(u8 value)
86 {
87 gpio_line_set(GPIO_SDA, !!value);
88 udelay(3);
89 }
90
91 static void set_str(u8 value)
92 {
93 gpio_line_set(GPIO_STR, !!value);
94 udelay(3);
95 }
96
97 static inline void set_control(int line, int value)
98 {
99 if (value)
100 control_value |= (1 << line);
101 else
102 control_value &= ~(1 << line);
103 }
104
105
106 static void output_control(void)
107 {
108 int i;
109
110 gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
111 gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
112
113 for (i = 0; i < 8; i++) {
114 set_scl(0);
115 set_sda(control_value & (0x80 >> i)); /* MSB first */
116 set_scl(1); /* active edge */
117 }
118
119 set_str(1);
120 set_str(0);
121
122 set_scl(0);
123 set_sda(1); /* Be ready for START */
124 set_scl(1);
125 }
126
127
128 static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
129
130 static int hss_set_clock(int port, unsigned int clock_type)
131 {
132 int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
133
134 switch (clock_type) {
135 case CLOCK_DEFAULT:
136 case CLOCK_EXT:
137 set_control(ctrl_int, 0);
138 output_control();
139 return CLOCK_EXT;
140
141 case CLOCK_INT:
142 set_control(ctrl_int, 1);
143 output_control();
144 return CLOCK_INT;
145
146 default:
147 return -EINVAL;
148 }
149 }
150
151 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
152 {
153 int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
154 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
155 set_carrier_cb_tab[port](pdev, !i);
156 return IRQ_HANDLED;
157 }
158
159
160 static int hss_open(int port, void *pdev,
161 void (*set_carrier_cb)(void *pdev, int carrier))
162 {
163 int i, irq;
164
165 if (!port)
166 irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
167 else
168 irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
169
170 gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i);
171 set_carrier_cb(pdev, !i);
172
173 set_carrier_cb_tab[!!port] = set_carrier_cb;
174
175 if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
176 printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
177 irq, i);
178 return i;
179 }
180
181 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
182 output_control();
183 gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
184 return 0;
185 }
186
187 static void hss_close(int port, void *pdev)
188 {
189 free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
190 IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
191 set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
192
193 set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
194 output_control();
195 gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
196 }
197
198
199 /* Flash memory */
200 static struct flash_platform_data flash_data = {
201 .map_name = "cfi_probe",
202 .width = 2,
203 };
204
205 static struct resource flash_resource = {
206 .flags = IORESOURCE_MEM,
207 };
208
209 static struct platform_device device_flash = {
210 .name = "IXP4XX-Flash",
211 .id = 0,
212 .dev = { .platform_data = &flash_data },
213 .num_resources = 1,
214 .resource = &flash_resource,
215 };
216
217
218 /* I^2C interface */
219 static struct i2c_gpio_platform_data i2c_data = {
220 .sda_pin = GPIO_SDA,
221 .scl_pin = GPIO_SCL,
222 };
223
224 static struct platform_device device_i2c = {
225 .name = "i2c-gpio",
226 .id = 0,
227 .dev = { .platform_data = &i2c_data },
228 };
229
230
231 /* IXP425 2 UART ports */
232 static struct resource uart_resources[] = {
233 {
234 .start = IXP4XX_UART1_BASE_PHYS,
235 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
236 .flags = IORESOURCE_MEM,
237 },
238 {
239 .start = IXP4XX_UART2_BASE_PHYS,
240 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
241 .flags = IORESOURCE_MEM,
242 }
243 };
244
245 static struct plat_serial8250_port uart_data[] = {
246 {
247 .mapbase = IXP4XX_UART1_BASE_PHYS,
248 .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
249 REG_OFFSET,
250 .irq = IRQ_IXP4XX_UART1,
251 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
252 .iotype = UPIO_MEM,
253 .regshift = 2,
254 .uartclk = IXP4XX_UART_XTAL,
255 },
256 {
257 .mapbase = IXP4XX_UART2_BASE_PHYS,
258 .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
259 REG_OFFSET,
260 .irq = IRQ_IXP4XX_UART2,
261 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
262 .iotype = UPIO_MEM,
263 .regshift = 2,
264 .uartclk = IXP4XX_UART_XTAL,
265 },
266 { },
267 };
268
269 static struct platform_device device_uarts = {
270 .name = "serial8250",
271 .id = PLAT8250_DEV_PLATFORM,
272 .dev.platform_data = uart_data,
273 .num_resources = 2,
274 .resource = uart_resources,
275 };
276
277
278 /* Built-in 10/100 Ethernet MAC interfaces */
279 static struct eth_plat_info eth_plat[] = {
280 {
281 .phy = 0,
282 .rxq = 3,
283 .txreadyq = 32,
284 }, {
285 .phy = 1,
286 .rxq = 4,
287 .txreadyq = 33,
288 }
289 };
290
291 static struct platform_device device_eth_tab[] = {
292 {
293 .name = "ixp4xx_eth",
294 .id = IXP4XX_ETH_NPEB,
295 .dev.platform_data = eth_plat,
296 }, {
297 .name = "ixp4xx_eth",
298 .id = IXP4XX_ETH_NPEC,
299 .dev.platform_data = eth_plat + 1,
300 }
301 };
302
303
304 /* IXP425 2 synchronous serial ports */
305 static struct hss_plat_info hss_plat[] = {
306 {
307 .set_clock = hss_set_clock,
308 .open = hss_open,
309 .close = hss_close,
310 .txreadyq = 34,
311 }, {
312 .set_clock = hss_set_clock,
313 .open = hss_open,
314 .close = hss_close,
315 .txreadyq = 35,
316 }
317 };
318
319 static struct platform_device device_hss_tab[] = {
320 {
321 .name = "ixp4xx_hss",
322 .id = 0,
323 .dev.platform_data = hss_plat,
324 }, {
325 .name = "ixp4xx_hss",
326 .id = 1,
327 .dev.platform_data = hss_plat + 1,
328 }
329 };
330
331
332 static struct platform_device *device_tab[6] __initdata = {
333 &device_flash, /* index 0 */
334 };
335
336 static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
337 {
338 #ifdef __ARMEB__
339 return __raw_readb(flash + addr);
340 #else
341 return __raw_readb(flash + (addr ^ 3));
342 #endif
343 }
344
345 static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
346 {
347 #ifdef __ARMEB__
348 return __raw_readw(flash + addr);
349 #else
350 return __raw_readw(flash + (addr ^ 2));
351 #endif
352 }
353
354 static void __init gmlr_init(void)
355 {
356 u8 __iomem *flash;
357 int i, devices = 1; /* flash */
358
359 ixp4xx_sys_init();
360
361 if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
362 printk(KERN_ERR "goramo-mlr: unable to access system"
363 " configuration data\n");
364 else {
365 system_rev = __raw_readl(flash + CFG_REV);
366 hw_bits = __raw_readl(flash + CFG_HW_BITS);
367
368 for (i = 0; i < ETH_ALEN; i++) {
369 eth_plat[0].hwaddr[i] =
370 flash_readb(flash, CFG_ETH0_ADDRESS + i);
371 eth_plat[1].hwaddr[i] =
372 flash_readb(flash, CFG_ETH1_ADDRESS + i);
373 }
374
375 __raw_writew(FLASH_CMD_READ_ID, flash);
376 system_serial_high = flash_readw(flash, FLASH_SER_OFF);
377 system_serial_high <<= 16;
378 system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
379 system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
380 system_serial_low <<= 16;
381 system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
382 __raw_writew(FLASH_CMD_READ_ARRAY, flash);
383
384 iounmap(flash);
385 }
386
387 switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
388 case CFG_HW_HAS_UART0:
389 memset(&uart_data[1], 0, sizeof(uart_data[1]));
390 device_uarts.num_resources = 1;
391 break;
392
393 case CFG_HW_HAS_UART1:
394 device_uarts.dev.platform_data = &uart_data[1];
395 device_uarts.resource = &uart_resources[1];
396 device_uarts.num_resources = 1;
397 break;
398 }
399 if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
400 device_tab[devices++] = &device_uarts; /* max index 1 */
401
402 if (hw_bits & CFG_HW_HAS_ETH0)
403 device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
404 if (hw_bits & CFG_HW_HAS_ETH1)
405 device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
406
407 if (hw_bits & CFG_HW_HAS_HSS0)
408 device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
409 if (hw_bits & CFG_HW_HAS_HSS1)
410 device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
411
412 if (hw_bits & CFG_HW_HAS_EEPROM)
413 device_tab[devices++] = &device_i2c; /* max index 6 */
414
415 gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT);
416 gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT);
417 gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT);
418 gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT);
419 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
420 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
421 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
422 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
423 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
424
425 set_control(CONTROL_HSS0_DTR_N, 1);
426 set_control(CONTROL_HSS1_DTR_N, 1);
427 set_control(CONTROL_EEPROM_WC_N, 1);
428 set_control(CONTROL_PCI_RESET_N, 1);
429 output_control();
430
431 msleep(1); /* Wait for PCI devices to initialize */
432
433 flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
434 flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
435
436 platform_add_devices(device_tab, devices);
437 }
438
439
440 #ifdef CONFIG_PCI
441 static void __init gmlr_pci_preinit(void)
442 {
443 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
444 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
445 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
446 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
447 ixp4xx_pci_preinit();
448 }
449
450 static void __init gmlr_pci_postinit(void)
451 {
452 if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
453 (hw_bits & CFG_HW_USB_PORTS) < 5) {
454 /* need to adjust number of USB ports on NEC chip */
455 u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
456 if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
457 value &= ~7;
458 value |= (hw_bits & CFG_HW_USB_PORTS);
459 ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
460 }
461 }
462 }
463
464 static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
465 {
466 switch(slot) {
467 case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
468 case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
469 case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
470 default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
471 }
472 }
473
474 static struct hw_pci gmlr_hw_pci __initdata = {
475 .nr_controllers = 1,
476 .ops = &ixp4xx_ops,
477 .preinit = gmlr_pci_preinit,
478 .postinit = gmlr_pci_postinit,
479 .setup = ixp4xx_setup,
480 .map_irq = gmlr_map_irq,
481 };
482
483 static int __init gmlr_pci_init(void)
484 {
485 if (machine_is_goramo_mlr() &&
486 (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
487 pci_common_init(&gmlr_hw_pci);
488 return 0;
489 }
490
491 subsys_initcall(gmlr_pci_init);
492 #endif /* CONFIG_PCI */
493
494
495 MACHINE_START(GORAMO_MLR, "MultiLink")
496 /* Maintainer: Krzysztof Halasa */
497 .map_io = ixp4xx_map_io,
498 .init_early = ixp4xx_init_early,
499 .init_irq = ixp4xx_init_irq,
500 .timer = &ixp4xx_timer,
501 .atag_offset = 0x100,
502 .init_machine = gmlr_init,
503 #if defined(CONFIG_PCI)
504 .dma_zone_size = SZ_64M,
505 #endif
506 .restart = ixp4xx_restart,
507 MACHINE_END
Linux ARM platform port for MOXA ART SoC