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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / arm / mach-kirkwood / common.c
blob1201191d7f1bb24c386df88f5fe4de14e172b006
1 /*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/ata_platform.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/clk-provider.h>
19 #include <linux/spinlock.h>
20 #include <linux/mv643xx_i2c.h>
21 #include <net/dsa.h>
22 #include <asm/page.h>
23 #include <asm/timex.h>
24 #include <asm/kexec.h>
25 #include <asm/mach/map.h>
26 #include <asm/mach/time.h>
27 #include <mach/kirkwood.h>
28 #include <mach/bridge-regs.h>
29 #include <plat/audio.h>
30 #include <plat/cache-feroceon-l2.h>
31 #include <plat/mvsdio.h>
32 #include <plat/orion_nand.h>
33 #include <plat/ehci-orion.h>
34 #include <plat/common.h>
35 #include <plat/time.h>
36 #include <plat/addr-map.h>
37 #include <plat/mv_xor.h>
38 #include "common.h"
39
40 /*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43 static struct map_desc kirkwood_io_desc[] __initdata = {
44 {
45 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
46 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
47 .length = KIRKWOOD_PCIE_IO_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
51 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
52 .length = KIRKWOOD_PCIE1_IO_SIZE,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = KIRKWOOD_REGS_VIRT_BASE,
56 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
57 .length = KIRKWOOD_REGS_SIZE,
58 .type = MT_DEVICE,
59 },
60 };
61
62 void __init kirkwood_map_io(void)
63 {
64 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
65 }
66
67 /*****************************************************************************
68 * CLK tree
69 ****************************************************************************/
70
71 static void enable_sata0(void)
72 {
73 /* Enable PLL and IVREF */
74 writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
75 /* Enable PHY */
76 writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
77 }
78
79 static void disable_sata0(void)
80 {
81 /* Disable PLL and IVREF */
82 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
83 /* Disable PHY */
84 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
85 }
86
87 static void enable_sata1(void)
88 {
89 /* Enable PLL and IVREF */
90 writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
91 /* Enable PHY */
92 writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
93 }
94
95 static void disable_sata1(void)
96 {
97 /* Disable PLL and IVREF */
98 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
99 /* Disable PHY */
100 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
101 }
102
103 static void disable_pcie0(void)
104 {
105 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
106 while (1)
107 if (readl(PCIE_STATUS) & 0x1)
108 break;
109 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
110 }
111
112 static void disable_pcie1(void)
113 {
114 u32 dev, rev;
115
116 kirkwood_pcie_id(&dev, &rev);
117
118 if (dev == MV88F6282_DEV_ID) {
119 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
120 while (1)
121 if (readl(PCIE1_STATUS) & 0x1)
122 break;
123 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
124 }
125 }
126
127 /* An extended version of the gated clk. This calls fn_en()/fn_dis
128 * before enabling/disabling the clock. We use this to turn on/off
129 * PHYs etc. */
130 struct clk_gate_fn {
131 struct clk_gate gate;
132 void (*fn_en)(void);
133 void (*fn_dis)(void);
134 };
135
136 #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
137 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
138
139 static int clk_gate_fn_enable(struct clk_hw *hw)
140 {
141 struct clk_gate *gate = to_clk_gate(hw);
142 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
143 int ret;
144
145 ret = clk_gate_ops.enable(hw);
146 if (!ret && gate_fn->fn_en)
147 gate_fn->fn_en();
148
149 return ret;
150 }
151
152 static void clk_gate_fn_disable(struct clk_hw *hw)
153 {
154 struct clk_gate *gate = to_clk_gate(hw);
155 struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
156
157 if (gate_fn->fn_dis)
158 gate_fn->fn_dis();
159
160 clk_gate_ops.disable(hw);
161 }
162
163 static struct clk_ops clk_gate_fn_ops;
164
165 static struct clk __init *clk_register_gate_fn(struct device *dev,
166 const char *name,
167 const char *parent_name, unsigned long flags,
168 void __iomem *reg, u8 bit_idx,
169 u8 clk_gate_flags, spinlock_t *lock,
170 void (*fn_en)(void), void (*fn_dis)(void))
171 {
172 struct clk_gate_fn *gate_fn;
173 struct clk *clk;
174 struct clk_init_data init;
175
176 gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
177 if (!gate_fn) {
178 pr_err("%s: could not allocate gated clk\n", __func__);
179 return ERR_PTR(-ENOMEM);
180 }
181
182 init.name = name;
183 init.ops = &clk_gate_fn_ops;
184 init.flags = flags;
185 init.parent_names = (parent_name ? &parent_name : NULL);
186 init.num_parents = (parent_name ? 1 : 0);
187
188 /* struct clk_gate assignments */
189 gate_fn->gate.reg = reg;
190 gate_fn->gate.bit_idx = bit_idx;
191 gate_fn->gate.flags = clk_gate_flags;
192 gate_fn->gate.lock = lock;
193 gate_fn->gate.hw.init = &init;
194 gate_fn->fn_en = fn_en;
195 gate_fn->fn_dis = fn_dis;
196
197 /* ops is the gate ops, but with our enable/disable functions */
198 if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
199 clk_gate_fn_ops.disable != clk_gate_fn_disable) {
200 clk_gate_fn_ops = clk_gate_ops;
201 clk_gate_fn_ops.enable = clk_gate_fn_enable;
202 clk_gate_fn_ops.disable = clk_gate_fn_disable;
203 }
204
205 clk = clk_register(dev, &gate_fn->gate.hw);
206
207 if (IS_ERR(clk))
208 kfree(gate_fn);
209
210 return clk;
211 }
212
213 static DEFINE_SPINLOCK(gating_lock);
214 static struct clk *tclk;
215
216 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
217 {
218 return clk_register_gate(NULL, name, "tclk", 0,
219 (void __iomem *)CLOCK_GATING_CTRL,
220 bit_idx, 0, &gating_lock);
221 }
222
223 static struct clk __init *kirkwood_register_gate_fn(const char *name,
224 u8 bit_idx,
225 void (*fn_en)(void),
226 void (*fn_dis)(void))
227 {
228 return clk_register_gate_fn(NULL, name, "tclk", 0,
229 (void __iomem *)CLOCK_GATING_CTRL,
230 bit_idx, 0, &gating_lock, fn_en, fn_dis);
231 }
232
233 static struct clk *ge0, *ge1;
234
235 void __init kirkwood_clk_init(void)
236 {
237 struct clk *runit, *sata0, *sata1, *usb0, *sdio;
238 struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
239
240 tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
241 CLK_IS_ROOT, kirkwood_tclk);
242
243 runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
244 ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
245 ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
246 sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
247 enable_sata0, disable_sata0);
248 sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
249 enable_sata1, disable_sata1);
250 usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
251 sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
252 crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
253 xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
254 xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
255 pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
256 NULL, disable_pcie0);
257 pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
258 NULL, disable_pcie1);
259 audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
260 kirkwood_register_gate("tdm", CGC_BIT_TDM);
261 kirkwood_register_gate("tsu", CGC_BIT_TSU);
262
263 /* clkdev entries, mapping clks to devices */
264 orion_clkdev_add(NULL, "orion_spi.0", runit);
265 orion_clkdev_add(NULL, "orion_spi.1", runit);
266 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
267 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
268 orion_clkdev_add(NULL, "orion_wdt", tclk);
269 orion_clkdev_add("0", "sata_mv.0", sata0);
270 orion_clkdev_add("1", "sata_mv.0", sata1);
271 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
272 orion_clkdev_add(NULL, "orion_nand", runit);
273 orion_clkdev_add(NULL, "mvsdio", sdio);
274 orion_clkdev_add(NULL, "mv_crypto", crypto);
275 orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
276 orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
277 orion_clkdev_add("0", "pcie", pex0);
278 orion_clkdev_add("1", "pcie", pex1);
279 orion_clkdev_add(NULL, "kirkwood-i2s", audio);
280 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
281
282 /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
283 * so should never be gated.
284 */
285 clk_prepare_enable(runit);
286 }
287
288 /*****************************************************************************
289 * EHCI0
290 ****************************************************************************/
291 void __init kirkwood_ehci_init(void)
292 {
293 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
294 }
295
296
297 /*****************************************************************************
298 * GE00
299 ****************************************************************************/
300 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
301 {
302 orion_ge00_init(eth_data,
303 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
304 IRQ_KIRKWOOD_GE00_ERR, 1600);
305 /* The interface forgets the MAC address assigned by u-boot if
306 the clock is turned off, so claim the clk now. */
307 clk_prepare_enable(ge0);
308 }
309
310
311 /*****************************************************************************
312 * GE01
313 ****************************************************************************/
314 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
315 {
316 orion_ge01_init(eth_data,
317 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
318 IRQ_KIRKWOOD_GE01_ERR, 1600);
319 clk_prepare_enable(ge1);
320 }
321
322
323 /*****************************************************************************
324 * Ethernet switch
325 ****************************************************************************/
326 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
327 {
328 orion_ge00_switch_init(d, irq);
329 }
330
331
332 /*****************************************************************************
333 * NAND flash
334 ****************************************************************************/
335 static struct resource kirkwood_nand_resource = {
336 .flags = IORESOURCE_MEM,
337 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
338 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
339 KIRKWOOD_NAND_MEM_SIZE - 1,
340 };
341
342 static struct orion_nand_data kirkwood_nand_data = {
343 .cle = 0,
344 .ale = 1,
345 .width = 8,
346 };
347
348 static struct platform_device kirkwood_nand_flash = {
349 .name = "orion_nand",
350 .id = -1,
351 .dev = {
352 .platform_data = &kirkwood_nand_data,
353 },
354 .resource = &kirkwood_nand_resource,
355 .num_resources = 1,
356 };
357
358 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
359 int chip_delay)
360 {
361 kirkwood_nand_data.parts = parts;
362 kirkwood_nand_data.nr_parts = nr_parts;
363 kirkwood_nand_data.chip_delay = chip_delay;
364 platform_device_register(&kirkwood_nand_flash);
365 }
366
367 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
368 int (*dev_ready)(struct mtd_info *))
369 {
370 kirkwood_nand_data.parts = parts;
371 kirkwood_nand_data.nr_parts = nr_parts;
372 kirkwood_nand_data.dev_ready = dev_ready;
373 platform_device_register(&kirkwood_nand_flash);
374 }
375
376 /*****************************************************************************
377 * SoC RTC
378 ****************************************************************************/
379 static void __init kirkwood_rtc_init(void)
380 {
381 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
382 }
383
384
385 /*****************************************************************************
386 * SATA
387 ****************************************************************************/
388 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
389 {
390 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
391 }
392
393
394 /*****************************************************************************
395 * SD/SDIO/MMC
396 ****************************************************************************/
397 static struct resource mvsdio_resources[] = {
398 [0] = {
399 .start = SDIO_PHYS_BASE,
400 .end = SDIO_PHYS_BASE + SZ_1K - 1,
401 .flags = IORESOURCE_MEM,
402 },
403 [1] = {
404 .start = IRQ_KIRKWOOD_SDIO,
405 .end = IRQ_KIRKWOOD_SDIO,
406 .flags = IORESOURCE_IRQ,
407 },
408 };
409
410 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
411
412 static struct platform_device kirkwood_sdio = {
413 .name = "mvsdio",
414 .id = -1,
415 .dev = {
416 .dma_mask = &mvsdio_dmamask,
417 .coherent_dma_mask = DMA_BIT_MASK(32),
418 },
419 .num_resources = ARRAY_SIZE(mvsdio_resources),
420 .resource = mvsdio_resources,
421 };
422
423 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
424 {
425 u32 dev, rev;
426
427 kirkwood_pcie_id(&dev, &rev);
428 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
429 mvsdio_data->clock = 100000000;
430 else
431 mvsdio_data->clock = 200000000;
432 kirkwood_sdio.dev.platform_data = mvsdio_data;
433 platform_device_register(&kirkwood_sdio);
434 }
435
436
437 /*****************************************************************************
438 * SPI
439 ****************************************************************************/
440 void __init kirkwood_spi_init()
441 {
442 orion_spi_init(SPI_PHYS_BASE);
443 }
444
445
446 /*****************************************************************************
447 * I2C
448 ****************************************************************************/
449 void __init kirkwood_i2c_init(void)
450 {
451 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
452 }
453
454
455 /*****************************************************************************
456 * UART0
457 ****************************************************************************/
458
459 void __init kirkwood_uart0_init(void)
460 {
461 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
462 IRQ_KIRKWOOD_UART_0, tclk);
463 }
464
465
466 /*****************************************************************************
467 * UART1
468 ****************************************************************************/
469 void __init kirkwood_uart1_init(void)
470 {
471 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
472 IRQ_KIRKWOOD_UART_1, tclk);
473 }
474
475 /*****************************************************************************
476 * Cryptographic Engines and Security Accelerator (CESA)
477 ****************************************************************************/
478 void __init kirkwood_crypto_init(void)
479 {
480 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
481 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
482 }
483
484
485 /*****************************************************************************
486 * XOR0
487 ****************************************************************************/
488 void __init kirkwood_xor0_init(void)
489 {
490 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
491 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
492 }
493
494
495 /*****************************************************************************
496 * XOR1
497 ****************************************************************************/
498 void __init kirkwood_xor1_init(void)
499 {
500 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
501 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
502 }
503
504
505 /*****************************************************************************
506 * Watchdog
507 ****************************************************************************/
508 void __init kirkwood_wdt_init(void)
509 {
510 orion_wdt_init();
511 }
512
513
514 /*****************************************************************************
515 * Time handling
516 ****************************************************************************/
517 void __init kirkwood_init_early(void)
518 {
519 orion_time_set_base(TIMER_VIRT_BASE);
520
521 /*
522 * Some Kirkwood devices allocate their coherent buffers from atomic
523 * context. Increase size of atomic coherent pool to make sure such
524 * the allocations won't fail.
525 */
526 init_dma_coherent_pool_size(SZ_1M);
527 }
528
529 int kirkwood_tclk;
530
531 static int __init kirkwood_find_tclk(void)
532 {
533 u32 dev, rev;
534
535 kirkwood_pcie_id(&dev, &rev);
536
537 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
538 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
539 return 200000000;
540
541 return 166666667;
542 }
543
544 static void __init kirkwood_timer_init(void)
545 {
546 kirkwood_tclk = kirkwood_find_tclk();
547
548 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
549 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
550 }
551
552 struct sys_timer kirkwood_timer = {
553 .init = kirkwood_timer_init,
554 };
555
556 /*****************************************************************************
557 * Audio
558 ****************************************************************************/
559 static struct resource kirkwood_i2s_resources[] = {
560 [0] = {
561 .start = AUDIO_PHYS_BASE,
562 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
563 .flags = IORESOURCE_MEM,
564 },
565 [1] = {
566 .start = IRQ_KIRKWOOD_I2S,
567 .end = IRQ_KIRKWOOD_I2S,
568 .flags = IORESOURCE_IRQ,
569 },
570 };
571
572 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
573 .burst = 128,
574 };
575
576 static struct platform_device kirkwood_i2s_device = {
577 .name = "kirkwood-i2s",
578 .id = -1,
579 .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
580 .resource = kirkwood_i2s_resources,
581 .dev = {
582 .platform_data = &kirkwood_i2s_data,
583 },
584 };
585
586 static struct platform_device kirkwood_pcm_device = {
587 .name = "kirkwood-pcm-audio",
588 .id = -1,
589 };
590
591 void __init kirkwood_audio_init(void)
592 {
593 platform_device_register(&kirkwood_i2s_device);
594 platform_device_register(&kirkwood_pcm_device);
595 }
596
597 /*****************************************************************************
598 * General
599 ****************************************************************************/
600 /*
601 * Identify device ID and revision.
602 */
603 char * __init kirkwood_id(void)
604 {
605 u32 dev, rev;
606
607 kirkwood_pcie_id(&dev, &rev);
608
609 if (dev == MV88F6281_DEV_ID) {
610 if (rev == MV88F6281_REV_Z0)
611 return "MV88F6281-Z0";
612 else if (rev == MV88F6281_REV_A0)
613 return "MV88F6281-A0";
614 else if (rev == MV88F6281_REV_A1)
615 return "MV88F6281-A1";
616 else
617 return "MV88F6281-Rev-Unsupported";
618 } else if (dev == MV88F6192_DEV_ID) {
619 if (rev == MV88F6192_REV_Z0)
620 return "MV88F6192-Z0";
621 else if (rev == MV88F6192_REV_A0)
622 return "MV88F6192-A0";
623 else if (rev == MV88F6192_REV_A1)
624 return "MV88F6192-A1";
625 else
626 return "MV88F6192-Rev-Unsupported";
627 } else if (dev == MV88F6180_DEV_ID) {
628 if (rev == MV88F6180_REV_A0)
629 return "MV88F6180-Rev-A0";
630 else if (rev == MV88F6180_REV_A1)
631 return "MV88F6180-Rev-A1";
632 else
633 return "MV88F6180-Rev-Unsupported";
634 } else if (dev == MV88F6282_DEV_ID) {
635 if (rev == MV88F6282_REV_A0)
636 return "MV88F6282-Rev-A0";
637 else if (rev == MV88F6282_REV_A1)
638 return "MV88F6282-Rev-A1";
639 else
640 return "MV88F6282-Rev-Unsupported";
641 } else {
642 return "Device-Unknown";
643 }
644 }
645
646 void __init kirkwood_l2_init(void)
647 {
648 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
649 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
650 feroceon_l2_init(1);
651 #else
652 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
653 feroceon_l2_init(0);
654 #endif
655 }
656
657 void __init kirkwood_init(void)
658 {
659 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
660 kirkwood_id(), kirkwood_tclk);
661
662 /*
663 * Disable propagation of mbus errors to the CPU local bus,
664 * as this causes mbus errors (which can occur for example
665 * for PCI aborts) to throw CPU aborts, which we're not set
666 * up to deal with.
667 */
668 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
669
670 kirkwood_setup_cpu_mbus();
671
672 #ifdef CONFIG_CACHE_FEROCEON_L2
673 kirkwood_l2_init();
674 #endif
675
676 /* Setup root of clk tree */
677 kirkwood_clk_init();
678
679 /* internal devices that every board has */
680 kirkwood_rtc_init();
681 kirkwood_wdt_init();
682 kirkwood_xor0_init();
683 kirkwood_xor1_init();
684 kirkwood_crypto_init();
685
686 #ifdef CONFIG_KEXEC
687 kexec_reinit = kirkwood_enable_pcie;
688 #endif
689 }
690
691 void kirkwood_restart(char mode, const char *cmd)
692 {
693 /*
694 * Enable soft reset to assert RSTOUTn.
695 */
696 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
697
698 /*
699 * Assert soft reset.
700 */
701 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
702
703 while (1)
704 ;
705 }
Linux ARM platform port for MOXA ART SoC