arch/arm/mach-mv78xx0/common.c

   1 /*
   2  * arch/arm/mach-mv78xx0/common.c
   3  *
   4  * Core functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/ethtool.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/mach/time.h>
  20 #include <mach/mv78xx0.h>
  21 #include <mach/bridge-regs.h>
  22 #include <plat/cache-feroceon-l2.h>
  23 #include <plat/ehci-orion.h>
  24 #include <plat/orion_nand.h>
  25 #include <plat/time.h>
  26 #include <plat/common.h>
  27 #include <plat/addr-map.h>
  28 #include "common.h"
  29
  30 static int get_tclk(void);
  31
  32 /*****************************************************************************
  33  * Common bits
  34  ****************************************************************************/
  35 int mv78xx0_core_index(void)
  36 {
  37         u32 extra;
  38
  39         /*
  40          * Read Extra Features register.
  41          */
  42         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
  43
  44         return !!(extra & 0x00004000);
  45 }
  46
  47 static int get_hclk(void)
  48 {
  49         int hclk;
  50
  51         /*
  52          * HCLK tick rate is configured by DEV_D[7:5] pins.
  53          */
  54         switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
  55         case 0:
  56                 hclk = 166666667;
  57                 break;
  58         case 1:
  59                 hclk = 200000000;
  60                 break;
  61         case 2:
  62                 hclk = 266666667;
  63                 break;
  64         case 3:
  65                 hclk = 333333333;
  66                 break;
  67         case 4:
  68                 hclk = 400000000;
  69                 break;
  70         default:
  71                 panic("unknown HCLK PLL setting: %.8x\n",
  72                         readl(SAMPLE_AT_RESET_LOW));
  73         }
  74
  75         return hclk;
  76 }
  77
  78 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
  79 {
  80         u32 cfg;
  81
  82         /*
  83          * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
  84          * PCLK/L2CLK by bits [19:14].
  85          */
  86         if (core_index == 0) {
  87                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
  88         } else {
  89                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
  90         }
  91
  92         /*
  93          * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
  94          * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
  95          */
  96         *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
  97
  98         /*
  99          * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
 100          * ratio (1, 2, 3).
 101          */
 102         *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
 103 }
 104
 105 static int get_tclk(void)
 106 {
 107         int tclk_freq;
 108
 109         /*
 110          * TCLK tick rate is configured by DEV_A[2:0] strap pins.
 111          */
 112         switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
 113         case 1:
 114                 tclk_freq = 166666667;
 115                 break;
 116         case 3:
 117                 tclk_freq = 200000000;
 118                 break;
 119         default:
 120                 panic("unknown TCLK PLL setting: %.8x\n",
 121                         readl(SAMPLE_AT_RESET_HIGH));
 122         }
 123
 124         return tclk_freq;
 125 }
 126
 127
 128 /*****************************************************************************
 129  * I/O Address Mapping
 130  ****************************************************************************/
 131 static struct map_desc mv78xx0_io_desc[] __initdata = {
 132         {
 133                 .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
 134                 .pfn            = 0,
 135                 .length         = MV78XX0_CORE_REGS_SIZE,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
 139                 .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
 140                 .length         = MV78XX0_PCIE_IO_SIZE * 8,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = MV78XX0_REGS_VIRT_BASE,
 144                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
 145                 .length         = MV78XX0_REGS_SIZE,
 146                 .type           = MT_DEVICE,
 147         },
 148 };
 149
 150 void __init mv78xx0_map_io(void)
 151 {
 152         unsigned long phys;
 153
 154         /*
 155          * Map the right set of per-core registers depending on
 156          * which core we are running on.
 157          */
 158         if (mv78xx0_core_index() == 0) {
 159                 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
 160         } else {
 161                 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
 162         }
 163         mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
 164
 165         iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
 166 }
 167
 168
 169 /*****************************************************************************
 170  * CLK tree
 171  ****************************************************************************/
 172 static struct clk *tclk;
 173
 174 static void __init clk_init(void)
 175 {
 176         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
 177                                        get_tclk());
 178
 179         orion_clkdev_init(tclk);
 180 }
 181
 182 /*****************************************************************************
 183  * EHCI
 184  ****************************************************************************/
 185 void __init mv78xx0_ehci0_init(void)
 186 {
 187         orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
 188 }
 189
 190
 191 /*****************************************************************************
 192  * EHCI1
 193  ****************************************************************************/
 194 void __init mv78xx0_ehci1_init(void)
 195 {
 196         orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 197 }
 198
 199
 200 /*****************************************************************************
 201  * EHCI2
 202  ****************************************************************************/
 203 void __init mv78xx0_ehci2_init(void)
 204 {
 205         orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 206 }
 207
 208
 209 /*****************************************************************************
 210  * GE00
 211  ****************************************************************************/
 212 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 213 {
 214         orion_ge00_init(eth_data,
 215                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
 216                         IRQ_MV78XX0_GE_ERR,
 217                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
 218 }
 219
 220
 221 /*****************************************************************************
 222  * GE01
 223  ****************************************************************************/
 224 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 225 {
 226         orion_ge01_init(eth_data,
 227                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
 228                         NO_IRQ,
 229                         MV643XX_TX_CSUM_DEFAULT_LIMIT);
 230 }
 231
 232
 233 /*****************************************************************************
 234  * GE10
 235  ****************************************************************************/
 236 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 237 {
 238         u32 dev, rev;
 239
 240         /*
 241          * On the Z0, ge10 and ge11 are internally connected back
 242          * to back, and not brought out.
 243          */
 244         mv78xx0_pcie_id(&dev, &rev);
 245         if (dev == MV78X00_Z0_DEV_ID) {
 246                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 247                 eth_data->speed = SPEED_1000;
 248                 eth_data->duplex = DUPLEX_FULL;
 249         }
 250
 251         orion_ge10_init(eth_data,
 252                         GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
 253                         NO_IRQ);
 254 }
 255
 256
 257 /*****************************************************************************
 258  * GE11
 259  ****************************************************************************/
 260 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 261 {
 262         u32 dev, rev;
 263
 264         /*
 265          * On the Z0, ge10 and ge11 are internally connected back
 266          * to back, and not brought out.
 267          */
 268         mv78xx0_pcie_id(&dev, &rev);
 269         if (dev == MV78X00_Z0_DEV_ID) {
 270                 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
 271                 eth_data->speed = SPEED_1000;
 272                 eth_data->duplex = DUPLEX_FULL;
 273         }
 274
 275         orion_ge11_init(eth_data,
 276                         GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
 277                         NO_IRQ);
 278 }
 279
 280 /*****************************************************************************
 281  * I2C
 282  ****************************************************************************/
 283 void __init mv78xx0_i2c_init(void)
 284 {
 285         orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
 286         orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
 287 }
 288
 289 /*****************************************************************************
 290  * SATA
 291  ****************************************************************************/
 292 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 293 {
 294         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 295 }
 296
 297
 298 /*****************************************************************************
 299  * UART0
 300  ****************************************************************************/
 301 void __init mv78xx0_uart0_init(void)
 302 {
 303         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 304                          IRQ_MV78XX0_UART_0, tclk);
 305 }
 306
 307
 308 /*****************************************************************************
 309  * UART1
 310  ****************************************************************************/
 311 void __init mv78xx0_uart1_init(void)
 312 {
 313         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 314                          IRQ_MV78XX0_UART_1, tclk);
 315 }
 316
 317
 318 /*****************************************************************************
 319  * UART2
 320  ****************************************************************************/
 321 void __init mv78xx0_uart2_init(void)
 322 {
 323         orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
 324                          IRQ_MV78XX0_UART_2, tclk);
 325 }
 326
 327 /*****************************************************************************
 328  * UART3
 329  ****************************************************************************/
 330 void __init mv78xx0_uart3_init(void)
 331 {
 332         orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
 333                          IRQ_MV78XX0_UART_3, tclk);
 334 }
 335
 336 /*****************************************************************************
 337  * Time handling
 338  ****************************************************************************/
 339 void __init mv78xx0_init_early(void)
 340 {
 341         orion_time_set_base(TIMER_VIRT_BASE);
 342 }
 343
 344 static void mv78xx0_timer_init(void)
 345 {
 346         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 347                         IRQ_MV78XX0_TIMER_1, get_tclk());
 348 }
 349
 350 struct sys_timer mv78xx0_timer = {
 351         .init = mv78xx0_timer_init,
 352 };
 353
 354
 355 /*****************************************************************************
 356  * General
 357  ****************************************************************************/
 358 static char * __init mv78xx0_id(void)
 359 {
 360         u32 dev, rev;
 361
 362         mv78xx0_pcie_id(&dev, &rev);
 363
 364         if (dev == MV78X00_Z0_DEV_ID) {
 365                 if (rev == MV78X00_REV_Z0)
 366                         return "MV78X00-Z0";
 367                 else
 368                         return "MV78X00-Rev-Unsupported";
 369         } else if (dev == MV78100_DEV_ID) {
 370                 if (rev == MV78100_REV_A0)
 371                         return "MV78100-A0";
 372                 else if (rev == MV78100_REV_A1)
 373                         return "MV78100-A1";
 374                 else
 375                         return "MV78100-Rev-Unsupported";
 376         } else if (dev == MV78200_DEV_ID) {
 377                 if (rev == MV78100_REV_A0)
 378                         return "MV78200-A0";
 379                 else
 380                         return "MV78200-Rev-Unsupported";
 381         } else {
 382                 return "Device-Unknown";
 383         }
 384 }
 385
 386 static int __init is_l2_writethrough(void)
 387 {
 388         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
 389 }
 390
 391 void __init mv78xx0_init(void)
 392 {
 393         int core_index;
 394         int hclk;
 395         int pclk;
 396         int l2clk;
 397
 398         core_index = mv78xx0_core_index();
 399         hclk = get_hclk();
 400         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
 401
 402         printk(KERN_INFO "%s ", mv78xx0_id());
 403         printk("core #%d, ", core_index);
 404         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
 405         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
 406         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
 407         printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
 408
 409         mv78xx0_setup_cpu_mbus();
 410
 411 #ifdef CONFIG_CACHE_FEROCEON_L2
 412         feroceon_l2_init(is_l2_writethrough());
 413 #endif
 414
 415         /* Setup root of clk tree */
 416         clk_init();
 417 }
 418
 419 void mv78xx0_restart(char mode, const char *cmd)
 420 {
 421         /*
 422          * Enable soft reset to assert RSTOUTn.
 423          */
 424         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 425
 426         /*
 427          * Assert soft reset.
 428          */
 429         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 430
 431         while (1)
 432                 ;
 433 }