4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * This program is free software,you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/linkage.h>
13 #include <asm/smp_scu.h>
14 #include <asm/memory.h>
15 #include <asm/hardware/cache-l2x0.h>
17 #include <plat/omap44xx.h>
18 #include <mach/omap-secure.h>
21 #include "omap4-sar-layout.h"
23 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
38 * =============================
39 * == CPU suspend finisher ==
40 * =============================
42 * void omap4_finish_suspend(unsigned long cpu_state)
44 * This function code saves the CPU context and performs the CPU
45 * power down sequence. Calling WFI effectively changes the CPU
46 * power domains states to the desired target power state.
48 * @cpu_state : contains context save state (r0)
50 * 1 - CPUx L1 and logic lost: MPUSS CSWR
51 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
52 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
53 * @return: This function never returns for CPU OFF and DORMANT power states.
54 * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
55 * from this follows a full CPU reset path via ROM code to CPU restore code.
56 * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
57 * It returns to the caller for CPU INACTIVE and ON power states or in case
58 * CPU failed to transition to targeted OFF/DORMANT state.
60 * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
61 * stack frame and it expects the caller to take care of it. Hence the entire
62 * stack frame is saved to avoid possible stack corruption.
64 ENTRY(omap4_finish_suspend)
65 stmfd sp!, {r4-r12, lr}
67 beq do_WFI @ No lowpower state, jump to WFI
70 * Flush all data from the L1 data cache before disabling
73 bl omap4_get_sar_ram_base
74 ldr r9, [r0, #OMAP_TYPE_OFFSET]
75 cmp r9, #0x1 @ Check for HS device
76 bne skip_secure_l1_clean
77 mov r0, #SCU_PM_NORMAL
78 mov r1, #0xFF @ clean seucre L1
79 stmfd r13!, {r4-r12, r14}
80 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
82 ldmfd r13!, {r4-r12, r14}
84 bl v7_flush_dcache_all
87 * Clear the SCTLR.C bit to prevent further data cache
88 * allocation. Clearing SCTLR.C would make all the data accesses
89 * strongly ordered and would not hit the cache.
91 mrc p15, 0, r0, c1, c0, 0
92 bic r0, r0, #(1 << 2) @ Disable the C bit
93 mcr p15, 0, r0, c1, c0, 0
97 * Invalidate L1 data cache. Even though only invalidate is
98 * necessary exported flush API is used here. Doing clean
99 * on already clean cache would be almost NOP.
101 bl v7_flush_dcache_all
104 * Switch the CPU from Symmetric Multiprocessing (SMP) mode
105 * to AsymmetricMultiprocessing (AMP) mode by programming
106 * the SCU power status to DORMANT or OFF mode.
107 * This enables the CPU to be taken out of coherency by
108 * preventing the CPU from receiving cache, TLB, or BTB
109 * maintenance operations broadcast by other CPUs in the cluster.
111 bl omap4_get_sar_ram_base
113 ldr r9, [r8, #OMAP_TYPE_OFFSET]
114 cmp r9, #0x1 @ Check for HS device
116 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
118 ldreq r0, [r8, #SCU_OFFSET0]
119 ldrne r0, [r8, #SCU_OFFSET1]
121 stmfd r13!, {r4-r12, r14}
122 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
124 ldmfd r13!, {r4-r12, r14}
127 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
129 ldreq r1, [r8, #SCU_OFFSET0]
130 ldrne r1, [r8, #SCU_OFFSET1]
131 bl omap4_get_scu_base
134 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
136 mrcne p15, 0, r0, c1, c0, 1
137 bicne r0, r0, #(1 << 6) @ Disable SMP bit
138 mcrne p15, 0, r0, c1, c0, 1
141 #ifdef CONFIG_CACHE_L2X0
143 * Clean and invalidate the L2 cache.
144 * Common cache-l2x0.c functions can't be used here since it
145 * uses spinlocks. We are out of coherency here with data cache
146 * disabled. The spinlock implementation uses exclusive load/store
147 * instruction which can fail without data cache being enabled.
148 * OMAP4 hardware doesn't support exclusive monitor which can
149 * overcome exclusive access issue. Because of this, CPU can
152 bl omap4_get_sar_ram_base
154 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
156 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
157 ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
160 #ifdef CONFIG_PL310_ERRATA_727915
162 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
165 bl omap4_get_l2cache_base
168 str r0, [r2, #L2X0_CLEAN_INV_WAY]
170 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
174 #ifdef CONFIG_PL310_ERRATA_727915
176 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
180 bl omap4_get_l2cache_base
183 str r0, [r2, #L2X0_CACHE_SYNC]
185 ldr r0, [r2, #L2X0_CACHE_SYNC]
194 * CPU is here when it failed to enter OFF/DORMANT or
195 * no low power state was attempted.
197 mrc p15, 0, r0, c1, c0, 0
198 tst r0, #(1 << 2) @ Check C bit enabled?
199 orreq r0, r0, #(1 << 2) @ Enable the C bit
200 mcreq p15, 0, r0, c1, c0, 0
204 * Ensure the CPU power state is set to NORMAL in
205 * SCU power state so that CPU is back in coherency.
206 * In non-coherent mode CPU can lock-up and lead to
209 mrc p15, 0, r0, c1, c0, 1
210 tst r0, #(1 << 6) @ Check SMP bit enabled?
211 orreq r0, r0, #(1 << 6)
212 mcreq p15, 0, r0, c1, c0, 1
214 bl omap4_get_sar_ram_base
216 ldr r9, [r8, #OMAP_TYPE_OFFSET]
217 cmp r9, #0x1 @ Check for HS device
219 mov r0, #SCU_PM_NORMAL
221 stmfd r13!, {r4-r12, r14}
222 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
224 ldmfd r13!, {r4-r12, r14}
227 bl omap4_get_scu_base
228 mov r1, #SCU_PM_NORMAL
233 ldmfd sp!, {r4-r12, pc}
234 ENDPROC(omap4_finish_suspend)
237 * ============================
238 * == CPU resume entry point ==
239 * ============================
241 * void omap4_cpu_resume(void)
243 * ROM code jumps to this function while waking up from CPU
244 * OFF or DORMANT state. Physical address of the function is
245 * stored in the SAR RAM while entering to OFF or DORMANT mode.
246 * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
248 ENTRY(omap4_cpu_resume)
250 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
251 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
252 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
253 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
254 * OMAP443X GP devices- SMP bit isn't accessible.
255 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
257 ldr r8, =OMAP44XX_SAR_RAM_BASE
258 ldr r9, [r8, #OMAP_TYPE_OFFSET]
259 cmp r9, #0x1 @ Skip if GP device
260 bne skip_ns_smp_enable
261 mrc p15, 0, r0, c0, c0, 5
263 beq skip_ns_smp_enable
265 mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
266 adr r3, ppa_zero_params @ Pointer to parameters
267 mov r1, #0x0 @ Process ID
270 mov r12, #0x00 @ Secure Service ID
272 cmp r0, #0x0 @ API returns 0 on success.
276 mrc p15, 0, r0, c1, c0, 1
277 tst r0, #(1 << 6) @ Check SMP bit enabled?
278 orreq r0, r0, #(1 << 6)
279 mcreq p15, 0, r0, c1, c0, 1
282 #ifdef CONFIG_CACHE_L2X0
284 * Restore the L2 AUXCTRL and enable the L2 cache.
285 * OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL
286 * OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
287 * register r0 contains value to be programmed.
288 * L2 cache is already invalidate by ROM code as part
289 * of MPUSS OFF wakeup path.
291 ldr r2, =OMAP44XX_L2CACHE_BASE
292 ldr r0, [r2, #L2X0_CTRL]
295 beq skip_l2en @ Skip if already enabled
296 ldr r3, =OMAP44XX_SAR_RAM_BASE
297 ldr r1, [r3, #OMAP_TYPE_OFFSET]
298 cmp r1, #0x1 @ Check for HS device
300 ldr r0, =OMAP4_PPA_L2_POR_INDEX
301 ldr r1, =OMAP44XX_SAR_RAM_BASE
302 ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
303 adr r3, ppa_por_params
305 mov r1, #0x0 @ Process ID
308 mov r12, #0x00 @ Secure Service ID
312 ldr r1, =OMAP44XX_SAR_RAM_BASE
313 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
314 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
317 ldr r1, =OMAP44XX_SAR_RAM_BASE
318 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
319 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
322 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
327 b cpu_resume @ Jump to generic resume
328 ENDPROC(omap4_cpu_resume)
331 #ifndef CONFIG_OMAP4_ERRATA_I688
334 ENDPROC(omap_bus_sync)
339 /* Drain interconnect write buffers. */
343 * Execute an ISB instruction to ensure that all of the
344 * CP15 register changes have been committed.
349 * Execute a barrier instruction to ensure that all cache,
350 * TLB and branch predictor maintenance operations issued
351 * by any CPU in the cluster have completed.
357 * Execute a WFI instruction and wait until the
358 * STANDBYWFI output is asserted to indicate that the
359 * CPU is in idle and low power state. CPU can specualatively
360 * prefetch the instructions so add NOPs after WFI. Sixteen
361 * NOPs as per Cortex-A9 pipeline.
363 wfi @ Wait For Interrupt