arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_dma.h>
  29 #include <linux/sh_timer.h>
  30 #include <linux/dma-mapping.h>
  31 #include <mach/dma-register.h>
  32 #include <mach/r8a7740.h>
  33 #include <mach/pm-rmobile.h>
  34 #include <mach/common.h>
  35 #include <mach/irqs.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/time.h>
  40
  41 static struct map_desc r8a7740_io_desc[] __initdata = {
  42          /*
  43           * for CPGA/INTC/PFC
  44           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  45           */
  46         {
  47                 .virtual        = 0xe6000000,
  48                 .pfn            = __phys_to_pfn(0xe6000000),
  49                 .length         = 160 << 20,
  50                 .type           = MT_DEVICE_NONSHARED
  51         },
  52 #ifdef CONFIG_CACHE_L2X0
  53         /*
  54          * for l2x0_init()
  55          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  56          */
  57         {
  58                 .virtual        = 0xf0002000,
  59                 .pfn            = __phys_to_pfn(0xf0100000),
  60                 .length         = PAGE_SIZE,
  61                 .type           = MT_DEVICE_NONSHARED
  62         },
  63 #endif
  64 };
  65
  66 void __init r8a7740_map_io(void)
  67 {
  68         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  69
  70         /*
  71          * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
  72          * enough to allocate the frame buffer memory.
  73          */
  74         init_consistent_dma_size(12 << 20);
  75 }
  76
  77 /* SCIFA0 */
  78 static struct plat_sci_port scif0_platform_data = {
  79         .mapbase        = 0xe6c40000,
  80         .flags          = UPF_BOOT_AUTOCONF,
  81         .scscr          = SCSCR_RE | SCSCR_TE,
  82         .scbrr_algo_id  = SCBRR_ALGO_4,
  83         .type           = PORT_SCIFA,
  84         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
  85 };
  86
  87 static struct platform_device scif0_device = {
  88         .name           = "sh-sci",
  89         .id             = 0,
  90         .dev            = {
  91                 .platform_data  = &scif0_platform_data,
  92         },
  93 };
  94
  95 /* SCIFA1 */
  96 static struct plat_sci_port scif1_platform_data = {
  97         .mapbase        = 0xe6c50000,
  98         .flags          = UPF_BOOT_AUTOCONF,
  99         .scscr          = SCSCR_RE | SCSCR_TE,
 100         .scbrr_algo_id  = SCBRR_ALGO_4,
 101         .type           = PORT_SCIFA,
 102         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
 103 };
 104
 105 static struct platform_device scif1_device = {
 106         .name           = "sh-sci",
 107         .id             = 1,
 108         .dev            = {
 109                 .platform_data  = &scif1_platform_data,
 110         },
 111 };
 112
 113 /* SCIFA2 */
 114 static struct plat_sci_port scif2_platform_data = {
 115         .mapbase        = 0xe6c60000,
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE,
 118         .scbrr_algo_id  = SCBRR_ALGO_4,
 119         .type           = PORT_SCIFA,
 120         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
 121 };
 122
 123 static struct platform_device scif2_device = {
 124         .name           = "sh-sci",
 125         .id             = 2,
 126         .dev            = {
 127                 .platform_data  = &scif2_platform_data,
 128         },
 129 };
 130
 131 /* SCIFA3 */
 132 static struct plat_sci_port scif3_platform_data = {
 133         .mapbase        = 0xe6c70000,
 134         .flags          = UPF_BOOT_AUTOCONF,
 135         .scscr          = SCSCR_RE | SCSCR_TE,
 136         .scbrr_algo_id  = SCBRR_ALGO_4,
 137         .type           = PORT_SCIFA,
 138         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
 139 };
 140
 141 static struct platform_device scif3_device = {
 142         .name           = "sh-sci",
 143         .id             = 3,
 144         .dev            = {
 145                 .platform_data  = &scif3_platform_data,
 146         },
 147 };
 148
 149 /* SCIFA4 */
 150 static struct plat_sci_port scif4_platform_data = {
 151         .mapbase        = 0xe6c80000,
 152         .flags          = UPF_BOOT_AUTOCONF,
 153         .scscr          = SCSCR_RE | SCSCR_TE,
 154         .scbrr_algo_id  = SCBRR_ALGO_4,
 155         .type           = PORT_SCIFA,
 156         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
 157 };
 158
 159 static struct platform_device scif4_device = {
 160         .name           = "sh-sci",
 161         .id             = 4,
 162         .dev            = {
 163                 .platform_data  = &scif4_platform_data,
 164         },
 165 };
 166
 167 /* SCIFA5 */
 168 static struct plat_sci_port scif5_platform_data = {
 169         .mapbase        = 0xe6cb0000,
 170         .flags          = UPF_BOOT_AUTOCONF,
 171         .scscr          = SCSCR_RE | SCSCR_TE,
 172         .scbrr_algo_id  = SCBRR_ALGO_4,
 173         .type           = PORT_SCIFA,
 174         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
 175 };
 176
 177 static struct platform_device scif5_device = {
 178         .name           = "sh-sci",
 179         .id             = 5,
 180         .dev            = {
 181                 .platform_data  = &scif5_platform_data,
 182         },
 183 };
 184
 185 /* SCIFA6 */
 186 static struct plat_sci_port scif6_platform_data = {
 187         .mapbase        = 0xe6cc0000,
 188         .flags          = UPF_BOOT_AUTOCONF,
 189         .scscr          = SCSCR_RE | SCSCR_TE,
 190         .scbrr_algo_id  = SCBRR_ALGO_4,
 191         .type           = PORT_SCIFA,
 192         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
 193 };
 194
 195 static struct platform_device scif6_device = {
 196         .name           = "sh-sci",
 197         .id             = 6,
 198         .dev            = {
 199                 .platform_data  = &scif6_platform_data,
 200         },
 201 };
 202
 203 /* SCIFA7 */
 204 static struct plat_sci_port scif7_platform_data = {
 205         .mapbase        = 0xe6cd0000,
 206         .flags          = UPF_BOOT_AUTOCONF,
 207         .scscr          = SCSCR_RE | SCSCR_TE,
 208         .scbrr_algo_id  = SCBRR_ALGO_4,
 209         .type           = PORT_SCIFA,
 210         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
 211 };
 212
 213 static struct platform_device scif7_device = {
 214         .name           = "sh-sci",
 215         .id             = 7,
 216         .dev            = {
 217                 .platform_data  = &scif7_platform_data,
 218         },
 219 };
 220
 221 /* SCIFB */
 222 static struct plat_sci_port scifb_platform_data = {
 223         .mapbase        = 0xe6c30000,
 224         .flags          = UPF_BOOT_AUTOCONF,
 225         .scscr          = SCSCR_RE | SCSCR_TE,
 226         .scbrr_algo_id  = SCBRR_ALGO_4,
 227         .type           = PORT_SCIFB,
 228         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
 229 };
 230
 231 static struct platform_device scifb_device = {
 232         .name           = "sh-sci",
 233         .id             = 8,
 234         .dev            = {
 235                 .platform_data  = &scifb_platform_data,
 236         },
 237 };
 238
 239 /* CMT */
 240 static struct sh_timer_config cmt10_platform_data = {
 241         .name = "CMT10",
 242         .channel_offset = 0x10,
 243         .timer_bit = 0,
 244         .clockevent_rating = 125,
 245         .clocksource_rating = 125,
 246 };
 247
 248 static struct resource cmt10_resources[] = {
 249         [0] = {
 250                 .name   = "CMT10",
 251                 .start  = 0xe6138010,
 252                 .end    = 0xe613801b,
 253                 .flags  = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start  = evt2irq(0x0b00),
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device cmt10_device = {
 262         .name           = "sh_cmt",
 263         .id             = 10,
 264         .dev = {
 265                 .platform_data  = &cmt10_platform_data,
 266         },
 267         .resource       = cmt10_resources,
 268         .num_resources  = ARRAY_SIZE(cmt10_resources),
 269 };
 270
 271 static struct platform_device *r8a7740_early_devices[] __initdata = {
 272         &scif0_device,
 273         &scif1_device,
 274         &scif2_device,
 275         &scif3_device,
 276         &scif4_device,
 277         &scif5_device,
 278         &scif6_device,
 279         &scif7_device,
 280         &scifb_device,
 281         &cmt10_device,
 282 };
 283
 284 /* DMA */
 285 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 286         {
 287                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 288                 .addr           = 0xe6850030,
 289                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 290                 .mid_rid        = 0xc1,
 291         }, {
 292                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 293                 .addr           = 0xe6850030,
 294                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 295                 .mid_rid        = 0xc2,
 296         }, {
 297                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 298                 .addr           = 0xe6860030,
 299                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 300                 .mid_rid        = 0xc9,
 301         }, {
 302                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 303                 .addr           = 0xe6860030,
 304                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 305                 .mid_rid        = 0xca,
 306         }, {
 307                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 308                 .addr           = 0xe6870030,
 309                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 310                 .mid_rid        = 0xcd,
 311         }, {
 312                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 313                 .addr           = 0xe6870030,
 314                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 315                 .mid_rid        = 0xce,
 316         }, {
 317                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 318                 .addr           = 0xfe1f0024,
 319                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 320                 .mid_rid        = 0xb1,
 321         }, {
 322                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 323                 .addr           = 0xfe1f0020,
 324                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 325                 .mid_rid        = 0xb2,
 326         }, {
 327                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 328                 .addr           = 0xfe1f0064,
 329                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 330                 .mid_rid        = 0xb5,
 331         },
 332 };
 333
 334 #define DMA_CHANNEL(a, b, c)                    \
 335 {                                               \
 336         .offset         = a,                    \
 337         .dmars          = b,                    \
 338         .dmars_bit      = c,                    \
 339         .chclr_offset   = (0x220 - 0x20) + a    \
 340 }
 341
 342 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 343         DMA_CHANNEL(0x00, 0, 0),
 344         DMA_CHANNEL(0x10, 0, 8),
 345         DMA_CHANNEL(0x20, 4, 0),
 346         DMA_CHANNEL(0x30, 4, 8),
 347         DMA_CHANNEL(0x50, 8, 0),
 348         DMA_CHANNEL(0x60, 8, 8),
 349 };
 350
 351 static struct sh_dmae_pdata dma_platform_data = {
 352         .slave          = r8a7740_dmae_slaves,
 353         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 354         .channel        = r8a7740_dmae_channels,
 355         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 356         .ts_low_shift   = TS_LOW_SHIFT,
 357         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 358         .ts_high_shift  = TS_HI_SHIFT,
 359         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 360         .ts_shift       = dma_ts_shift,
 361         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 362         .dmaor_init     = DMAOR_DME,
 363         .chclr_present  = 1,
 364 };
 365
 366 /* Resource order important! */
 367 static struct resource r8a7740_dmae0_resources[] = {
 368         {
 369                 /* Channel registers and DMAOR */
 370                 .start  = 0xfe008020,
 371                 .end    = 0xfe00828f,
 372                 .flags  = IORESOURCE_MEM,
 373         },
 374         {
 375                 /* DMARSx */
 376                 .start  = 0xfe009000,
 377                 .end    = 0xfe00900b,
 378                 .flags  = IORESOURCE_MEM,
 379         },
 380         {
 381                 .name   = "error_irq",
 382                 .start  = evt2irq(0x20c0),
 383                 .end    = evt2irq(0x20c0),
 384                 .flags  = IORESOURCE_IRQ,
 385         },
 386         {
 387                 /* IRQ for channels 0-5 */
 388                 .start  = evt2irq(0x2000),
 389                 .end    = evt2irq(0x20a0),
 390                 .flags  = IORESOURCE_IRQ,
 391         },
 392 };
 393
 394 /* Resource order important! */
 395 static struct resource r8a7740_dmae1_resources[] = {
 396         {
 397                 /* Channel registers and DMAOR */
 398                 .start  = 0xfe018020,
 399                 .end    = 0xfe01828f,
 400                 .flags  = IORESOURCE_MEM,
 401         },
 402         {
 403                 /* DMARSx */
 404                 .start  = 0xfe019000,
 405                 .end    = 0xfe01900b,
 406                 .flags  = IORESOURCE_MEM,
 407         },
 408         {
 409                 .name   = "error_irq",
 410                 .start  = evt2irq(0x21c0),
 411                 .end    = evt2irq(0x21c0),
 412                 .flags  = IORESOURCE_IRQ,
 413         },
 414         {
 415                 /* IRQ for channels 0-5 */
 416                 .start  = evt2irq(0x2100),
 417                 .end    = evt2irq(0x21a0),
 418                 .flags  = IORESOURCE_IRQ,
 419         },
 420 };
 421
 422 /* Resource order important! */
 423 static struct resource r8a7740_dmae2_resources[] = {
 424         {
 425                 /* Channel registers and DMAOR */
 426                 .start  = 0xfe028020,
 427                 .end    = 0xfe02828f,
 428                 .flags  = IORESOURCE_MEM,
 429         },
 430         {
 431                 /* DMARSx */
 432                 .start  = 0xfe029000,
 433                 .end    = 0xfe02900b,
 434                 .flags  = IORESOURCE_MEM,
 435         },
 436         {
 437                 .name   = "error_irq",
 438                 .start  = evt2irq(0x22c0),
 439                 .end    = evt2irq(0x22c0),
 440                 .flags  = IORESOURCE_IRQ,
 441         },
 442         {
 443                 /* IRQ for channels 0-5 */
 444                 .start  = evt2irq(0x2200),
 445                 .end    = evt2irq(0x22a0),
 446                 .flags  = IORESOURCE_IRQ,
 447         },
 448 };
 449
 450 static struct platform_device dma0_device = {
 451         .name           = "sh-dma-engine",
 452         .id             = 0,
 453         .resource       = r8a7740_dmae0_resources,
 454         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 455         .dev            = {
 456                 .platform_data  = &dma_platform_data,
 457         },
 458 };
 459
 460 static struct platform_device dma1_device = {
 461         .name           = "sh-dma-engine",
 462         .id             = 1,
 463         .resource       = r8a7740_dmae1_resources,
 464         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 465         .dev            = {
 466                 .platform_data  = &dma_platform_data,
 467         },
 468 };
 469
 470 static struct platform_device dma2_device = {
 471         .name           = "sh-dma-engine",
 472         .id             = 2,
 473         .resource       = r8a7740_dmae2_resources,
 474         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 475         .dev            = {
 476                 .platform_data  = &dma_platform_data,
 477         },
 478 };
 479
 480 /* USB-DMAC */
 481 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 482         {
 483                 .offset = 0,
 484         }, {
 485                 .offset = 0x20,
 486         },
 487 };
 488
 489 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 490         {
 491                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 492                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 493         }, {
 494                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 495                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 496         },
 497 };
 498
 499 static struct sh_dmae_pdata usb_dma_platform_data = {
 500         .slave          = r8a7740_usb_dma_slaves,
 501         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 502         .channel        = r8a7740_usb_dma_channels,
 503         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 504         .ts_low_shift   = USBTS_LOW_SHIFT,
 505         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 506         .ts_high_shift  = USBTS_HI_SHIFT,
 507         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 508         .ts_shift       = dma_usbts_shift,
 509         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 510         .dmaor_init     = DMAOR_DME,
 511         .chcr_offset    = 0x14,
 512         .chcr_ie_bit    = 1 << 5,
 513         .dmaor_is_32bit = 1,
 514         .needs_tend_set = 1,
 515         .no_dmars       = 1,
 516         .slave_only     = 1,
 517 };
 518
 519 static struct resource r8a7740_usb_dma_resources[] = {
 520         {
 521                 /* Channel registers and DMAOR */
 522                 .start  = 0xe68a0020,
 523                 .end    = 0xe68a0064 - 1,
 524                 .flags  = IORESOURCE_MEM,
 525         },
 526         {
 527                 /* VCR/SWR/DMICR */
 528                 .start  = 0xe68a0000,
 529                 .end    = 0xe68a0014 - 1,
 530                 .flags  = IORESOURCE_MEM,
 531         },
 532         {
 533                 /* IRQ for channels */
 534                 .start  = evt2irq(0x0a00),
 535                 .end    = evt2irq(0x0a00),
 536                 .flags  = IORESOURCE_IRQ,
 537         },
 538 };
 539
 540 static struct platform_device usb_dma_device = {
 541         .name           = "sh-dma-engine",
 542         .id             = 3,
 543         .resource       = r8a7740_usb_dma_resources,
 544         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 545         .dev            = {
 546                 .platform_data  = &usb_dma_platform_data,
 547         },
 548 };
 549
 550 /* I2C */
 551 static struct resource i2c0_resources[] = {
 552         [0] = {
 553                 .name   = "IIC0",
 554                 .start  = 0xfff20000,
 555                 .end    = 0xfff20425 - 1,
 556                 .flags  = IORESOURCE_MEM,
 557         },
 558         [1] = {
 559                 .start  = intcs_evt2irq(0xe00),
 560                 .end    = intcs_evt2irq(0xe60),
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563 };
 564
 565 static struct resource i2c1_resources[] = {
 566         [0] = {
 567                 .name   = "IIC1",
 568                 .start  = 0xe6c20000,
 569                 .end    = 0xe6c20425 - 1,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         [1] = {
 573                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 574                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 575                 .flags  = IORESOURCE_IRQ,
 576         },
 577 };
 578
 579 static struct platform_device i2c0_device = {
 580         .name           = "i2c-sh_mobile",
 581         .id             = 0,
 582         .resource       = i2c0_resources,
 583         .num_resources  = ARRAY_SIZE(i2c0_resources),
 584 };
 585
 586 static struct platform_device i2c1_device = {
 587         .name           = "i2c-sh_mobile",
 588         .id             = 1,
 589         .resource       = i2c1_resources,
 590         .num_resources  = ARRAY_SIZE(i2c1_resources),
 591 };
 592
 593 static struct platform_device *r8a7740_late_devices[] __initdata = {
 594         &i2c0_device,
 595         &i2c1_device,
 596         &dma0_device,
 597         &dma1_device,
 598         &dma2_device,
 599         &usb_dma_device,
 600 };
 601
 602 /*
 603  * r8a7740 chip has lasting errata on MERAM buffer.
 604  * this is work-around for it.
 605  * see
 606  *      "Media RAM (MERAM)" on r8a7740 documentation
 607  */
 608 #define MEBUFCNTR       0xFE950098
 609 void r8a7740_meram_workaround(void)
 610 {
 611         void __iomem *reg;
 612
 613         reg = ioremap_nocache(MEBUFCNTR, 4);
 614         if (reg) {
 615                 iowrite32(0x01600164, reg);
 616                 iounmap(reg);
 617         }
 618 }
 619
 620 #define ICCR    0x0004
 621 #define ICSTART 0x0070
 622
 623 #define i2c_read(reg, offset)           ioread8(reg + offset)
 624 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 625
 626 /*
 627  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 628  * this is work-around for it.
 629  */
 630 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 631 {
 632         struct resource *res;
 633         void __iomem *reg;
 634
 635         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 636         if (unlikely(!res)) {
 637                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 638                 return;
 639         }
 640
 641         reg = ioremap(res->start, resource_size(res));
 642         if (unlikely(!reg)) {
 643                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 644                 return;
 645         }
 646
 647         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 648         i2c_read(reg, ICCR); /* dummy read */
 649
 650         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 651         i2c_read(reg, ICSTART); /* dummy read */
 652
 653         udelay(10);
 654
 655         i2c_write(reg, ICCR, 0x01);
 656         i2c_write(reg, ICSTART, 0x00);
 657
 658         udelay(10);
 659
 660         i2c_write(reg, ICCR, 0x10);
 661         udelay(10);
 662         i2c_write(reg, ICCR, 0x00);
 663         udelay(10);
 664         i2c_write(reg, ICCR, 0x10);
 665         udelay(10);
 666
 667         iounmap(reg);
 668 }
 669
 670 void __init r8a7740_add_standard_devices(void)
 671 {
 672         /* I2C work-around */
 673         r8a7740_i2c_workaround(&i2c0_device);
 674         r8a7740_i2c_workaround(&i2c1_device);
 675
 676         /* PM domain */
 677         rmobile_init_pm_domain(&r8a7740_pd_a4s);
 678         rmobile_init_pm_domain(&r8a7740_pd_a3sp);
 679         rmobile_init_pm_domain(&r8a7740_pd_a4lc);
 680
 681         rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
 682
 683         /* add devices */
 684         platform_add_devices(r8a7740_early_devices,
 685                             ARRAY_SIZE(r8a7740_early_devices));
 686         platform_add_devices(r8a7740_late_devices,
 687                              ARRAY_SIZE(r8a7740_late_devices));
 688
 689         /* add devices to PM domain  */
 690
 691         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif0_device);
 692         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif1_device);
 693         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif2_device);
 694         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif3_device);
 695         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif4_device);
 696         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif5_device);
 697         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif6_device);
 698         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif7_device);
 699         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scifb_device);
 700         rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &i2c1_device);
 701 }
 702
 703 static void __init r8a7740_earlytimer_init(void)
 704 {
 705         r8a7740_clock_init(0);
 706         shmobile_earlytimer_init();
 707 }
 708
 709 void __init r8a7740_add_early_devices(void)
 710 {
 711         early_platform_add_devices(r8a7740_early_devices,
 712                                    ARRAY_SIZE(r8a7740_early_devices));
 713
 714         /* setup early console here as well */
 715         shmobile_setup_console();
 716
 717         /* override timer setup with soc-specific code */
 718         shmobile_timer.init = r8a7740_earlytimer_init;
 719 }
 720
 721 #ifdef CONFIG_USE_OF
 722
 723 void __init r8a7740_add_early_devices_dt(void)
 724 {
 725         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 726
 727         early_platform_add_devices(r8a7740_early_devices,
 728                                    ARRAY_SIZE(r8a7740_early_devices));
 729
 730         /* setup early console here as well */
 731         shmobile_setup_console();
 732 }
 733
 734 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
 735         { }
 736 };
 737
 738 void __init r8a7740_add_standard_devices_dt(void)
 739 {
 740         /* clocks are setup late during boot in the case of DT */
 741         r8a7740_clock_init(0);
 742
 743         platform_add_devices(r8a7740_early_devices,
 744                             ARRAY_SIZE(r8a7740_early_devices));
 745
 746         of_platform_populate(NULL, of_default_bus_match_table,
 747                              r8a7740_auxdata_lookup, NULL);
 748 }
 749
 750 static const char *r8a7740_boards_compat_dt[] __initdata = {
 751         "renesas,r8a7740",
 752         NULL,
 753 };
 754
 755 DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
 756         .map_io         = r8a7740_map_io,
 757         .init_early     = r8a7740_add_early_devices_dt,
 758         .init_irq       = r8a7740_init_irq,
 759         .handle_irq     = shmobile_handle_irq_intc,
 760         .init_machine   = r8a7740_add_standard_devices_dt,
 761         .timer          = &shmobile_timer,
 762         .dt_compat      = r8a7740_boards_compat_dt,
 763 MACHINE_END
 764
 765 #endif /* CONFIG_USE_OF */