arch/arm/mach-shmobile/smp-r8a7779.c

   1 /*
   2  * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <mach/common.h>
  27 #include <mach/r8a7779.h>
  28 #include <asm/smp_plat.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/smp_twd.h>
  31 #include <asm/hardware/gic.h>
  32
  33 #define AVECR IOMEM(0xfe700040)
  34
  35 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
  36         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  37         .chan_bit = 1, /* ARM1 */
  38         .isr_bit = 1, /* ARM1 */
  39 };
  40
  41 static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
  42         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  43         .chan_bit = 2, /* ARM2 */
  44         .isr_bit = 2, /* ARM2 */
  45 };
  46
  47 static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
  48         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
  49         .chan_bit = 3, /* ARM3 */
  50         .isr_bit = 3, /* ARM3 */
  51 };
  52
  53 static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
  54         [1] = &r8a7779_ch_cpu1,
  55         [2] = &r8a7779_ch_cpu2,
  56         [3] = &r8a7779_ch_cpu3,
  57 };
  58
  59 static void __iomem *scu_base_addr(void)
  60 {
  61         return (void __iomem *)0xf0000000;
  62 }
  63
  64 static DEFINE_SPINLOCK(scu_lock);
  65 static unsigned long tmp;
  66
  67 #ifdef CONFIG_HAVE_ARM_TWD
  68 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
  69
  70 void __init r8a7779_register_twd(void)
  71 {
  72         twd_local_timer_register(&twd_local_timer);
  73 }
  74 #endif
  75
  76 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
  77 {
  78         void __iomem *scu_base = scu_base_addr();
  79
  80         spin_lock(&scu_lock);
  81         tmp = __raw_readl(scu_base + 8);
  82         tmp &= ~clr;
  83         tmp |= set;
  84         spin_unlock(&scu_lock);
  85
  86         /* disable cache coherency after releasing the lock */
  87         __raw_writel(tmp, scu_base + 8);
  88 }
  89
  90 unsigned int __init r8a7779_get_core_count(void)
  91 {
  92         void __iomem *scu_base = scu_base_addr();
  93
  94         return scu_get_core_count(scu_base);
  95 }
  96
  97 int r8a7779_platform_cpu_kill(unsigned int cpu)
  98 {
  99         struct r8a7779_pm_ch *ch = NULL;
 100         int ret = -EIO;
 101
 102         cpu = cpu_logical_map(cpu);
 103
 104         /* disable cache coherency */
 105         modify_scu_cpu_psr(3 << (cpu * 8), 0);
 106
 107         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
 108                 ch = r8a7779_ch_cpu[cpu];
 109
 110         if (ch)
 111                 ret = r8a7779_sysc_power_down(ch);
 112
 113         return ret ? ret : 1;
 114 }
 115
 116 void __cpuinit r8a7779_secondary_init(unsigned int cpu)
 117 {
 118         gic_secondary_init(0);
 119 }
 120
 121 int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
 122 {
 123         struct r8a7779_pm_ch *ch = NULL;
 124         int ret = -EIO;
 125
 126         cpu = cpu_logical_map(cpu);
 127
 128         /* enable cache coherency */
 129         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 130
 131         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
 132                 ch = r8a7779_ch_cpu[cpu];
 133
 134         if (ch)
 135                 ret = r8a7779_sysc_power_up(ch);
 136
 137         return ret;
 138 }
 139
 140 void __init r8a7779_smp_prepare_cpus(void)
 141 {
 142         int cpu = cpu_logical_map(0);
 143
 144         scu_enable(scu_base_addr());
 145
 146         /* Map the reset vector (in headsmp.S) */
 147         __raw_writel(__pa(shmobile_secondary_vector), AVECR);
 148
 149         /* enable cache coherency on CPU0 */
 150         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 151
 152         r8a7779_pm_init();
 153
 154         /* power off secondary CPUs */
 155         r8a7779_platform_cpu_kill(1);
 156         r8a7779_platform_cpu_kill(2);
 157         r8a7779_platform_cpu_kill(3);
 158 }