arch/arm/mach-tegra/clock.h

   1 /*
   2  * arch/arm/mach-tegra/include/mach/clock.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #ifndef __MACH_TEGRA_CLOCK_H
  21 #define __MACH_TEGRA_CLOCK_H
  22
  23 #include <linux/clkdev.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26
  27 #include <mach/clk.h>
  28
  29 #define DIV_BUS                 (1 << 0)
  30 #define DIV_U71                 (1 << 1)
  31 #define DIV_U71_FIXED           (1 << 2)
  32 #define DIV_2                   (1 << 3)
  33 #define DIV_U16                 (1 << 4)
  34 #define PLL_FIXED               (1 << 5)
  35 #define PLL_HAS_CPCON           (1 << 6)
  36 #define MUX                     (1 << 7)
  37 #define PLLD                    (1 << 8)
  38 #define PERIPH_NO_RESET         (1 << 9)
  39 #define PERIPH_NO_ENB           (1 << 10)
  40 #define PERIPH_EMC_ENB          (1 << 11)
  41 #define PERIPH_MANUAL_RESET     (1 << 12)
  42 #define PLL_ALT_MISC_REG        (1 << 13)
  43 #define PLLU                    (1 << 14)
  44 #define PLLX                    (1 << 15)
  45 #define MUX_PWM                 (1 << 16)
  46 #define MUX8                    (1 << 17)
  47 #define DIV_U71_UART            (1 << 18)
  48 #define MUX_CLK_OUT             (1 << 19)
  49 #define PLLM                    (1 << 20)
  50 #define DIV_U71_INT             (1 << 21)
  51 #define DIV_U71_IDLE            (1 << 22)
  52 #define ENABLE_ON_INIT          (1 << 28)
  53 #define PERIPH_ON_APB           (1 << 29)
  54
  55 struct clk;
  56
  57 struct clk_mux_sel {
  58         struct clk      *input;
  59         u32             value;
  60 };
  61
  62 struct clk_pll_freq_table {
  63         unsigned long   input_rate;
  64         unsigned long   output_rate;
  65         u16             n;
  66         u16             m;
  67         u8              p;
  68         u8              cpcon;
  69 };
  70
  71 struct clk_ops {
  72         void            (*init)(struct clk *);
  73         int             (*enable)(struct clk *);
  74         void            (*disable)(struct clk *);
  75         int             (*set_parent)(struct clk *, struct clk *);
  76         int             (*set_rate)(struct clk *, unsigned long);
  77         long            (*round_rate)(struct clk *, unsigned long);
  78         void            (*reset)(struct clk *, bool);
  79         int             (*clk_cfg_ex)(struct clk *,
  80                                 enum tegra_clk_ex_param, u32);
  81 };
  82
  83 enum clk_state {
  84         UNINITIALIZED = 0,
  85         ON,
  86         OFF,
  87 };
  88
  89 struct clk {
  90         /* node for master clocks list */
  91         struct list_head        node;           /* node for list of all clocks */
  92         struct clk_lookup       lookup;
  93
  94 #ifdef CONFIG_DEBUG_FS
  95         struct dentry           *dent;
  96 #endif
  97         bool                    set;
  98         struct clk_ops          *ops;
  99         unsigned long           rate;
 100         unsigned long           max_rate;
 101         unsigned long           min_rate;
 102         u32                     flags;
 103         const char              *name;
 104
 105         u32                     refcnt;
 106         enum clk_state          state;
 107         struct clk              *parent;
 108         u32                     div;
 109         u32                     mul;
 110
 111         const struct clk_mux_sel        *inputs;
 112         u32                             reg;
 113         u32                             reg_shift;
 114
 115         struct list_head                shared_bus_list;
 116
 117         union {
 118                 struct {
 119                         unsigned int                    clk_num;
 120                 } periph;
 121                 struct {
 122                         unsigned long                   input_min;
 123                         unsigned long                   input_max;
 124                         unsigned long                   cf_min;
 125                         unsigned long                   cf_max;
 126                         unsigned long                   vco_min;
 127                         unsigned long                   vco_max;
 128                         const struct clk_pll_freq_table *freq_table;
 129                         int                             lock_delay;
 130                         unsigned long                   fixed_rate;
 131                 } pll;
 132                 struct {
 133                         u32                             sel;
 134                         u32                             reg_mask;
 135                 } mux;
 136                 struct {
 137                         struct clk                      *main;
 138                         struct clk                      *backup;
 139                 } cpu;
 140                 struct {
 141                         struct list_head                node;
 142                         bool                            enabled;
 143                         unsigned long                   rate;
 144                 } shared_bus_user;
 145         } u;
 146
 147         spinlock_t spinlock;
 148 };
 149
 150 struct clk_duplicate {
 151         const char *name;
 152         struct clk_lookup lookup;
 153 };
 154
 155 struct tegra_clk_init_table {
 156         const char *name;
 157         const char *parent;
 158         unsigned long rate;
 159         bool enabled;
 160 };
 161
 162 void tegra2_init_clocks(void);
 163 void tegra30_init_clocks(void);
 164 void clk_init(struct clk *clk);
 165 struct clk *tegra_get_clock_by_name(const char *name);
 166 int clk_reparent(struct clk *c, struct clk *parent);
 167 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 168 unsigned long clk_get_rate_locked(struct clk *c);
 169 int clk_set_rate_locked(struct clk *c, unsigned long rate);
 170
 171 #endif