arch/arm/mach-tegra/include/mach/smmu.h

   1 /*
   2  * IOMMU API for SMMU in Tegra30
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #ifndef MACH_SMMU_H
  21 #define MACH_SMMU_H
  22
  23 enum smmu_hwgrp {
  24         HWGRP_AFI,
  25         HWGRP_AVPC,
  26         HWGRP_DC,
  27         HWGRP_DCB,
  28         HWGRP_EPP,
  29         HWGRP_G2,
  30         HWGRP_HC,
  31         HWGRP_HDA,
  32         HWGRP_ISP,
  33         HWGRP_MPE,
  34         HWGRP_NV,
  35         HWGRP_NV2,
  36         HWGRP_PPCS,
  37         HWGRP_SATA,
  38         HWGRP_VDE,
  39         HWGRP_VI,
  40
  41         HWGRP_COUNT,
  42
  43         HWGRP_END = ~0,
  44 };
  45
  46 #define HWG_AFI         (1 << HWGRP_AFI)
  47 #define HWG_AVPC        (1 << HWGRP_AVPC)
  48 #define HWG_DC          (1 << HWGRP_DC)
  49 #define HWG_DCB         (1 << HWGRP_DCB)
  50 #define HWG_EPP         (1 << HWGRP_EPP)
  51 #define HWG_G2          (1 << HWGRP_G2)
  52 #define HWG_HC          (1 << HWGRP_HC)
  53 #define HWG_HDA         (1 << HWGRP_HDA)
  54 #define HWG_ISP         (1 << HWGRP_ISP)
  55 #define HWG_MPE         (1 << HWGRP_MPE)
  56 #define HWG_NV          (1 << HWGRP_NV)
  57 #define HWG_NV2         (1 << HWGRP_NV2)
  58 #define HWG_PPCS        (1 << HWGRP_PPCS)
  59 #define HWG_SATA        (1 << HWGRP_SATA)
  60 #define HWG_VDE         (1 << HWGRP_VDE)
  61 #define HWG_VI          (1 << HWGRP_VI)
  62
  63 #endif  /* MACH_SMMU_H */