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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / arm / mach-tegra / tegra2_clocks.c
bloba703844b20612c5231fa580bbf3681fb1640c1fb
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34 #include "tegra2_emc.h"
35
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
40
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
45
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
48
49 #define OSC_CTRL 0x50
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
59
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73 #define PERIPH_CLK_SOURCE_PWM_SHIFT 28
74 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
75 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
76 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
77 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78
79 #define SDMMC_CLK_INT_FB_SEL (1 << 23)
80 #define SDMMC_CLK_INT_FB_DLY_SHIFT 16
81 #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82
83 #define PLL_BASE 0x0
84 #define PLL_BASE_BYPASS (1<<31)
85 #define PLL_BASE_ENABLE (1<<30)
86 #define PLL_BASE_REF_ENABLE (1<<29)
87 #define PLL_BASE_OVERRIDE (1<<28)
88 #define PLL_BASE_DIVP_MASK (0x7<<20)
89 #define PLL_BASE_DIVP_SHIFT 20
90 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
91 #define PLL_BASE_DIVN_SHIFT 8
92 #define PLL_BASE_DIVM_MASK (0x1F)
93 #define PLL_BASE_DIVM_SHIFT 0
94
95 #define PLL_OUT_RATIO_MASK (0xFF<<8)
96 #define PLL_OUT_RATIO_SHIFT 8
97 #define PLL_OUT_OVERRIDE (1<<2)
98 #define PLL_OUT_CLKEN (1<<1)
99 #define PLL_OUT_RESET_DISABLE (1<<0)
100
101 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102
103 #define PLL_MISC_DCCON_SHIFT 20
104 #define PLL_MISC_CPCON_SHIFT 8
105 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
106 #define PLL_MISC_LFCON_SHIFT 4
107 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
108 #define PLL_MISC_VCOCON_SHIFT 0
109 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
110
111 #define PLLU_BASE_POST_DIV (1<<20)
112
113 #define PLLD_MISC_CLKENABLE (1<<30)
114 #define PLLD_MISC_DIV_RST (1<<23)
115 #define PLLD_MISC_DCCON_SHIFT 12
116
117 #define PLLE_MISC_READY (1 << 15)
118
119 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
120 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
121 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
122
123 #define SUPER_CLK_MUX 0x00
124 #define SUPER_STATE_SHIFT 28
125 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
127 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
128 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
129 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
130 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
131 #define SUPER_SOURCE_MASK 0xF
132 #define SUPER_FIQ_SOURCE_SHIFT 12
133 #define SUPER_IRQ_SOURCE_SHIFT 8
134 #define SUPER_RUN_SOURCE_SHIFT 4
135 #define SUPER_IDLE_SOURCE_SHIFT 0
136
137 #define SUPER_CLK_DIVIDER 0x04
138
139 #define BUS_CLK_DISABLE (1<<3)
140 #define BUS_CLK_DIV_MASK 0x3
141
142 #define PMC_CTRL 0x0
143 #define PMC_CTRL_BLINK_ENB (1 << 7)
144
145 #define PMC_DPD_PADS_ORIDE 0x1c
146 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
147
148 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
149 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
150 #define PMC_BLINK_TIMER_ENB (1 << 15)
151 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
152 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
153
154 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
155 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
156
157 /*
158 * Some clocks share a register with other clocks. Any clock op that
159 * non-atomically modifies a register used by another clock must lock
160 * clock_register_lock first.
161 */
162 static DEFINE_SPINLOCK(clock_register_lock);
163
164 /*
165 * Some peripheral clocks share an enable bit, so refcount the enable bits
166 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
167 */
168 static int tegra_periph_clk_enable_refcount[3 * 32];
169
170 #define clk_writel(value, reg) \
171 __raw_writel(value, reg_clk_base + (reg))
172 #define clk_readl(reg) \
173 __raw_readl(reg_clk_base + (reg))
174 #define pmc_writel(value, reg) \
175 __raw_writel(value, reg_pmc_base + (reg))
176 #define pmc_readl(reg) \
177 __raw_readl(reg_pmc_base + (reg))
178
179 static unsigned long clk_measure_input_freq(void)
180 {
181 u32 clock_autodetect;
182 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
183 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
184 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
185 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
186 return 12000000;
187 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
188 return 13000000;
189 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
190 return 19200000;
191 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
192 return 26000000;
193 } else {
194 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
195 BUG();
196 return 0;
197 }
198 }
199
200 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
201 {
202 s64 divider_u71 = parent_rate * 2;
203 divider_u71 += rate - 1;
204 do_div(divider_u71, rate);
205
206 if (divider_u71 - 2 < 0)
207 return 0;
208
209 if (divider_u71 - 2 > 255)
210 return -EINVAL;
211
212 return divider_u71 - 2;
213 }
214
215 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
216 {
217 s64 divider_u16;
218
219 divider_u16 = parent_rate;
220 divider_u16 += rate - 1;
221 do_div(divider_u16, rate);
222
223 if (divider_u16 - 1 < 0)
224 return 0;
225
226 if (divider_u16 - 1 > 255)
227 return -EINVAL;
228
229 return divider_u16 - 1;
230 }
231
232 /* clk_m functions */
233 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
234 {
235 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
236
237 c->rate = clk_measure_input_freq();
238 switch (c->rate) {
239 case 12000000:
240 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
241 break;
242 case 13000000:
243 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
244 break;
245 case 19200000:
246 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
247 break;
248 case 26000000:
249 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
250 break;
251 default:
252 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
253 BUG();
254 }
255 clk_writel(auto_clock_control, OSC_CTRL);
256 return c->rate;
257 }
258
259 static void tegra2_clk_m_init(struct clk *c)
260 {
261 pr_debug("%s on clock %s\n", __func__, c->name);
262 tegra2_clk_m_autodetect_rate(c);
263 }
264
265 static int tegra2_clk_m_enable(struct clk *c)
266 {
267 pr_debug("%s on clock %s\n", __func__, c->name);
268 return 0;
269 }
270
271 static void tegra2_clk_m_disable(struct clk *c)
272 {
273 pr_debug("%s on clock %s\n", __func__, c->name);
274 BUG();
275 }
276
277 static struct clk_ops tegra_clk_m_ops = {
278 .init = tegra2_clk_m_init,
279 .enable = tegra2_clk_m_enable,
280 .disable = tegra2_clk_m_disable,
281 };
282
283 /* super clock functions */
284 /* "super clocks" on tegra have two-stage muxes and a clock skipping
285 * super divider. We will ignore the clock skipping divider, since we
286 * can't lower the voltage when using the clock skip, but we can if we
287 * lower the PLL frequency.
288 */
289 static void tegra2_super_clk_init(struct clk *c)
290 {
291 u32 val;
292 int source;
293 int shift;
294 const struct clk_mux_sel *sel;
295 val = clk_readl(c->reg + SUPER_CLK_MUX);
296 c->state = ON;
297 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
298 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
299 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
300 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
301 source = (val >> shift) & SUPER_SOURCE_MASK;
302 for (sel = c->inputs; sel->input != NULL; sel++) {
303 if (sel->value == source)
304 break;
305 }
306 BUG_ON(sel->input == NULL);
307 c->parent = sel->input;
308 }
309
310 static int tegra2_super_clk_enable(struct clk *c)
311 {
312 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
313 return 0;
314 }
315
316 static void tegra2_super_clk_disable(struct clk *c)
317 {
318 pr_debug("%s on clock %s\n", __func__, c->name);
319
320 /* oops - don't disable the CPU clock! */
321 BUG();
322 }
323
324 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
325 {
326 u32 val;
327 const struct clk_mux_sel *sel;
328 int shift;
329
330 val = clk_readl(c->reg + SUPER_CLK_MUX);
331 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
332 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
333 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
334 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
335 for (sel = c->inputs; sel->input != NULL; sel++) {
336 if (sel->input == p) {
337 val &= ~(SUPER_SOURCE_MASK << shift);
338 val |= sel->value << shift;
339
340 if (c->refcnt)
341 clk_enable(p);
342
343 clk_writel(val, c->reg);
344
345 if (c->refcnt && c->parent)
346 clk_disable(c->parent);
347
348 clk_reparent(c, p);
349 return 0;
350 }
351 }
352 return -EINVAL;
353 }
354
355 /*
356 * Super clocks have "clock skippers" instead of dividers. Dividing using
357 * a clock skipper does not allow the voltage to be scaled down, so instead
358 * adjust the rate of the parent clock. This requires that the parent of a
359 * super clock have no other children, otherwise the rate will change
360 * underneath the other children.
361 */
362 static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
363 {
364 return clk_set_rate(c->parent, rate);
365 }
366
367 static struct clk_ops tegra_super_ops = {
368 .init = tegra2_super_clk_init,
369 .enable = tegra2_super_clk_enable,
370 .disable = tegra2_super_clk_disable,
371 .set_parent = tegra2_super_clk_set_parent,
372 .set_rate = tegra2_super_clk_set_rate,
373 };
374
375 /* virtual cpu clock functions */
376 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
377 To change the frequency of these clocks, the parent pll may need to be
378 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
379 and then the clock moved back to the pll. To hide this sequence, a virtual
380 clock handles it.
381 */
382 static void tegra2_cpu_clk_init(struct clk *c)
383 {
384 }
385
386 static int tegra2_cpu_clk_enable(struct clk *c)
387 {
388 return 0;
389 }
390
391 static void tegra2_cpu_clk_disable(struct clk *c)
392 {
393 pr_debug("%s on clock %s\n", __func__, c->name);
394
395 /* oops - don't disable the CPU clock! */
396 BUG();
397 }
398
399 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
400 {
401 int ret;
402 /*
403 * Take an extra reference to the main pll so it doesn't turn
404 * off when we move the cpu off of it
405 */
406 clk_enable(c->u.cpu.main);
407
408 ret = clk_set_parent(c->parent, c->u.cpu.backup);
409 if (ret) {
410 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
411 goto out;
412 }
413
414 if (rate == clk_get_rate(c->u.cpu.backup))
415 goto out;
416
417 ret = clk_set_rate(c->u.cpu.main, rate);
418 if (ret) {
419 pr_err("Failed to change cpu pll to %lu\n", rate);
420 goto out;
421 }
422
423 ret = clk_set_parent(c->parent, c->u.cpu.main);
424 if (ret) {
425 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
426 goto out;
427 }
428
429 out:
430 clk_disable(c->u.cpu.main);
431 return ret;
432 }
433
434 static struct clk_ops tegra_cpu_ops = {
435 .init = tegra2_cpu_clk_init,
436 .enable = tegra2_cpu_clk_enable,
437 .disable = tegra2_cpu_clk_disable,
438 .set_rate = tegra2_cpu_clk_set_rate,
439 };
440
441 /* virtual cop clock functions. Used to acquire the fake 'cop' clock to
442 * reset the COP block (i.e. AVP) */
443 static void tegra2_cop_clk_reset(struct clk *c, bool assert)
444 {
445 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
446
447 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
448 clk_writel(1 << 1, reg);
449 }
450
451 static struct clk_ops tegra_cop_ops = {
452 .reset = tegra2_cop_clk_reset,
453 };
454
455 /* bus clock functions */
456 static void tegra2_bus_clk_init(struct clk *c)
457 {
458 u32 val = clk_readl(c->reg);
459 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
460 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
461 c->mul = 1;
462 }
463
464 static int tegra2_bus_clk_enable(struct clk *c)
465 {
466 u32 val;
467 unsigned long flags;
468
469 spin_lock_irqsave(&clock_register_lock, flags);
470
471 val = clk_readl(c->reg);
472 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
473 clk_writel(val, c->reg);
474
475 spin_unlock_irqrestore(&clock_register_lock, flags);
476
477 return 0;
478 }
479
480 static void tegra2_bus_clk_disable(struct clk *c)
481 {
482 u32 val;
483 unsigned long flags;
484
485 spin_lock_irqsave(&clock_register_lock, flags);
486
487 val = clk_readl(c->reg);
488 val |= BUS_CLK_DISABLE << c->reg_shift;
489 clk_writel(val, c->reg);
490
491 spin_unlock_irqrestore(&clock_register_lock, flags);
492 }
493
494 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
495 {
496 u32 val;
497 unsigned long parent_rate = clk_get_rate(c->parent);
498 unsigned long flags;
499 int ret = -EINVAL;
500 int i;
501
502 spin_lock_irqsave(&clock_register_lock, flags);
503
504 val = clk_readl(c->reg);
505 for (i = 1; i <= 4; i++) {
506 if (rate == parent_rate / i) {
507 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
508 val |= (i - 1) << c->reg_shift;
509 clk_writel(val, c->reg);
510 c->div = i;
511 c->mul = 1;
512 ret = 0;
513 break;
514 }
515 }
516
517 spin_unlock_irqrestore(&clock_register_lock, flags);
518
519 return ret;
520 }
521
522 static struct clk_ops tegra_bus_ops = {
523 .init = tegra2_bus_clk_init,
524 .enable = tegra2_bus_clk_enable,
525 .disable = tegra2_bus_clk_disable,
526 .set_rate = tegra2_bus_clk_set_rate,
527 };
528
529 /* Blink output functions */
530
531 static void tegra2_blink_clk_init(struct clk *c)
532 {
533 u32 val;
534
535 val = pmc_readl(PMC_CTRL);
536 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
537 c->mul = 1;
538 val = pmc_readl(c->reg);
539
540 if (val & PMC_BLINK_TIMER_ENB) {
541 unsigned int on_off;
542
543 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
544 PMC_BLINK_TIMER_DATA_ON_MASK;
545 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
546 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
547 on_off += val;
548 /* each tick in the blink timer is 4 32KHz clocks */
549 c->div = on_off * 4;
550 } else {
551 c->div = 1;
552 }
553 }
554
555 static int tegra2_blink_clk_enable(struct clk *c)
556 {
557 u32 val;
558
559 val = pmc_readl(PMC_DPD_PADS_ORIDE);
560 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
561
562 val = pmc_readl(PMC_CTRL);
563 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
564
565 return 0;
566 }
567
568 static void tegra2_blink_clk_disable(struct clk *c)
569 {
570 u32 val;
571
572 val = pmc_readl(PMC_CTRL);
573 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
574
575 val = pmc_readl(PMC_DPD_PADS_ORIDE);
576 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
577 }
578
579 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
580 {
581 unsigned long parent_rate = clk_get_rate(c->parent);
582 if (rate >= parent_rate) {
583 c->div = 1;
584 pmc_writel(0, c->reg);
585 } else {
586 unsigned int on_off;
587 u32 val;
588
589 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
590 c->div = on_off * 8;
591
592 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
593 PMC_BLINK_TIMER_DATA_ON_SHIFT;
594 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
595 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
596 val |= on_off;
597 val |= PMC_BLINK_TIMER_ENB;
598 pmc_writel(val, c->reg);
599 }
600
601 return 0;
602 }
603
604 static struct clk_ops tegra_blink_clk_ops = {
605 .init = &tegra2_blink_clk_init,
606 .enable = &tegra2_blink_clk_enable,
607 .disable = &tegra2_blink_clk_disable,
608 .set_rate = &tegra2_blink_clk_set_rate,
609 };
610
611 /* PLL Functions */
612 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
613 {
614 udelay(c->u.pll.lock_delay);
615
616 return 0;
617 }
618
619 static void tegra2_pll_clk_init(struct clk *c)
620 {
621 u32 val = clk_readl(c->reg + PLL_BASE);
622
623 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
624
625 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
626 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
627 c->mul = 1;
628 c->div = 1;
629 } else if (val & PLL_BASE_BYPASS) {
630 c->mul = 1;
631 c->div = 1;
632 } else {
633 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
634 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
635 if (c->flags & PLLU)
636 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
637 else
638 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
639 }
640 }
641
642 static int tegra2_pll_clk_enable(struct clk *c)
643 {
644 u32 val;
645 pr_debug("%s on clock %s\n", __func__, c->name);
646
647 val = clk_readl(c->reg + PLL_BASE);
648 val &= ~PLL_BASE_BYPASS;
649 val |= PLL_BASE_ENABLE;
650 clk_writel(val, c->reg + PLL_BASE);
651
652 tegra2_pll_clk_wait_for_lock(c);
653
654 return 0;
655 }
656
657 static void tegra2_pll_clk_disable(struct clk *c)
658 {
659 u32 val;
660 pr_debug("%s on clock %s\n", __func__, c->name);
661
662 val = clk_readl(c->reg);
663 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
664 clk_writel(val, c->reg);
665 }
666
667 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
668 {
669 u32 val;
670 unsigned long input_rate;
671 const struct clk_pll_freq_table *sel;
672
673 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
674
675 input_rate = clk_get_rate(c->parent);
676 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
677 if (sel->input_rate == input_rate && sel->output_rate == rate) {
678 c->mul = sel->n;
679 c->div = sel->m * sel->p;
680
681 val = clk_readl(c->reg + PLL_BASE);
682 if (c->flags & PLL_FIXED)
683 val |= PLL_BASE_OVERRIDE;
684 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
685 PLL_BASE_DIVM_MASK);
686 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
687 (sel->n << PLL_BASE_DIVN_SHIFT);
688 BUG_ON(sel->p < 1 || sel->p > 2);
689 if (c->flags & PLLU) {
690 if (sel->p == 1)
691 val |= PLLU_BASE_POST_DIV;
692 } else {
693 if (sel->p == 2)
694 val |= 1 << PLL_BASE_DIVP_SHIFT;
695 }
696 clk_writel(val, c->reg + PLL_BASE);
697
698 if (c->flags & PLL_HAS_CPCON) {
699 val = clk_readl(c->reg + PLL_MISC(c));
700 val &= ~PLL_MISC_CPCON_MASK;
701 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
702 clk_writel(val, c->reg + PLL_MISC(c));
703 }
704
705 if (c->state == ON)
706 tegra2_pll_clk_enable(c);
707
708 return 0;
709 }
710 }
711 return -EINVAL;
712 }
713
714 static struct clk_ops tegra_pll_ops = {
715 .init = tegra2_pll_clk_init,
716 .enable = tegra2_pll_clk_enable,
717 .disable = tegra2_pll_clk_disable,
718 .set_rate = tegra2_pll_clk_set_rate,
719 };
720
721 static void tegra2_pllx_clk_init(struct clk *c)
722 {
723 tegra2_pll_clk_init(c);
724
725 if (tegra_sku_id == 7)
726 c->max_rate = 750000000;
727 }
728
729 static struct clk_ops tegra_pllx_ops = {
730 .init = tegra2_pllx_clk_init,
731 .enable = tegra2_pll_clk_enable,
732 .disable = tegra2_pll_clk_disable,
733 .set_rate = tegra2_pll_clk_set_rate,
734 };
735
736 static int tegra2_plle_clk_enable(struct clk *c)
737 {
738 u32 val;
739
740 pr_debug("%s on clock %s\n", __func__, c->name);
741
742 mdelay(1);
743
744 val = clk_readl(c->reg + PLL_BASE);
745 if (!(val & PLLE_MISC_READY))
746 return -EBUSY;
747
748 val = clk_readl(c->reg + PLL_BASE);
749 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
750 clk_writel(val, c->reg + PLL_BASE);
751
752 return 0;
753 }
754
755 static struct clk_ops tegra_plle_ops = {
756 .init = tegra2_pll_clk_init,
757 .enable = tegra2_plle_clk_enable,
758 .set_rate = tegra2_pll_clk_set_rate,
759 };
760
761 /* Clock divider ops */
762 static void tegra2_pll_div_clk_init(struct clk *c)
763 {
764 u32 val = clk_readl(c->reg);
765 u32 divu71;
766 val >>= c->reg_shift;
767 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
768 if (!(val & PLL_OUT_RESET_DISABLE))
769 c->state = OFF;
770
771 if (c->flags & DIV_U71) {
772 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
773 c->div = (divu71 + 2);
774 c->mul = 2;
775 } else if (c->flags & DIV_2) {
776 c->div = 2;
777 c->mul = 1;
778 } else {
779 c->div = 1;
780 c->mul = 1;
781 }
782 }
783
784 static int tegra2_pll_div_clk_enable(struct clk *c)
785 {
786 u32 val;
787 u32 new_val;
788 unsigned long flags;
789
790 pr_debug("%s: %s\n", __func__, c->name);
791 if (c->flags & DIV_U71) {
792 spin_lock_irqsave(&clock_register_lock, flags);
793 val = clk_readl(c->reg);
794 new_val = val >> c->reg_shift;
795 new_val &= 0xFFFF;
796
797 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
798
799 val &= ~(0xFFFF << c->reg_shift);
800 val |= new_val << c->reg_shift;
801 clk_writel(val, c->reg);
802 spin_unlock_irqrestore(&clock_register_lock, flags);
803 return 0;
804 } else if (c->flags & DIV_2) {
805 BUG_ON(!(c->flags & PLLD));
806 spin_lock_irqsave(&clock_register_lock, flags);
807 val = clk_readl(c->reg);
808 val &= ~PLLD_MISC_DIV_RST;
809 clk_writel(val, c->reg);
810 spin_unlock_irqrestore(&clock_register_lock, flags);
811 return 0;
812 }
813 return -EINVAL;
814 }
815
816 static void tegra2_pll_div_clk_disable(struct clk *c)
817 {
818 u32 val;
819 u32 new_val;
820 unsigned long flags;
821
822 pr_debug("%s: %s\n", __func__, c->name);
823 if (c->flags & DIV_U71) {
824 spin_lock_irqsave(&clock_register_lock, flags);
825 val = clk_readl(c->reg);
826 new_val = val >> c->reg_shift;
827 new_val &= 0xFFFF;
828
829 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
830
831 val &= ~(0xFFFF << c->reg_shift);
832 val |= new_val << c->reg_shift;
833 clk_writel(val, c->reg);
834 spin_unlock_irqrestore(&clock_register_lock, flags);
835 } else if (c->flags & DIV_2) {
836 BUG_ON(!(c->flags & PLLD));
837 spin_lock_irqsave(&clock_register_lock, flags);
838 val = clk_readl(c->reg);
839 val |= PLLD_MISC_DIV_RST;
840 clk_writel(val, c->reg);
841 spin_unlock_irqrestore(&clock_register_lock, flags);
842 }
843 }
844
845 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
846 {
847 u32 val;
848 u32 new_val;
849 int divider_u71;
850 unsigned long parent_rate = clk_get_rate(c->parent);
851 unsigned long flags;
852
853 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
854 if (c->flags & DIV_U71) {
855 divider_u71 = clk_div71_get_divider(parent_rate, rate);
856 if (divider_u71 >= 0) {
857 spin_lock_irqsave(&clock_register_lock, flags);
858 val = clk_readl(c->reg);
859 new_val = val >> c->reg_shift;
860 new_val &= 0xFFFF;
861 if (c->flags & DIV_U71_FIXED)
862 new_val |= PLL_OUT_OVERRIDE;
863 new_val &= ~PLL_OUT_RATIO_MASK;
864 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
865
866 val &= ~(0xFFFF << c->reg_shift);
867 val |= new_val << c->reg_shift;
868 clk_writel(val, c->reg);
869 c->div = divider_u71 + 2;
870 c->mul = 2;
871 spin_unlock_irqrestore(&clock_register_lock, flags);
872 return 0;
873 }
874 } else if (c->flags & DIV_2) {
875 if (parent_rate == rate * 2)
876 return 0;
877 }
878 return -EINVAL;
879 }
880
881 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
882 {
883 int divider;
884 unsigned long parent_rate = clk_get_rate(c->parent);
885 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
886
887 if (c->flags & DIV_U71) {
888 divider = clk_div71_get_divider(parent_rate, rate);
889 if (divider < 0)
890 return divider;
891 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
892 } else if (c->flags & DIV_2) {
893 return DIV_ROUND_UP(parent_rate, 2);
894 }
895 return -EINVAL;
896 }
897
898 static struct clk_ops tegra_pll_div_ops = {
899 .init = tegra2_pll_div_clk_init,
900 .enable = tegra2_pll_div_clk_enable,
901 .disable = tegra2_pll_div_clk_disable,
902 .set_rate = tegra2_pll_div_clk_set_rate,
903 .round_rate = tegra2_pll_div_clk_round_rate,
904 };
905
906 /* Periph clk ops */
907
908 static void tegra2_periph_clk_init(struct clk *c)
909 {
910 u32 val = clk_readl(c->reg);
911 const struct clk_mux_sel *mux = NULL;
912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
924 if (c->flags & MUX) {
925 for (sel = c->inputs; sel->input != NULL; sel++) {
926 if ((val & mask) >> shift == sel->value)
927 mux = sel;
928 }
929 BUG_ON(!mux);
930
931 c->parent = mux->input;
932 } else {
933 c->parent = c->inputs[0].input;
934 }
935
936 if (c->flags & DIV_U71) {
937 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
938 c->div = divu71 + 2;
939 c->mul = 2;
940 } else if (c->flags & DIV_U16) {
941 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
942 c->div = divu16 + 1;
943 c->mul = 1;
944 } else {
945 c->div = 1;
946 c->mul = 1;
947 }
948
949 c->state = ON;
950
951 if (!c->u.periph.clk_num)
952 return;
953
954 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
955 PERIPH_CLK_TO_ENB_BIT(c)))
956 c->state = OFF;
957
958 if (!(c->flags & PERIPH_NO_RESET))
959 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
960 PERIPH_CLK_TO_ENB_BIT(c))
961 c->state = OFF;
962 }
963
964 static int tegra2_periph_clk_enable(struct clk *c)
965 {
966 u32 val;
967 unsigned long flags;
968 int refcount;
969 pr_debug("%s on clock %s\n", __func__, c->name);
970
971 if (!c->u.periph.clk_num)
972 return 0;
973
974 spin_lock_irqsave(&clock_register_lock, flags);
975
976 refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
977
978 if (refcount > 1)
979 goto out;
980
981 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
982 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
983 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
984 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
985 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
986 if (c->flags & PERIPH_EMC_ENB) {
987 /* The EMC peripheral clock has 2 extra enable bits */
988 /* FIXME: Do they need to be disabled? */
989 val = clk_readl(c->reg);
990 val |= 0x3 << 24;
991 clk_writel(val, c->reg);
992 }
993
994 out:
995 spin_unlock_irqrestore(&clock_register_lock, flags);
996
997 return 0;
998 }
999
1000 static void tegra2_periph_clk_disable(struct clk *c)
1001 {
1002 unsigned long flags;
1003
1004 pr_debug("%s on clock %s\n", __func__, c->name);
1005
1006 if (!c->u.periph.clk_num)
1007 return;
1008
1009 spin_lock_irqsave(&clock_register_lock, flags);
1010
1011 if (c->refcnt)
1012 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1013
1014 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
1015 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1016 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1017
1018 spin_unlock_irqrestore(&clock_register_lock, flags);
1019 }
1020
1021 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
1022 {
1023 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1024
1025 pr_debug("%s %s on clock %s\n", __func__,
1026 assert ? "assert" : "deassert", c->name);
1027
1028 BUG_ON(!c->u.periph.clk_num);
1029
1030 if (!(c->flags & PERIPH_NO_RESET))
1031 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1032 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1033 }
1034
1035 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1036 {
1037 u32 val;
1038 const struct clk_mux_sel *sel;
1039 u32 mask, shift;
1040
1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1042
1043 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1045 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1046 } else {
1047 shift = PERIPH_CLK_SOURCE_SHIFT;
1048 mask = PERIPH_CLK_SOURCE_MASK;
1049 }
1050
1051 for (sel = c->inputs; sel->input != NULL; sel++) {
1052 if (sel->input == p) {
1053 val = clk_readl(c->reg);
1054 val &= ~mask;
1055 val |= (sel->value) << shift;
1056
1057 if (c->refcnt)
1058 clk_enable(p);
1059
1060 clk_writel(val, c->reg);
1061
1062 if (c->refcnt && c->parent)
1063 clk_disable(c->parent);
1064
1065 clk_reparent(c, p);
1066 return 0;
1067 }
1068 }
1069
1070 return -EINVAL;
1071 }
1072
1073 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
1074 {
1075 u32 val;
1076 int divider;
1077 unsigned long parent_rate = clk_get_rate(c->parent);
1078
1079 if (c->flags & DIV_U71) {
1080 divider = clk_div71_get_divider(parent_rate, rate);
1081 if (divider >= 0) {
1082 val = clk_readl(c->reg);
1083 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1084 val |= divider;
1085 clk_writel(val, c->reg);
1086 c->div = divider + 2;
1087 c->mul = 2;
1088 return 0;
1089 }
1090 } else if (c->flags & DIV_U16) {
1091 divider = clk_div16_get_divider(parent_rate, rate);
1092 if (divider >= 0) {
1093 val = clk_readl(c->reg);
1094 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1095 val |= divider;
1096 clk_writel(val, c->reg);
1097 c->div = divider + 1;
1098 c->mul = 1;
1099 return 0;
1100 }
1101 } else if (parent_rate <= rate) {
1102 c->div = 1;
1103 c->mul = 1;
1104 return 0;
1105 }
1106 return -EINVAL;
1107 }
1108
1109 static long tegra2_periph_clk_round_rate(struct clk *c,
1110 unsigned long rate)
1111 {
1112 int divider;
1113 unsigned long parent_rate = clk_get_rate(c->parent);
1114 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1115
1116 if (c->flags & DIV_U71) {
1117 divider = clk_div71_get_divider(parent_rate, rate);
1118 if (divider < 0)
1119 return divider;
1120
1121 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1122 } else if (c->flags & DIV_U16) {
1123 divider = clk_div16_get_divider(parent_rate, rate);
1124 if (divider < 0)
1125 return divider;
1126 return DIV_ROUND_UP(parent_rate, divider + 1);
1127 }
1128 return -EINVAL;
1129 }
1130
1131 static struct clk_ops tegra_periph_clk_ops = {
1132 .init = &tegra2_periph_clk_init,
1133 .enable = &tegra2_periph_clk_enable,
1134 .disable = &tegra2_periph_clk_disable,
1135 .set_parent = &tegra2_periph_clk_set_parent,
1136 .set_rate = &tegra2_periph_clk_set_rate,
1137 .round_rate = &tegra2_periph_clk_round_rate,
1138 .reset = &tegra2_periph_clk_reset,
1139 };
1140
1141 /* The SDMMC controllers have extra bits in the clock source register that
1142 * adjust the delay between the clock and data to compenstate for delays
1143 * on the PCB. */
1144 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1145 {
1146 u32 reg;
1147 unsigned long flags;
1148
1149 spin_lock_irqsave(&c->spinlock, flags);
1150
1151 delay = clamp(delay, 0, 15);
1152 reg = clk_readl(c->reg);
1153 reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
1154 reg |= SDMMC_CLK_INT_FB_SEL;
1155 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1156 clk_writel(reg, c->reg);
1157
1158 spin_unlock_irqrestore(&c->spinlock, flags);
1159 }
1160
1161 /* External memory controller clock ops */
1162 static void tegra2_emc_clk_init(struct clk *c)
1163 {
1164 tegra2_periph_clk_init(c);
1165 c->max_rate = clk_get_rate_locked(c);
1166 }
1167
1168 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
1169 {
1170 long emc_rate;
1171 long clk_rate;
1172
1173 /*
1174 * The slowest entry in the EMC clock table that is at least as
1175 * fast as rate.
1176 */
1177 emc_rate = tegra_emc_round_rate(rate);
1178 if (emc_rate < 0)
1179 return c->max_rate;
1180
1181 /*
1182 * The fastest rate the PLL will generate that is at most the
1183 * requested rate.
1184 */
1185 clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
1186
1187 /*
1188 * If this fails, and emc_rate > clk_rate, it's because the maximum
1189 * rate in the EMC tables is larger than the maximum rate of the EMC
1190 * clock. The EMC clock's max rate is the rate it was running when the
1191 * kernel booted. Such a mismatch is probably due to using the wrong
1192 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1193 */
1194 WARN_ONCE(emc_rate != clk_rate,
1195 "emc_rate %ld != clk_rate %ld",
1196 emc_rate, clk_rate);
1197
1198 return emc_rate;
1199 }
1200
1201 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
1202 {
1203 int ret;
1204 /*
1205 * The Tegra2 memory controller has an interlock with the clock
1206 * block that allows memory shadowed registers to be updated,
1207 * and then transfer them to the main registers at the same
1208 * time as the clock update without glitches.
1209 */
1210 ret = tegra_emc_set_rate(rate);
1211 if (ret < 0)
1212 return ret;
1213
1214 ret = tegra2_periph_clk_set_rate(c, rate);
1215 udelay(1);
1216
1217 return ret;
1218 }
1219
1220 static struct clk_ops tegra_emc_clk_ops = {
1221 .init = &tegra2_emc_clk_init,
1222 .enable = &tegra2_periph_clk_enable,
1223 .disable = &tegra2_periph_clk_disable,
1224 .set_parent = &tegra2_periph_clk_set_parent,
1225 .set_rate = &tegra2_emc_clk_set_rate,
1226 .round_rate = &tegra2_emc_clk_round_rate,
1227 .reset = &tegra2_periph_clk_reset,
1228 };
1229
1230 /* Clock doubler ops */
1231 static void tegra2_clk_double_init(struct clk *c)
1232 {
1233 c->mul = 2;
1234 c->div = 1;
1235 c->state = ON;
1236
1237 if (!c->u.periph.clk_num)
1238 return;
1239
1240 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1241 PERIPH_CLK_TO_ENB_BIT(c)))
1242 c->state = OFF;
1243 };
1244
1245 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1246 {
1247 if (rate != 2 * clk_get_rate(c->parent))
1248 return -EINVAL;
1249 c->mul = 2;
1250 c->div = 1;
1251 return 0;
1252 }
1253
1254 static struct clk_ops tegra_clk_double_ops = {
1255 .init = &tegra2_clk_double_init,
1256 .enable = &tegra2_periph_clk_enable,
1257 .disable = &tegra2_periph_clk_disable,
1258 .set_rate = &tegra2_clk_double_set_rate,
1259 };
1260
1261 /* Audio sync clock ops */
1262 static void tegra2_audio_sync_clk_init(struct clk *c)
1263 {
1264 int source;
1265 const struct clk_mux_sel *sel;
1266 u32 val = clk_readl(c->reg);
1267 c->state = (val & (1<<4)) ? OFF : ON;
1268 source = val & 0xf;
1269 for (sel = c->inputs; sel->input != NULL; sel++)
1270 if (sel->value == source)
1271 break;
1272 BUG_ON(sel->input == NULL);
1273 c->parent = sel->input;
1274 }
1275
1276 static int tegra2_audio_sync_clk_enable(struct clk *c)
1277 {
1278 clk_writel(0, c->reg);
1279 return 0;
1280 }
1281
1282 static void tegra2_audio_sync_clk_disable(struct clk *c)
1283 {
1284 clk_writel(1, c->reg);
1285 }
1286
1287 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1288 {
1289 u32 val;
1290 const struct clk_mux_sel *sel;
1291 for (sel = c->inputs; sel->input != NULL; sel++) {
1292 if (sel->input == p) {
1293 val = clk_readl(c->reg);
1294 val &= ~0xf;
1295 val |= sel->value;
1296
1297 if (c->refcnt)
1298 clk_enable(p);
1299
1300 clk_writel(val, c->reg);
1301
1302 if (c->refcnt && c->parent)
1303 clk_disable(c->parent);
1304
1305 clk_reparent(c, p);
1306 return 0;
1307 }
1308 }
1309
1310 return -EINVAL;
1311 }
1312
1313 static struct clk_ops tegra_audio_sync_clk_ops = {
1314 .init = tegra2_audio_sync_clk_init,
1315 .enable = tegra2_audio_sync_clk_enable,
1316 .disable = tegra2_audio_sync_clk_disable,
1317 .set_parent = tegra2_audio_sync_clk_set_parent,
1318 };
1319
1320 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1321
1322 static void tegra2_cdev_clk_init(struct clk *c)
1323 {
1324 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1325 * currently done in the pinmux code. */
1326 c->state = ON;
1327
1328 BUG_ON(!c->u.periph.clk_num);
1329
1330 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1331 PERIPH_CLK_TO_ENB_BIT(c)))
1332 c->state = OFF;
1333 }
1334
1335 static int tegra2_cdev_clk_enable(struct clk *c)
1336 {
1337 BUG_ON(!c->u.periph.clk_num);
1338
1339 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1340 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1341 return 0;
1342 }
1343
1344 static void tegra2_cdev_clk_disable(struct clk *c)
1345 {
1346 BUG_ON(!c->u.periph.clk_num);
1347
1348 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1349 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1350 }
1351
1352 static struct clk_ops tegra_cdev_clk_ops = {
1353 .init = &tegra2_cdev_clk_init,
1354 .enable = &tegra2_cdev_clk_enable,
1355 .disable = &tegra2_cdev_clk_disable,
1356 };
1357
1358 /* shared bus ops */
1359 /*
1360 * Some clocks may have multiple downstream users that need to request a
1361 * higher clock rate. Shared bus clocks provide a unique shared_bus_user
1362 * clock to each user. The frequency of the bus is set to the highest
1363 * enabled shared_bus_user clock, with a minimum value set by the
1364 * shared bus.
1365 */
1366 static int tegra_clk_shared_bus_update(struct clk *bus)
1367 {
1368 struct clk *c;
1369 unsigned long rate = bus->min_rate;
1370
1371 list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
1372 if (c->u.shared_bus_user.enabled)
1373 rate = max(c->u.shared_bus_user.rate, rate);
1374
1375 if (rate == clk_get_rate_locked(bus))
1376 return 0;
1377
1378 return clk_set_rate_locked(bus, rate);
1379 };
1380
1381 static void tegra_clk_shared_bus_init(struct clk *c)
1382 {
1383 unsigned long flags;
1384
1385 c->max_rate = c->parent->max_rate;
1386 c->u.shared_bus_user.rate = c->parent->max_rate;
1387 c->state = OFF;
1388 c->set = true;
1389
1390 spin_lock_irqsave(&c->parent->spinlock, flags);
1391
1392 list_add_tail(&c->u.shared_bus_user.node,
1393 &c->parent->shared_bus_list);
1394
1395 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1396 }
1397
1398 static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
1399 {
1400 unsigned long flags;
1401 int ret;
1402 long new_rate = rate;
1403
1404 new_rate = clk_round_rate(c->parent, new_rate);
1405 if (new_rate < 0)
1406 return new_rate;
1407
1408 spin_lock_irqsave(&c->parent->spinlock, flags);
1409
1410 c->u.shared_bus_user.rate = new_rate;
1411 ret = tegra_clk_shared_bus_update(c->parent);
1412
1413 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1414
1415 return ret;
1416 }
1417
1418 static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
1419 {
1420 return clk_round_rate(c->parent, rate);
1421 }
1422
1423 static int tegra_clk_shared_bus_enable(struct clk *c)
1424 {
1425 unsigned long flags;
1426 int ret;
1427
1428 spin_lock_irqsave(&c->parent->spinlock, flags);
1429
1430 c->u.shared_bus_user.enabled = true;
1431 ret = tegra_clk_shared_bus_update(c->parent);
1432
1433 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1434
1435 return ret;
1436 }
1437
1438 static void tegra_clk_shared_bus_disable(struct clk *c)
1439 {
1440 unsigned long flags;
1441 int ret;
1442
1443 spin_lock_irqsave(&c->parent->spinlock, flags);
1444
1445 c->u.shared_bus_user.enabled = false;
1446 ret = tegra_clk_shared_bus_update(c->parent);
1447 WARN_ON_ONCE(ret);
1448
1449 spin_unlock_irqrestore(&c->parent->spinlock, flags);
1450 }
1451
1452 static struct clk_ops tegra_clk_shared_bus_ops = {
1453 .init = tegra_clk_shared_bus_init,
1454 .enable = tegra_clk_shared_bus_enable,
1455 .disable = tegra_clk_shared_bus_disable,
1456 .set_rate = tegra_clk_shared_bus_set_rate,
1457 .round_rate = tegra_clk_shared_bus_round_rate,
1458 };
1459
1460
1461 /* Clock definitions */
1462 static struct clk tegra_clk_32k = {
1463 .name = "clk_32k",
1464 .rate = 32768,
1465 .ops = NULL,
1466 .max_rate = 32768,
1467 };
1468
1469 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1470 {32768, 12000000, 366, 1, 1, 0},
1471 {32768, 13000000, 397, 1, 1, 0},
1472 {32768, 19200000, 586, 1, 1, 0},
1473 {32768, 26000000, 793, 1, 1, 0},
1474 {0, 0, 0, 0, 0, 0},
1475 };
1476
1477 static struct clk tegra_pll_s = {
1478 .name = "pll_s",
1479 .flags = PLL_ALT_MISC_REG,
1480 .ops = &tegra_pll_ops,
1481 .parent = &tegra_clk_32k,
1482 .max_rate = 26000000,
1483 .reg = 0xf0,
1484 .u.pll = {
1485 .input_min = 32768,
1486 .input_max = 32768,
1487 .cf_min = 0, /* FIXME */
1488 .cf_max = 0, /* FIXME */
1489 .vco_min = 12000000,
1490 .vco_max = 26000000,
1491 .freq_table = tegra_pll_s_freq_table,
1492 .lock_delay = 300,
1493 },
1494 };
1495
1496 static struct clk_mux_sel tegra_clk_m_sel[] = {
1497 { .input = &tegra_clk_32k, .value = 0},
1498 { .input = &tegra_pll_s, .value = 1},
1499 { NULL , 0},
1500 };
1501
1502 static struct clk tegra_clk_m = {
1503 .name = "clk_m",
1504 .flags = ENABLE_ON_INIT,
1505 .ops = &tegra_clk_m_ops,
1506 .inputs = tegra_clk_m_sel,
1507 .reg = 0x1fc,
1508 .reg_shift = 28,
1509 .max_rate = 26000000,
1510 };
1511
1512 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1513 { 12000000, 600000000, 600, 12, 1, 8 },
1514 { 13000000, 600000000, 600, 13, 1, 8 },
1515 { 19200000, 600000000, 500, 16, 1, 6 },
1516 { 26000000, 600000000, 600, 26, 1, 8 },
1517 { 0, 0, 0, 0, 0, 0 },
1518 };
1519
1520 static struct clk tegra_pll_c = {
1521 .name = "pll_c",
1522 .flags = PLL_HAS_CPCON,
1523 .ops = &tegra_pll_ops,
1524 .reg = 0x80,
1525 .parent = &tegra_clk_m,
1526 .max_rate = 600000000,
1527 .u.pll = {
1528 .input_min = 2000000,
1529 .input_max = 31000000,
1530 .cf_min = 1000000,
1531 .cf_max = 6000000,
1532 .vco_min = 20000000,
1533 .vco_max = 1400000000,
1534 .freq_table = tegra_pll_c_freq_table,
1535 .lock_delay = 300,
1536 },
1537 };
1538
1539 static struct clk tegra_pll_c_out1 = {
1540 .name = "pll_c_out1",
1541 .ops = &tegra_pll_div_ops,
1542 .flags = DIV_U71,
1543 .parent = &tegra_pll_c,
1544 .reg = 0x84,
1545 .reg_shift = 0,
1546 .max_rate = 600000000,
1547 };
1548
1549 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1550 { 12000000, 666000000, 666, 12, 1, 8},
1551 { 13000000, 666000000, 666, 13, 1, 8},
1552 { 19200000, 666000000, 555, 16, 1, 8},
1553 { 26000000, 666000000, 666, 26, 1, 8},
1554 { 12000000, 600000000, 600, 12, 1, 8},
1555 { 13000000, 600000000, 600, 13, 1, 8},
1556 { 19200000, 600000000, 375, 12, 1, 6},
1557 { 26000000, 600000000, 600, 26, 1, 8},
1558 { 0, 0, 0, 0, 0, 0 },
1559 };
1560
1561 static struct clk tegra_pll_m = {
1562 .name = "pll_m",
1563 .flags = PLL_HAS_CPCON,
1564 .ops = &tegra_pll_ops,
1565 .reg = 0x90,
1566 .parent = &tegra_clk_m,
1567 .max_rate = 800000000,
1568 .u.pll = {
1569 .input_min = 2000000,
1570 .input_max = 31000000,
1571 .cf_min = 1000000,
1572 .cf_max = 6000000,
1573 .vco_min = 20000000,
1574 .vco_max = 1200000000,
1575 .freq_table = tegra_pll_m_freq_table,
1576 .lock_delay = 300,
1577 },
1578 };
1579
1580 static struct clk tegra_pll_m_out1 = {
1581 .name = "pll_m_out1",
1582 .ops = &tegra_pll_div_ops,
1583 .flags = DIV_U71,
1584 .parent = &tegra_pll_m,
1585 .reg = 0x94,
1586 .reg_shift = 0,
1587 .max_rate = 600000000,
1588 };
1589
1590 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1591 { 12000000, 216000000, 432, 12, 2, 8},
1592 { 13000000, 216000000, 432, 13, 2, 8},
1593 { 19200000, 216000000, 90, 4, 2, 1},
1594 { 26000000, 216000000, 432, 26, 2, 8},
1595 { 12000000, 432000000, 432, 12, 1, 8},
1596 { 13000000, 432000000, 432, 13, 1, 8},
1597 { 19200000, 432000000, 90, 4, 1, 1},
1598 { 26000000, 432000000, 432, 26, 1, 8},
1599 { 0, 0, 0, 0, 0, 0 },
1600 };
1601
1602 static struct clk tegra_pll_p = {
1603 .name = "pll_p",
1604 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1605 .ops = &tegra_pll_ops,
1606 .reg = 0xa0,
1607 .parent = &tegra_clk_m,
1608 .max_rate = 432000000,
1609 .u.pll = {
1610 .input_min = 2000000,
1611 .input_max = 31000000,
1612 .cf_min = 1000000,
1613 .cf_max = 6000000,
1614 .vco_min = 20000000,
1615 .vco_max = 1400000000,
1616 .freq_table = tegra_pll_p_freq_table,
1617 .lock_delay = 300,
1618 },
1619 };
1620
1621 static struct clk tegra_pll_p_out1 = {
1622 .name = "pll_p_out1",
1623 .ops = &tegra_pll_div_ops,
1624 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1625 .parent = &tegra_pll_p,
1626 .reg = 0xa4,
1627 .reg_shift = 0,
1628 .max_rate = 432000000,
1629 };
1630
1631 static struct clk tegra_pll_p_out2 = {
1632 .name = "pll_p_out2",
1633 .ops = &tegra_pll_div_ops,
1634 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1635 .parent = &tegra_pll_p,
1636 .reg = 0xa4,
1637 .reg_shift = 16,
1638 .max_rate = 432000000,
1639 };
1640
1641 static struct clk tegra_pll_p_out3 = {
1642 .name = "pll_p_out3",
1643 .ops = &tegra_pll_div_ops,
1644 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1645 .parent = &tegra_pll_p,
1646 .reg = 0xa8,
1647 .reg_shift = 0,
1648 .max_rate = 432000000,
1649 };
1650
1651 static struct clk tegra_pll_p_out4 = {
1652 .name = "pll_p_out4",
1653 .ops = &tegra_pll_div_ops,
1654 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1655 .parent = &tegra_pll_p,
1656 .reg = 0xa8,
1657 .reg_shift = 16,
1658 .max_rate = 432000000,
1659 };
1660
1661 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1662 { 28800000, 56448000, 49, 25, 1, 1},
1663 { 28800000, 73728000, 64, 25, 1, 1},
1664 { 28800000, 24000000, 5, 6, 1, 1},
1665 { 0, 0, 0, 0, 0, 0 },
1666 };
1667
1668 static struct clk tegra_pll_a = {
1669 .name = "pll_a",
1670 .flags = PLL_HAS_CPCON,
1671 .ops = &tegra_pll_ops,
1672 .reg = 0xb0,
1673 .parent = &tegra_pll_p_out1,
1674 .max_rate = 73728000,
1675 .u.pll = {
1676 .input_min = 2000000,
1677 .input_max = 31000000,
1678 .cf_min = 1000000,
1679 .cf_max = 6000000,
1680 .vco_min = 20000000,
1681 .vco_max = 1400000000,
1682 .freq_table = tegra_pll_a_freq_table,
1683 .lock_delay = 300,
1684 },
1685 };
1686
1687 static struct clk tegra_pll_a_out0 = {
1688 .name = "pll_a_out0",
1689 .ops = &tegra_pll_div_ops,
1690 .flags = DIV_U71,
1691 .parent = &tegra_pll_a,
1692 .reg = 0xb4,
1693 .reg_shift = 0,
1694 .max_rate = 73728000,
1695 };
1696
1697 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1698 { 12000000, 216000000, 216, 12, 1, 4},
1699 { 13000000, 216000000, 216, 13, 1, 4},
1700 { 19200000, 216000000, 135, 12, 1, 3},
1701 { 26000000, 216000000, 216, 26, 1, 4},
1702
1703 { 12000000, 594000000, 594, 12, 1, 8},
1704 { 13000000, 594000000, 594, 13, 1, 8},
1705 { 19200000, 594000000, 495, 16, 1, 8},
1706 { 26000000, 594000000, 594, 26, 1, 8},
1707
1708 { 12000000, 1000000000, 1000, 12, 1, 12},
1709 { 13000000, 1000000000, 1000, 13, 1, 12},
1710 { 19200000, 1000000000, 625, 12, 1, 8},
1711 { 26000000, 1000000000, 1000, 26, 1, 12},
1712
1713 { 0, 0, 0, 0, 0, 0 },
1714 };
1715
1716 static struct clk tegra_pll_d = {
1717 .name = "pll_d",
1718 .flags = PLL_HAS_CPCON | PLLD,
1719 .ops = &tegra_pll_ops,
1720 .reg = 0xd0,
1721 .parent = &tegra_clk_m,
1722 .max_rate = 1000000000,
1723 .u.pll = {
1724 .input_min = 2000000,
1725 .input_max = 40000000,
1726 .cf_min = 1000000,
1727 .cf_max = 6000000,
1728 .vco_min = 40000000,
1729 .vco_max = 1000000000,
1730 .freq_table = tegra_pll_d_freq_table,
1731 .lock_delay = 1000,
1732 },
1733 };
1734
1735 static struct clk tegra_pll_d_out0 = {
1736 .name = "pll_d_out0",
1737 .ops = &tegra_pll_div_ops,
1738 .flags = DIV_2 | PLLD,
1739 .parent = &tegra_pll_d,
1740 .max_rate = 500000000,
1741 };
1742
1743 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1744 { 12000000, 480000000, 960, 12, 2, 0},
1745 { 13000000, 480000000, 960, 13, 2, 0},
1746 { 19200000, 480000000, 200, 4, 2, 0},
1747 { 26000000, 480000000, 960, 26, 2, 0},
1748 { 0, 0, 0, 0, 0, 0 },
1749 };
1750
1751 static struct clk tegra_pll_u = {
1752 .name = "pll_u",
1753 .flags = PLLU,
1754 .ops = &tegra_pll_ops,
1755 .reg = 0xc0,
1756 .parent = &tegra_clk_m,
1757 .max_rate = 480000000,
1758 .u.pll = {
1759 .input_min = 2000000,
1760 .input_max = 40000000,
1761 .cf_min = 1000000,
1762 .cf_max = 6000000,
1763 .vco_min = 480000000,
1764 .vco_max = 960000000,
1765 .freq_table = tegra_pll_u_freq_table,
1766 .lock_delay = 1000,
1767 },
1768 };
1769
1770 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1771 /* 1 GHz */
1772 { 12000000, 1000000000, 1000, 12, 1, 12},
1773 { 13000000, 1000000000, 1000, 13, 1, 12},
1774 { 19200000, 1000000000, 625, 12, 1, 8},
1775 { 26000000, 1000000000, 1000, 26, 1, 12},
1776
1777 /* 912 MHz */
1778 { 12000000, 912000000, 912, 12, 1, 12},
1779 { 13000000, 912000000, 912, 13, 1, 12},
1780 { 19200000, 912000000, 760, 16, 1, 8},
1781 { 26000000, 912000000, 912, 26, 1, 12},
1782
1783 /* 816 MHz */
1784 { 12000000, 816000000, 816, 12, 1, 12},
1785 { 13000000, 816000000, 816, 13, 1, 12},
1786 { 19200000, 816000000, 680, 16, 1, 8},
1787 { 26000000, 816000000, 816, 26, 1, 12},
1788
1789 /* 760 MHz */
1790 { 12000000, 760000000, 760, 12, 1, 12},
1791 { 13000000, 760000000, 760, 13, 1, 12},
1792 { 19200000, 760000000, 950, 24, 1, 8},
1793 { 26000000, 760000000, 760, 26, 1, 12},
1794
1795 /* 750 MHz */
1796 { 12000000, 750000000, 750, 12, 1, 12},
1797 { 13000000, 750000000, 750, 13, 1, 12},
1798 { 19200000, 750000000, 625, 16, 1, 8},
1799 { 26000000, 750000000, 750, 26, 1, 12},
1800
1801 /* 608 MHz */
1802 { 12000000, 608000000, 608, 12, 1, 12},
1803 { 13000000, 608000000, 608, 13, 1, 12},
1804 { 19200000, 608000000, 380, 12, 1, 8},
1805 { 26000000, 608000000, 608, 26, 1, 12},
1806
1807 /* 456 MHz */
1808 { 12000000, 456000000, 456, 12, 1, 12},
1809 { 13000000, 456000000, 456, 13, 1, 12},
1810 { 19200000, 456000000, 380, 16, 1, 8},
1811 { 26000000, 456000000, 456, 26, 1, 12},
1812
1813 /* 312 MHz */
1814 { 12000000, 312000000, 312, 12, 1, 12},
1815 { 13000000, 312000000, 312, 13, 1, 12},
1816 { 19200000, 312000000, 260, 16, 1, 8},
1817 { 26000000, 312000000, 312, 26, 1, 12},
1818
1819 { 0, 0, 0, 0, 0, 0 },
1820 };
1821
1822 static struct clk tegra_pll_x = {
1823 .name = "pll_x",
1824 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1825 .ops = &tegra_pllx_ops,
1826 .reg = 0xe0,
1827 .parent = &tegra_clk_m,
1828 .max_rate = 1000000000,
1829 .u.pll = {
1830 .input_min = 2000000,
1831 .input_max = 31000000,
1832 .cf_min = 1000000,
1833 .cf_max = 6000000,
1834 .vco_min = 20000000,
1835 .vco_max = 1200000000,
1836 .freq_table = tegra_pll_x_freq_table,
1837 .lock_delay = 300,
1838 },
1839 };
1840
1841 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1842 { 12000000, 100000000, 200, 24, 1, 0 },
1843 { 0, 0, 0, 0, 0, 0 },
1844 };
1845
1846 static struct clk tegra_pll_e = {
1847 .name = "pll_e",
1848 .flags = PLL_ALT_MISC_REG,
1849 .ops = &tegra_plle_ops,
1850 .parent = &tegra_clk_m,
1851 .reg = 0xe8,
1852 .max_rate = 100000000,
1853 .u.pll = {
1854 .input_min = 12000000,
1855 .input_max = 12000000,
1856 .freq_table = tegra_pll_e_freq_table,
1857 },
1858 };
1859
1860 static struct clk tegra_clk_d = {
1861 .name = "clk_d",
1862 .flags = PERIPH_NO_RESET,
1863 .ops = &tegra_clk_double_ops,
1864 .reg = 0x34,
1865 .reg_shift = 12,
1866 .parent = &tegra_clk_m,
1867 .max_rate = 52000000,
1868 .u.periph = {
1869 .clk_num = 90,
1870 },
1871 };
1872
1873 /* dap_mclk1, belongs to the cdev1 pingroup. */
1874 static struct clk tegra_clk_cdev1 = {
1875 .name = "cdev1",
1876 .ops = &tegra_cdev_clk_ops,
1877 .rate = 26000000,
1878 .max_rate = 26000000,
1879 .u.periph = {
1880 .clk_num = 94,
1881 },
1882 };
1883
1884 /* dap_mclk2, belongs to the cdev2 pingroup. */
1885 static struct clk tegra_clk_cdev2 = {
1886 .name = "cdev2",
1887 .ops = &tegra_cdev_clk_ops,
1888 .rate = 26000000,
1889 .max_rate = 26000000,
1890 .u.periph = {
1891 .clk_num = 93,
1892 },
1893 };
1894
1895 /* initialized before peripheral clocks */
1896 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1897 static const struct audio_sources {
1898 const char *name;
1899 int value;
1900 } mux_audio_sync_clk_sources[] = {
1901 { .name = "spdif_in", .value = 0 },
1902 { .name = "i2s1", .value = 1 },
1903 { .name = "i2s2", .value = 2 },
1904 { .name = "pll_a_out0", .value = 4 },
1905 #if 0 /* FIXME: not implemented */
1906 { .name = "ac97", .value = 3 },
1907 { .name = "ext_audio_clk2", .value = 5 },
1908 { .name = "ext_audio_clk1", .value = 6 },
1909 { .name = "ext_vimclk", .value = 7 },
1910 #endif
1911 { NULL, 0 }
1912 };
1913
1914 static struct clk tegra_clk_audio = {
1915 .name = "audio",
1916 .inputs = mux_audio_sync_clk,
1917 .reg = 0x38,
1918 .max_rate = 73728000,
1919 .ops = &tegra_audio_sync_clk_ops
1920 };
1921
1922 static struct clk tegra_clk_audio_2x = {
1923 .name = "audio_2x",
1924 .flags = PERIPH_NO_RESET,
1925 .max_rate = 48000000,
1926 .ops = &tegra_clk_double_ops,
1927 .reg = 0x34,
1928 .reg_shift = 8,
1929 .parent = &tegra_clk_audio,
1930 .u.periph = {
1931 .clk_num = 89,
1932 },
1933 };
1934
1935 static struct clk_lookup tegra_audio_clk_lookups[] = {
1936 { .con_id = "audio", .clk = &tegra_clk_audio },
1937 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1938 };
1939
1940 /* This is called after peripheral clocks are initialized, as the
1941 * audio_sync clock depends on some of the peripheral clocks.
1942 */
1943
1944 static void init_audio_sync_clock_mux(void)
1945 {
1946 int i;
1947 struct clk_mux_sel *sel = mux_audio_sync_clk;
1948 const struct audio_sources *src = mux_audio_sync_clk_sources;
1949 struct clk_lookup *lookup;
1950
1951 for (i = 0; src->name; i++, sel++, src++) {
1952 sel->input = tegra_get_clock_by_name(src->name);
1953 if (!sel->input)
1954 pr_err("%s: could not find clk %s\n", __func__,
1955 src->name);
1956 sel->value = src->value;
1957 }
1958
1959 lookup = tegra_audio_clk_lookups;
1960 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1961 clk_init(lookup->clk);
1962 clkdev_add(lookup);
1963 }
1964 }
1965
1966 static struct clk_mux_sel mux_cclk[] = {
1967 { .input = &tegra_clk_m, .value = 0},
1968 { .input = &tegra_pll_c, .value = 1},
1969 { .input = &tegra_clk_32k, .value = 2},
1970 { .input = &tegra_pll_m, .value = 3},
1971 { .input = &tegra_pll_p, .value = 4},
1972 { .input = &tegra_pll_p_out4, .value = 5},
1973 { .input = &tegra_pll_p_out3, .value = 6},
1974 { .input = &tegra_clk_d, .value = 7},
1975 { .input = &tegra_pll_x, .value = 8},
1976 { NULL, 0},
1977 };
1978
1979 static struct clk_mux_sel mux_sclk[] = {
1980 { .input = &tegra_clk_m, .value = 0},
1981 { .input = &tegra_pll_c_out1, .value = 1},
1982 { .input = &tegra_pll_p_out4, .value = 2},
1983 { .input = &tegra_pll_p_out3, .value = 3},
1984 { .input = &tegra_pll_p_out2, .value = 4},
1985 { .input = &tegra_clk_d, .value = 5},
1986 { .input = &tegra_clk_32k, .value = 6},
1987 { .input = &tegra_pll_m_out1, .value = 7},
1988 { NULL, 0},
1989 };
1990
1991 static struct clk tegra_clk_cclk = {
1992 .name = "cclk",
1993 .inputs = mux_cclk,
1994 .reg = 0x20,
1995 .ops = &tegra_super_ops,
1996 .max_rate = 1000000000,
1997 };
1998
1999 static struct clk tegra_clk_sclk = {
2000 .name = "sclk",
2001 .inputs = mux_sclk,
2002 .reg = 0x28,
2003 .ops = &tegra_super_ops,
2004 .max_rate = 240000000,
2005 .min_rate = 120000000,
2006 };
2007
2008 static struct clk tegra_clk_virtual_cpu = {
2009 .name = "cpu",
2010 .parent = &tegra_clk_cclk,
2011 .ops = &tegra_cpu_ops,
2012 .max_rate = 1000000000,
2013 .u.cpu = {
2014 .main = &tegra_pll_x,
2015 .backup = &tegra_pll_p,
2016 },
2017 };
2018
2019 static struct clk tegra_clk_cop = {
2020 .name = "cop",
2021 .parent = &tegra_clk_sclk,
2022 .ops = &tegra_cop_ops,
2023 .max_rate = 240000000,
2024 };
2025
2026 static struct clk tegra_clk_hclk = {
2027 .name = "hclk",
2028 .flags = DIV_BUS,
2029 .parent = &tegra_clk_sclk,
2030 .reg = 0x30,
2031 .reg_shift = 4,
2032 .ops = &tegra_bus_ops,
2033 .max_rate = 240000000,
2034 };
2035
2036 static struct clk tegra_clk_pclk = {
2037 .name = "pclk",
2038 .flags = DIV_BUS,
2039 .parent = &tegra_clk_hclk,
2040 .reg = 0x30,
2041 .reg_shift = 0,
2042 .ops = &tegra_bus_ops,
2043 .max_rate = 120000000,
2044 };
2045
2046 static struct clk tegra_clk_blink = {
2047 .name = "blink",
2048 .parent = &tegra_clk_32k,
2049 .reg = 0x40,
2050 .ops = &tegra_blink_clk_ops,
2051 .max_rate = 32768,
2052 };
2053
2054 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2055 { .input = &tegra_pll_m, .value = 0},
2056 { .input = &tegra_pll_c, .value = 1},
2057 { .input = &tegra_pll_p, .value = 2},
2058 { .input = &tegra_pll_a_out0, .value = 3},
2059 { NULL, 0},
2060 };
2061
2062 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
2063 { .input = &tegra_pll_m, .value = 0},
2064 { .input = &tegra_pll_c, .value = 1},
2065 { .input = &tegra_pll_p, .value = 2},
2066 { .input = &tegra_clk_m, .value = 3},
2067 { NULL, 0},
2068 };
2069
2070 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2071 { .input = &tegra_pll_p, .value = 0},
2072 { .input = &tegra_pll_c, .value = 1},
2073 { .input = &tegra_pll_m, .value = 2},
2074 { .input = &tegra_clk_m, .value = 3},
2075 { NULL, 0},
2076 };
2077
2078 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
2079 {.input = &tegra_pll_a_out0, .value = 0},
2080 {.input = &tegra_clk_audio_2x, .value = 1},
2081 {.input = &tegra_pll_p, .value = 2},
2082 {.input = &tegra_clk_m, .value = 3},
2083 { NULL, 0},
2084 };
2085
2086 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2087 {.input = &tegra_pll_p, .value = 0},
2088 {.input = &tegra_pll_d_out0, .value = 1},
2089 {.input = &tegra_pll_c, .value = 2},
2090 {.input = &tegra_clk_m, .value = 3},
2091 { NULL, 0},
2092 };
2093
2094 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
2095 {.input = &tegra_pll_p, .value = 0},
2096 {.input = &tegra_pll_c, .value = 1},
2097 {.input = &tegra_clk_audio, .value = 2},
2098 {.input = &tegra_clk_m, .value = 3},
2099 {.input = &tegra_clk_32k, .value = 4},
2100 { NULL, 0},
2101 };
2102
2103 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2104 {.input = &tegra_pll_p, .value = 0},
2105 {.input = &tegra_pll_c, .value = 1},
2106 {.input = &tegra_pll_m, .value = 2},
2107 { NULL, 0},
2108 };
2109
2110 static struct clk_mux_sel mux_clk_m[] = {
2111 { .input = &tegra_clk_m, .value = 0},
2112 { NULL, 0},
2113 };
2114
2115 static struct clk_mux_sel mux_pllp_out3[] = {
2116 { .input = &tegra_pll_p_out3, .value = 0},
2117 { NULL, 0},
2118 };
2119
2120 static struct clk_mux_sel mux_plld[] = {
2121 { .input = &tegra_pll_d, .value = 0},
2122 { NULL, 0},
2123 };
2124
2125 static struct clk_mux_sel mux_clk_32k[] = {
2126 { .input = &tegra_clk_32k, .value = 0},
2127 { NULL, 0},
2128 };
2129
2130 static struct clk_mux_sel mux_pclk[] = {
2131 { .input = &tegra_clk_pclk, .value = 0},
2132 { NULL, 0},
2133 };
2134
2135 static struct clk tegra_clk_emc = {
2136 .name = "emc",
2137 .ops = &tegra_emc_clk_ops,
2138 .reg = 0x19c,
2139 .max_rate = 800000000,
2140 .inputs = mux_pllm_pllc_pllp_clkm,
2141 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
2142 .u.periph = {
2143 .clk_num = 57,
2144 },
2145 };
2146
2147 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2148 { \
2149 .name = _name, \
2150 .lookup = { \
2151 .dev_id = _dev, \
2152 .con_id = _con, \
2153 }, \
2154 .ops = &tegra_periph_clk_ops, \
2155 .reg = _reg, \
2156 .inputs = _inputs, \
2157 .flags = _flags, \
2158 .max_rate = _max, \
2159 .u.periph = { \
2160 .clk_num = _clk_num, \
2161 }, \
2162 }
2163
2164 #define SHARED_CLK(_name, _dev, _con, _parent) \
2165 { \
2166 .name = _name, \
2167 .lookup = { \
2168 .dev_id = _dev, \
2169 .con_id = _con, \
2170 }, \
2171 .ops = &tegra_clk_shared_bus_ops, \
2172 .parent = _parent, \
2173 }
2174
2175 static struct clk tegra_list_clks[] = {
2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2187 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2188 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2189 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2190 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2191 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2192 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2193 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2194 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2195 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2196 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2197 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2198 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2199 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2200 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2201 PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
2202 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2203 /* FIXME: what is la? */
2204 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2205 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2206 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2207 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2208 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2209 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2210 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2211 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
2212 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2224 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
2225 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2226 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2227 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2228 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2229 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2230 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2231 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2232 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2233 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
2234 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2235 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2236 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2237 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
2238 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
2239 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2240 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2241 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2242 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2243 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
2244
2245 SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
2246 SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
2247 SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
2248 SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
2249 SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
2250 SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
2251 SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
2252 SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
2253 SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
2254 SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
2255 SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
2256 };
2257
2258 #define CLK_DUPLICATE(_name, _dev, _con) \
2259 { \
2260 .name = _name, \
2261 .lookup = { \
2262 .dev_id = _dev, \
2263 .con_id = _con, \
2264 }, \
2265 }
2266
2267 /* Some clocks may be used by different drivers depending on the board
2268 * configuration. List those here to register them twice in the clock lookup
2269 * table under two names.
2270 */
2271 static struct clk_duplicate tegra_clk_duplicates[] = {
2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
2285 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
2286 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
2287 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
2288 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2289 };
2290
2291 #define CLK(dev, con, ck) \
2292 { \
2293 .dev_id = dev, \
2294 .con_id = con, \
2295 .clk = ck, \
2296 }
2297
2298 static struct clk *tegra_ptr_clks[] = {
2299 &tegra_clk_32k,
2300 &tegra_pll_s,
2301 &tegra_clk_m,
2302 &tegra_pll_m,
2303 &tegra_pll_m_out1,
2304 &tegra_pll_c,
2305 &tegra_pll_c_out1,
2306 &tegra_pll_p,
2307 &tegra_pll_p_out1,
2308 &tegra_pll_p_out2,
2309 &tegra_pll_p_out3,
2310 &tegra_pll_p_out4,
2311 &tegra_pll_a,
2312 &tegra_pll_a_out0,
2313 &tegra_pll_d,
2314 &tegra_pll_d_out0,
2315 &tegra_pll_u,
2316 &tegra_pll_x,
2317 &tegra_pll_e,
2318 &tegra_clk_cclk,
2319 &tegra_clk_sclk,
2320 &tegra_clk_hclk,
2321 &tegra_clk_pclk,
2322 &tegra_clk_d,
2323 &tegra_clk_cdev1,
2324 &tegra_clk_cdev2,
2325 &tegra_clk_virtual_cpu,
2326 &tegra_clk_blink,
2327 &tegra_clk_cop,
2328 &tegra_clk_emc,
2329 };
2330
2331 static void tegra2_init_one_clock(struct clk *c)
2332 {
2333 clk_init(c);
2334 INIT_LIST_HEAD(&c->shared_bus_list);
2335 if (!c->lookup.dev_id && !c->lookup.con_id)
2336 c->lookup.con_id = c->name;
2337 c->lookup.clk = c;
2338 clkdev_add(&c->lookup);
2339 }
2340
2341 void __init tegra2_init_clocks(void)
2342 {
2343 int i;
2344 struct clk *c;
2345
2346 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2347 tegra2_init_one_clock(tegra_ptr_clks[i]);
2348
2349 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2350 tegra2_init_one_clock(&tegra_list_clks[i]);
2351
2352 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2353 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2354 if (!c) {
2355 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2356 tegra_clk_duplicates[i].name);
2357 continue;
2358 }
2359
2360 tegra_clk_duplicates[i].lookup.clk = c;
2361 clkdev_add(&tegra_clk_duplicates[i].lookup);
2362 }
2363
2364 init_audio_sync_clock_mux();
2365 }
2366
2367 #ifdef CONFIG_PM
2368 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2369 PERIPH_CLK_SOURCE_NUM + 22];
2370
2371 void tegra_clk_suspend(void)
2372 {
2373 unsigned long off, i;
2374 u32 *ctx = clk_rst_suspend;
2375
2376 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2377 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2378 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2379 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2380 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2381 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
2382 *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2383 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
2384 *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2385 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
2386 *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2387
2388 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2389 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2390 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2391
2392 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2393 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2394
2395 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2396 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2397 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2398
2399 *ctx++ = clk_readl(tegra_clk_audio.reg);
2400
2401 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2402 off += 4) {
2403 if (off == PERIPH_CLK_SOURCE_EMC)
2404 continue;
2405 *ctx++ = clk_readl(off);
2406 }
2407
2408 off = RST_DEVICES;
2409 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2410 *ctx++ = clk_readl(off);
2411
2412 off = CLK_OUT_ENB;
2413 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2414 *ctx++ = clk_readl(off);
2415
2416 *ctx++ = clk_readl(MISC_CLK_ENB);
2417 *ctx++ = clk_readl(CLK_MASK_ARM);
2418
2419 BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
2420 }
2421
2422 void tegra_clk_resume(void)
2423 {
2424 unsigned long off, i;
2425 const u32 *ctx = clk_rst_suspend;
2426 u32 val;
2427
2428 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2429 val |= *ctx++;
2430 clk_writel(val, OSC_CTRL);
2431
2432 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2433 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2434 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2435 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2436 clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
2437 clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
2438 clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
2439 clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
2440 clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
2441 clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
2442 udelay(1000);
2443
2444 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2445 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2446 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2447
2448 clk_writel(*ctx++, tegra_clk_cclk.reg);
2449 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2450
2451 clk_writel(*ctx++, tegra_clk_sclk.reg);
2452 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2453 clk_writel(*ctx++, tegra_clk_pclk.reg);
2454
2455 clk_writel(*ctx++, tegra_clk_audio.reg);
2456
2457 /* enable all clocks before configuring clock sources */
2458 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2459 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2460 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2461 wmb();
2462
2463 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2464 off += 4) {
2465 if (off == PERIPH_CLK_SOURCE_EMC)
2466 continue;
2467 clk_writel(*ctx++, off);
2468 }
2469 wmb();
2470
2471 off = RST_DEVICES;
2472 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2473 clk_writel(*ctx++, off);
2474 wmb();
2475
2476 off = CLK_OUT_ENB;
2477 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2478 clk_writel(*ctx++, off);
2479 wmb();
2480
2481 clk_writel(*ctx++, MISC_CLK_ENB);
2482 clk_writel(*ctx++, CLK_MASK_ARM);
2483 }
2484 #endif
Linux ARM platform port for MOXA ART SoC