arch/arm/mach-tegra/tegra2_emc.c

   1 /*
   2  * Copyright (C) 2011 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/clk.h>
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/platform_data/tegra_emc.h>
  27
  28 #include <mach/iomap.h>
  29
  30 #include "tegra2_emc.h"
  31 #include "fuse.h"
  32
  33 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
  34 static bool emc_enable = true;
  35 #else
  36 static bool emc_enable;
  37 #endif
  38 module_param(emc_enable, bool, 0644);
  39
  40 static struct platform_device *emc_pdev;
  41 static void __iomem *emc_regbase;
  42
  43 static inline void emc_writel(u32 val, unsigned long addr)
  44 {
  45         writel(val, emc_regbase + addr);
  46 }
  47
  48 static inline u32 emc_readl(unsigned long addr)
  49 {
  50         return readl(emc_regbase + addr);
  51 }
  52
  53 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
  54         0x2c,   /* RC */
  55         0x30,   /* RFC */
  56         0x34,   /* RAS */
  57         0x38,   /* RP */
  58         0x3c,   /* R2W */
  59         0x40,   /* W2R */
  60         0x44,   /* R2P */
  61         0x48,   /* W2P */
  62         0x4c,   /* RD_RCD */
  63         0x50,   /* WR_RCD */
  64         0x54,   /* RRD */
  65         0x58,   /* REXT */
  66         0x5c,   /* WDV */
  67         0x60,   /* QUSE */
  68         0x64,   /* QRST */
  69         0x68,   /* QSAFE */
  70         0x6c,   /* RDV */
  71         0x70,   /* REFRESH */
  72         0x74,   /* BURST_REFRESH_NUM */
  73         0x78,   /* PDEX2WR */
  74         0x7c,   /* PDEX2RD */
  75         0x80,   /* PCHG2PDEN */
  76         0x84,   /* ACT2PDEN */
  77         0x88,   /* AR2PDEN */
  78         0x8c,   /* RW2PDEN */
  79         0x90,   /* TXSR */
  80         0x94,   /* TCKE */
  81         0x98,   /* TFAW */
  82         0x9c,   /* TRPAB */
  83         0xa0,   /* TCLKSTABLE */
  84         0xa4,   /* TCLKSTOP */
  85         0xa8,   /* TREFBW */
  86         0xac,   /* QUSE_EXTRA */
  87         0x114,  /* FBIO_CFG6 */
  88         0xb0,   /* ODT_WRITE */
  89         0xb4,   /* ODT_READ */
  90         0x104,  /* FBIO_CFG5 */
  91         0x2bc,  /* CFG_DIG_DLL */
  92         0x2c0,  /* DLL_XFORM_DQS */
  93         0x2c4,  /* DLL_XFORM_QUSE */
  94         0x2e0,  /* ZCAL_REF_CNT */
  95         0x2e4,  /* ZCAL_WAIT_CNT */
  96         0x2a8,  /* AUTO_CAL_INTERVAL */
  97         0x2d0,  /* CFG_CLKTRIM_0 */
  98         0x2d4,  /* CFG_CLKTRIM_1 */
  99         0x2d8,  /* CFG_CLKTRIM_2 */
 100 };
 101
 102 /* Select the closest EMC rate that is higher than the requested rate */
 103 long tegra_emc_round_rate(unsigned long rate)
 104 {
 105         struct tegra_emc_pdata *pdata;
 106         int i;
 107         int best = -1;
 108         unsigned long distance = ULONG_MAX;
 109
 110         if (!emc_pdev)
 111                 return -EINVAL;
 112
 113         pdata = emc_pdev->dev.platform_data;
 114
 115         pr_debug("%s: %lu\n", __func__, rate);
 116
 117         /*
 118          * The EMC clock rate is twice the bus rate, and the bus rate is
 119          * measured in kHz
 120          */
 121         rate = rate / 2 / 1000;
 122
 123         for (i = 0; i < pdata->num_tables; i++) {
 124                 if (pdata->tables[i].rate >= rate &&
 125                     (pdata->tables[i].rate - rate) < distance) {
 126                         distance = pdata->tables[i].rate - rate;
 127                         best = i;
 128                 }
 129         }
 130
 131         if (best < 0)
 132                 return -EINVAL;
 133
 134         pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
 135
 136         return pdata->tables[best].rate * 2 * 1000;
 137 }
 138
 139 /*
 140  * The EMC registers have shadow registers.  When the EMC clock is updated
 141  * in the clock controller, the shadow registers are copied to the active
 142  * registers, allowing glitchless memory bus frequency changes.
 143  * This function updates the shadow registers for a new clock frequency,
 144  * and relies on the clock lock on the emc clock to avoid races between
 145  * multiple frequency changes
 146  */
 147 int tegra_emc_set_rate(unsigned long rate)
 148 {
 149         struct tegra_emc_pdata *pdata;
 150         int i;
 151         int j;
 152
 153         if (!emc_pdev)
 154                 return -EINVAL;
 155
 156         pdata = emc_pdev->dev.platform_data;
 157
 158         /*
 159          * The EMC clock rate is twice the bus rate, and the bus rate is
 160          * measured in kHz
 161          */
 162         rate = rate / 2 / 1000;
 163
 164         for (i = 0; i < pdata->num_tables; i++)
 165                 if (pdata->tables[i].rate == rate)
 166                         break;
 167
 168         if (i >= pdata->num_tables)
 169                 return -EINVAL;
 170
 171         pr_debug("%s: setting to %lu\n", __func__, rate);
 172
 173         for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
 174                 emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
 175
 176         emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
 177
 178         return 0;
 179 }
 180
 181 #ifdef CONFIG_OF
 182 static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
 183 {
 184         struct device_node *iter;
 185         u32 reg;
 186
 187         for_each_child_of_node(np, iter) {
 188                 if (of_property_read_u32(np, "nvidia,ram-code", &reg))
 189                         continue;
 190                 if (reg == tegra_bct_strapping)
 191                         return of_node_get(iter);
 192         }
 193
 194         return NULL;
 195 }
 196
 197 static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
 198                 struct platform_device *pdev)
 199 {
 200         struct device_node *np = pdev->dev.of_node;
 201         struct device_node *tnp, *iter;
 202         struct tegra_emc_pdata *pdata;
 203         int ret, i, num_tables;
 204
 205         if (!np)
 206                 return NULL;
 207
 208         if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
 209                 tnp = tegra_emc_ramcode_devnode(np);
 210                 if (!tnp)
 211                         dev_warn(&pdev->dev,
 212                                  "can't find emc table for ram-code 0x%02x\n",
 213                                  tegra_bct_strapping);
 214         } else
 215                 tnp = of_node_get(np);
 216
 217         if (!tnp)
 218                 return NULL;
 219
 220         num_tables = 0;
 221         for_each_child_of_node(tnp, iter)
 222                 if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
 223                         num_tables++;
 224
 225         if (!num_tables) {
 226                 pdata = NULL;
 227                 goto out;
 228         }
 229
 230         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 231         pdata->tables = devm_kzalloc(&pdev->dev,
 232                                      sizeof(*pdata->tables) * num_tables,
 233                                      GFP_KERNEL);
 234
 235         i = 0;
 236         for_each_child_of_node(tnp, iter) {
 237                 u32 prop;
 238
 239                 ret = of_property_read_u32(iter, "clock-frequency", &prop);
 240                 if (ret) {
 241                         dev_err(&pdev->dev, "no clock-frequency in %s\n",
 242                                 iter->full_name);
 243                         continue;
 244                 }
 245                 pdata->tables[i].rate = prop;
 246
 247                 ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
 248                                                  pdata->tables[i].regs,
 249                                                  TEGRA_EMC_NUM_REGS);
 250                 if (ret) {
 251                         dev_err(&pdev->dev,
 252                                 "malformed emc-registers property in %s\n",
 253                                 iter->full_name);
 254                         continue;
 255                 }
 256
 257                 i++;
 258         }
 259         pdata->num_tables = i;
 260
 261 out:
 262         of_node_put(tnp);
 263         return pdata;
 264 }
 265 #else
 266 static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
 267                 struct platform_device *pdev)
 268 {
 269         return NULL;
 270 }
 271 #endif
 272
 273 static struct tegra_emc_pdata __devinit *tegra_emc_fill_pdata(struct platform_device *pdev)
 274 {
 275         struct clk *c = clk_get_sys(NULL, "emc");
 276         struct tegra_emc_pdata *pdata;
 277         unsigned long khz;
 278         int i;
 279
 280         WARN_ON(pdev->dev.platform_data);
 281         BUG_ON(IS_ERR_OR_NULL(c));
 282
 283         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 284         pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
 285                                      GFP_KERNEL);
 286
 287         pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
 288
 289         for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
 290                 pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
 291
 292         pdata->num_tables = 1;
 293
 294         khz = pdata->tables[0].rate;
 295         dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
 296                  "%ld kHz mem\n", khz * 2, khz);
 297
 298         return pdata;
 299 }
 300
 301 static int __devinit tegra_emc_probe(struct platform_device *pdev)
 302 {
 303         struct tegra_emc_pdata *pdata;
 304         struct resource *res;
 305
 306         if (!emc_enable) {
 307                 dev_err(&pdev->dev, "disabled per module parameter\n");
 308                 return -ENODEV;
 309         }
 310
 311         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 312         if (!res) {
 313                 dev_err(&pdev->dev, "missing register base\n");
 314                 return -ENOMEM;
 315         }
 316
 317         emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
 318         if (!emc_regbase) {
 319                 dev_err(&pdev->dev, "failed to remap registers\n");
 320                 return -ENOMEM;
 321         }
 322
 323         pdata = pdev->dev.platform_data;
 324
 325         if (!pdata)
 326                 pdata = tegra_emc_dt_parse_pdata(pdev);
 327
 328         if (!pdata)
 329                 pdata = tegra_emc_fill_pdata(pdev);
 330
 331         pdev->dev.platform_data = pdata;
 332
 333         emc_pdev = pdev;
 334
 335         return 0;
 336 }
 337
 338 static struct of_device_id tegra_emc_of_match[] __devinitdata = {
 339         { .compatible = "nvidia,tegra20-emc", },
 340         { },
 341 };
 342
 343 static struct platform_driver tegra_emc_driver = {
 344         .driver         = {
 345                 .name   = "tegra-emc",
 346                 .owner  = THIS_MODULE,
 347                 .of_match_table = tegra_emc_of_match,
 348         },
 349         .probe          = tegra_emc_probe,
 350 };
 351
 352 static int __init tegra_emc_init(void)
 353 {
 354         return platform_driver_register(&tegra_emc_driver);
 355 }
 356 device_initcall(tegra_emc_init);