arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-2012 Texas Instruments
  10  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31
  32 #include "sram.h"
  33
  34 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
  35 #include "../mach-omap2/iomap.h"
  36 #include "../mach-omap2/prm2xxx_3xxx.h"
  37 #include "../mach-omap2/sdrc.h"
  38
  39 #define OMAP1_SRAM_PA           0x20000000
  40 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  41 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  42 #ifdef CONFIG_OMAP4_ERRATA_I688
  43 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  44 #else
  45 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  46 #endif
  47 #define OMAP5_SRAM_PA           0x40300000
  48
  49 #if defined(CONFIG_ARCH_OMAP2PLUS)
  50 #define SRAM_BOOTLOADER_SZ      0x00
  51 #else
  52 #define SRAM_BOOTLOADER_SZ      0x80
  53 #endif
  54
  55 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  56 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  57 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  58
  59 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  60 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  61 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  62 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  63 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  64
  65 #define GP_DEVICE               0x300
  66
  67 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  68
  69 static unsigned long omap_sram_start;
  70 static void __iomem *omap_sram_base;
  71 static unsigned long omap_sram_skip;
  72 static unsigned long omap_sram_size;
  73 static void __iomem *omap_sram_ceil;
  74
  75 /*
  76  * Depending on the target RAMFS firewall setup, the public usable amount of
  77  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  78  * device allows ARM11 but not other initiators for full size. This
  79  * functionality seems ok until some nice security API happens.
  80  */
  81 static int is_sram_locked(void)
  82 {
  83         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  84                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  85                 if (cpu_is_omap242x()) {
  86                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  87                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  88                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  89                 }
  90                 if (cpu_is_omap34xx()) {
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  92                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  93                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  94                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  95                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  96                 }
  97                 return 0;
  98         } else
  99                 return 1; /* assume locked with no PPA or security driver */
 100 }
 101
 102 /*
 103  * The amount of SRAM depends on the core type.
 104  * Note that we cannot try to test for SRAM here because writes
 105  * to secure SRAM will hang the system. Also the SRAM is not
 106  * yet mapped at this point.
 107  */
 108 static void __init omap_detect_sram(void)
 109 {
 110         omap_sram_skip = SRAM_BOOTLOADER_SZ;
 111         if (cpu_class_is_omap2()) {
 112                 if (is_sram_locked()) {
 113                         if (cpu_is_omap34xx()) {
 114                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 115                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 116                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 117                                         omap_sram_size = 0x7000; /* 28K */
 118                                         omap_sram_skip += SZ_16K;
 119                                 } else {
 120                                         omap_sram_size = 0x8000; /* 32K */
 121                                 }
 122                         } else if (cpu_is_omap44xx()) {
 123                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 124                                 omap_sram_size = 0xa000; /* 40K */
 125                         } else if (soc_is_omap54xx()) {
 126                                 omap_sram_start = OMAP5_SRAM_PA;
 127                                 omap_sram_size = SZ_128K; /* 128KB */
 128                         } else {
 129                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 130                                 omap_sram_size = 0x800; /* 2K */
 131                         }
 132                 } else {
 133                         if (soc_is_am33xx()) {
 134                                 omap_sram_start = AM33XX_SRAM_PA;
 135                                 omap_sram_size = 0x10000; /* 64K */
 136                         } else if (cpu_is_omap34xx()) {
 137                                 omap_sram_start = OMAP3_SRAM_PA;
 138                                 omap_sram_size = 0x10000; /* 64K */
 139                         } else if (cpu_is_omap44xx()) {
 140                                 omap_sram_start = OMAP4_SRAM_PA;
 141                                 omap_sram_size = 0xe000; /* 56K */
 142                         } else if (soc_is_omap54xx()) {
 143                                 omap_sram_start = OMAP5_SRAM_PA;
 144                                 omap_sram_size = SZ_128K; /* 128KB */
 145                         } else {
 146                                 omap_sram_start = OMAP2_SRAM_PA;
 147                                 if (cpu_is_omap242x())
 148                                         omap_sram_size = 0xa0000; /* 640K */
 149                                 else if (cpu_is_omap243x())
 150                                         omap_sram_size = 0x10000; /* 64K */
 151                         }
 152                 }
 153         } else {
 154                 omap_sram_start = OMAP1_SRAM_PA;
 155
 156                 if (cpu_is_omap7xx())
 157                         omap_sram_size = 0x32000;       /* 200K */
 158                 else if (cpu_is_omap15xx())
 159                         omap_sram_size = 0x30000;       /* 192K */
 160                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
 161                                 cpu_is_omap1621() || cpu_is_omap1710())
 162                         omap_sram_size = 0x4000;        /* 16K */
 163                 else {
 164                         pr_err("Could not detect SRAM size\n");
 165                         omap_sram_size = 0x4000;
 166                 }
 167         }
 168 }
 169
 170 /*
 171  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 172  */
 173 static void __init omap_map_sram(void)
 174 {
 175         int cached = 1;
 176
 177         if (omap_sram_size == 0)
 178                 return;
 179
 180 #ifdef CONFIG_OMAP4_ERRATA_I688
 181         if (cpu_is_omap44xx()) {
 182                 omap_sram_start += PAGE_SIZE;
 183                 omap_sram_size -= SZ_16K;
 184         }
 185 #endif
 186         if (cpu_is_omap34xx()) {
 187                 /*
 188                  * SRAM must be marked as non-cached on OMAP3 since the
 189                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 190                  * SDRAM controller disabled, and if it is marked cached,
 191                  * the ARM may attempt to write cache lines back to SDRAM
 192                  * which will cause the system to hang.
 193                  */
 194                 cached = 0;
 195         }
 196
 197         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 198         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 199                                                 cached);
 200         if (!omap_sram_base) {
 201                 pr_err("SRAM: Could not map\n");
 202                 return;
 203         }
 204
 205         omap_sram_ceil = omap_sram_base + omap_sram_size;
 206
 207         /*
 208          * Looks like we need to preserve some bootloader code at the
 209          * beginning of SRAM for jumping to flash for reboot to work...
 210          */
 211         memset_io(omap_sram_base + omap_sram_skip, 0,
 212                   omap_sram_size - omap_sram_skip);
 213 }
 214
 215 /*
 216  * Memory allocator for SRAM: calculates the new ceiling address
 217  * for pushing a function using the fncpy API.
 218  *
 219  * Note that fncpy requires the returned address to be aligned
 220  * to an 8-byte boundary.
 221  */
 222 void *omap_sram_push_address(unsigned long size)
 223 {
 224         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 225
 226         available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
 227
 228         if (size > available) {
 229                 pr_err("Not enough space in SRAM\n");
 230                 return NULL;
 231         }
 232
 233         new_ceil -= size;
 234         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 235         omap_sram_ceil = IOMEM(new_ceil);
 236
 237         return (void *)omap_sram_ceil;
 238 }
 239
 240 #ifdef CONFIG_ARCH_OMAP1
 241
 242 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 243
 244 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 245 {
 246         BUG_ON(!_omap_sram_reprogram_clock);
 247         /* On 730, bit 13 must always be 1 */
 248         if (cpu_is_omap7xx())
 249                 ckctl |= 0x2000;
 250         _omap_sram_reprogram_clock(dpllctl, ckctl);
 251 }
 252
 253 static int __init omap1_sram_init(void)
 254 {
 255         _omap_sram_reprogram_clock =
 256                         omap_sram_push(omap1_sram_reprogram_clock,
 257                                         omap1_sram_reprogram_clock_sz);
 258
 259         return 0;
 260 }
 261
 262 #else
 263 #define omap1_sram_init()       do {} while (0)
 264 #endif
 265
 266 #if defined(CONFIG_ARCH_OMAP2)
 267
 268 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 269                               u32 base_cs, u32 force_unlock);
 270
 271 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 272                    u32 base_cs, u32 force_unlock)
 273 {
 274         BUG_ON(!_omap2_sram_ddr_init);
 275         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 276                              base_cs, force_unlock);
 277 }
 278
 279 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 280                                           u32 mem_type);
 281
 282 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 283 {
 284         BUG_ON(!_omap2_sram_reprogram_sdrc);
 285         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 286 }
 287
 288 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 289
 290 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 291 {
 292         BUG_ON(!_omap2_set_prcm);
 293         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 294 }
 295 #endif
 296
 297 #ifdef CONFIG_SOC_OMAP2420
 298 static int __init omap242x_sram_init(void)
 299 {
 300         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 301                                         omap242x_sram_ddr_init_sz);
 302
 303         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 304                                             omap242x_sram_reprogram_sdrc_sz);
 305
 306         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 307                                          omap242x_sram_set_prcm_sz);
 308
 309         return 0;
 310 }
 311 #else
 312 static inline int omap242x_sram_init(void)
 313 {
 314         return 0;
 315 }
 316 #endif
 317
 318 #ifdef CONFIG_SOC_OMAP2430
 319 static int __init omap243x_sram_init(void)
 320 {
 321         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 322                                         omap243x_sram_ddr_init_sz);
 323
 324         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 325                                             omap243x_sram_reprogram_sdrc_sz);
 326
 327         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 328                                          omap243x_sram_set_prcm_sz);
 329
 330         return 0;
 331 }
 332 #else
 333 static inline int omap243x_sram_init(void)
 334 {
 335         return 0;
 336 }
 337 #endif
 338
 339 #ifdef CONFIG_ARCH_OMAP3
 340
 341 static u32 (*_omap3_sram_configure_core_dpll)(
 342                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 343                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 344                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 345                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 346                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 347
 348 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 349                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 350                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 351                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 352                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 353 {
 354         BUG_ON(!_omap3_sram_configure_core_dpll);
 355         return _omap3_sram_configure_core_dpll(
 356                         m2, unlock_dll, f, inc,
 357                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 358                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 359                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 360                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 361 }
 362
 363 void omap3_sram_restore_context(void)
 364 {
 365         omap_sram_ceil = omap_sram_base + omap_sram_size;
 366
 367         _omap3_sram_configure_core_dpll =
 368                 omap_sram_push(omap3_sram_configure_core_dpll,
 369                                omap3_sram_configure_core_dpll_sz);
 370         omap_push_sram_idle();
 371 }
 372
 373 static inline int omap34xx_sram_init(void)
 374 {
 375         omap3_sram_restore_context();
 376         return 0;
 377 }
 378 #else
 379 static inline int omap34xx_sram_init(void)
 380 {
 381         return 0;
 382 }
 383 #endif /* CONFIG_ARCH_OMAP3 */
 384
 385 static inline int am33xx_sram_init(void)
 386 {
 387         return 0;
 388 }
 389
 390 int __init omap_sram_init(void)
 391 {
 392         omap_detect_sram();
 393         omap_map_sram();
 394
 395         if (!(cpu_class_is_omap2()))
 396                 omap1_sram_init();
 397         else if (cpu_is_omap242x())
 398                 omap242x_sram_init();
 399         else if (cpu_is_omap2430())
 400                 omap243x_sram_init();
 401         else if (soc_is_am33xx())
 402                 am33xx_sram_init();
 403         else if (cpu_is_omap34xx())
 404                 omap34xx_sram_init();
 405
 406         return 0;
 407 }