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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
blobc2cf1ae31189cb2ce0be5d04e4b6450dc209bebe
1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/platform_device.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #include <linux/irq.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/usb/musb.h>
20 #include <asm/bfin6xx_spi.h>
21 #include <asm/dma.h>
22 #include <asm/gpio.h>
23 #include <asm/nand.h>
24 #include <asm/dpmc.h>
25 #include <asm/portmux.h>
26 #include <asm/bfin_sdh.h>
27 #include <linux/input.h>
28 #include <linux/spi/ad7877.h>
29
30 /*
31 * Name the Board for the /proc/cpuinfo
32 */
33 const char bfin_board_name[] = "ADI BF609-EZKIT";
34
35 /*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
40 #include <linux/usb/isp1760.h>
41 static struct resource bfin_isp1760_resources[] = {
42 [0] = {
43 .start = 0x2C0C0000,
44 .end = 0x2C0C0000 + 0xfffff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = IRQ_PG7,
49 .end = IRQ_PG7,
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53
54 static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
61 };
62
63 static struct platform_device bfin_isp1760_device = {
64 .name = "isp1760",
65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
71 };
72 #endif
73
74 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
75 #include <asm/bfin_rotary.h>
76
77 static struct bfin_rotary_platform_data bfin_rotary_data = {
78 /*.rotary_up_key = KEY_UP,*/
79 /*.rotary_down_key = KEY_DOWN,*/
80 .rotary_rel_code = REL_WHEEL,
81 .rotary_button_key = KEY_ENTER,
82 .debounce = 10, /* 0..17 */
83 .mode = ROT_QUAD_ENC | ROT_DEBE,
84 };
85
86 static struct resource bfin_rotary_resources[] = {
87 {
88 .start = IRQ_CNT,
89 .end = IRQ_CNT,
90 .flags = IORESOURCE_IRQ,
91 },
92 };
93
94 static struct platform_device bfin_rotary_device = {
95 .name = "bfin-rotary",
96 .id = -1,
97 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
98 .resource = bfin_rotary_resources,
99 .dev = {
100 .platform_data = &bfin_rotary_data,
101 },
102 };
103 #endif
104
105 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
106 #include <linux/stmmac.h>
107
108 static unsigned short pins[] = P_RMII0;
109
110 static struct stmmac_mdio_bus_data phy_private_data = {
111 .bus_id = 0,
112 .phy_mask = 1,
113 };
114
115 static struct plat_stmmacenet_data eth_private_data = {
116 .bus_id = 0,
117 .enh_desc = 1,
118 .phy_addr = 1,
119 .mdio_bus_data = &phy_private_data,
120 };
121
122 static struct platform_device bfin_eth_device = {
123 .name = "stmmaceth",
124 .id = 0,
125 .num_resources = 2,
126 .resource = (struct resource[]) {
127 {
128 .start = EMAC0_MACCFG,
129 .end = EMAC0_MACCFG + 0x1274,
130 .flags = IORESOURCE_MEM,
131 },
132 {
133 .name = "macirq",
134 .start = IRQ_EMAC0_STAT,
135 .end = IRQ_EMAC0_STAT,
136 .flags = IORESOURCE_IRQ,
137 },
138 },
139 .dev = {
140 .power.can_wakeup = 1,
141 .platform_data = &eth_private_data,
142 }
143 };
144 #endif
145
146 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
147 #include <linux/input/adxl34x.h>
148 static const struct adxl34x_platform_data adxl34x_info = {
149 .x_axis_offset = 0,
150 .y_axis_offset = 0,
151 .z_axis_offset = 0,
152 .tap_threshold = 0x31,
153 .tap_duration = 0x10,
154 .tap_latency = 0x60,
155 .tap_window = 0xF0,
156 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
157 .act_axis_control = 0xFF,
158 .activity_threshold = 5,
159 .inactivity_threshold = 3,
160 .inactivity_time = 4,
161 .free_fall_threshold = 0x7,
162 .free_fall_time = 0x20,
163 .data_rate = 0x8,
164 .data_range = ADXL_FULL_RES,
165
166 .ev_type = EV_ABS,
167 .ev_code_x = ABS_X, /* EV_REL */
168 .ev_code_y = ABS_Y, /* EV_REL */
169 .ev_code_z = ABS_Z, /* EV_REL */
170
171 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
172
173 /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
174 /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
175 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
176 .fifo_mode = ADXL_FIFO_STREAM,
177 .orientation_enable = ADXL_EN_ORIENTATION_3D,
178 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
179 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
180 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
181 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
182 };
183 #endif
184
185 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
186 static struct platform_device rtc_device = {
187 .name = "rtc-bfin",
188 .id = -1,
189 };
190 #endif
191
192 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
193 #ifdef CONFIG_SERIAL_BFIN_UART0
194 static struct resource bfin_uart0_resources[] = {
195 {
196 .start = UART0_REVID,
197 .end = UART0_RXDIV+4,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = IRQ_UART0_TX,
202 .end = IRQ_UART0_TX,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .start = IRQ_UART0_RX,
207 .end = IRQ_UART0_RX,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = IRQ_UART0_STAT,
212 .end = IRQ_UART0_STAT,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = CH_UART0_TX,
217 .end = CH_UART0_TX,
218 .flags = IORESOURCE_DMA,
219 },
220 {
221 .start = CH_UART0_RX,
222 .end = CH_UART0_RX,
223 .flags = IORESOURCE_DMA,
224 },
225 #ifdef CONFIG_BFIN_UART0_CTSRTS
226 { /* CTS pin -- 0 means not supported */
227 .start = GPIO_PD10,
228 .end = GPIO_PD10,
229 .flags = IORESOURCE_IO,
230 },
231 { /* RTS pin -- 0 means not supported */
232 .start = GPIO_PD9,
233 .end = GPIO_PD9,
234 .flags = IORESOURCE_IO,
235 },
236 #endif
237 };
238
239 static unsigned short bfin_uart0_peripherals[] = {
240 P_UART0_TX, P_UART0_RX,
241 #ifdef CONFIG_BFIN_UART0_CTSRTS
242 P_UART0_RTS, P_UART0_CTS,
243 #endif
244 0
245 };
246
247 static struct platform_device bfin_uart0_device = {
248 .name = "bfin-uart",
249 .id = 0,
250 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
251 .resource = bfin_uart0_resources,
252 .dev = {
253 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
254 },
255 };
256 #endif
257 #ifdef CONFIG_SERIAL_BFIN_UART1
258 static struct resource bfin_uart1_resources[] = {
259 {
260 .start = UART1_REVID,
261 .end = UART1_RXDIV+4,
262 .flags = IORESOURCE_MEM,
263 },
264 {
265 .start = IRQ_UART1_TX,
266 .end = IRQ_UART1_TX,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .start = IRQ_UART1_RX,
271 .end = IRQ_UART1_RX,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .start = IRQ_UART1_STAT,
276 .end = IRQ_UART1_STAT,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .start = CH_UART1_TX,
281 .end = CH_UART1_TX,
282 .flags = IORESOURCE_DMA,
283 },
284 {
285 .start = CH_UART1_RX,
286 .end = CH_UART1_RX,
287 .flags = IORESOURCE_DMA,
288 },
289 #ifdef CONFIG_BFIN_UART1_CTSRTS
290 { /* CTS pin -- 0 means not supported */
291 .start = GPIO_PG13,
292 .end = GPIO_PG13,
293 .flags = IORESOURCE_IO,
294 },
295 { /* RTS pin -- 0 means not supported */
296 .start = GPIO_PG10,
297 .end = GPIO_PG10,
298 .flags = IORESOURCE_IO,
299 },
300 #endif
301 };
302
303 static unsigned short bfin_uart1_peripherals[] = {
304 P_UART1_TX, P_UART1_RX,
305 #ifdef CONFIG_BFIN_UART1_CTSRTS
306 P_UART1_RTS, P_UART1_CTS,
307 #endif
308 0
309 };
310
311 static struct platform_device bfin_uart1_device = {
312 .name = "bfin-uart",
313 .id = 1,
314 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
315 .resource = bfin_uart1_resources,
316 .dev = {
317 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
318 },
319 };
320 #endif
321 #endif
322
323 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
324 #ifdef CONFIG_BFIN_SIR0
325 static struct resource bfin_sir0_resources[] = {
326 {
327 .start = 0xFFC00400,
328 .end = 0xFFC004FF,
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .start = IRQ_UART0_TX,
333 .end = IRQ_UART0_TX+1,
334 .flags = IORESOURCE_IRQ,
335 },
336 {
337 .start = CH_UART0_TX,
338 .end = CH_UART0_TX+1,
339 .flags = IORESOURCE_DMA,
340 },
341 };
342 static struct platform_device bfin_sir0_device = {
343 .name = "bfin_sir",
344 .id = 0,
345 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
346 .resource = bfin_sir0_resources,
347 };
348 #endif
349 #ifdef CONFIG_BFIN_SIR1
350 static struct resource bfin_sir1_resources[] = {
351 {
352 .start = 0xFFC02000,
353 .end = 0xFFC020FF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .start = IRQ_UART1_TX,
358 .end = IRQ_UART1_TX+1,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .start = CH_UART1_TX,
363 .end = CH_UART1_TX+1,
364 .flags = IORESOURCE_DMA,
365 },
366 };
367 static struct platform_device bfin_sir1_device = {
368 .name = "bfin_sir",
369 .id = 1,
370 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
371 .resource = bfin_sir1_resources,
372 };
373 #endif
374 #endif
375
376 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
377 static struct resource musb_resources[] = {
378 [0] = {
379 .start = 0xFFCC1000,
380 .end = 0xFFCC1398,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = { /* general IRQ */
384 .start = IRQ_USB_STAT,
385 .end = IRQ_USB_STAT,
386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
387 .name = "mc"
388 },
389 [2] = { /* DMA IRQ */
390 .start = IRQ_USB_DMA,
391 .end = IRQ_USB_DMA,
392 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
393 .name = "dma"
394 },
395 };
396
397 static struct musb_hdrc_config musb_config = {
398 .multipoint = 1,
399 .dyn_fifo = 0,
400 .dma = 1,
401 .num_eps = 16,
402 .dma_channels = 8,
403 .clkin = 48, /* musb CLKIN in MHZ */
404 };
405
406 static struct musb_hdrc_platform_data musb_plat = {
407 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
408 .mode = MUSB_OTG,
409 #elif defined(CONFIG_USB_MUSB_HDRC)
410 .mode = MUSB_HOST,
411 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
412 .mode = MUSB_PERIPHERAL,
413 #endif
414 .config = &musb_config,
415 };
416
417 static u64 musb_dmamask = ~(u32)0;
418
419 static struct platform_device musb_device = {
420 .name = "musb-blackfin",
421 .id = 0,
422 .dev = {
423 .dma_mask = &musb_dmamask,
424 .coherent_dma_mask = 0xffffffff,
425 .platform_data = &musb_plat,
426 },
427 .num_resources = ARRAY_SIZE(musb_resources),
428 .resource = musb_resources,
429 };
430 #endif
431
432 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
433 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
434 static struct resource bfin_sport0_uart_resources[] = {
435 {
436 .start = SPORT0_TCR1,
437 .end = SPORT0_MRCS3+4,
438 .flags = IORESOURCE_MEM,
439 },
440 {
441 .start = IRQ_SPORT0_RX,
442 .end = IRQ_SPORT0_RX+1,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .start = IRQ_SPORT0_ERROR,
447 .end = IRQ_SPORT0_ERROR,
448 .flags = IORESOURCE_IRQ,
449 },
450 };
451
452 static unsigned short bfin_sport0_peripherals[] = {
453 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
454 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
455 };
456
457 static struct platform_device bfin_sport0_uart_device = {
458 .name = "bfin-sport-uart",
459 .id = 0,
460 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
461 .resource = bfin_sport0_uart_resources,
462 .dev = {
463 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
464 },
465 };
466 #endif
467 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
468 static struct resource bfin_sport1_uart_resources[] = {
469 {
470 .start = SPORT1_TCR1,
471 .end = SPORT1_MRCS3+4,
472 .flags = IORESOURCE_MEM,
473 },
474 {
475 .start = IRQ_SPORT1_RX,
476 .end = IRQ_SPORT1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = IRQ_SPORT1_ERROR,
481 .end = IRQ_SPORT1_ERROR,
482 .flags = IORESOURCE_IRQ,
483 },
484 };
485
486 static unsigned short bfin_sport1_peripherals[] = {
487 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
488 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
489 };
490
491 static struct platform_device bfin_sport1_uart_device = {
492 .name = "bfin-sport-uart",
493 .id = 1,
494 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
495 .resource = bfin_sport1_uart_resources,
496 .dev = {
497 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
498 },
499 };
500 #endif
501 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
502 static struct resource bfin_sport2_uart_resources[] = {
503 {
504 .start = SPORT2_TCR1,
505 .end = SPORT2_MRCS3+4,
506 .flags = IORESOURCE_MEM,
507 },
508 {
509 .start = IRQ_SPORT2_RX,
510 .end = IRQ_SPORT2_RX+1,
511 .flags = IORESOURCE_IRQ,
512 },
513 {
514 .start = IRQ_SPORT2_ERROR,
515 .end = IRQ_SPORT2_ERROR,
516 .flags = IORESOURCE_IRQ,
517 },
518 };
519
520 static unsigned short bfin_sport2_peripherals[] = {
521 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
522 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
523 };
524
525 static struct platform_device bfin_sport2_uart_device = {
526 .name = "bfin-sport-uart",
527 .id = 2,
528 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
529 .resource = bfin_sport2_uart_resources,
530 .dev = {
531 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
532 },
533 };
534 #endif
535 #endif
536
537 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
538
539 static unsigned short bfin_can0_peripherals[] = {
540 P_CAN0_RX, P_CAN0_TX, 0
541 };
542
543 static struct resource bfin_can0_resources[] = {
544 {
545 .start = 0xFFC00A00,
546 .end = 0xFFC00FFF,
547 .flags = IORESOURCE_MEM,
548 },
549 {
550 .start = IRQ_CAN0_RX,
551 .end = IRQ_CAN0_RX,
552 .flags = IORESOURCE_IRQ,
553 },
554 {
555 .start = IRQ_CAN0_TX,
556 .end = IRQ_CAN0_TX,
557 .flags = IORESOURCE_IRQ,
558 },
559 {
560 .start = IRQ_CAN0_STAT,
561 .end = IRQ_CAN0_STAT,
562 .flags = IORESOURCE_IRQ,
563 },
564 };
565
566 static struct platform_device bfin_can0_device = {
567 .name = "bfin_can",
568 .id = 0,
569 .num_resources = ARRAY_SIZE(bfin_can0_resources),
570 .resource = bfin_can0_resources,
571 .dev = {
572 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
573 },
574 };
575
576 #endif
577
578 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
579 static struct mtd_partition partition_info[] = {
580 {
581 .name = "bootloader(nand)",
582 .offset = 0,
583 .size = 0x80000,
584 }, {
585 .name = "linux kernel(nand)",
586 .offset = MTDPART_OFS_APPEND,
587 .size = 4 * 1024 * 1024,
588 },
589 {
590 .name = "file system(nand)",
591 .offset = MTDPART_OFS_APPEND,
592 .size = MTDPART_SIZ_FULL,
593 },
594 };
595
596 static struct bf5xx_nand_platform bfin_nand_platform = {
597 .data_width = NFC_NWIDTH_8,
598 .partitions = partition_info,
599 .nr_partitions = ARRAY_SIZE(partition_info),
600 .rd_dly = 3,
601 .wr_dly = 3,
602 };
603
604 static struct resource bfin_nand_resources[] = {
605 {
606 .start = 0xFFC03B00,
607 .end = 0xFFC03B4F,
608 .flags = IORESOURCE_MEM,
609 },
610 {
611 .start = CH_NFC,
612 .end = CH_NFC,
613 .flags = IORESOURCE_IRQ,
614 },
615 };
616
617 static struct platform_device bfin_nand_device = {
618 .name = "bfin-nand",
619 .id = 0,
620 .num_resources = ARRAY_SIZE(bfin_nand_resources),
621 .resource = bfin_nand_resources,
622 .dev = {
623 .platform_data = &bfin_nand_platform,
624 },
625 };
626 #endif
627
628 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
629
630 static struct bfin_sd_host bfin_sdh_data = {
631 .dma_chan = CH_RSI,
632 .irq_int0 = IRQ_RSI_INT0,
633 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
634 };
635
636 static struct platform_device bfin_sdh_device = {
637 .name = "bfin-sdh",
638 .id = 0,
639 .dev = {
640 .platform_data = &bfin_sdh_data,
641 },
642 };
643 #endif
644
645 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
646 static struct mtd_partition ezkit_partitions[] = {
647 {
648 .name = "bootloader(nor)",
649 .size = 0x80000,
650 .offset = 0,
651 }, {
652 .name = "linux kernel(nor)",
653 .size = 0x400000,
654 .offset = MTDPART_OFS_APPEND,
655 }, {
656 .name = "file system(nor)",
657 .size = 0x1000000 - 0x80000 - 0x400000,
658 .offset = MTDPART_OFS_APPEND,
659 },
660 };
661
662 int bf609_nor_flash_init(struct platform_device *dev)
663 {
664 #define CONFIG_SMC_GCTL_VAL 0x00000010
665 const unsigned short pins[] = {
666 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
667 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
668 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
669 };
670
671 peripheral_request_list(pins, "smc0");
672
673 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
674 bfin_write32(SMC_B0CTL, 0x01002011);
675 bfin_write32(SMC_B0TIM, 0x08170977);
676 bfin_write32(SMC_B0ETIM, 0x00092231);
677 return 0;
678 }
679
680 void bf609_nor_flash_exit(struct platform_device *dev)
681 {
682 const unsigned short pins[] = {
683 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
684 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
685 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
686 };
687
688 peripheral_free_list(pins);
689
690 bfin_write32(SMC_GCTL, 0);
691 }
692
693 static struct physmap_flash_data ezkit_flash_data = {
694 .width = 2,
695 .parts = ezkit_partitions,
696 .init = bf609_nor_flash_init,
697 .exit = bf609_nor_flash_exit,
698 .nr_parts = ARRAY_SIZE(ezkit_partitions),
699 #ifdef CONFIG_ROMKERNEL
700 .probe_type = "map_rom",
701 #endif
702 };
703
704 static struct resource ezkit_flash_resource = {
705 .start = 0xb0000000,
706 .end = 0xb0ffffff,
707 .flags = IORESOURCE_MEM,
708 };
709
710 static struct platform_device ezkit_flash_device = {
711 .name = "physmap-flash",
712 .id = 0,
713 .dev = {
714 .platform_data = &ezkit_flash_data,
715 },
716 .num_resources = 1,
717 .resource = &ezkit_flash_resource,
718 };
719 #endif
720
721 #if defined(CONFIG_MTD_M25P80) \
722 || defined(CONFIG_MTD_M25P80_MODULE)
723 /* SPI flash chip (w25q32) */
724 static struct mtd_partition bfin_spi_flash_partitions[] = {
725 {
726 .name = "bootloader(spi)",
727 .size = 0x00080000,
728 .offset = 0,
729 .mask_flags = MTD_CAP_ROM
730 }, {
731 .name = "linux kernel(spi)",
732 .size = 0x00180000,
733 .offset = MTDPART_OFS_APPEND,
734 }, {
735 .name = "file system(spi)",
736 .size = MTDPART_SIZ_FULL,
737 .offset = MTDPART_OFS_APPEND,
738 }
739 };
740
741 static struct flash_platform_data bfin_spi_flash_data = {
742 .name = "m25p80",
743 .parts = bfin_spi_flash_partitions,
744 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
745 .type = "w25q32",
746 };
747
748 static struct bfin6xx_spi_chip spi_flash_chip_info = {
749 .enable_dma = true, /* use dma transfer with this chip*/
750 };
751 #endif
752
753 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
754 static struct bfin6xx_spi_chip spidev_chip_info = {
755 .enable_dma = true,
756 };
757 #endif
758
759 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
760 static struct platform_device bfin_i2s_pcm = {
761 .name = "bfin-i2s-pcm-audio",
762 .id = -1,
763 };
764 #endif
765
766 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
767 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
768 #include <asm/bfin_sport3.h>
769 static struct resource bfin_snd_resources[] = {
770 {
771 .start = SPORT0_CTL_A,
772 .end = SPORT0_CTL_A,
773 .flags = IORESOURCE_MEM,
774 },
775 {
776 .start = SPORT0_CTL_B,
777 .end = SPORT0_CTL_B,
778 .flags = IORESOURCE_MEM,
779 },
780 {
781 .start = CH_SPORT0_TX,
782 .end = CH_SPORT0_TX,
783 .flags = IORESOURCE_DMA,
784 },
785 {
786 .start = CH_SPORT0_RX,
787 .end = CH_SPORT0_RX,
788 .flags = IORESOURCE_DMA,
789 },
790 {
791 .start = IRQ_SPORT0_TX_STAT,
792 .end = IRQ_SPORT0_TX_STAT,
793 .flags = IORESOURCE_IRQ,
794 },
795 {
796 .start = IRQ_SPORT0_RX_STAT,
797 .end = IRQ_SPORT0_RX_STAT,
798 .flags = IORESOURCE_IRQ,
799 },
800 };
801
802 static const unsigned short bfin_snd_pin[] = {
803 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
804 P_SPORT0_BFS, P_SPORT0_BD0, 0,
805 };
806
807 static struct bfin_snd_platform_data bfin_snd_data = {
808 .pin_req = bfin_snd_pin,
809 };
810
811 static struct platform_device bfin_i2s = {
812 .name = "bfin-i2s",
813 .num_resources = ARRAY_SIZE(bfin_snd_resources),
814 .resource = bfin_snd_resources,
815 .dev = {
816 .platform_data = &bfin_snd_data,
817 },
818 };
819 #endif
820
821 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
822 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
823 static struct platform_device adau1761_device = {
824 .name = "bfin-eval-adau1x61",
825 };
826 #endif
827
828 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
829 #include <sound/adau17x1.h>
830 static struct adau1761_platform_data adau1761_info = {
831 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
832 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
833 };
834 #endif
835
836 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
837 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
838 #include <linux/videodev2.h>
839 #include <media/blackfin/bfin_capture.h>
840 #include <media/blackfin/ppi.h>
841
842 static const unsigned short ppi_req[] = {
843 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
844 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
845 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
846 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
847 #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
848 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
849 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
850 #endif
851 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
852 0,
853 };
854
855 static const struct ppi_info ppi_info = {
856 .type = PPI_TYPE_EPPI3,
857 .dma_ch = CH_EPPI0_CH0,
858 .irq_err = IRQ_EPPI0_STAT,
859 .base = (void __iomem *)EPPI0_STAT,
860 .pin_req = ppi_req,
861 };
862
863 #if defined(CONFIG_VIDEO_VS6624) \
864 || defined(CONFIG_VIDEO_VS6624_MODULE)
865 static struct v4l2_input vs6624_inputs[] = {
866 {
867 .index = 0,
868 .name = "Camera",
869 .type = V4L2_INPUT_TYPE_CAMERA,
870 .std = V4L2_STD_UNKNOWN,
871 },
872 };
873
874 static struct bcap_route vs6624_routes[] = {
875 {
876 .input = 0,
877 .output = 0,
878 },
879 };
880
881 static const unsigned vs6624_ce_pin = GPIO_PE4;
882
883 static struct bfin_capture_config bfin_capture_data = {
884 .card_name = "BF609",
885 .inputs = vs6624_inputs,
886 .num_inputs = ARRAY_SIZE(vs6624_inputs),
887 .routes = vs6624_routes,
888 .i2c_adapter_id = 0,
889 .board_info = {
890 .type = "vs6624",
891 .addr = 0x10,
892 .platform_data = (void *)&vs6624_ce_pin,
893 },
894 .ppi_info = &ppi_info,
895 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
896 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
897 .blank_pixels = 4,
898 };
899 #endif
900
901 #if defined(CONFIG_VIDEO_ADV7842) \
902 || defined(CONFIG_VIDEO_ADV7842_MODULE)
903 #include <media/adv7842.h>
904
905 static struct v4l2_input adv7842_inputs[] = {
906 {
907 .index = 0,
908 .name = "Composite",
909 .type = V4L2_INPUT_TYPE_CAMERA,
910 .std = V4L2_STD_ALL,
911 .capabilities = V4L2_IN_CAP_STD,
912 },
913 {
914 .index = 1,
915 .name = "S-Video",
916 .type = V4L2_INPUT_TYPE_CAMERA,
917 .std = V4L2_STD_ALL,
918 .capabilities = V4L2_IN_CAP_STD,
919 },
920 {
921 .index = 2,
922 .name = "Component",
923 .type = V4L2_INPUT_TYPE_CAMERA,
924 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
925 },
926 {
927 .index = 3,
928 .name = "VGA",
929 .type = V4L2_INPUT_TYPE_CAMERA,
930 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
931 },
932 {
933 .index = 4,
934 .name = "HDMI",
935 .type = V4L2_INPUT_TYPE_CAMERA,
936 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
937 },
938 };
939
940 static struct bcap_route adv7842_routes[] = {
941 {
942 .input = 3,
943 .output = 0,
944 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
945 | EPPI_CTL_ACTIVE656),
946 },
947 {
948 .input = 4,
949 .output = 0,
950 },
951 {
952 .input = 2,
953 .output = 0,
954 },
955 {
956 .input = 1,
957 .output = 0,
958 },
959 {
960 .input = 0,
961 .output = 1,
962 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
963 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
964 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
965 },
966 };
967
968 static struct adv7842_output_format adv7842_opf[] = {
969 {
970 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
971 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
972 .op_656_range = 1,
973 .blank_data = 1,
974 .insert_av_codes = 1,
975 },
976 {
977 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
978 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
979 .op_656_range = 1,
980 .blank_data = 1,
981 },
982 };
983
984 static struct adv7842_platform_data adv7842_data = {
985 .opf = adv7842_opf,
986 .num_opf = ARRAY_SIZE(adv7842_opf),
987 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
988 .prim_mode = ADV7842_PRIM_MODE_SDP,
989 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
990 .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
991 .i2c_sdp_io = 0x40,
992 .i2c_sdp = 0x41,
993 .i2c_cp = 0x42,
994 .i2c_vdp = 0x43,
995 .i2c_afe = 0x44,
996 .i2c_hdmi = 0x45,
997 .i2c_repeater = 0x46,
998 .i2c_edid = 0x47,
999 .i2c_infoframe = 0x48,
1000 .i2c_cec = 0x49,
1001 .i2c_avlink = 0x4a,
1002 .i2c_ex = 0x26,
1003 };
1004
1005 static struct bfin_capture_config bfin_capture_data = {
1006 .card_name = "BF609",
1007 .inputs = adv7842_inputs,
1008 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1009 .routes = adv7842_routes,
1010 .i2c_adapter_id = 0,
1011 .board_info = {
1012 .type = "adv7842",
1013 .addr = 0x20,
1014 .platform_data = (void *)&adv7842_data,
1015 },
1016 .ppi_info = &ppi_info,
1017 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1018 | EPPI_CTL_ACTIVE656),
1019 };
1020 #endif
1021
1022 static struct platform_device bfin_capture_device = {
1023 .name = "bfin_capture",
1024 .dev = {
1025 .platform_data = &bfin_capture_data,
1026 },
1027 };
1028 #endif
1029
1030 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1031 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1032 #include <linux/videodev2.h>
1033 #include <media/blackfin/bfin_display.h>
1034 #include <media/blackfin/ppi.h>
1035
1036 static const unsigned short ppi_req_disp[] = {
1037 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1038 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1039 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1040 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1041 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1042 0,
1043 };
1044
1045 static const struct ppi_info ppi_info = {
1046 .type = PPI_TYPE_EPPI3,
1047 .dma_ch = CH_EPPI0_CH0,
1048 .irq_err = IRQ_EPPI0_STAT,
1049 .base = (void __iomem *)EPPI0_STAT,
1050 .pin_req = ppi_req_disp,
1051 };
1052
1053 #if defined(CONFIG_VIDEO_ADV7511) \
1054 || defined(CONFIG_VIDEO_ADV7511_MODULE)
1055 #include <media/adv7511.h>
1056
1057 static struct v4l2_output adv7511_outputs[] = {
1058 {
1059 .index = 0,
1060 .name = "HDMI",
1061 .type = V4L2_INPUT_TYPE_CAMERA,
1062 .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
1063 },
1064 };
1065
1066 static struct disp_route adv7511_routes[] = {
1067 {
1068 .output = 0,
1069 },
1070 };
1071
1072 static struct adv7511_platform_data adv7511_data = {
1073 .edid_addr = 0x7e,
1074 .i2c_ex = 0x25,
1075 };
1076
1077 static struct bfin_display_config bfin_display_data = {
1078 .card_name = "BF609",
1079 .outputs = adv7511_outputs,
1080 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1081 .routes = adv7511_routes,
1082 .i2c_adapter_id = 0,
1083 .board_info = {
1084 .type = "adv7511",
1085 .addr = 0x39,
1086 .platform_data = (void *)&adv7511_data,
1087 },
1088 .ppi_info = &ppi_info,
1089 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1090 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1091 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1092 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1093 };
1094 #endif
1095
1096 static struct platform_device bfin_display_device = {
1097 .name = "bfin_display",
1098 .dev = {
1099 .platform_data = &bfin_display_data,
1100 },
1101 };
1102 #endif
1103
1104 #if defined(CONFIG_BFIN_CRC)
1105 #define BFIN_CRC_NAME "bfin-crc"
1106
1107 static struct resource bfin_crc0_resources[] = {
1108 {
1109 .start = REG_CRC0_CTL,
1110 .end = REG_CRC0_REVID+4,
1111 .flags = IORESOURCE_MEM,
1112 },
1113 {
1114 .start = IRQ_CRC0_DCNTEXP,
1115 .end = IRQ_CRC0_DCNTEXP,
1116 .flags = IORESOURCE_IRQ,
1117 },
1118 {
1119 .start = CH_MEM_STREAM0_SRC_CRC0,
1120 .end = CH_MEM_STREAM0_SRC_CRC0,
1121 .flags = IORESOURCE_DMA,
1122 },
1123 {
1124 .start = CH_MEM_STREAM0_DEST_CRC0,
1125 .end = CH_MEM_STREAM0_DEST_CRC0,
1126 .flags = IORESOURCE_DMA,
1127 },
1128 };
1129
1130 static struct platform_device bfin_crc0_device = {
1131 .name = BFIN_CRC_NAME,
1132 .id = 0,
1133 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1134 .resource = bfin_crc0_resources,
1135 };
1136
1137 static struct resource bfin_crc1_resources[] = {
1138 {
1139 .start = REG_CRC1_CTL,
1140 .end = REG_CRC1_REVID+4,
1141 .flags = IORESOURCE_MEM,
1142 },
1143 {
1144 .start = IRQ_CRC1_DCNTEXP,
1145 .end = IRQ_CRC1_DCNTEXP,
1146 .flags = IORESOURCE_IRQ,
1147 },
1148 {
1149 .start = CH_MEM_STREAM1_SRC_CRC1,
1150 .end = CH_MEM_STREAM1_SRC_CRC1,
1151 .flags = IORESOURCE_DMA,
1152 },
1153 {
1154 .start = CH_MEM_STREAM1_DEST_CRC1,
1155 .end = CH_MEM_STREAM1_DEST_CRC1,
1156 .flags = IORESOURCE_DMA,
1157 },
1158 };
1159
1160 static struct platform_device bfin_crc1_device = {
1161 .name = BFIN_CRC_NAME,
1162 .id = 1,
1163 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1164 .resource = bfin_crc1_resources,
1165 };
1166 #endif
1167
1168 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1169 #define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1170 #define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1171
1172 static struct resource bfin_crypto_crc_resources[] = {
1173 {
1174 .start = REG_CRC0_CTL,
1175 .end = REG_CRC0_REVID+4,
1176 .flags = IORESOURCE_MEM,
1177 },
1178 {
1179 .start = IRQ_CRC0_DCNTEXP,
1180 .end = IRQ_CRC0_DCNTEXP,
1181 .flags = IORESOURCE_IRQ,
1182 },
1183 {
1184 .start = CH_MEM_STREAM0_SRC_CRC0,
1185 .end = CH_MEM_STREAM0_SRC_CRC0,
1186 .flags = IORESOURCE_DMA,
1187 },
1188 };
1189
1190 static struct platform_device bfin_crypto_crc_device = {
1191 .name = BFIN_CRYPTO_CRC_NAME,
1192 .id = 0,
1193 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1194 .resource = bfin_crypto_crc_resources,
1195 .dev = {
1196 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1197 },
1198 };
1199 #endif
1200
1201 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1202 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1203 .model = 7877,
1204 .vref_delay_usecs = 50, /* internal, no capacitor */
1205 .x_plate_ohms = 419,
1206 .y_plate_ohms = 486,
1207 .pressure_max = 1000,
1208 .pressure_min = 0,
1209 .stopacq_polarity = 1,
1210 .first_conversion_delay = 3,
1211 .acquisition_time = 1,
1212 .averaging = 1,
1213 .pen_down_acc_interval = 1,
1214 };
1215 #endif
1216
1217 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1218 #include <linux/input.h>
1219 #include <linux/gpio_keys.h>
1220
1221 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1222 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1223 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1224 };
1225
1226 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1227 .buttons = bfin_gpio_keys_table,
1228 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1229 };
1230
1231 static struct platform_device bfin_device_gpiokeys = {
1232 .name = "gpio-keys",
1233 .dev = {
1234 .platform_data = &bfin_gpio_keys_data,
1235 },
1236 };
1237 #endif
1238
1239 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1240 #if defined(CONFIG_MTD_M25P80) \
1241 || defined(CONFIG_MTD_M25P80_MODULE)
1242 {
1243 /* the modalias must be the same as spi device driver name */
1244 .modalias = "m25p80", /* Name of spi_driver for this device */
1245 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1246 .bus_num = 0, /* Framework bus number */
1247 .chip_select = 1, /* SPI_SSEL1*/
1248 .platform_data = &bfin_spi_flash_data,
1249 .controller_data = &spi_flash_chip_info,
1250 .mode = SPI_MODE_3,
1251 },
1252 #endif
1253 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1254 {
1255 .modalias = "ad7877",
1256 .platform_data = &bfin_ad7877_ts_info,
1257 .irq = IRQ_PD9,
1258 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1259 .bus_num = 0,
1260 .chip_select = 4,
1261 },
1262 #endif
1263 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1264 {
1265 .modalias = "spidev",
1266 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1267 .bus_num = 0,
1268 .chip_select = 1,
1269 .controller_data = &spidev_chip_info,
1270 },
1271 #endif
1272 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1273 {
1274 .modalias = "adxl34x",
1275 .platform_data = &adxl34x_info,
1276 .irq = IRQ_PC5,
1277 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1278 .bus_num = 1,
1279 .chip_select = 2,
1280 .mode = SPI_MODE_3,
1281 },
1282 #endif
1283 };
1284 #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1285 /* SPI (0) */
1286 static struct resource bfin_spi0_resource[] = {
1287 {
1288 .start = SPI0_REGBASE,
1289 .end = SPI0_REGBASE + 0xFF,
1290 .flags = IORESOURCE_MEM,
1291 },
1292 {
1293 .start = CH_SPI0_TX,
1294 .end = CH_SPI0_TX,
1295 .flags = IORESOURCE_DMA,
1296 },
1297 {
1298 .start = CH_SPI0_RX,
1299 .end = CH_SPI0_RX,
1300 .flags = IORESOURCE_DMA,
1301 },
1302 };
1303
1304 /* SPI (1) */
1305 static struct resource bfin_spi1_resource[] = {
1306 {
1307 .start = SPI1_REGBASE,
1308 .end = SPI1_REGBASE + 0xFF,
1309 .flags = IORESOURCE_MEM,
1310 },
1311 {
1312 .start = CH_SPI1_TX,
1313 .end = CH_SPI1_TX,
1314 .flags = IORESOURCE_DMA,
1315 },
1316 {
1317 .start = CH_SPI1_RX,
1318 .end = CH_SPI1_RX,
1319 .flags = IORESOURCE_DMA,
1320 },
1321
1322 };
1323
1324 /* SPI controller data */
1325 static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
1326 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1327 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1328 };
1329
1330 static struct platform_device bf60x_spi_master0 = {
1331 .name = "bfin-spi",
1332 .id = 0, /* Bus number */
1333 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1334 .resource = bfin_spi0_resource,
1335 .dev = {
1336 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1337 },
1338 };
1339
1340 static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
1341 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1342 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1343 };
1344
1345 static struct platform_device bf60x_spi_master1 = {
1346 .name = "bfin-spi",
1347 .id = 1, /* Bus number */
1348 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1349 .resource = bfin_spi1_resource,
1350 .dev = {
1351 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1352 },
1353 };
1354 #endif /* spi master and devices */
1355
1356 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1357 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1358
1359 static struct resource bfin_twi0_resource[] = {
1360 [0] = {
1361 .start = TWI0_CLKDIV,
1362 .end = TWI0_CLKDIV + 0xFF,
1363 .flags = IORESOURCE_MEM,
1364 },
1365 [1] = {
1366 .start = IRQ_TWI0,
1367 .end = IRQ_TWI0,
1368 .flags = IORESOURCE_IRQ,
1369 },
1370 };
1371
1372 static struct platform_device i2c_bfin_twi0_device = {
1373 .name = "i2c-bfin-twi",
1374 .id = 0,
1375 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1376 .resource = bfin_twi0_resource,
1377 .dev = {
1378 .platform_data = &bfin_twi0_pins,
1379 },
1380 };
1381
1382 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1383
1384 static struct resource bfin_twi1_resource[] = {
1385 [0] = {
1386 .start = TWI1_CLKDIV,
1387 .end = TWI1_CLKDIV + 0xFF,
1388 .flags = IORESOURCE_MEM,
1389 },
1390 [1] = {
1391 .start = IRQ_TWI1,
1392 .end = IRQ_TWI1,
1393 .flags = IORESOURCE_IRQ,
1394 },
1395 };
1396
1397 static struct platform_device i2c_bfin_twi1_device = {
1398 .name = "i2c-bfin-twi",
1399 .id = 1,
1400 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1401 .resource = bfin_twi1_resource,
1402 .dev = {
1403 .platform_data = &bfin_twi1_pins,
1404 },
1405 };
1406 #endif
1407
1408 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1409 #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1410 {
1411 I2C_BOARD_INFO("adxl34x", 0x53),
1412 .irq = IRQ_PC5,
1413 .platform_data = (void *)&adxl34x_info,
1414 },
1415 #endif
1416 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1417 {
1418 I2C_BOARD_INFO("adau1761", 0x38),
1419 .platform_data = (void *)&adau1761_info
1420 },
1421 #endif
1422 #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1423 {
1424 I2C_BOARD_INFO("ssm2602", 0x1b),
1425 },
1426 #endif
1427 };
1428
1429 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1430 };
1431
1432 static const unsigned int cclk_vlev_datasheet[] =
1433 {
1434 /*
1435 * Internal VLEV BF54XSBBC1533
1436 ****temporarily using these values until data sheet is updated
1437 */
1438 VRPAIR(VLEV_085, 150000000),
1439 VRPAIR(VLEV_090, 250000000),
1440 VRPAIR(VLEV_110, 276000000),
1441 VRPAIR(VLEV_115, 301000000),
1442 VRPAIR(VLEV_120, 525000000),
1443 VRPAIR(VLEV_125, 550000000),
1444 VRPAIR(VLEV_130, 600000000),
1445 };
1446
1447 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1448 .tuple_tab = cclk_vlev_datasheet,
1449 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1450 .vr_settling_time = 25 /* us */,
1451 };
1452
1453 static struct platform_device bfin_dpmc = {
1454 .name = "bfin dpmc",
1455 .dev = {
1456 .platform_data = &bfin_dmpc_vreg_data,
1457 },
1458 };
1459
1460 static struct platform_device *ezkit_devices[] __initdata = {
1461
1462 &bfin_dpmc,
1463
1464 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1465 &rtc_device,
1466 #endif
1467
1468 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1469 #ifdef CONFIG_SERIAL_BFIN_UART0
1470 &bfin_uart0_device,
1471 #endif
1472 #ifdef CONFIG_SERIAL_BFIN_UART1
1473 &bfin_uart1_device,
1474 #endif
1475 #endif
1476
1477 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1478 #ifdef CONFIG_BFIN_SIR0
1479 &bfin_sir0_device,
1480 #endif
1481 #ifdef CONFIG_BFIN_SIR1
1482 &bfin_sir1_device,
1483 #endif
1484 #endif
1485
1486 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1487 &bfin_eth_device,
1488 #endif
1489
1490 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1491 &musb_device,
1492 #endif
1493
1494 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1495 &bfin_isp1760_device,
1496 #endif
1497
1498 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1499 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1500 &bfin_sport0_uart_device,
1501 #endif
1502 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1503 &bfin_sport1_uart_device,
1504 #endif
1505 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1506 &bfin_sport2_uart_device,
1507 #endif
1508 #endif
1509
1510 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1511 &bfin_can0_device,
1512 #endif
1513
1514 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1515 &bfin_nand_device,
1516 #endif
1517
1518 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1519 &bfin_sdh_device,
1520 #endif
1521
1522 #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1523 &bf60x_spi_master0,
1524 &bf60x_spi_master1,
1525 #endif
1526
1527 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
1528 &bfin_rotary_device,
1529 #endif
1530
1531 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1532 &i2c_bfin_twi0_device,
1533 #if !defined(CONFIG_BF542)
1534 &i2c_bfin_twi1_device,
1535 #endif
1536 #endif
1537
1538 #if defined(CONFIG_BFIN_CRC)
1539 &bfin_crc0_device,
1540 &bfin_crc1_device,
1541 #endif
1542 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1543 &bfin_crypto_crc_device,
1544 #endif
1545
1546 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1547 &bfin_device_gpiokeys,
1548 #endif
1549
1550 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1551 &ezkit_flash_device,
1552 #endif
1553 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1554 &bfin_i2s_pcm,
1555 #endif
1556 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
1557 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
1558 &bfin_i2s,
1559 #endif
1560 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
1561 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
1562 &adau1761_device,
1563 #endif
1564 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1565 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1566 &bfin_capture_device,
1567 #endif
1568 #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1569 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1570 &bfin_display_device,
1571 #endif
1572
1573 };
1574
1575 static int __init ezkit_init(void)
1576 {
1577 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1578
1579 i2c_register_board_info(0, bfin_i2c_board_info0,
1580 ARRAY_SIZE(bfin_i2c_board_info0));
1581 i2c_register_board_info(1, bfin_i2c_board_info1,
1582 ARRAY_SIZE(bfin_i2c_board_info1));
1583
1584 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1585 if (!peripheral_request_list(pins, "emac0"))
1586 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1587 #endif
1588
1589 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1590
1591 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
1592
1593 return 0;
1594 }
1595
1596 arch_initcall(ezkit_init);
1597
1598 static struct platform_device *ezkit_early_devices[] __initdata = {
1599 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1600 #ifdef CONFIG_SERIAL_BFIN_UART0
1601 &bfin_uart0_device,
1602 #endif
1603 #ifdef CONFIG_SERIAL_BFIN_UART1
1604 &bfin_uart1_device,
1605 #endif
1606 #endif
1607
1608 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1609 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1610 &bfin_sport0_uart_device,
1611 #endif
1612 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1613 &bfin_sport1_uart_device,
1614 #endif
1615 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1616 &bfin_sport2_uart_device,
1617 #endif
1618 #endif
1619 };
1620
1621 void __init native_machine_early_platform_add_devices(void)
1622 {
1623 printk(KERN_INFO "register early platform devices\n");
1624 early_platform_add_devices(ezkit_early_devices,
1625 ARRAY_SIZE(ezkit_early_devices));
1626 }
Linux ARM platform port for MOXA ART SoC