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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / m68k / include / asm / m532xsim.h
blob5ca7b298c6eb1686bb044c987a73b1f7196b2a04
1 /****************************************************************************/
2
3 /*
4 * m532xsim.h -- ColdFire 5329 registers
5 */
6
7 /****************************************************************************/
8 #ifndef m532xsim_h
9 #define m532xsim_h
10 /****************************************************************************/
11
12 #define CPU_NAME "COLDFIRE(m532x)"
13 #define CPU_INSTR_PER_JIFFY 3
14 #define MCF_BUSCLK (MCF_CLK / 3)
15
16 #include <asm/m53xxacr.h>
17
18 #define MCF_REG32(x) (*(volatile unsigned long *)(x))
19 #define MCF_REG16(x) (*(volatile unsigned short *)(x))
20 #define MCF_REG08(x) (*(volatile unsigned char *)(x))
21
22 #define MCFINT_VECBASE 64
23 #define MCFINT_UART0 26 /* Interrupt number for UART0 */
24 #define MCFINT_UART1 27 /* Interrupt number for UART1 */
25 #define MCFINT_UART2 28 /* Interrupt number for UART2 */
26 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */
27 #define MCFINT_FECRX0 36 /* Interrupt number for FEC */
28 #define MCFINT_FECTX0 40 /* Interrupt number for FEC */
29 #define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
30
31 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
32 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
33 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
34
35 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
36 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
37 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
38
39 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
40
41 #define MCF_WTM_WCR MCF_REG16(0xFC098000)
42
43 /*
44 * Define the 532x SIM register set addresses.
45 */
46 #define MCFSIM_IPRL 0xFC048004
47 #define MCFSIM_IPRH 0xFC048000
48 #define MCFSIM_IPR MCFSIM_IPRL
49 #define MCFSIM_IMRL 0xFC04800C
50 #define MCFSIM_IMRH 0xFC048008
51 #define MCFSIM_IMR MCFSIM_IMRL
52 #define MCFSIM_ICR0 0xFC048040
53 #define MCFSIM_ICR1 0xFC048041
54 #define MCFSIM_ICR2 0xFC048042
55 #define MCFSIM_ICR3 0xFC048043
56 #define MCFSIM_ICR4 0xFC048044
57 #define MCFSIM_ICR5 0xFC048045
58 #define MCFSIM_ICR6 0xFC048046
59 #define MCFSIM_ICR7 0xFC048047
60 #define MCFSIM_ICR8 0xFC048048
61 #define MCFSIM_ICR9 0xFC048049
62 #define MCFSIM_ICR10 0xFC04804A
63 #define MCFSIM_ICR11 0xFC04804B
64
65 /*
66 * Some symbol defines for the above...
67 */
68 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
69 #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
70 #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
71 #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
72 #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
73 #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
74 #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
75 #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
76 #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
77
78
79 #define MCFINTC0_SIMR 0xFC04801C
80 #define MCFINTC0_CIMR 0xFC04801D
81 #define MCFINTC0_ICR0 0xFC048040
82 #define MCFINTC1_SIMR 0xFC04C01C
83 #define MCFINTC1_CIMR 0xFC04C01D
84 #define MCFINTC1_ICR0 0xFC04C040
85 #define MCFINTC2_SIMR (0)
86 #define MCFINTC2_CIMR (0)
87 #define MCFINTC2_ICR0 (0)
88
89 #define MCFSIM_ICR_TIMER1 (0xFC048040+32)
90 #define MCFSIM_ICR_TIMER2 (0xFC048040+33)
91
92 /*
93 * Define system peripheral IRQ usage.
94 */
95 #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
96 #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
97
98 /*
99 * UART module.
100 */
101 #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
102 #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
103 #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
104
105 /*
106 * FEC module.
107 */
108 #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
109 #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
110
111 /*
112 * QSPI module.
113 */
114 #define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
115 #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
116
117 #define MCFQSPI_CS0 84
118 #define MCFQSPI_CS1 85
119 #define MCFQSPI_CS2 86
120
121 /*
122 * Timer module.
123 */
124 #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
125 #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
126 #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
127 #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
128
129 /*********************************************************************
130 *
131 * Reset Controller Module
132 *
133 *********************************************************************/
134
135 #define MCF_RCR 0xFC0A0000
136 #define MCF_RSR 0xFC0A0001
137
138 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
139 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
140
141
142 /*
143 * Power Management
144 */
145 #define MCFPM_WCR 0xfc040013
146 #define MCFPM_PPMSR0 0xfc04002c
147 #define MCFPM_PPMCR0 0xfc04002d
148 #define MCFPM_PPMSR1 0xfc04002e
149 #define MCFPM_PPMCR1 0xfc04002f
150 #define MCFPM_PPMHR0 0xfc040030
151 #define MCFPM_PPMLR0 0xfc040034
152 #define MCFPM_PPMHR1 0xfc040038
153 #define MCFPM_LPCR 0xec090007
154
155 /*********************************************************************
156 *
157 * Inter-IC (I2C) Module
158 *
159 *********************************************************************/
160
161 /* Read/Write access macros for general use */
162 #define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
163 #define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
164 #define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
165 #define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
166 #define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
167
168 /* Bit level definitions and macros */
169 #define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
170
171 #define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
172
173 #define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
174 #define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
175 #define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
176 #define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
177 #define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
178 #define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
179
180 #define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
181 #define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
182 #define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
183 #define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
184 #define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
185 #define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
186 #define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
187
188 #define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
189
190
191 /*
192 * The M5329EVB board needs a help getting its devices initialized
193 * at kernel start time if dBUG doesn't set it up (for example
194 * it is not used), so we need to do it manually.
195 */
196 #ifdef __ASSEMBLER__
197 .macro m5329EVB_setup
198 movel #0xFC098000, %a7
199 movel #0x0, (%a7)
200 #define CORE_SRAM 0x80000000
201 #define CORE_SRAM_SIZE 0x8000
202 movel #CORE_SRAM, %d0
203 addl #0x221, %d0
204 movec %d0,%RAMBAR1
205 movel #CORE_SRAM, %sp
206 addl #CORE_SRAM_SIZE, %sp
207 jsr sysinit
208 .endm
209 #define PLATFORM_SETUP m5329EVB_setup
210
211 #endif /* __ASSEMBLER__ */
212
213 /*********************************************************************
214 *
215 * Chip Configuration Module (CCM)
216 *
217 *********************************************************************/
218
219 /* Register read/write macros */
220 #define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
221 #define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
222 #define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
223 #define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
224 #define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
225 #define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
226 #define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
227
228 /* Bit definitions and macros for MCF_CCM_CCR */
229 #define MCF_CCM_CCR_RESERVED (0x0001)
230 #define MCF_CCM_CCR_PLL_MODE (0x0003)
231 #define MCF_CCM_CCR_OSC_MODE (0x0005)
232 #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
233 #define MCF_CCM_CCR_LOAD (0x0021)
234 #define MCF_CCM_CCR_LIMP (0x0041)
235 #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
236
237 /* Bit definitions and macros for MCF_CCM_RCON */
238 #define MCF_CCM_RCON_RESERVED (0x0001)
239 #define MCF_CCM_RCON_PLL_MODE (0x0003)
240 #define MCF_CCM_RCON_OSC_MODE (0x0005)
241 #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
242 #define MCF_CCM_RCON_LOAD (0x0021)
243 #define MCF_CCM_RCON_LIMP (0x0041)
244 #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
245
246 /* Bit definitions and macros for MCF_CCM_CIR */
247 #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
248 #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
249
250 /* Bit definitions and macros for MCF_CCM_MISCCR */
251 #define MCF_CCM_MISCCR_USBSRC (0x0001)
252 #define MCF_CCM_MISCCR_USBDIV (0x0002)
253 #define MCF_CCM_MISCCR_SSI_SRC (0x0010)
254 #define MCF_CCM_MISCCR_TIM_DMA (0x0020)
255 #define MCF_CCM_MISCCR_SSI_PUS (0x0040)
256 #define MCF_CCM_MISCCR_SSI_PUE (0x0080)
257 #define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
258 #define MCF_CCM_MISCCR_LIMP (0x1000)
259 #define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
260
261 /* Bit definitions and macros for MCF_CCM_CDR */
262 #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
263 #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
264
265 /* Bit definitions and macros for MCF_CCM_UHCSR */
266 #define MCF_CCM_UHCSR_XPDE (0x0001)
267 #define MCF_CCM_UHCSR_UHMIE (0x0002)
268 #define MCF_CCM_UHCSR_WKUP (0x0004)
269 #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
270
271 /* Bit definitions and macros for MCF_CCM_UOCSR */
272 #define MCF_CCM_UOCSR_XPDE (0x0001)
273 #define MCF_CCM_UOCSR_UOMIE (0x0002)
274 #define MCF_CCM_UOCSR_WKUP (0x0004)
275 #define MCF_CCM_UOCSR_PWRFLT (0x0008)
276 #define MCF_CCM_UOCSR_SEND (0x0010)
277 #define MCF_CCM_UOCSR_VVLD (0x0020)
278 #define MCF_CCM_UOCSR_BVLD (0x0040)
279 #define MCF_CCM_UOCSR_AVLD (0x0080)
280 #define MCF_CCM_UOCSR_DPPU (0x0100)
281 #define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
282 #define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
283 #define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
284 #define MCF_CCM_UOCSR_DMPD (0x1000)
285 #define MCF_CCM_UOCSR_DPPD (0x2000)
286 #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
287
288 /*********************************************************************
289 *
290 * DMA Timers (DTIM)
291 *
292 *********************************************************************/
293
294 /* Register read/write macros */
295 #define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
296 #define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
297 #define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
298 #define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
299 #define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
300 #define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
301 #define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
302 #define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
303 #define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
304 #define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
305 #define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
306 #define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
307 #define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
308 #define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
309 #define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
310 #define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
311 #define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
312 #define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
313 #define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
314 #define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
315 #define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
316 #define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
317 #define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
318 #define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
319 #define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
320 #define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
321 #define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
322 #define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
323 #define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
324 #define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
325
326 /* Bit definitions and macros for MCF_DTIM_DTMR */
327 #define MCF_DTIM_DTMR_RST (0x0001)
328 #define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
329 #define MCF_DTIM_DTMR_FRR (0x0008)
330 #define MCF_DTIM_DTMR_ORRI (0x0010)
331 #define MCF_DTIM_DTMR_OM (0x0020)
332 #define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
333 #define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
334 #define MCF_DTIM_DTMR_CE_ANY (0x00C0)
335 #define MCF_DTIM_DTMR_CE_FALL (0x0080)
336 #define MCF_DTIM_DTMR_CE_RISE (0x0040)
337 #define MCF_DTIM_DTMR_CE_NONE (0x0000)
338 #define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
339 #define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
340 #define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
341 #define MCF_DTIM_DTMR_CLK_STOP (0x0000)
342
343 /* Bit definitions and macros for MCF_DTIM_DTXMR */
344 #define MCF_DTIM_DTXMR_MODE16 (0x01)
345 #define MCF_DTIM_DTXMR_DMAEN (0x80)
346
347 /* Bit definitions and macros for MCF_DTIM_DTER */
348 #define MCF_DTIM_DTER_CAP (0x01)
349 #define MCF_DTIM_DTER_REF (0x02)
350
351 /* Bit definitions and macros for MCF_DTIM_DTRR */
352 #define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
353
354 /* Bit definitions and macros for MCF_DTIM_DTCR */
355 #define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
356
357 /* Bit definitions and macros for MCF_DTIM_DTCN */
358 #define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
359
360 /*********************************************************************
361 *
362 * FlexBus Chip Selects (FBCS)
363 *
364 *********************************************************************/
365
366 /* Register read/write macros */
367 #define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
368 #define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
369 #define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
370 #define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
371 #define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
372 #define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
373 #define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
374 #define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
375 #define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
376 #define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
377 #define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
378 #define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
379 #define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
380 #define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
381 #define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
382 #define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
383 #define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
384 #define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
385 #define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
386 #define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
387 #define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
388
389 /* Bit definitions and macros for MCF_FBCS_CSAR */
390 #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
391
392 /* Bit definitions and macros for MCF_FBCS_CSMR */
393 #define MCF_FBCS_CSMR_V (0x00000001)
394 #define MCF_FBCS_CSMR_WP (0x00000100)
395 #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
396 #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
397 #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
398 #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
399 #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
400 #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
401 #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
402 #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
403 #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
404 #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
405 #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
406 #define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
407 #define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
408 #define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
409 #define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
410 #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
411 #define MCF_FBCS_CSMR_BAM_512K (0x00070000)
412 #define MCF_FBCS_CSMR_BAM_256K (0x00030000)
413 #define MCF_FBCS_CSMR_BAM_128K (0x00010000)
414 #define MCF_FBCS_CSMR_BAM_64K (0x00000000)
415
416 /* Bit definitions and macros for MCF_FBCS_CSCR */
417 #define MCF_FBCS_CSCR_BSTW (0x00000008)
418 #define MCF_FBCS_CSCR_BSTR (0x00000010)
419 #define MCF_FBCS_CSCR_BEM (0x00000020)
420 #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
421 #define MCF_FBCS_CSCR_AA (0x00000100)
422 #define MCF_FBCS_CSCR_SBM (0x00000200)
423 #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
424 #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
425 #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
426 #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
427 #define MCF_FBCS_CSCR_SWSEN (0x00800000)
428 #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
429 #define MCF_FBCS_CSCR_PS_8 (0x0040)
430 #define MCF_FBCS_CSCR_PS_16 (0x0080)
431 #define MCF_FBCS_CSCR_PS_32 (0x0000)
432
433 /*********************************************************************
434 *
435 * General Purpose I/O (GPIO)
436 *
437 *********************************************************************/
438
439 /* Register read/write macros */
440 #define MCFGPIO_PODR_FECH (0xFC0A4000)
441 #define MCFGPIO_PODR_FECL (0xFC0A4001)
442 #define MCFGPIO_PODR_SSI (0xFC0A4002)
443 #define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
444 #define MCFGPIO_PODR_BE (0xFC0A4004)
445 #define MCFGPIO_PODR_CS (0xFC0A4005)
446 #define MCFGPIO_PODR_PWM (0xFC0A4006)
447 #define MCFGPIO_PODR_FECI2C (0xFC0A4007)
448 #define MCFGPIO_PODR_UART (0xFC0A4009)
449 #define MCFGPIO_PODR_QSPI (0xFC0A400A)
450 #define MCFGPIO_PODR_TIMER (0xFC0A400B)
451 #define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
452 #define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
453 #define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
454 #define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
455 #define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
456 #define MCFGPIO_PDDR_FECH (0xFC0A4014)
457 #define MCFGPIO_PDDR_FECL (0xFC0A4015)
458 #define MCFGPIO_PDDR_SSI (0xFC0A4016)
459 #define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
460 #define MCFGPIO_PDDR_BE (0xFC0A4018)
461 #define MCFGPIO_PDDR_CS (0xFC0A4019)
462 #define MCFGPIO_PDDR_PWM (0xFC0A401A)
463 #define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
464 #define MCFGPIO_PDDR_UART (0xFC0A401C)
465 #define MCFGPIO_PDDR_QSPI (0xFC0A401E)
466 #define MCFGPIO_PDDR_TIMER (0xFC0A401F)
467 #define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
468 #define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
469 #define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
470 #define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
471 #define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
472 #define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
473 #define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
474 #define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
475 #define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
476 #define MCFGPIO_PPDSDR_BE (0xFC0A402C)
477 #define MCFGPIO_PPDSDR_CS (0xFC0A402D)
478 #define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
479 #define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
480 #define MCFGPIO_PPDSDR_UART (0xFC0A4031)
481 #define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
482 #define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
483 #define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
484 #define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
485 #define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
486 #define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
487 #define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
488 #define MCFGPIO_PCLRR_FECH (0xFC0A403C)
489 #define MCFGPIO_PCLRR_FECL (0xFC0A403D)
490 #define MCFGPIO_PCLRR_SSI (0xFC0A403E)
491 #define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
492 #define MCFGPIO_PCLRR_BE (0xFC0A4040)
493 #define MCFGPIO_PCLRR_CS (0xFC0A4041)
494 #define MCFGPIO_PCLRR_PWM (0xFC0A4042)
495 #define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
496 #define MCFGPIO_PCLRR_UART (0xFC0A4045)
497 #define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
498 #define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
499 #define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
500 #define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
501 #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
502 #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
503 #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
504 #define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
505 #define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
506 #define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
507 #define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053)
508 #define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054)
509 #define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055)
510 #define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056)
511 #define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058)
512 #define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A)
513 #define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
514 #define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D)
515 #define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E)
516 #define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060)
517 #define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064)
518 #define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065)
519 #define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068)
520 #define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069)
521 #define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A)
522 #define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
523 #define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
524 #define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D)
525 #define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E)
526 #define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F)
527 #define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070)
528 #define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071)
529 #define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072)
530
531 /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
532 #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
533 #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
534 #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
535 #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
536 #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
537 #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
538 #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
539 #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
540
541 /* Bit definitions and macros for MCF_GPIO_PODR_FECL */
542 #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
543 #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
544 #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
545 #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
546 #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
547 #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
548 #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
549 #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
550
551 /* Bit definitions and macros for MCF_GPIO_PODR_SSI */
552 #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
553 #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
554 #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
555 #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
556 #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
557
558 /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
559 #define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
560 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
561 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
562 #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
563
564 /* Bit definitions and macros for MCF_GPIO_PODR_BE */
565 #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
566 #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
567 #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
568 #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
569
570 /* Bit definitions and macros for MCF_GPIO_PODR_CS */
571 #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
572 #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
573 #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
574 #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
575 #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
576
577 /* Bit definitions and macros for MCF_GPIO_PODR_PWM */
578 #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
579 #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
580 #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
581 #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
582
583 /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
584 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
585 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
586 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
587 #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
588
589 /* Bit definitions and macros for MCF_GPIO_PODR_UART */
590 #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
591 #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
592 #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
593 #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
594 #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
595 #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
596 #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
597 #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
598
599 /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
600 #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
601 #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
602 #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
603 #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
604 #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
605 #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
606
607 /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
608 #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
609 #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
610 #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
611 #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
612
613 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
614 #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
615 #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
616
617 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
618 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
619 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
620 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
621 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
622 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
623 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
624 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
625 #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
626
627 /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
628 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
629 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
630 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
631 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
632 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
633 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
634 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
635 #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
636
637 /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
638 #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
639
640 /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
641 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
642 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
643 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
644 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
645 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
646 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
647 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
648 #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
649
650 /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
651 #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
652 #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
653 #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
654 #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
655 #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
656 #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
657 #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
658 #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
659
660 /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
661 #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
662 #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
663 #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
664 #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
665 #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
666 #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
667 #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
668 #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
669
670 /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
671 #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
672 #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
673 #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
674 #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
675 #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
676
677 /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
678 #define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
679 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
680 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
681 #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
682
683 /* Bit definitions and macros for MCF_GPIO_PDDR_BE */
684 #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
685 #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
686 #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
687 #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
688
689 /* Bit definitions and macros for MCF_GPIO_PDDR_CS */
690 #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
691 #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
692 #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
693 #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
694 #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
695
696 /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
697 #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
698 #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
699 #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
700 #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
701
702 /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
703 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
704 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
705 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
706 #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
707
708 /* Bit definitions and macros for MCF_GPIO_PDDR_UART */
709 #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
710 #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
711 #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
712 #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
713 #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
714 #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
715 #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
716 #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
717
718 /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
719 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
720 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
721 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
722 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
723 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
724 #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
725
726 /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
727 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
728 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
729 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
730 #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
731
732 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
733 #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
734 #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
735
736 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
737 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
738 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
739 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
740 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
741 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
742 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
743 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
744 #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
745
746 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
747 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
748 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
749 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
750 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
751 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
752 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
753 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
754 #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
755
756 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
757 #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
758
759 /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
760 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
761 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
762 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
763 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
764 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
765 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
766 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
767 #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
768
769 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
770 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
771 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
772 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
773 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
774 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
775 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
776 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
777 #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
778
779 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
780 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
781 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
782 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
783 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
784 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
785 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
786 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
787 #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
788
789 /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
790 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
791 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
792 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
793 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
794 #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
795
796 /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
797 #define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
798 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
799 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
800 #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
801
802 /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
803 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
804 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
805 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
806 #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
807
808 /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
809 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
810 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
811 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
812 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
813 #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
814
815 /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
816 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
817 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
818 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
819 #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
820
821 /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
822 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
823 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
824 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
825 #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
826
827 /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
828 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
829 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
830 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
831 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
832 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
833 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
834 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
835 #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
836
837 /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
838 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
839 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
840 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
841 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
842 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
843 #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
844
845 /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
846 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
847 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
848 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
849 #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
850
851 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
852 #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
853 #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
854
855 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
856 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
857 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
858 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
859 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
860 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
861 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
862 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
863 #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
864
865 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
866 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
867 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
868 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
869 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
870 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
871 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
872 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
873 #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
874
875 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
876 #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
877
878 /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
879 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
880 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
881 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
882 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
883 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
884 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
885 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
886 #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
887
888 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
889 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
890 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
891 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
892 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
893 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
894 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
895 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
896 #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
897
898 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
899 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
900 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
901 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
902 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
903 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
904 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
905 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
906 #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
907
908 /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
909 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
910 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
911 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
912 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
913 #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
914
915 /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
916 #define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
917 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
918 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
919 #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
920
921 /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
922 #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
923 #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
924 #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
925 #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
926
927 /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
928 #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
929 #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
930 #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
931 #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
932 #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
933
934 /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
935 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
936 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
937 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
938 #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
939
940 /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
941 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
942 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
943 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
944 #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
945
946 /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
947 #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
948 #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
949 #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
950 #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
951 #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
952 #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
953 #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
954 #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
955
956 /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
957 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
958 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
959 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
960 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
961 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
962 #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
963
964 /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
965 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
966 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
967 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
968 #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
969
970 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
971 #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
972 #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
973
974 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
975 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
976 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
977 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
978 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
979 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
980 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
981 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
982 #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
983
984 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
985 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
986 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
987 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
988 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
989 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
990 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
991 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
992 #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
993
994 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
995 #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
996
997 /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
998 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
999 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
1000 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
1001 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
1002 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
1003 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
1004 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
1005 #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
1006
1007 /* Bit definitions and macros for MCF_GPIO_PAR_FEC */
1008 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
1009 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
1010 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
1011 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
1012 #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
1013 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
1014 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
1015 #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
1016
1017 /* Bit definitions and macros for MCF_GPIO_PAR_PWM */
1018 #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
1019 #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
1020 #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
1021 #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
1022
1023 /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
1024 #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
1025 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
1026 #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
1027 #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
1028 #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
1029 #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
1030 #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
1031 #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
1032 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
1033 #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
1034 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
1035 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
1036 #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
1037
1038 /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
1039 #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
1040 #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
1041 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
1042 #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
1043 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
1044 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
1045 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
1046 #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
1047 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
1048 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
1049 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
1050 #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
1051 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
1052 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
1053 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
1054 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
1055 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
1056 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
1057
1058 /* Bit definitions and macros for MCF_GPIO_PAR_BE */
1059 #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
1060 #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
1061 #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
1062 #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
1063
1064 /* Bit definitions and macros for MCF_GPIO_PAR_CS */
1065 #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
1066 #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
1067 #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
1068 #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
1069 #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
1070 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
1071 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
1072 #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
1073
1074 /* Bit definitions and macros for MCF_GPIO_PAR_SSI */
1075 #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
1076 #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
1077 #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
1078 #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
1079 #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
1080
1081 /* Bit definitions and macros for MCF_GPIO_PAR_UART */
1082 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
1083 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
1084 #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
1085 #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
1086 #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
1087 #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
1088 #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
1089 #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
1090 #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
1091 #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
1092 #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
1093 #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
1094 #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
1095 #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
1096 #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
1097 #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
1098 #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
1099 #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
1100 #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
1101 #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
1102 #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
1103 #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
1104 #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
1105 #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
1106
1107 /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
1108 #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
1109 #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
1110 #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
1111 #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
1112 #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
1113 #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
1114
1115 /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
1116 #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
1117 #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
1118 #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
1119 #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
1120 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
1121 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
1122 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
1123 #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
1124 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
1125 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
1126 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
1127 #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
1128 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
1129 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
1130 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
1131 #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
1132 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
1133 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
1134 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
1135 #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
1136
1137 /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
1138 #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
1139 #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
1140 #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
1141 #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
1142
1143 /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
1144 #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
1145 #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
1146 #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
1147 #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
1148 #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
1149 #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
1150 #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
1151 #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
1152 #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
1153
1154 /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
1155 #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
1156 #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
1157 #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
1158 #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
1159 #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
1160
1161 /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
1162 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
1163 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
1164 #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
1165
1166 /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
1167 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
1168 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
1169 #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
1170
1171 /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
1172 #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
1173
1174 /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
1175 #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
1176
1177 /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
1178 #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
1179
1180 /* Bit definitions and macros for MCF_GPIO_DSCR_UART */
1181 #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
1182 #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
1183
1184 /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
1185 #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
1186
1187 /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
1188 #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
1189
1190 /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
1191 #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
1192
1193 /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
1194 #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
1195
1196 /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
1197 #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
1198
1199 /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
1200 #define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
1201
1202 /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1203 #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
1204
1205 /*
1206 * Generic GPIO support
1207 */
1208 #define MCFGPIO_PODR MCFGPIO_PODR_FECH
1209 #define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
1210 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
1211 #define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
1212 #define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
1213
1214 #define MCFGPIO_PIN_MAX 136
1215 #define MCFGPIO_IRQ_MAX 8
1216 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1217
1218
1219 /*********************************************************************
1220 *
1221 * Interrupt Controller (INTC)
1222 *
1223 *********************************************************************/
1224
1225 /* Register read/write macros */
1226 #define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1227 #define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1228 #define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1229 #define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1230 #define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1231 #define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1232 #define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1233 #define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1234 #define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1235 #define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1236 #define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1237 #define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1238 #define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1239 #define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1240 #define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1241 #define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1242 #define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1243 #define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1244 #define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1245 #define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1246 #define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1247 #define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1248 #define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1249 #define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1250 #define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1251 #define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1252 #define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1253 #define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1254 #define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1255 #define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1256 #define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1257 #define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1258 #define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1259 #define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1260 #define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1261 #define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1262 #define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1263 #define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1264 #define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1265 #define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1266 #define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1267 #define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1268 #define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1269 #define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1270 #define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1271 #define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1272 #define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1273 #define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1274 #define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1275 #define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1276 #define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1277 #define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1278 #define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1279 #define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1280 #define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1281 #define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1282 #define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1283 #define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1284 #define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1285 #define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1286 #define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1287 #define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1288 #define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1289 #define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1290 #define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1291 #define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1292 #define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1293 #define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1294 #define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1295 #define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1296 #define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1297 #define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1298 #define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1299 #define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1300 #define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1301 #define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1302 #define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1303 #define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1304 #define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1305 #define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1306 #define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1307 #define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1308 #define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1309 #define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1310 #define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1311 #define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1312 #define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1313 #define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1314 #define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1315 #define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1316 #define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1317 #define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1318 #define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1319 #define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1320 #define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1321 #define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1322 #define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1323 #define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1324 #define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1325 #define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1326 #define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1327 #define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1328 #define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1329 #define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1330 #define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1331 #define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1332 #define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1333 #define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1334 #define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1335 #define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1336 #define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1337 #define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1338 #define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1339 #define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1340 #define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1341 #define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1342 #define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1343 #define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1344 #define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1345 #define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1346 #define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1347 #define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1348 #define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1349 #define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1350 #define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1351 #define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1352 #define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1353 #define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1354 #define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1355 #define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1356 #define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1357 #define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1358 #define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1359 #define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1360 #define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1361 #define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1362 #define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1363 #define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1364 #define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1365 #define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1366 #define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1367 #define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1368 #define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1369 #define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1370 #define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1371 #define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1372 #define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1373 #define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1374 #define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1375 #define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1376 #define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1377 #define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1378 #define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1379 #define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1380 #define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1381 #define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1382 #define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1383 #define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1384 #define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1385 #define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1386 #define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1387 #define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1388 #define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1389 #define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1390 #define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1391 #define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1392 #define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1393 #define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1394 #define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1395 #define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1396 #define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1397 #define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1398 #define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1399 #define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1400 #define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1401 #define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1402 #define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1403 #define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1404 #define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1405 #define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1406 #define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1407 #define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1408 #define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1409 #define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1410 #define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1411 #define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1412 #define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1413 #define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1414 #define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1415 #define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1416 #define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1417 #define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1418 #define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1419 #define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1420 #define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1421 #define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1422 #define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1423 #define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1424 #define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1425 #define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1426 #define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1427 #define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1428 #define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1429 #define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1430 #define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1431 #define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1432 #define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1433 #define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1434 #define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1435 #define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1436 #define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1437 #define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1438 #define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1439 #define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1440 #define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1441 #define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1442 #define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1443 #define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1444 #define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1445 #define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1446 #define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1447 #define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1448 #define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1449 #define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1450 #define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1451 #define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1452 #define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1453 #define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1454 #define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1455 #define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1456 #define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1457 #define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1458 #define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1459 #define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1460 #define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1461 #define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1462 #define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1463 #define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1464 #define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1465 #define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1466 #define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1467 #define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1468 #define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1469 #define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1470 #define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1471 #define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1472 #define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1473 #define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1474 #define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1475 #define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1476 #define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1477 #define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1478 #define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1479
1480 /* Bit definitions and macros for MCF_INTC_IPRH */
1481 #define MCF_INTC_IPRH_INT32 (0x00000001)
1482 #define MCF_INTC_IPRH_INT33 (0x00000002)
1483 #define MCF_INTC_IPRH_INT34 (0x00000004)
1484 #define MCF_INTC_IPRH_INT35 (0x00000008)
1485 #define MCF_INTC_IPRH_INT36 (0x00000010)
1486 #define MCF_INTC_IPRH_INT37 (0x00000020)
1487 #define MCF_INTC_IPRH_INT38 (0x00000040)
1488 #define MCF_INTC_IPRH_INT39 (0x00000080)
1489 #define MCF_INTC_IPRH_INT40 (0x00000100)
1490 #define MCF_INTC_IPRH_INT41 (0x00000200)
1491 #define MCF_INTC_IPRH_INT42 (0x00000400)
1492 #define MCF_INTC_IPRH_INT43 (0x00000800)
1493 #define MCF_INTC_IPRH_INT44 (0x00001000)
1494 #define MCF_INTC_IPRH_INT45 (0x00002000)
1495 #define MCF_INTC_IPRH_INT46 (0x00004000)
1496 #define MCF_INTC_IPRH_INT47 (0x00008000)
1497 #define MCF_INTC_IPRH_INT48 (0x00010000)
1498 #define MCF_INTC_IPRH_INT49 (0x00020000)
1499 #define MCF_INTC_IPRH_INT50 (0x00040000)
1500 #define MCF_INTC_IPRH_INT51 (0x00080000)
1501 #define MCF_INTC_IPRH_INT52 (0x00100000)
1502 #define MCF_INTC_IPRH_INT53 (0x00200000)
1503 #define MCF_INTC_IPRH_INT54 (0x00400000)
1504 #define MCF_INTC_IPRH_INT55 (0x00800000)
1505 #define MCF_INTC_IPRH_INT56 (0x01000000)
1506 #define MCF_INTC_IPRH_INT57 (0x02000000)
1507 #define MCF_INTC_IPRH_INT58 (0x04000000)
1508 #define MCF_INTC_IPRH_INT59 (0x08000000)
1509 #define MCF_INTC_IPRH_INT60 (0x10000000)
1510 #define MCF_INTC_IPRH_INT61 (0x20000000)
1511 #define MCF_INTC_IPRH_INT62 (0x40000000)
1512 #define MCF_INTC_IPRH_INT63 (0x80000000)
1513
1514 /* Bit definitions and macros for MCF_INTC_IPRL */
1515 #define MCF_INTC_IPRL_INT0 (0x00000001)
1516 #define MCF_INTC_IPRL_INT1 (0x00000002)
1517 #define MCF_INTC_IPRL_INT2 (0x00000004)
1518 #define MCF_INTC_IPRL_INT3 (0x00000008)
1519 #define MCF_INTC_IPRL_INT4 (0x00000010)
1520 #define MCF_INTC_IPRL_INT5 (0x00000020)
1521 #define MCF_INTC_IPRL_INT6 (0x00000040)
1522 #define MCF_INTC_IPRL_INT7 (0x00000080)
1523 #define MCF_INTC_IPRL_INT8 (0x00000100)
1524 #define MCF_INTC_IPRL_INT9 (0x00000200)
1525 #define MCF_INTC_IPRL_INT10 (0x00000400)
1526 #define MCF_INTC_IPRL_INT11 (0x00000800)
1527 #define MCF_INTC_IPRL_INT12 (0x00001000)
1528 #define MCF_INTC_IPRL_INT13 (0x00002000)
1529 #define MCF_INTC_IPRL_INT14 (0x00004000)
1530 #define MCF_INTC_IPRL_INT15 (0x00008000)
1531 #define MCF_INTC_IPRL_INT16 (0x00010000)
1532 #define MCF_INTC_IPRL_INT17 (0x00020000)
1533 #define MCF_INTC_IPRL_INT18 (0x00040000)
1534 #define MCF_INTC_IPRL_INT19 (0x00080000)
1535 #define MCF_INTC_IPRL_INT20 (0x00100000)
1536 #define MCF_INTC_IPRL_INT21 (0x00200000)
1537 #define MCF_INTC_IPRL_INT22 (0x00400000)
1538 #define MCF_INTC_IPRL_INT23 (0x00800000)
1539 #define MCF_INTC_IPRL_INT24 (0x01000000)
1540 #define MCF_INTC_IPRL_INT25 (0x02000000)
1541 #define MCF_INTC_IPRL_INT26 (0x04000000)
1542 #define MCF_INTC_IPRL_INT27 (0x08000000)
1543 #define MCF_INTC_IPRL_INT28 (0x10000000)
1544 #define MCF_INTC_IPRL_INT29 (0x20000000)
1545 #define MCF_INTC_IPRL_INT30 (0x40000000)
1546 #define MCF_INTC_IPRL_INT31 (0x80000000)
1547
1548 /* Bit definitions and macros for MCF_INTC_IMRH */
1549 #define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1550 #define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1551 #define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1552 #define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1553 #define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1554 #define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1555 #define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1556 #define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1557 #define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1558 #define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1559 #define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1560 #define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1561 #define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1562 #define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1563 #define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1564 #define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1565 #define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1566 #define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1567 #define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1568 #define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1569 #define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1570 #define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1571 #define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1572 #define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1573 #define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1574 #define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1575 #define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1576 #define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1577 #define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1578 #define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1579 #define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1580 #define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1581
1582 /* Bit definitions and macros for MCF_INTC_IMRL */
1583 #define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1584 #define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1585 #define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1586 #define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1587 #define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1588 #define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1589 #define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1590 #define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1591 #define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1592 #define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1593 #define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1594 #define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1595 #define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1596 #define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1597 #define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1598 #define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1599 #define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1600 #define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1601 #define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1602 #define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1603 #define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1604 #define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1605 #define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1606 #define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1607 #define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1608 #define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1609 #define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1610 #define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1611 #define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1612 #define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1613 #define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1614 #define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1615
1616 /* Bit definitions and macros for MCF_INTC_INTFRCH */
1617 #define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1618 #define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1619 #define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1620 #define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1621 #define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1622 #define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1623 #define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1624 #define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1625 #define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1626 #define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1627 #define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1628 #define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1629 #define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1630 #define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1631 #define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1632 #define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1633 #define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1634 #define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1635 #define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1636 #define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1637 #define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1638 #define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1639 #define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1640 #define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1641 #define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1642 #define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1643 #define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1644 #define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1645 #define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1646 #define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1647 #define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1648 #define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1649
1650 /* Bit definitions and macros for MCF_INTC_INTFRCL */
1651 #define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1652 #define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1653 #define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1654 #define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1655 #define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1656 #define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1657 #define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1658 #define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1659 #define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1660 #define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1661 #define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1662 #define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1663 #define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1664 #define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1665 #define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1666 #define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1667 #define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1668 #define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1669 #define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1670 #define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1671 #define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1672 #define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1673 #define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1674 #define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1675 #define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1676 #define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1677 #define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1678 #define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1679 #define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1680 #define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1681 #define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1682 #define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1683
1684 /* Bit definitions and macros for MCF_INTC_ICONFIG */
1685 #define MCF_INTC_ICONFIG_EMASK (0x0020)
1686 #define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1687 #define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1688 #define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1689 #define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1690 #define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1691 #define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1692 #define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1693
1694 /* Bit definitions and macros for MCF_INTC_SIMR */
1695 #define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1696
1697 /* Bit definitions and macros for MCF_INTC_CIMR */
1698 #define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1699
1700 /* Bit definitions and macros for MCF_INTC_CLMASK */
1701 #define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1702
1703 /* Bit definitions and macros for MCF_INTC_SLMASK */
1704 #define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1705
1706 /* Bit definitions and macros for MCF_INTC_ICR */
1707 #define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1708
1709 /* Bit definitions and macros for MCF_INTC_SWIACK */
1710 #define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1711
1712 /* Bit definitions and macros for MCF_INTC_LIACK */
1713 #define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1714
1715 /********************************************************************/
1716 /*********************************************************************
1717 *
1718 * LCD Controller (LCDC)
1719 *
1720 *********************************************************************/
1721
1722 /* Register read/write macros */
1723 #define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1724 #define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1725 #define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1726 #define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1727 #define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1728 #define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1729 #define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1730 #define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1731 #define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1732 #define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1733 #define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1734 #define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1735 #define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1736 #define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1737 #define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1738 #define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1739 #define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1740 #define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1741 #define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1742 #define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1743 #define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1744 #define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1745 #define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1746 #define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1747 #define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1748 #define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1749
1750 /* Bit definitions and macros for MCF_LCDC_LSSAR */
1751 #define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1752
1753 /* Bit definitions and macros for MCF_LCDC_LSR */
1754 #define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1755 #define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1756
1757 /* Bit definitions and macros for MCF_LCDC_LVPWR */
1758 #define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1759
1760 /* Bit definitions and macros for MCF_LCDC_LCPR */
1761 #define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1762 #define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1763 #define MCF_LCDC_LCPR_OP (0x10000000)
1764 #define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1765 #define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1766 #define MCF_LCDC_LCPR_CC_OR (0x40000000)
1767 #define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1768 #define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1769 #define MCF_LCDC_LCPR_OP_ON (0x10000000)
1770 #define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1771
1772 /* Bit definitions and macros for MCF_LCDC_LCWHBR */
1773 #define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1774 #define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1775 #define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1776 #define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1777 #define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1778 #define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1779
1780 /* Bit definitions and macros for MCF_LCDC_LCCMR */
1781 #define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1782 #define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1783 #define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1784
1785 /* Bit definitions and macros for MCF_LCDC_LPCR */
1786 #define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1787 #define MCF_LCDC_LPCR_SHARP (0x00000040)
1788 #define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1789 #define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1790 #define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1791 #define MCF_LCDC_LPCR_REV_VS (0x00010000)
1792 #define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1793 #define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1794 #define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1795 #define MCF_LCDC_LPCR_OEPOL (0x00100000)
1796 #define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1797 #define MCF_LCDC_LPCR_LPPOL (0x00400000)
1798 #define MCF_LCDC_LPCR_FLM (0x00800000)
1799 #define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1800 #define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1801 #define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1802 #define MCF_LCDC_LPCR_COLOR (0x40000000)
1803 #define MCF_LCDC_LPCR_TFT (0x80000000)
1804 #define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1805 #define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1806 #define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1807 #define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1808 #define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1809 #define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1810 #define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1811 #define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1812 #define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1813 #define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1814 #define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1815 #define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1816 #define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1817 #define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1818
1819 #define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1820
1821 /* Bit definitions and macros for MCF_LCDC_LHCR */
1822 #define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1823 #define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1824 #define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1825
1826 /* Bit definitions and macros for MCF_LCDC_LVCR */
1827 #define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1828 #define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1829 #define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1830
1831 /* Bit definitions and macros for MCF_LCDC_LPOR */
1832 #define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1833
1834 /* Bit definitions and macros for MCF_LCDC_LPCCR */
1835 #define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1836 #define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1837 #define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1838 #define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1839 #define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1840 #define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1841 #define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1842 #define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1843
1844 /* Bit definitions and macros for MCF_LCDC_LDCR */
1845 #define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1846 #define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1847 #define MCF_LCDC_LDCR_BURST (0x80000000)
1848
1849 /* Bit definitions and macros for MCF_LCDC_LRMCR */
1850 #define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1851
1852 /* Bit definitions and macros for MCF_LCDC_LICR */
1853 #define MCF_LCDC_LICR_INTCON (0x00000001)
1854 #define MCF_LCDC_LICR_INTSYN (0x00000004)
1855 #define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1856
1857 /* Bit definitions and macros for MCF_LCDC_LIER */
1858 #define MCF_LCDC_LIER_BOF_EN (0x00000001)
1859 #define MCF_LCDC_LIER_EOF_EN (0x00000002)
1860 #define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1861 #define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1862 #define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1863 #define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1864 #define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1865 #define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1866
1867 /* Bit definitions and macros for MCF_LCDC_LISR */
1868 #define MCF_LCDC_LISR_BOF (0x00000001)
1869 #define MCF_LCDC_LISR_EOF (0x00000002)
1870 #define MCF_LCDC_LISR_ERR_RES (0x00000004)
1871 #define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1872 #define MCF_LCDC_LISR_GW_BOF (0x00000010)
1873 #define MCF_LCDC_LISR_GW_EOF (0x00000020)
1874 #define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1875 #define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1876
1877 /* Bit definitions and macros for MCF_LCDC_LGWSAR */
1878 #define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1879
1880 /* Bit definitions and macros for MCF_LCDC_LGWSR */
1881 #define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1882 #define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1883
1884 /* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1885 #define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1886
1887 /* Bit definitions and macros for MCF_LCDC_LGWPOR */
1888 #define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1889
1890 /* Bit definitions and macros for MCF_LCDC_LGWPR */
1891 #define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1892 #define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1893
1894 /* Bit definitions and macros for MCF_LCDC_LGWCR */
1895 #define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1896 #define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1897 #define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1898 #define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1899 #define MCF_LCDC_LGWCR_GWE (0x00400000)
1900 #define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1901 #define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1902
1903 /* Bit definitions and macros for MCF_LCDC_LGWDCR */
1904 #define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1905 #define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1906 #define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1907
1908 /* Bit definitions and macros for MCF_LCDC_LSCR */
1909 #define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1910 #define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1911 #define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1912 #define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1913 #define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1914
1915 /* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1916 #define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1917
1918 /* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1919 #define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1920
1921 /*********************************************************************
1922 *
1923 * Phase Locked Loop (PLL)
1924 *
1925 *********************************************************************/
1926
1927 /* Register read/write macros */
1928 #define MCF_PLL_PODR MCF_REG08(0xFC0C0000)
1929 #define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
1930 #define MCF_PLL_PMDR MCF_REG08(0xFC0C0008)
1931 #define MCF_PLL_PFDR MCF_REG08(0xFC0C000C)
1932
1933 /* Bit definitions and macros for MCF_PLL_PODR */
1934 #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
1935 #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1936
1937 /* Bit definitions and macros for MCF_PLL_PLLCR */
1938 #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
1939 #define MCF_PLL_PLLCR_DITHEN (0x80)
1940
1941 /* Bit definitions and macros for MCF_PLL_PMDR */
1942 #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
1943
1944 /* Bit definitions and macros for MCF_PLL_PFDR */
1945 #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
1946
1947 /*********************************************************************
1948 *
1949 * System Control Module Registers (SCM)
1950 *
1951 *********************************************************************/
1952
1953 /* Register read/write macros */
1954 #define MCF_SCM_MPR MCF_REG32(0xFC000000)
1955 #define MCF_SCM_PACRA MCF_REG32(0xFC000020)
1956 #define MCF_SCM_PACRB MCF_REG32(0xFC000024)
1957 #define MCF_SCM_PACRC MCF_REG32(0xFC000028)
1958 #define MCF_SCM_PACRD MCF_REG32(0xFC00002C)
1959 #define MCF_SCM_PACRE MCF_REG32(0xFC000040)
1960 #define MCF_SCM_PACRF MCF_REG32(0xFC000044)
1961
1962 #define MCF_SCM_BCR MCF_REG32(0xFC040024)
1963
1964 /*********************************************************************
1965 *
1966 * SDRAM Controller (SDRAMC)
1967 *
1968 *********************************************************************/
1969
1970 /* Register read/write macros */
1971 #define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000)
1972 #define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004)
1973 #define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008)
1974 #define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C)
1975 #define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080)
1976 #define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100)
1977 #define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110)
1978 #define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114)
1979 #define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118)
1980 #define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C)
1981 #define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
1982
1983 /* Bit definitions and macros for MCF_SDRAMC_SDMR */
1984 #define MCF_SDRAMC_SDMR_CMD (0x00010000)
1985 #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1986 #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
1987 #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1988 #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1989
1990 /* Bit definitions and macros for MCF_SDRAMC_SDCR */
1991 #define MCF_SDRAMC_SDCR_IPALL (0x00000002)
1992 #define MCF_SDRAMC_SDCR_IREF (0x00000004)
1993 #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1994 #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
1995 #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1996 #define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
1997 #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1998 #define MCF_SDRAMC_SDCR_REF (0x10000000)
1999 #define MCF_SDRAMC_SDCR_DDR (0x20000000)
2000 #define MCF_SDRAMC_SDCR_CKE (0x40000000)
2001 #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
2002 #define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
2003 #define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
2004
2005 /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
2006 #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
2007 #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
2008 #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
2009 #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
2010 #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
2011 #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
2012 #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
2013
2014 /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
2015 #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
2016 #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
2017 #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
2018 #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
2019
2020 /* Device Errata - LIMP mode work around */
2021 #define MCF_SDRAMC_REFRESH (0x40000000)
2022
2023 /* Bit definitions and macros for MCF_SDRAMC_SDDS */
2024 #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
2025 #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
2026 #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
2027 #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
2028 #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
2029
2030 /* Bit definitions and macros for MCF_SDRAMC_SDCS */
2031 #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
2032 #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
2033 #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
2034 #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
2035 #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
2036 #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
2037 #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
2038 #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
2039 #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
2040 #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
2041 #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
2042 #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
2043 #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
2044 #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
2045 #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
2046 #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
2047 #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
2048
2049 /*********************************************************************
2050 *
2051 * FlexCAN module registers
2052 *
2053 *********************************************************************/
2054 #define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2055 #define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2056 #define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2057 #define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2058 #define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2059 #define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2060 #define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2061 #define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2062 #define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2063 #define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2064 #define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2065
2066 #define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2067 #define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2068 #define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2069
2070 /*
2071 * FlexCAN Module Configuration Register
2072 */
2073 #define CANMCR_MDIS (0x80000000)
2074 #define CANMCR_FRZ (0x40000000)
2075 #define CANMCR_HALT (0x10000000)
2076 #define CANMCR_SOFTRST (0x02000000)
2077 #define CANMCR_FRZACK (0x01000000)
2078 #define CANMCR_SUPV (0x00800000)
2079 #define CANMCR_MAXMB(x) ((x)&0x0F)
2080
2081 /*
2082 * FlexCAN Control Register
2083 */
2084 #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2085 #define CANCTRL_RJW(x) (((x)&0x03)<<22)
2086 #define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2087 #define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2088 #define CANCTRL_BOFFMSK (0x00008000)
2089 #define CANCTRL_ERRMSK (0x00004000)
2090 #define CANCTRL_CLKSRC (0x00002000)
2091 #define CANCTRL_LPB (0x00001000)
2092 #define CANCTRL_SAMP (0x00000080)
2093 #define CANCTRL_BOFFREC (0x00000040)
2094 #define CANCTRL_TSYNC (0x00000020)
2095 #define CANCTRL_LBUF (0x00000010)
2096 #define CANCTRL_LOM (0x00000008)
2097 #define CANCTRL_PROPSEG(x) ((x)&0x07)
2098
2099 /*
2100 * FlexCAN Error Counter Register
2101 */
2102 #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2103 #define ERRCNT_TXECTR(x) ((x)&0xFF)
2104
2105 /*
2106 * FlexCAN Error and Status Register
2107 */
2108 #define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2109 #define ERRSTAT_ACKERR (0x00002000)
2110 #define ERRSTAT_CRCERR (0x00001000)
2111 #define ERRSTAT_FRMERR (0x00000800)
2112 #define ERRSTAT_STFERR (0x00000400)
2113 #define ERRSTAT_TXWRN (0x00000200)
2114 #define ERRSTAT_RXWRN (0x00000100)
2115 #define ERRSTAT_IDLE (0x00000080)
2116 #define ERRSTAT_TXRX (0x00000040)
2117 #define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2118 #define ERRSTAT_BOFFINT (0x00000004)
2119 #define ERRSTAT_ERRINT (0x00000002)
2120
2121 /*
2122 * Interrupt Mask Register
2123 */
2124 #define IMASK_BUF15M (0x8000)
2125 #define IMASK_BUF14M (0x4000)
2126 #define IMASK_BUF13M (0x2000)
2127 #define IMASK_BUF12M (0x1000)
2128 #define IMASK_BUF11M (0x0800)
2129 #define IMASK_BUF10M (0x0400)
2130 #define IMASK_BUF9M (0x0200)
2131 #define IMASK_BUF8M (0x0100)
2132 #define IMASK_BUF7M (0x0080)
2133 #define IMASK_BUF6M (0x0040)
2134 #define IMASK_BUF5M (0x0020)
2135 #define IMASK_BUF4M (0x0010)
2136 #define IMASK_BUF3M (0x0008)
2137 #define IMASK_BUF2M (0x0004)
2138 #define IMASK_BUF1M (0x0002)
2139 #define IMASK_BUF0M (0x0001)
2140 #define IMASK_BUFnM(x) (0x1<<(x))
2141 #define IMASK_BUFF_ENABLE_ALL (0x1111)
2142 #define IMASK_BUFF_DISABLE_ALL (0x0000)
2143
2144 /*
2145 * Interrupt Flag Register
2146 */
2147 #define IFLAG_BUF15M (0x8000)
2148 #define IFLAG_BUF14M (0x4000)
2149 #define IFLAG_BUF13M (0x2000)
2150 #define IFLAG_BUF12M (0x1000)
2151 #define IFLAG_BUF11M (0x0800)
2152 #define IFLAG_BUF10M (0x0400)
2153 #define IFLAG_BUF9M (0x0200)
2154 #define IFLAG_BUF8M (0x0100)
2155 #define IFLAG_BUF7M (0x0080)
2156 #define IFLAG_BUF6M (0x0040)
2157 #define IFLAG_BUF5M (0x0020)
2158 #define IFLAG_BUF4M (0x0010)
2159 #define IFLAG_BUF3M (0x0008)
2160 #define IFLAG_BUF2M (0x0004)
2161 #define IFLAG_BUF1M (0x0002)
2162 #define IFLAG_BUF0M (0x0001)
2163 #define IFLAG_BUFF_SET_ALL (0xFFFF)
2164 #define IFLAG_BUFF_CLEAR_ALL (0x0000)
2165 #define IFLAG_BUFnM(x) (0x1<<(x))
2166
2167 /*
2168 * Message Buffers
2169 */
2170 #define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2171 #define MB_CNT_SRR (0x00400000)
2172 #define MB_CNT_IDE (0x00200000)
2173 #define MB_CNT_RTR (0x00100000)
2174 #define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2175 #define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2176 #define MB_ID_STD(x) (((x)&0x07FF)<<18)
2177 #define MB_ID_EXT(x) ((x)&0x3FFFF)
2178
2179 /*********************************************************************
2180 *
2181 * Edge Port Module (EPORT)
2182 *
2183 *********************************************************************/
2184
2185 /* Register read/write macros */
2186 #define MCFEPORT_EPPAR (0xFC094000)
2187 #define MCFEPORT_EPDDR (0xFC094002)
2188 #define MCFEPORT_EPIER (0xFC094003)
2189 #define MCFEPORT_EPDR (0xFC094004)
2190 #define MCFEPORT_EPPDR (0xFC094005)
2191 #define MCFEPORT_EPFR (0xFC094006)
2192
2193 /* Bit definitions and macros for MCF_EPORT_EPPAR */
2194 #define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2195 #define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2196 #define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2197 #define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2198 #define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2199 #define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2200 #define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2201 #define MCF_EPORT_EPPAR_LEVEL (0)
2202 #define MCF_EPORT_EPPAR_RISING (1)
2203 #define MCF_EPORT_EPPAR_FALLING (2)
2204 #define MCF_EPORT_EPPAR_BOTH (3)
2205 #define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2206 #define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2207 #define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2208 #define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2209 #define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2210 #define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2211 #define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2212 #define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2213 #define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2214 #define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2215 #define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2216 #define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2217 #define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2218 #define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2219 #define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2220 #define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2221 #define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2222 #define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2223 #define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2224 #define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2225 #define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2226 #define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2227 #define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2228 #define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2229 #define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2230 #define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2231 #define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2232 #define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2233
2234 /* Bit definitions and macros for MCF_EPORT_EPDDR */
2235 #define MCF_EPORT_EPDDR_EPDD1 (0x02)
2236 #define MCF_EPORT_EPDDR_EPDD2 (0x04)
2237 #define MCF_EPORT_EPDDR_EPDD3 (0x08)
2238 #define MCF_EPORT_EPDDR_EPDD4 (0x10)
2239 #define MCF_EPORT_EPDDR_EPDD5 (0x20)
2240 #define MCF_EPORT_EPDDR_EPDD6 (0x40)
2241 #define MCF_EPORT_EPDDR_EPDD7 (0x80)
2242
2243 /* Bit definitions and macros for MCF_EPORT_EPIER */
2244 #define MCF_EPORT_EPIER_EPIE1 (0x02)
2245 #define MCF_EPORT_EPIER_EPIE2 (0x04)
2246 #define MCF_EPORT_EPIER_EPIE3 (0x08)
2247 #define MCF_EPORT_EPIER_EPIE4 (0x10)
2248 #define MCF_EPORT_EPIER_EPIE5 (0x20)
2249 #define MCF_EPORT_EPIER_EPIE6 (0x40)
2250 #define MCF_EPORT_EPIER_EPIE7 (0x80)
2251
2252 /* Bit definitions and macros for MCF_EPORT_EPDR */
2253 #define MCF_EPORT_EPDR_EPD1 (0x02)
2254 #define MCF_EPORT_EPDR_EPD2 (0x04)
2255 #define MCF_EPORT_EPDR_EPD3 (0x08)
2256 #define MCF_EPORT_EPDR_EPD4 (0x10)
2257 #define MCF_EPORT_EPDR_EPD5 (0x20)
2258 #define MCF_EPORT_EPDR_EPD6 (0x40)
2259 #define MCF_EPORT_EPDR_EPD7 (0x80)
2260
2261 /* Bit definitions and macros for MCF_EPORT_EPPDR */
2262 #define MCF_EPORT_EPPDR_EPPD1 (0x02)
2263 #define MCF_EPORT_EPPDR_EPPD2 (0x04)
2264 #define MCF_EPORT_EPPDR_EPPD3 (0x08)
2265 #define MCF_EPORT_EPPDR_EPPD4 (0x10)
2266 #define MCF_EPORT_EPPDR_EPPD5 (0x20)
2267 #define MCF_EPORT_EPPDR_EPPD6 (0x40)
2268 #define MCF_EPORT_EPPDR_EPPD7 (0x80)
2269
2270 /* Bit definitions and macros for MCF_EPORT_EPFR */
2271 #define MCF_EPORT_EPFR_EPF1 (0x02)
2272 #define MCF_EPORT_EPFR_EPF2 (0x04)
2273 #define MCF_EPORT_EPFR_EPF3 (0x08)
2274 #define MCF_EPORT_EPFR_EPF4 (0x10)
2275 #define MCF_EPORT_EPFR_EPF5 (0x20)
2276 #define MCF_EPORT_EPFR_EPF6 (0x40)
2277 #define MCF_EPORT_EPFR_EPF7 (0x80)
2278
2279 /********************************************************************/
2280 #endif /* m532xsim_h */
Linux ARM platform port for MOXA ART SoC