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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / mips / include / asm / mach-bcm63xx / bcm63xx_cpu.h
blobe104ddb694a88b0c6a0556a2eef8dad22a3a537f
1 #ifndef BCM63XX_CPU_H_
2 #define BCM63XX_CPU_H_
3
4 #include <linux/types.h>
5 #include <linux/init.h>
6
7 /*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12 #define BCM6328_CPU_ID 0x6328
13 #define BCM6338_CPU_ID 0x6338
14 #define BCM6345_CPU_ID 0x6345
15 #define BCM6348_CPU_ID 0x6348
16 #define BCM6358_CPU_ID 0x6358
17 #define BCM6368_CPU_ID 0x6368
18
19 void __init bcm63xx_cpu_init(void);
20 u16 __bcm63xx_get_cpu_id(void);
21 u16 bcm63xx_get_cpu_rev(void);
22 unsigned int bcm63xx_get_cpu_freq(void);
23
24 #ifdef CONFIG_BCM63XX_CPU_6328
25 # ifdef bcm63xx_get_cpu_id
26 # undef bcm63xx_get_cpu_id
27 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28 # define BCMCPU_RUNTIME_DETECT
29 # else
30 # define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31 # endif
32 # define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33 #else
34 # define BCMCPU_IS_6328() (0)
35 #endif
36
37 #ifdef CONFIG_BCM63XX_CPU_6338
38 # ifdef bcm63xx_get_cpu_id
39 # undef bcm63xx_get_cpu_id
40 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
41 # define BCMCPU_RUNTIME_DETECT
42 # else
43 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
44 # endif
45 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
46 #else
47 # define BCMCPU_IS_6338() (0)
48 #endif
49
50 #ifdef CONFIG_BCM63XX_CPU_6345
51 # ifdef bcm63xx_get_cpu_id
52 # undef bcm63xx_get_cpu_id
53 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
54 # define BCMCPU_RUNTIME_DETECT
55 # else
56 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
57 # endif
58 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
59 #else
60 # define BCMCPU_IS_6345() (0)
61 #endif
62
63 #ifdef CONFIG_BCM63XX_CPU_6348
64 # ifdef bcm63xx_get_cpu_id
65 # undef bcm63xx_get_cpu_id
66 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
67 # define BCMCPU_RUNTIME_DETECT
68 # else
69 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
70 # endif
71 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
72 #else
73 # define BCMCPU_IS_6348() (0)
74 #endif
75
76 #ifdef CONFIG_BCM63XX_CPU_6358
77 # ifdef bcm63xx_get_cpu_id
78 # undef bcm63xx_get_cpu_id
79 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
80 # define BCMCPU_RUNTIME_DETECT
81 # else
82 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
83 # endif
84 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
85 #else
86 # define BCMCPU_IS_6358() (0)
87 #endif
88
89 #ifdef CONFIG_BCM63XX_CPU_6368
90 # ifdef bcm63xx_get_cpu_id
91 # undef bcm63xx_get_cpu_id
92 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
93 # define BCMCPU_RUNTIME_DETECT
94 # else
95 # define bcm63xx_get_cpu_id() BCM6368_CPU_ID
96 # endif
97 # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
98 #else
99 # define BCMCPU_IS_6368() (0)
100 #endif
101
102 #ifndef bcm63xx_get_cpu_id
103 #error "No CPU support configured"
104 #endif
105
106 /*
107 * While registers sets are (mostly) the same across 63xx CPU, base
108 * address of these sets do change.
109 */
110 enum bcm63xx_regs_set {
111 RSET_DSL_LMEM = 0,
112 RSET_PERF,
113 RSET_TIMER,
114 RSET_WDT,
115 RSET_UART0,
116 RSET_UART1,
117 RSET_GPIO,
118 RSET_SPI,
119 RSET_UDC0,
120 RSET_OHCI0,
121 RSET_OHCI_PRIV,
122 RSET_USBH_PRIV,
123 RSET_MPI,
124 RSET_PCMCIA,
125 RSET_PCIE,
126 RSET_DSL,
127 RSET_ENET0,
128 RSET_ENET1,
129 RSET_ENETDMA,
130 RSET_ENETDMAC,
131 RSET_ENETDMAS,
132 RSET_ENETSW,
133 RSET_EHCI0,
134 RSET_SDRAM,
135 RSET_MEMC,
136 RSET_DDR,
137 RSET_M2M,
138 RSET_ATM,
139 RSET_XTM,
140 RSET_XTMDMA,
141 RSET_XTMDMAC,
142 RSET_XTMDMAS,
143 RSET_PCM,
144 RSET_PCMDMA,
145 RSET_PCMDMAC,
146 RSET_PCMDMAS,
147 RSET_RNG,
148 RSET_MISC
149 };
150
151 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
152 #define RSET_DSL_SIZE 4096
153 #define RSET_WDT_SIZE 12
154 #define BCM_6338_RSET_SPI_SIZE 64
155 #define BCM_6348_RSET_SPI_SIZE 64
156 #define BCM_6358_RSET_SPI_SIZE 1804
157 #define BCM_6368_RSET_SPI_SIZE 1804
158 #define RSET_ENET_SIZE 2048
159 #define RSET_ENETDMA_SIZE 2048
160 #define RSET_ENETSW_SIZE 65536
161 #define RSET_UART_SIZE 24
162 #define RSET_UDC_SIZE 256
163 #define RSET_OHCI_SIZE 256
164 #define RSET_EHCI_SIZE 256
165 #define RSET_PCMCIA_SIZE 12
166 #define RSET_M2M_SIZE 256
167 #define RSET_ATM_SIZE 4096
168 #define RSET_XTM_SIZE 10240
169 #define RSET_XTMDMA_SIZE 256
170 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
171 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
172 #define RSET_RNG_SIZE 20
173
174 /*
175 * 6328 register sets base address
176 */
177 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
178 #define BCM_6328_PERF_BASE (0xb0000000)
179 #define BCM_6328_TIMER_BASE (0xb0000040)
180 #define BCM_6328_WDT_BASE (0xb000005c)
181 #define BCM_6328_UART0_BASE (0xb0000100)
182 #define BCM_6328_UART1_BASE (0xb0000120)
183 #define BCM_6328_GPIO_BASE (0xb0000080)
184 #define BCM_6328_SPI_BASE (0xdeadbeef)
185 #define BCM_6328_UDC0_BASE (0xdeadbeef)
186 #define BCM_6328_USBDMA_BASE (0xdeadbeef)
187 #define BCM_6328_OHCI0_BASE (0xdeadbeef)
188 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
189 #define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
190 #define BCM_6328_MPI_BASE (0xdeadbeef)
191 #define BCM_6328_PCMCIA_BASE (0xdeadbeef)
192 #define BCM_6328_PCIE_BASE (0xb0e40000)
193 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
194 #define BCM_6328_DSL_BASE (0xb0001900)
195 #define BCM_6328_UBUS_BASE (0xdeadbeef)
196 #define BCM_6328_ENET0_BASE (0xdeadbeef)
197 #define BCM_6328_ENET1_BASE (0xdeadbeef)
198 #define BCM_6328_ENETDMA_BASE (0xb000d800)
199 #define BCM_6328_ENETDMAC_BASE (0xb000da00)
200 #define BCM_6328_ENETDMAS_BASE (0xb000dc00)
201 #define BCM_6328_ENETSW_BASE (0xb0e00000)
202 #define BCM_6328_EHCI0_BASE (0x10002500)
203 #define BCM_6328_SDRAM_BASE (0xdeadbeef)
204 #define BCM_6328_MEMC_BASE (0xdeadbeef)
205 #define BCM_6328_DDR_BASE (0xb0003000)
206 #define BCM_6328_M2M_BASE (0xdeadbeef)
207 #define BCM_6328_ATM_BASE (0xdeadbeef)
208 #define BCM_6328_XTM_BASE (0xdeadbeef)
209 #define BCM_6328_XTMDMA_BASE (0xb000b800)
210 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
211 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
212 #define BCM_6328_PCM_BASE (0xb000a800)
213 #define BCM_6328_PCMDMA_BASE (0xdeadbeef)
214 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
215 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
216 #define BCM_6328_RNG_BASE (0xdeadbeef)
217 #define BCM_6328_MISC_BASE (0xb0001800)
218 /*
219 * 6338 register sets base address
220 */
221 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
222 #define BCM_6338_PERF_BASE (0xfffe0000)
223 #define BCM_6338_BB_BASE (0xfffe0100)
224 #define BCM_6338_TIMER_BASE (0xfffe0200)
225 #define BCM_6338_WDT_BASE (0xfffe021c)
226 #define BCM_6338_UART0_BASE (0xfffe0300)
227 #define BCM_6338_UART1_BASE (0xdeadbeef)
228 #define BCM_6338_GPIO_BASE (0xfffe0400)
229 #define BCM_6338_SPI_BASE (0xfffe0c00)
230 #define BCM_6338_UDC0_BASE (0xdeadbeef)
231 #define BCM_6338_USBDMA_BASE (0xfffe2400)
232 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
233 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
234 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
235 #define BCM_6338_MPI_BASE (0xfffe3160)
236 #define BCM_6338_PCMCIA_BASE (0xdeadbeef)
237 #define BCM_6338_PCIE_BASE (0xdeadbeef)
238 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
239 #define BCM_6338_DSL_BASE (0xfffe1000)
240 #define BCM_6338_UBUS_BASE (0xdeadbeef)
241 #define BCM_6338_ENET0_BASE (0xfffe2800)
242 #define BCM_6338_ENET1_BASE (0xdeadbeef)
243 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
244 #define BCM_6338_ENETDMAC_BASE (0xfffe2500)
245 #define BCM_6338_ENETDMAS_BASE (0xfffe2600)
246 #define BCM_6338_ENETSW_BASE (0xdeadbeef)
247 #define BCM_6338_EHCI0_BASE (0xdeadbeef)
248 #define BCM_6338_SDRAM_BASE (0xfffe3100)
249 #define BCM_6338_MEMC_BASE (0xdeadbeef)
250 #define BCM_6338_DDR_BASE (0xdeadbeef)
251 #define BCM_6338_M2M_BASE (0xdeadbeef)
252 #define BCM_6338_ATM_BASE (0xfffe2000)
253 #define BCM_6338_XTM_BASE (0xdeadbeef)
254 #define BCM_6338_XTMDMA_BASE (0xdeadbeef)
255 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
256 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
257 #define BCM_6338_PCM_BASE (0xdeadbeef)
258 #define BCM_6338_PCMDMA_BASE (0xdeadbeef)
259 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
260 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
261 #define BCM_6338_RNG_BASE (0xdeadbeef)
262 #define BCM_6338_MISC_BASE (0xdeadbeef)
263
264 /*
265 * 6345 register sets base address
266 */
267 #define BCM_6345_DSL_LMEM_BASE (0xfff00000)
268 #define BCM_6345_PERF_BASE (0xfffe0000)
269 #define BCM_6345_BB_BASE (0xfffe0100)
270 #define BCM_6345_TIMER_BASE (0xfffe0200)
271 #define BCM_6345_WDT_BASE (0xfffe021c)
272 #define BCM_6345_UART0_BASE (0xfffe0300)
273 #define BCM_6345_UART1_BASE (0xdeadbeef)
274 #define BCM_6345_GPIO_BASE (0xfffe0400)
275 #define BCM_6345_SPI_BASE (0xdeadbeef)
276 #define BCM_6345_UDC0_BASE (0xdeadbeef)
277 #define BCM_6345_USBDMA_BASE (0xfffe2800)
278 #define BCM_6345_ENET0_BASE (0xfffe1800)
279 #define BCM_6345_ENETDMA_BASE (0xfffe2800)
280 #define BCM_6345_ENETDMAC_BASE (0xfffe2900)
281 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
282 #define BCM_6345_ENETSW_BASE (0xdeadbeef)
283 #define BCM_6345_PCMCIA_BASE (0xfffe2028)
284 #define BCM_6345_MPI_BASE (0xfffe2000)
285 #define BCM_6345_PCIE_BASE (0xdeadbeef)
286 #define BCM_6345_OHCI0_BASE (0xfffe2100)
287 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
288 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
289 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
290 #define BCM_6345_DSL_BASE (0xdeadbeef)
291 #define BCM_6345_UBUS_BASE (0xdeadbeef)
292 #define BCM_6345_ENET1_BASE (0xdeadbeef)
293 #define BCM_6345_EHCI0_BASE (0xdeadbeef)
294 #define BCM_6345_SDRAM_BASE (0xfffe2300)
295 #define BCM_6345_MEMC_BASE (0xdeadbeef)
296 #define BCM_6345_DDR_BASE (0xdeadbeef)
297 #define BCM_6345_M2M_BASE (0xdeadbeef)
298 #define BCM_6345_ATM_BASE (0xfffe4000)
299 #define BCM_6345_XTM_BASE (0xdeadbeef)
300 #define BCM_6345_XTMDMA_BASE (0xdeadbeef)
301 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
302 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
303 #define BCM_6345_PCM_BASE (0xdeadbeef)
304 #define BCM_6345_PCMDMA_BASE (0xdeadbeef)
305 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
306 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
307 #define BCM_6345_RNG_BASE (0xdeadbeef)
308 #define BCM_6345_MISC_BASE (0xdeadbeef)
309
310 /*
311 * 6348 register sets base address
312 */
313 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
314 #define BCM_6348_PERF_BASE (0xfffe0000)
315 #define BCM_6348_TIMER_BASE (0xfffe0200)
316 #define BCM_6348_WDT_BASE (0xfffe021c)
317 #define BCM_6348_UART0_BASE (0xfffe0300)
318 #define BCM_6348_UART1_BASE (0xdeadbeef)
319 #define BCM_6348_GPIO_BASE (0xfffe0400)
320 #define BCM_6348_SPI_BASE (0xfffe0c00)
321 #define BCM_6348_UDC0_BASE (0xfffe1000)
322 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
323 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
324 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
325 #define BCM_6348_MPI_BASE (0xfffe2000)
326 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
327 #define BCM_6348_PCIE_BASE (0xdeadbeef)
328 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
329 #define BCM_6348_M2M_BASE (0xfffe2800)
330 #define BCM_6348_DSL_BASE (0xfffe3000)
331 #define BCM_6348_ENET0_BASE (0xfffe6000)
332 #define BCM_6348_ENET1_BASE (0xfffe6800)
333 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
334 #define BCM_6348_ENETDMAC_BASE (0xfffe7100)
335 #define BCM_6348_ENETDMAS_BASE (0xfffe7200)
336 #define BCM_6348_ENETSW_BASE (0xdeadbeef)
337 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
338 #define BCM_6348_SDRAM_BASE (0xfffe2300)
339 #define BCM_6348_MEMC_BASE (0xdeadbeef)
340 #define BCM_6348_DDR_BASE (0xdeadbeef)
341 #define BCM_6348_ATM_BASE (0xfffe4000)
342 #define BCM_6348_XTM_BASE (0xdeadbeef)
343 #define BCM_6348_XTMDMA_BASE (0xdeadbeef)
344 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
345 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
346 #define BCM_6348_PCM_BASE (0xdeadbeef)
347 #define BCM_6348_PCMDMA_BASE (0xdeadbeef)
348 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
349 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
350 #define BCM_6348_RNG_BASE (0xdeadbeef)
351 #define BCM_6348_MISC_BASE (0xdeadbeef)
352
353 /*
354 * 6358 register sets base address
355 */
356 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
357 #define BCM_6358_PERF_BASE (0xfffe0000)
358 #define BCM_6358_TIMER_BASE (0xfffe0040)
359 #define BCM_6358_WDT_BASE (0xfffe005c)
360 #define BCM_6358_UART0_BASE (0xfffe0100)
361 #define BCM_6358_UART1_BASE (0xfffe0120)
362 #define BCM_6358_GPIO_BASE (0xfffe0080)
363 #define BCM_6358_SPI_BASE (0xfffe0800)
364 #define BCM_6358_UDC0_BASE (0xfffe0800)
365 #define BCM_6358_OHCI0_BASE (0xfffe1400)
366 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
367 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
368 #define BCM_6358_MPI_BASE (0xfffe1000)
369 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
370 #define BCM_6358_PCIE_BASE (0xdeadbeef)
371 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
372 #define BCM_6358_M2M_BASE (0xdeadbeef)
373 #define BCM_6358_DSL_BASE (0xfffe3000)
374 #define BCM_6358_ENET0_BASE (0xfffe4000)
375 #define BCM_6358_ENET1_BASE (0xfffe4800)
376 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
377 #define BCM_6358_ENETDMAC_BASE (0xfffe5100)
378 #define BCM_6358_ENETDMAS_BASE (0xfffe5200)
379 #define BCM_6358_ENETSW_BASE (0xdeadbeef)
380 #define BCM_6358_EHCI0_BASE (0xfffe1300)
381 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
382 #define BCM_6358_MEMC_BASE (0xfffe1200)
383 #define BCM_6358_DDR_BASE (0xfffe12a0)
384 #define BCM_6358_ATM_BASE (0xfffe2000)
385 #define BCM_6358_XTM_BASE (0xdeadbeef)
386 #define BCM_6358_XTMDMA_BASE (0xdeadbeef)
387 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
388 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
389 #define BCM_6358_PCM_BASE (0xfffe1600)
390 #define BCM_6358_PCMDMA_BASE (0xfffe1800)
391 #define BCM_6358_PCMDMAC_BASE (0xfffe1900)
392 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
393 #define BCM_6358_RNG_BASE (0xdeadbeef)
394 #define BCM_6358_MISC_BASE (0xdeadbeef)
395
396
397 /*
398 * 6368 register sets base address
399 */
400 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
401 #define BCM_6368_PERF_BASE (0xb0000000)
402 #define BCM_6368_TIMER_BASE (0xb0000040)
403 #define BCM_6368_WDT_BASE (0xb000005c)
404 #define BCM_6368_UART0_BASE (0xb0000100)
405 #define BCM_6368_UART1_BASE (0xb0000120)
406 #define BCM_6368_GPIO_BASE (0xb0000080)
407 #define BCM_6368_SPI_BASE (0xb0000800)
408 #define BCM_6368_UDC0_BASE (0xdeadbeef)
409 #define BCM_6368_OHCI0_BASE (0xb0001600)
410 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
411 #define BCM_6368_USBH_PRIV_BASE (0xb0001700)
412 #define BCM_6368_MPI_BASE (0xb0001000)
413 #define BCM_6368_PCMCIA_BASE (0xb0001054)
414 #define BCM_6368_PCIE_BASE (0xdeadbeef)
415 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
416 #define BCM_6368_M2M_BASE (0xdeadbeef)
417 #define BCM_6368_DSL_BASE (0xdeadbeef)
418 #define BCM_6368_ENET0_BASE (0xdeadbeef)
419 #define BCM_6368_ENET1_BASE (0xdeadbeef)
420 #define BCM_6368_ENETDMA_BASE (0xb0006800)
421 #define BCM_6368_ENETDMAC_BASE (0xb0006a00)
422 #define BCM_6368_ENETDMAS_BASE (0xb0006c00)
423 #define BCM_6368_ENETSW_BASE (0xb0f00000)
424 #define BCM_6368_EHCI0_BASE (0xb0001500)
425 #define BCM_6368_SDRAM_BASE (0xdeadbeef)
426 #define BCM_6368_MEMC_BASE (0xb0001200)
427 #define BCM_6368_DDR_BASE (0xb0001280)
428 #define BCM_6368_ATM_BASE (0xdeadbeef)
429 #define BCM_6368_XTM_BASE (0xb0001800)
430 #define BCM_6368_XTMDMA_BASE (0xb0005000)
431 #define BCM_6368_XTMDMAC_BASE (0xb0005200)
432 #define BCM_6368_XTMDMAS_BASE (0xb0005400)
433 #define BCM_6368_PCM_BASE (0xb0004000)
434 #define BCM_6368_PCMDMA_BASE (0xb0005800)
435 #define BCM_6368_PCMDMAC_BASE (0xb0005a00)
436 #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
437 #define BCM_6368_RNG_BASE (0xb0004180)
438 #define BCM_6368_MISC_BASE (0xdeadbeef)
439
440
441 extern const unsigned long *bcm63xx_regs_base;
442
443 #define __GEN_RSET_BASE(__cpu, __rset) \
444 case RSET_## __rset : \
445 return BCM_## __cpu ##_## __rset ##_BASE;
446
447 #define __GEN_RSET(__cpu) \
448 switch (set) { \
449 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
450 __GEN_RSET_BASE(__cpu, PERF) \
451 __GEN_RSET_BASE(__cpu, TIMER) \
452 __GEN_RSET_BASE(__cpu, WDT) \
453 __GEN_RSET_BASE(__cpu, UART0) \
454 __GEN_RSET_BASE(__cpu, UART1) \
455 __GEN_RSET_BASE(__cpu, GPIO) \
456 __GEN_RSET_BASE(__cpu, SPI) \
457 __GEN_RSET_BASE(__cpu, UDC0) \
458 __GEN_RSET_BASE(__cpu, OHCI0) \
459 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
460 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
461 __GEN_RSET_BASE(__cpu, MPI) \
462 __GEN_RSET_BASE(__cpu, PCMCIA) \
463 __GEN_RSET_BASE(__cpu, PCIE) \
464 __GEN_RSET_BASE(__cpu, DSL) \
465 __GEN_RSET_BASE(__cpu, ENET0) \
466 __GEN_RSET_BASE(__cpu, ENET1) \
467 __GEN_RSET_BASE(__cpu, ENETDMA) \
468 __GEN_RSET_BASE(__cpu, ENETDMAC) \
469 __GEN_RSET_BASE(__cpu, ENETDMAS) \
470 __GEN_RSET_BASE(__cpu, ENETSW) \
471 __GEN_RSET_BASE(__cpu, EHCI0) \
472 __GEN_RSET_BASE(__cpu, SDRAM) \
473 __GEN_RSET_BASE(__cpu, MEMC) \
474 __GEN_RSET_BASE(__cpu, DDR) \
475 __GEN_RSET_BASE(__cpu, M2M) \
476 __GEN_RSET_BASE(__cpu, ATM) \
477 __GEN_RSET_BASE(__cpu, XTM) \
478 __GEN_RSET_BASE(__cpu, XTMDMA) \
479 __GEN_RSET_BASE(__cpu, XTMDMAC) \
480 __GEN_RSET_BASE(__cpu, XTMDMAS) \
481 __GEN_RSET_BASE(__cpu, PCM) \
482 __GEN_RSET_BASE(__cpu, PCMDMA) \
483 __GEN_RSET_BASE(__cpu, PCMDMAC) \
484 __GEN_RSET_BASE(__cpu, PCMDMAS) \
485 __GEN_RSET_BASE(__cpu, RNG) \
486 __GEN_RSET_BASE(__cpu, MISC) \
487 }
488
489 #define __GEN_CPU_REGS_TABLE(__cpu) \
490 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
491 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
492 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
493 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
494 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
495 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
496 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
497 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
498 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
499 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
500 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
501 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
502 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
503 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
504 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
505 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
506 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
507 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
508 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
509 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
510 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
511 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
512 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
513 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
514 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
515 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
516 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
517 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
518 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
519 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
520 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
521 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
522 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
523 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
524 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
525 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
526 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
527 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
528
529
530 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
531 {
532 #ifdef BCMCPU_RUNTIME_DETECT
533 return bcm63xx_regs_base[set];
534 #else
535 #ifdef CONFIG_BCM63XX_CPU_6328
536 __GEN_RSET(6328)
537 #endif
538 #ifdef CONFIG_BCM63XX_CPU_6338
539 __GEN_RSET(6338)
540 #endif
541 #ifdef CONFIG_BCM63XX_CPU_6345
542 __GEN_RSET(6345)
543 #endif
544 #ifdef CONFIG_BCM63XX_CPU_6348
545 __GEN_RSET(6348)
546 #endif
547 #ifdef CONFIG_BCM63XX_CPU_6358
548 __GEN_RSET(6358)
549 #endif
550 #ifdef CONFIG_BCM63XX_CPU_6368
551 __GEN_RSET(6368)
552 #endif
553 #endif
554 /* unreached */
555 return 0;
556 }
557
558 /*
559 * IRQ number changes across CPU too
560 */
561 enum bcm63xx_irq {
562 IRQ_TIMER = 0,
563 IRQ_SPI,
564 IRQ_UART0,
565 IRQ_UART1,
566 IRQ_DSL,
567 IRQ_ENET0,
568 IRQ_ENET1,
569 IRQ_ENET_PHY,
570 IRQ_OHCI0,
571 IRQ_EHCI0,
572 IRQ_ENET0_RXDMA,
573 IRQ_ENET0_TXDMA,
574 IRQ_ENET1_RXDMA,
575 IRQ_ENET1_TXDMA,
576 IRQ_PCI,
577 IRQ_PCMCIA,
578 IRQ_ATM,
579 IRQ_ENETSW_RXDMA0,
580 IRQ_ENETSW_RXDMA1,
581 IRQ_ENETSW_RXDMA2,
582 IRQ_ENETSW_RXDMA3,
583 IRQ_ENETSW_TXDMA0,
584 IRQ_ENETSW_TXDMA1,
585 IRQ_ENETSW_TXDMA2,
586 IRQ_ENETSW_TXDMA3,
587 IRQ_XTM,
588 IRQ_XTM_DMA0,
589 };
590
591 /*
592 * 6328 irqs
593 */
594 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
595
596 #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
597 #define BCM_6328_SPI_IRQ 0
598 #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
599 #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
600 #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
601 #define BCM_6328_UDC0_IRQ 0
602 #define BCM_6328_ENET0_IRQ 0
603 #define BCM_6328_ENET1_IRQ 0
604 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
605 #define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
606 #define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
607 #define BCM_6328_PCMCIA_IRQ 0
608 #define BCM_6328_ENET0_RXDMA_IRQ 0
609 #define BCM_6328_ENET0_TXDMA_IRQ 0
610 #define BCM_6328_ENET1_RXDMA_IRQ 0
611 #define BCM_6328_ENET1_TXDMA_IRQ 0
612 #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
613 #define BCM_6328_ATM_IRQ 0
614 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
615 #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
616 #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
617 #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
618 #define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
619 #define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
620 #define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
621 #define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
622 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
623 #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
624
625 #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
626 #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
627 #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
628 #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
629 #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
630 #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
631
632 /*
633 * 6338 irqs
634 */
635 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
636 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
637 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
638 #define BCM_6338_UART1_IRQ 0
639 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
640 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
641 #define BCM_6338_ENET1_IRQ 0
642 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
643 #define BCM_6338_OHCI0_IRQ 0
644 #define BCM_6338_EHCI0_IRQ 0
645 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
646 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
647 #define BCM_6338_ENET1_RXDMA_IRQ 0
648 #define BCM_6338_ENET1_TXDMA_IRQ 0
649 #define BCM_6338_PCI_IRQ 0
650 #define BCM_6338_PCMCIA_IRQ 0
651 #define BCM_6338_ATM_IRQ 0
652 #define BCM_6338_ENETSW_RXDMA0_IRQ 0
653 #define BCM_6338_ENETSW_RXDMA1_IRQ 0
654 #define BCM_6338_ENETSW_RXDMA2_IRQ 0
655 #define BCM_6338_ENETSW_RXDMA3_IRQ 0
656 #define BCM_6338_ENETSW_TXDMA0_IRQ 0
657 #define BCM_6338_ENETSW_TXDMA1_IRQ 0
658 #define BCM_6338_ENETSW_TXDMA2_IRQ 0
659 #define BCM_6338_ENETSW_TXDMA3_IRQ 0
660 #define BCM_6338_XTM_IRQ 0
661 #define BCM_6338_XTM_DMA0_IRQ 0
662
663 /*
664 * 6345 irqs
665 */
666 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
667 #define BCM_6345_SPI_IRQ 0
668 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
669 #define BCM_6345_UART1_IRQ 0
670 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
671 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
672 #define BCM_6345_ENET1_IRQ 0
673 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
674 #define BCM_6345_OHCI0_IRQ 0
675 #define BCM_6345_EHCI0_IRQ 0
676 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
677 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
678 #define BCM_6345_ENET1_RXDMA_IRQ 0
679 #define BCM_6345_ENET1_TXDMA_IRQ 0
680 #define BCM_6345_PCI_IRQ 0
681 #define BCM_6345_PCMCIA_IRQ 0
682 #define BCM_6345_ATM_IRQ 0
683 #define BCM_6345_ENETSW_RXDMA0_IRQ 0
684 #define BCM_6345_ENETSW_RXDMA1_IRQ 0
685 #define BCM_6345_ENETSW_RXDMA2_IRQ 0
686 #define BCM_6345_ENETSW_RXDMA3_IRQ 0
687 #define BCM_6345_ENETSW_TXDMA0_IRQ 0
688 #define BCM_6345_ENETSW_TXDMA1_IRQ 0
689 #define BCM_6345_ENETSW_TXDMA2_IRQ 0
690 #define BCM_6345_ENETSW_TXDMA3_IRQ 0
691 #define BCM_6345_XTM_IRQ 0
692 #define BCM_6345_XTM_DMA0_IRQ 0
693
694 /*
695 * 6348 irqs
696 */
697 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
698 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
699 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
700 #define BCM_6348_UART1_IRQ 0
701 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
702 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
703 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
704 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
705 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
706 #define BCM_6348_EHCI0_IRQ 0
707 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
708 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
709 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
710 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
711 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
712 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
713 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
714 #define BCM_6348_ENETSW_RXDMA0_IRQ 0
715 #define BCM_6348_ENETSW_RXDMA1_IRQ 0
716 #define BCM_6348_ENETSW_RXDMA2_IRQ 0
717 #define BCM_6348_ENETSW_RXDMA3_IRQ 0
718 #define BCM_6348_ENETSW_TXDMA0_IRQ 0
719 #define BCM_6348_ENETSW_TXDMA1_IRQ 0
720 #define BCM_6348_ENETSW_TXDMA2_IRQ 0
721 #define BCM_6348_ENETSW_TXDMA3_IRQ 0
722 #define BCM_6348_XTM_IRQ 0
723 #define BCM_6348_XTM_DMA0_IRQ 0
724
725 /*
726 * 6358 irqs
727 */
728 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
729 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
730 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
731 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
732 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
733 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
734 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
735 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
736 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
737 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
738 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
739 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
740 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
741 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
742 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
743 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
744 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
745 #define BCM_6358_ENETSW_RXDMA0_IRQ 0
746 #define BCM_6358_ENETSW_RXDMA1_IRQ 0
747 #define BCM_6358_ENETSW_RXDMA2_IRQ 0
748 #define BCM_6358_ENETSW_RXDMA3_IRQ 0
749 #define BCM_6358_ENETSW_TXDMA0_IRQ 0
750 #define BCM_6358_ENETSW_TXDMA1_IRQ 0
751 #define BCM_6358_ENETSW_TXDMA2_IRQ 0
752 #define BCM_6358_ENETSW_TXDMA3_IRQ 0
753 #define BCM_6358_XTM_IRQ 0
754 #define BCM_6358_XTM_DMA0_IRQ 0
755
756 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
757 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
758 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
759 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
760 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
761 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
762
763 /*
764 * 6368 irqs
765 */
766 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
767
768 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
769 #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
770 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
771 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
772 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
773 #define BCM_6368_ENET0_IRQ 0
774 #define BCM_6368_ENET1_IRQ 0
775 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
776 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
777 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
778 #define BCM_6368_PCMCIA_IRQ 0
779 #define BCM_6368_ENET0_RXDMA_IRQ 0
780 #define BCM_6368_ENET0_TXDMA_IRQ 0
781 #define BCM_6368_ENET1_RXDMA_IRQ 0
782 #define BCM_6368_ENET1_TXDMA_IRQ 0
783 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
784 #define BCM_6368_ATM_IRQ 0
785 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
786 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
787 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
788 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
789 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
790 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
791 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
792 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
793 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
794 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
795
796 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
797 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
798 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
799 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
800 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
801 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
802 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
803 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
804
805 extern const int *bcm63xx_irqs;
806
807 #define __GEN_CPU_IRQ_TABLE(__cpu) \
808 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
809 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
810 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
811 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
812 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
813 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
814 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
815 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
816 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
817 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
818 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
819 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
820 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
821 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
822 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
823 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
824 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
825 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
826 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
827 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
828 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
829 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
830 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
831 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
832 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
833 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
834 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
835
836 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
837 {
838 return bcm63xx_irqs[irq];
839 }
840
841 /*
842 * return installed memory size
843 */
844 unsigned int bcm63xx_get_memory_size(void);
845
846 void bcm63xx_machine_halt(void);
847
848 void bcm63xx_machine_reboot(void);
849
850 #endif /* !BCM63XX_CPU_H_ */
Linux ARM platform port for MOXA ART SoC