| blob | b40e0b4815b3f5297154fa9c6e8a66fa4ce7c574 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
31 #include <asm/bug.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
37 /*
38 * System calls.
39 */
40 .section ".toc","aw"
41 .SYS_CALL_TABLE:
42 .tc .sys_call_table[TC],.sys_call_table
44 /* This value is used to mark exception frames on the stack. */
45 exception_marker:
46 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
48 .section ".text"
49 .align 7
51 #undef SHOW_SYSCALLS
53 .globl system_call_common
54 system_call_common:
55 andi. r10,r12,MSR_PR
56 mr r10,r1
57 addi r1,r1,-INT_FRAME_SIZE
58 beq- 1f
59 ld r1,PACAKSAVE(r13)
60 1: std r10,0(r1)
61 std r11,_NIP(r1)
62 std r12,_MSR(r1)
63 std r0,GPR0(r1)
64 std r10,GPR1(r1)
65 ACCOUNT_CPU_USER_ENTRY(r10, r11)
66 std r2,GPR2(r1)
67 std r3,GPR3(r1)
68 mfcr r2
69 std r4,GPR4(r1)
70 std r5,GPR5(r1)
71 std r6,GPR6(r1)
72 std r7,GPR7(r1)
73 std r8,GPR8(r1)
74 li r11,0
75 std r11,GPR9(r1)
76 std r11,GPR10(r1)
77 std r11,GPR11(r1)
78 std r11,GPR12(r1)
79 std r11,_XER(r1)
80 std r11,_CTR(r1)
81 std r9,GPR13(r1)
82 mflr r10
83 /*
84 * This clears CR0.SO (bit 28), which is the error indication on
85 * return from this system call.
86 */
87 rldimi r2,r11,28,(63-28)
88 li r11,0xc01
89 std r10,_LINK(r1)
90 std r11,_TRAP(r1)
91 std r3,ORIG_GPR3(r1)
92 std r2,_CCR(r1)
93 ld r2,PACATOC(r13)
94 addi r9,r1,STACK_FRAME_OVERHEAD
95 ld r11,exception_marker@toc(r2)
96 std r11,-16(r9) /* "regshere" marker */
97 #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR)
98 BEGIN_FW_FTR_SECTION
99 beq 33f
100 /* if from user, see if there are any DTL entries to process */
101 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
102 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
103 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
104 cmpd cr1,r11,r10
105 beq+ cr1,33f
106 bl .accumulate_stolen_time
107 REST_GPR(0,r1)
108 REST_4GPRS(3,r1)
109 REST_2GPRS(7,r1)
110 addi r9,r1,STACK_FRAME_OVERHEAD
111 33:
112 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
113 #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
115 /*
116 * A syscall should always be called with interrupts enabled
117 * so we just unconditionally hard-enable here. When some kind
118 * of irq tracing is used, we additionally check that condition
119 * is correct
120 */
121 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
122 lbz r10,PACASOFTIRQEN(r13)
123 xori r10,r10,1
124 1: tdnei r10,0
125 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
126 #endif
128 #ifdef CONFIG_PPC_BOOK3E
129 wrteei 1
130 #else
131 ld r11,PACAKMSR(r13)
132 ori r11,r11,MSR_EE
133 mtmsrd r11,1
134 #endif /* CONFIG_PPC_BOOK3E */
136 /* We do need to set SOFTE in the stack frame or the return
137 * from interrupt will be painful
138 */
139 li r10,1
140 std r10,SOFTE(r1)
142 #ifdef SHOW_SYSCALLS
143 bl .do_show_syscall
144 REST_GPR(0,r1)
145 REST_4GPRS(3,r1)
146 REST_2GPRS(7,r1)
147 addi r9,r1,STACK_FRAME_OVERHEAD
148 #endif
149 CURRENT_THREAD_INFO(r11, r1)
150 ld r10,TI_FLAGS(r11)
151 andi. r11,r10,_TIF_SYSCALL_T_OR_A
152 bne- syscall_dotrace
153 .Lsyscall_dotrace_cont:
154 cmpldi 0,r0,NR_syscalls
155 bge- syscall_enosys
157 system_call: /* label this so stack traces look sane */
158 /*
159 * Need to vector to 32 Bit or default sys_call_table here,
160 * based on caller's run-mode / personality.
161 */
162 ld r11,.SYS_CALL_TABLE@toc(2)
163 andi. r10,r10,_TIF_32BIT
164 beq 15f
165 addi r11,r11,8 /* use 32-bit syscall entries */
166 clrldi r3,r3,32
167 clrldi r4,r4,32
168 clrldi r5,r5,32
169 clrldi r6,r6,32
170 clrldi r7,r7,32
171 clrldi r8,r8,32
172 15:
173 slwi r0,r0,4
174 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
175 mtctr r10
176 bctrl /* Call handler */
178 syscall_exit:
179 std r3,RESULT(r1)
180 #ifdef SHOW_SYSCALLS
181 bl .do_show_syscall_exit
182 ld r3,RESULT(r1)
183 #endif
184 CURRENT_THREAD_INFO(r12, r1)
186 ld r8,_MSR(r1)
187 #ifdef CONFIG_PPC_BOOK3S
188 /* No MSR:RI on BookE */
189 andi. r10,r8,MSR_RI
190 beq- unrecov_restore
191 #endif
192 /*
193 * Disable interrupts so current_thread_info()->flags can't change,
194 * and so that we don't get interrupted after loading SRR0/1.
195 */
196 #ifdef CONFIG_PPC_BOOK3E
197 wrteei 0
198 #else
199 ld r10,PACAKMSR(r13)
200 /*
201 * For performance reasons we clear RI the same time that we
202 * clear EE. We only need to clear RI just before we restore r13
203 * below, but batching it with EE saves us one expensive mtmsrd call.
204 * We have to be careful to restore RI if we branch anywhere from
205 * here (eg syscall_exit_work).
206 */
207 li r9,MSR_RI
208 andc r11,r10,r9
209 mtmsrd r11,1
210 #endif /* CONFIG_PPC_BOOK3E */
212 ld r9,TI_FLAGS(r12)
213 li r11,-_LAST_ERRNO
214 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
215 bne- syscall_exit_work
216 cmpld r3,r11
217 ld r5,_CCR(r1)
218 bge- syscall_error
219 .Lsyscall_error_cont:
220 ld r7,_NIP(r1)
221 BEGIN_FTR_SECTION
222 stdcx. r0,0,r1 /* to clear the reservation */
223 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
224 andi. r6,r8,MSR_PR
225 ld r4,_LINK(r1)
227 beq- 1f
228 ACCOUNT_CPU_USER_EXIT(r11, r12)
229 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
230 1: ld r2,GPR2(r1)
231 ld r1,GPR1(r1)
232 mtlr r4
233 mtcr r5
234 mtspr SPRN_SRR0,r7
235 mtspr SPRN_SRR1,r8
236 RFI
237 b . /* prevent speculative execution */
239 syscall_error:
240 oris r5,r5,0x1000 /* Set SO bit in CR */
241 neg r3,r3
242 std r5,_CCR(r1)
243 b .Lsyscall_error_cont
245 /* Traced system call support */
246 syscall_dotrace:
247 bl .save_nvgprs
248 addi r3,r1,STACK_FRAME_OVERHEAD
249 bl .do_syscall_trace_enter
250 /*
251 * Restore argument registers possibly just changed.
252 * We use the return value of do_syscall_trace_enter
253 * for the call number to look up in the table (r0).
254 */
255 mr r0,r3
256 ld r3,GPR3(r1)
257 ld r4,GPR4(r1)
258 ld r5,GPR5(r1)
259 ld r6,GPR6(r1)
260 ld r7,GPR7(r1)
261 ld r8,GPR8(r1)
262 addi r9,r1,STACK_FRAME_OVERHEAD
263 CURRENT_THREAD_INFO(r10, r1)
264 ld r10,TI_FLAGS(r10)
265 b .Lsyscall_dotrace_cont
267 syscall_enosys:
268 li r3,-ENOSYS
269 b syscall_exit
271 syscall_exit_work:
272 #ifdef CONFIG_PPC_BOOK3S
273 mtmsrd r10,1 /* Restore RI */
274 #endif
275 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
276 If TIF_NOERROR is set, just save r3 as it is. */
278 andi. r0,r9,_TIF_RESTOREALL
279 beq+ 0f
280 REST_NVGPRS(r1)
281 b 2f
282 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
283 blt+ 1f
284 andi. r0,r9,_TIF_NOERROR
285 bne- 1f
286 ld r5,_CCR(r1)
287 neg r3,r3
288 oris r5,r5,0x1000 /* Set SO bit in CR */
289 std r5,_CCR(r1)
290 1: std r3,GPR3(r1)
291 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
292 beq 4f
294 /* Clear per-syscall TIF flags if any are set. */
296 li r11,_TIF_PERSYSCALL_MASK
297 addi r12,r12,TI_FLAGS
298 3: ldarx r10,0,r12
299 andc r10,r10,r11
300 stdcx. r10,0,r12
301 bne- 3b
302 subi r12,r12,TI_FLAGS
304 4: /* Anything else left to do? */
305 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
306 beq .ret_from_except_lite
308 /* Re-enable interrupts */
309 #ifdef CONFIG_PPC_BOOK3E
310 wrteei 1
311 #else
312 ld r10,PACAKMSR(r13)
313 ori r10,r10,MSR_EE
314 mtmsrd r10,1
315 #endif /* CONFIG_PPC_BOOK3E */
317 bl .save_nvgprs
318 addi r3,r1,STACK_FRAME_OVERHEAD
319 bl .do_syscall_trace_leave
320 b .ret_from_except
322 /* Save non-volatile GPRs, if not already saved. */
323 _GLOBAL(save_nvgprs)
324 ld r11,_TRAP(r1)
325 andi. r0,r11,1
326 beqlr-
327 SAVE_NVGPRS(r1)
328 clrrdi r0,r11,1
329 std r0,_TRAP(r1)
330 blr
333 /*
334 * The sigsuspend and rt_sigsuspend system calls can call do_signal
335 * and thus put the process into the stopped state where we might
336 * want to examine its user state with ptrace. Therefore we need
337 * to save all the nonvolatile registers (r14 - r31) before calling
338 * the C code. Similarly, fork, vfork and clone need the full
339 * register state on the stack so that it can be copied to the child.
340 */
342 _GLOBAL(ppc_fork)
343 bl .save_nvgprs
344 bl .sys_fork
345 b syscall_exit
347 _GLOBAL(ppc_vfork)
348 bl .save_nvgprs
349 bl .sys_vfork
350 b syscall_exit
352 _GLOBAL(ppc_clone)
353 bl .save_nvgprs
354 bl .sys_clone
355 b syscall_exit
357 _GLOBAL(ppc32_swapcontext)
358 bl .save_nvgprs
359 bl .compat_sys_swapcontext
360 b syscall_exit
362 _GLOBAL(ppc64_swapcontext)
363 bl .save_nvgprs
364 bl .sys_swapcontext
365 b syscall_exit
367 _GLOBAL(ret_from_fork)
368 bl .schedule_tail
369 REST_NVGPRS(r1)
370 li r3,0
371 b syscall_exit
373 .section ".toc","aw"
374 DSCR_DEFAULT:
375 .tc dscr_default[TC],dscr_default
377 .section ".text"
379 /*
380 * This routine switches between two different tasks. The process
381 * state of one is saved on its kernel stack. Then the state
382 * of the other is restored from its kernel stack. The memory
383 * management hardware is updated to the second process's state.
384 * Finally, we can return to the second process, via ret_from_except.
385 * On entry, r3 points to the THREAD for the current task, r4
386 * points to the THREAD for the new task.
387 *
388 * Note: there are two ways to get to the "going out" portion
389 * of this code; either by coming in via the entry (_switch)
390 * or via "fork" which must set up an environment equivalent
391 * to the "_switch" path. If you change this you'll have to change
392 * the fork code also.
393 *
394 * The code which creates the new task context is in 'copy_thread'
395 * in arch/powerpc/kernel/process.c
396 */
397 .align 7
398 _GLOBAL(_switch)
399 mflr r0
400 std r0,16(r1)
401 stdu r1,-SWITCH_FRAME_SIZE(r1)
402 /* r3-r13 are caller saved -- Cort */
403 SAVE_8GPRS(14, r1)
404 SAVE_10GPRS(22, r1)
405 mflr r20 /* Return to switch caller */
406 mfmsr r22
407 li r0, MSR_FP
408 #ifdef CONFIG_VSX
409 BEGIN_FTR_SECTION
410 oris r0,r0,MSR_VSX@h /* Disable VSX */
411 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
412 #endif /* CONFIG_VSX */
413 #ifdef CONFIG_ALTIVEC
414 BEGIN_FTR_SECTION
415 oris r0,r0,MSR_VEC@h /* Disable altivec */
416 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
417 std r24,THREAD_VRSAVE(r3)
418 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
419 #endif /* CONFIG_ALTIVEC */
420 #ifdef CONFIG_PPC64
421 BEGIN_FTR_SECTION
422 mfspr r25,SPRN_DSCR
423 std r25,THREAD_DSCR(r3)
424 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
425 #endif
426 and. r0,r0,r22
427 beq+ 1f
428 andc r22,r22,r0
429 MTMSRD(r22)
430 isync
431 1: std r20,_NIP(r1)
432 mfcr r23
433 std r23,_CCR(r1)
434 std r1,KSP(r3) /* Set old stack pointer */
436 #ifdef CONFIG_SMP
437 /* We need a sync somewhere here to make sure that if the
438 * previous task gets rescheduled on another CPU, it sees all
439 * stores it has performed on this one.
440 */
441 sync
442 #endif /* CONFIG_SMP */
444 /*
445 * If we optimise away the clear of the reservation in system
446 * calls because we know the CPU tracks the address of the
447 * reservation, then we need to clear it here to cover the
448 * case that the kernel context switch path has no larx
449 * instructions.
450 */
451 BEGIN_FTR_SECTION
452 ldarx r6,0,r1
453 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
455 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
456 std r6,PACACURRENT(r13) /* Set new 'current' */
458 ld r8,KSP(r4) /* new stack pointer */
459 #ifdef CONFIG_PPC_BOOK3S
460 BEGIN_FTR_SECTION
461 BEGIN_FTR_SECTION_NESTED(95)
462 clrrdi r6,r8,28 /* get its ESID */
463 clrrdi r9,r1,28 /* get current sp ESID */
464 FTR_SECTION_ELSE_NESTED(95)
465 clrrdi r6,r8,40 /* get its 1T ESID */
466 clrrdi r9,r1,40 /* get current sp 1T ESID */
467 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
468 FTR_SECTION_ELSE
469 b 2f
470 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
471 clrldi. r0,r6,2 /* is new ESID c00000000? */
472 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
473 cror eq,4*cr1+eq,eq
474 beq 2f /* if yes, don't slbie it */
476 /* Bolt in the new stack SLB entry */
477 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
478 oris r0,r6,(SLB_ESID_V)@h
479 ori r0,r0,(SLB_NUM_BOLTED-1)@l
480 BEGIN_FTR_SECTION
481 li r9,MMU_SEGSIZE_1T /* insert B field */
482 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
483 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
484 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
486 /* Update the last bolted SLB. No write barriers are needed
487 * here, provided we only update the current CPU's SLB shadow
488 * buffer.
489 */
490 ld r9,PACA_SLBSHADOWPTR(r13)
491 li r12,0
492 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
493 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
494 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
496 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
497 * we have 1TB segments, the only CPUs known to have the errata
498 * only support less than 1TB of system memory and we'll never
499 * actually hit this code path.
500 */
502 slbie r6
503 slbie r6 /* Workaround POWER5 < DD2.1 issue */
504 slbmte r7,r0
505 isync
506 2:
507 #endif /* !CONFIG_PPC_BOOK3S */
509 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
510 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
511 because we don't need to leave the 288-byte ABI gap at the
512 top of the kernel stack. */
513 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
515 mr r1,r8 /* start using new stack pointer */
516 std r7,PACAKSAVE(r13)
518 #ifdef CONFIG_ALTIVEC
519 BEGIN_FTR_SECTION
520 ld r0,THREAD_VRSAVE(r4)
521 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
522 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
523 #endif /* CONFIG_ALTIVEC */
524 #ifdef CONFIG_PPC64
525 BEGIN_FTR_SECTION
526 lwz r6,THREAD_DSCR_INHERIT(r4)
527 ld r7,DSCR_DEFAULT@toc(2)
528 ld r0,THREAD_DSCR(r4)
529 cmpwi r6,0
530 bne 1f
531 ld r0,0(r7)
532 1: cmpd r0,r25
533 beq 2f
534 mtspr SPRN_DSCR,r0
535 2:
536 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
537 #endif
539 ld r6,_CCR(r1)
540 mtcrf 0xFF,r6
542 /* r3-r13 are destroyed -- Cort */
543 REST_8GPRS(14, r1)
544 REST_10GPRS(22, r1)
546 /* convert old thread to its task_struct for return value */
547 addi r3,r3,-THREAD
548 ld r7,_NIP(r1) /* Return to _switch caller in new task */
549 mtlr r7
550 addi r1,r1,SWITCH_FRAME_SIZE
551 blr
553 .align 7
554 _GLOBAL(ret_from_except)
555 ld r11,_TRAP(r1)
556 andi. r0,r11,1
557 bne .ret_from_except_lite
558 REST_NVGPRS(r1)
560 _GLOBAL(ret_from_except_lite)
561 /*
562 * Disable interrupts so that current_thread_info()->flags
563 * can't change between when we test it and when we return
564 * from the interrupt.
565 */
566 #ifdef CONFIG_PPC_BOOK3E
567 wrteei 0
568 #else
569 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
570 mtmsrd r10,1 /* Update machine state */
571 #endif /* CONFIG_PPC_BOOK3E */
573 CURRENT_THREAD_INFO(r9, r1)
574 ld r3,_MSR(r1)
575 ld r4,TI_FLAGS(r9)
576 andi. r3,r3,MSR_PR
577 beq resume_kernel
579 /* Check current_thread_info()->flags */
580 andi. r0,r4,_TIF_USER_WORK_MASK
581 beq restore
583 andi. r0,r4,_TIF_NEED_RESCHED
584 beq 1f
585 bl .restore_interrupts
586 bl .schedule
587 b .ret_from_except_lite
589 1: bl .save_nvgprs
590 bl .restore_interrupts
591 addi r3,r1,STACK_FRAME_OVERHEAD
592 bl .do_notify_resume
593 b .ret_from_except
595 resume_kernel:
596 #ifdef CONFIG_PREEMPT
597 /* Check if we need to preempt */
598 andi. r0,r4,_TIF_NEED_RESCHED
599 beq+ restore
600 /* Check that preempt_count() == 0 and interrupts are enabled */
601 lwz r8,TI_PREEMPT(r9)
602 cmpwi cr1,r8,0
603 ld r0,SOFTE(r1)
604 cmpdi r0,0
605 crandc eq,cr1*4+eq,eq
606 bne restore
608 /*
609 * Here we are preempting the current task. We want to make
610 * sure we are soft-disabled first
611 */
612 SOFT_DISABLE_INTS(r3,r4)
613 1: bl .preempt_schedule_irq
615 /* Re-test flags and eventually loop */
616 CURRENT_THREAD_INFO(r9, r1)
617 ld r4,TI_FLAGS(r9)
618 andi. r0,r4,_TIF_NEED_RESCHED
619 bne 1b
620 #endif /* CONFIG_PREEMPT */
622 .globl fast_exc_return_irq
623 fast_exc_return_irq:
624 restore:
625 /*
626 * This is the main kernel exit path. First we check if we
627 * are about to re-enable interrupts
628 */
629 ld r5,SOFTE(r1)
630 lbz r6,PACASOFTIRQEN(r13)
631 cmpwi cr0,r5,0
632 beq restore_irq_off
634 /* We are enabling, were we already enabled ? Yes, just return */
635 cmpwi cr0,r6,1
636 beq cr0,do_restore
638 /*
639 * We are about to soft-enable interrupts (we are hard disabled
640 * at this point). We check if there's anything that needs to
641 * be replayed first.
642 */
643 lbz r0,PACAIRQHAPPENED(r13)
644 cmpwi cr0,r0,0
645 bne- restore_check_irq_replay
647 /*
648 * Get here when nothing happened while soft-disabled, just
649 * soft-enable and move-on. We will hard-enable as a side
650 * effect of rfi
651 */
652 restore_no_replay:
653 TRACE_ENABLE_INTS
654 li r0,1
655 stb r0,PACASOFTIRQEN(r13);
657 /*
658 * Final return path. BookE is handled in a different file
659 */
660 do_restore:
661 #ifdef CONFIG_PPC_BOOK3E
662 b .exception_return_book3e
663 #else
664 /*
665 * Clear the reservation. If we know the CPU tracks the address of
666 * the reservation then we can potentially save some cycles and use
667 * a larx. On POWER6 and POWER7 this is significantly faster.
668 */
669 BEGIN_FTR_SECTION
670 stdcx. r0,0,r1 /* to clear the reservation */
671 FTR_SECTION_ELSE
672 ldarx r4,0,r1
673 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
675 /*
676 * Some code path such as load_up_fpu or altivec return directly
677 * here. They run entirely hard disabled and do not alter the
678 * interrupt state. They also don't use lwarx/stwcx. and thus
679 * are known not to leave dangling reservations.
680 */
681 .globl fast_exception_return
682 fast_exception_return:
683 ld r3,_MSR(r1)
684 ld r4,_CTR(r1)
685 ld r0,_LINK(r1)
686 mtctr r4
687 mtlr r0
688 ld r4,_XER(r1)
689 mtspr SPRN_XER,r4
691 REST_8GPRS(5, r1)
693 andi. r0,r3,MSR_RI
694 beq- unrecov_restore
696 /*
697 * Clear RI before restoring r13. If we are returning to
698 * userspace and we take an exception after restoring r13,
699 * we end up corrupting the userspace r13 value.
700 */
701 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
702 andc r4,r4,r0 /* r0 contains MSR_RI here */
703 mtmsrd r4,1
705 /*
706 * r13 is our per cpu area, only restore it if we are returning to
707 * userspace the value stored in the stack frame may belong to
708 * another CPU.
709 */
710 andi. r0,r3,MSR_PR
711 beq 1f
712 ACCOUNT_CPU_USER_EXIT(r2, r4)
713 REST_GPR(13, r1)
714 1:
715 mtspr SPRN_SRR1,r3
717 ld r2,_CCR(r1)
718 mtcrf 0xFF,r2
719 ld r2,_NIP(r1)
720 mtspr SPRN_SRR0,r2
722 ld r0,GPR0(r1)
723 ld r2,GPR2(r1)
724 ld r3,GPR3(r1)
725 ld r4,GPR4(r1)
726 ld r1,GPR1(r1)
728 rfid
729 b . /* prevent speculative execution */
731 #endif /* CONFIG_PPC_BOOK3E */
733 /*
734 * We are returning to a context with interrupts soft disabled.
735 *
736 * However, we may also about to hard enable, so we need to
737 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
738 * or that bit can get out of sync and bad things will happen
739 */
740 restore_irq_off:
741 ld r3,_MSR(r1)
742 lbz r7,PACAIRQHAPPENED(r13)
743 andi. r0,r3,MSR_EE
744 beq 1f
745 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
746 stb r7,PACAIRQHAPPENED(r13)
747 1: li r0,0
748 stb r0,PACASOFTIRQEN(r13);
749 TRACE_DISABLE_INTS
750 b do_restore
752 /*
753 * Something did happen, check if a re-emit is needed
754 * (this also clears paca->irq_happened)
755 */
756 restore_check_irq_replay:
757 /* XXX: We could implement a fast path here where we check
758 * for irq_happened being just 0x01, in which case we can
759 * clear it and return. That means that we would potentially
760 * miss a decrementer having wrapped all the way around.
761 *
762 * Still, this might be useful for things like hash_page
763 */
764 bl .__check_irq_replay
765 cmpwi cr0,r3,0
766 beq restore_no_replay
768 /*
769 * We need to re-emit an interrupt. We do so by re-using our
770 * existing exception frame. We first change the trap value,
771 * but we need to ensure we preserve the low nibble of it
772 */
773 ld r4,_TRAP(r1)
774 clrldi r4,r4,60
775 or r4,r4,r3
776 std r4,_TRAP(r1)
778 /*
779 * Then find the right handler and call it. Interrupts are
780 * still soft-disabled and we keep them that way.
781 */
782 cmpwi cr0,r3,0x500
783 bne 1f
784 addi r3,r1,STACK_FRAME_OVERHEAD;
785 bl .do_IRQ
786 b .ret_from_except
787 1: cmpwi cr0,r3,0x900
788 bne 1f
789 addi r3,r1,STACK_FRAME_OVERHEAD;
790 bl .timer_interrupt
791 b .ret_from_except
792 #ifdef CONFIG_PPC_BOOK3E
793 1: cmpwi cr0,r3,0x280
794 bne 1f
795 addi r3,r1,STACK_FRAME_OVERHEAD;
796 bl .doorbell_exception
797 b .ret_from_except
798 #endif /* CONFIG_PPC_BOOK3E */
799 1: b .ret_from_except /* What else to do here ? */
801 unrecov_restore:
802 addi r3,r1,STACK_FRAME_OVERHEAD
803 bl .unrecoverable_exception
804 b unrecov_restore
806 #ifdef CONFIG_PPC_RTAS
807 /*
808 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
809 * called with the MMU off.
810 *
811 * In addition, we need to be in 32b mode, at least for now.
812 *
813 * Note: r3 is an input parameter to rtas, so don't trash it...
814 */
815 _GLOBAL(enter_rtas)
816 mflr r0
817 std r0,16(r1)
818 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
820 /* Because RTAS is running in 32b mode, it clobbers the high order half
821 * of all registers that it saves. We therefore save those registers
822 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
823 */
824 SAVE_GPR(2, r1) /* Save the TOC */
825 SAVE_GPR(13, r1) /* Save paca */
826 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
827 SAVE_10GPRS(22, r1) /* ditto */
829 mfcr r4
830 std r4,_CCR(r1)
831 mfctr r5
832 std r5,_CTR(r1)
833 mfspr r6,SPRN_XER
834 std r6,_XER(r1)
835 mfdar r7
836 std r7,_DAR(r1)
837 mfdsisr r8
838 std r8,_DSISR(r1)
840 /* Temporary workaround to clear CR until RTAS can be modified to
841 * ignore all bits.
842 */
843 li r0,0
844 mtcr r0
846 #ifdef CONFIG_BUG
847 /* There is no way it is acceptable to get here with interrupts enabled,
848 * check it with the asm equivalent of WARN_ON
849 */
850 lbz r0,PACASOFTIRQEN(r13)
851 1: tdnei r0,0
852 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
853 #endif
855 /* Hard-disable interrupts */
856 mfmsr r6
857 rldicl r7,r6,48,1
858 rotldi r7,r7,16
859 mtmsrd r7,1
861 /* Unfortunately, the stack pointer and the MSR are also clobbered,
862 * so they are saved in the PACA which allows us to restore
863 * our original state after RTAS returns.
864 */
865 std r1,PACAR1(r13)
866 std r6,PACASAVEDMSR(r13)
868 /* Setup our real return addr */
869 LOAD_REG_ADDR(r4,.rtas_return_loc)
870 clrldi r4,r4,2 /* convert to realmode address */
871 mtlr r4
873 li r0,0
874 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
875 andc r0,r6,r0
877 li r9,1
878 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
879 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
880 andc r6,r0,r9
881 sync /* disable interrupts so SRR0/1 */
882 mtmsrd r0 /* don't get trashed */
884 LOAD_REG_ADDR(r4, rtas)
885 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
886 ld r4,RTASBASE(r4) /* get the rtas->base value */
888 mtspr SPRN_SRR0,r5
889 mtspr SPRN_SRR1,r6
890 rfid
891 b . /* prevent speculative execution */
893 _STATIC(rtas_return_loc)
894 /* relocation is off at this point */
895 GET_PACA(r4)
896 clrldi r4,r4,2 /* convert to realmode address */
898 bcl 20,31,$+4
899 0: mflr r3
900 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
902 mfmsr r6
903 li r0,MSR_RI
904 andc r6,r6,r0
905 sync
906 mtmsrd r6
908 ld r1,PACAR1(r4) /* Restore our SP */
909 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
911 mtspr SPRN_SRR0,r3
912 mtspr SPRN_SRR1,r4
913 rfid
914 b . /* prevent speculative execution */
916 .align 3
917 1: .llong .rtas_restore_regs
919 _STATIC(rtas_restore_regs)
920 /* relocation is on at this point */
921 REST_GPR(2, r1) /* Restore the TOC */
922 REST_GPR(13, r1) /* Restore paca */
923 REST_8GPRS(14, r1) /* Restore the non-volatiles */
924 REST_10GPRS(22, r1) /* ditto */
926 GET_PACA(r13)
928 ld r4,_CCR(r1)
929 mtcr r4
930 ld r5,_CTR(r1)
931 mtctr r5
932 ld r6,_XER(r1)
933 mtspr SPRN_XER,r6
934 ld r7,_DAR(r1)
935 mtdar r7
936 ld r8,_DSISR(r1)
937 mtdsisr r8
939 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
940 ld r0,16(r1) /* get return address */
942 mtlr r0
943 blr /* return to caller */
945 #endif /* CONFIG_PPC_RTAS */
947 _GLOBAL(enter_prom)
948 mflr r0
949 std r0,16(r1)
950 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
952 /* Because PROM is running in 32b mode, it clobbers the high order half
953 * of all registers that it saves. We therefore save those registers
954 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
955 */
956 SAVE_GPR(2, r1)
957 SAVE_GPR(13, r1)
958 SAVE_8GPRS(14, r1)
959 SAVE_10GPRS(22, r1)
960 mfcr r10
961 mfmsr r11
962 std r10,_CCR(r1)
963 std r11,_MSR(r1)
965 /* Get the PROM entrypoint */
966 mtlr r4
968 /* Switch MSR to 32 bits mode
969 */
970 #ifdef CONFIG_PPC_BOOK3E
971 rlwinm r11,r11,0,1,31
972 mtmsr r11
973 #else /* CONFIG_PPC_BOOK3E */
974 mfmsr r11
975 li r12,1
976 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
977 andc r11,r11,r12
978 li r12,1
979 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
980 andc r11,r11,r12
981 mtmsrd r11
982 #endif /* CONFIG_PPC_BOOK3E */
983 isync
985 /* Enter PROM here... */
986 blrl
988 /* Just make sure that r1 top 32 bits didn't get
989 * corrupt by OF
990 */
991 rldicl r1,r1,0,32
993 /* Restore the MSR (back to 64 bits) */
994 ld r0,_MSR(r1)
995 MTMSRD(r0)
996 isync
998 /* Restore other registers */
999 REST_GPR(2, r1)
1000 REST_GPR(13, r1)
1001 REST_8GPRS(14, r1)
1002 REST_10GPRS(22, r1)
1003 ld r4,_CCR(r1)
1004 mtcr r4
1006 addi r1,r1,PROM_FRAME_SIZE
1007 ld r0,16(r1)
1008 mtlr r0
1009 blr
1011 #ifdef CONFIG_FUNCTION_TRACER
1012 #ifdef CONFIG_DYNAMIC_FTRACE
1013 _GLOBAL(mcount)
1014 _GLOBAL(_mcount)
1015 blr
1017 _GLOBAL(ftrace_caller)
1018 /* Taken from output of objdump from lib64/glibc */
1019 mflr r3
1020 ld r11, 0(r1)
1021 stdu r1, -112(r1)
1022 std r3, 128(r1)
1023 ld r4, 16(r11)
1024 subi r3, r3, MCOUNT_INSN_SIZE
1025 .globl ftrace_call
1026 ftrace_call:
1027 bl ftrace_stub
1028 nop
1029 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1030 .globl ftrace_graph_call
1031 ftrace_graph_call:
1032 b ftrace_graph_stub
1033 _GLOBAL(ftrace_graph_stub)
1034 #endif
1035 ld r0, 128(r1)
1036 mtlr r0
1037 addi r1, r1, 112
1038 _GLOBAL(ftrace_stub)
1039 blr
1040 #else
1041 _GLOBAL(mcount)
1042 blr
1044 _GLOBAL(_mcount)
1045 /* Taken from output of objdump from lib64/glibc */
1046 mflr r3
1047 ld r11, 0(r1)
1048 stdu r1, -112(r1)
1049 std r3, 128(r1)
1050 ld r4, 16(r11)
1052 subi r3, r3, MCOUNT_INSN_SIZE
1053 LOAD_REG_ADDR(r5,ftrace_trace_function)
1054 ld r5,0(r5)
1055 ld r5,0(r5)
1056 mtctr r5
1057 bctrl
1058 nop
1061 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1062 b ftrace_graph_caller
1063 #endif
1064 ld r0, 128(r1)
1065 mtlr r0
1066 addi r1, r1, 112
1067 _GLOBAL(ftrace_stub)
1068 blr
1070 #endif /* CONFIG_DYNAMIC_FTRACE */
1072 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1073 _GLOBAL(ftrace_graph_caller)
1074 /* load r4 with local address */
1075 ld r4, 128(r1)
1076 subi r4, r4, MCOUNT_INSN_SIZE
1078 /* get the parent address */
1079 ld r11, 112(r1)
1080 addi r3, r11, 16
1082 bl .prepare_ftrace_return
1083 nop
1085 ld r0, 128(r1)
1086 mtlr r0
1087 addi r1, r1, 112
1088 blr
1090 _GLOBAL(return_to_handler)
1091 /* need to save return values */
1092 std r4, -24(r1)
1093 std r3, -16(r1)
1094 std r31, -8(r1)
1095 mr r31, r1
1096 stdu r1, -112(r1)
1098 bl .ftrace_return_to_handler
1099 nop
1101 /* return value has real return address */
1102 mtlr r3
1104 ld r1, 0(r1)
1105 ld r4, -24(r1)
1106 ld r3, -16(r1)
1107 ld r31, -8(r1)
1109 /* Jump back to real return address */
1110 blr
1112 _GLOBAL(mod_return_to_handler)
1113 /* need to save return values */
1114 std r4, -32(r1)
1115 std r3, -24(r1)
1116 /* save TOC */
1117 std r2, -16(r1)
1118 std r31, -8(r1)
1119 mr r31, r1
1120 stdu r1, -112(r1)
1122 /*
1123 * We are in a module using the module's TOC.
1124 * Switch to our TOC to run inside the core kernel.
1125 */
1126 ld r2, PACATOC(r13)
1128 bl .ftrace_return_to_handler
1129 nop
1131 /* return value has real return address */
1132 mtlr r3
1134 ld r1, 0(r1)
1135 ld r4, -32(r1)
1136 ld r3, -24(r1)
1137 ld r2, -16(r1)
1138 ld r31, -8(r1)
1140 /* Jump back to real return address */
1141 blr
1142 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1143 #endif /* CONFIG_FUNCTION_TRACER */