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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / arch / powerpc / kernel / traps.c
blobae0843fa7a61f64540214b2fbf658265d24879df
1 /*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14 /*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
42 #include <asm/io.h>
43 #include <asm/machdep.h>
44 #include <asm/rtas.h>
45 #include <asm/pmc.h>
46 #ifdef CONFIG_PPC32
47 #include <asm/reg.h>
48 #endif
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
51 #endif
52 #ifdef CONFIG_PPC64
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
55 #endif
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
58 #include <asm/rio.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
61 #include <asm/debug.h>
62
63 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
64 int (*__debugger)(struct pt_regs *regs) __read_mostly;
65 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
66 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
71
72 EXPORT_SYMBOL(__debugger);
73 EXPORT_SYMBOL(__debugger_ipi);
74 EXPORT_SYMBOL(__debugger_bpt);
75 EXPORT_SYMBOL(__debugger_sstep);
76 EXPORT_SYMBOL(__debugger_iabr_match);
77 EXPORT_SYMBOL(__debugger_dabr_match);
78 EXPORT_SYMBOL(__debugger_fault_handler);
79 #endif
80
81 /*
82 * Trap & Exception support
83 */
84
85 #ifdef CONFIG_PMAC_BACKLIGHT
86 static void pmac_backlight_unblank(void)
87 {
88 mutex_lock(&pmac_backlight_mutex);
89 if (pmac_backlight) {
90 struct backlight_properties *props;
91
92 props = &pmac_backlight->props;
93 props->brightness = props->max_brightness;
94 props->power = FB_BLANK_UNBLANK;
95 backlight_update_status(pmac_backlight);
96 }
97 mutex_unlock(&pmac_backlight_mutex);
98 }
99 #else
100 static inline void pmac_backlight_unblank(void) { }
101 #endif
102
103 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
104 static int die_owner = -1;
105 static unsigned int die_nest_count;
106 static int die_counter;
107
108 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
109 {
110 int cpu;
111 unsigned long flags;
112
113 if (debugger(regs))
114 return 1;
115
116 oops_enter();
117
118 /* racy, but better than risking deadlock. */
119 raw_local_irq_save(flags);
120 cpu = smp_processor_id();
121 if (!arch_spin_trylock(&die_lock)) {
122 if (cpu == die_owner)
123 /* nested oops. should stop eventually */;
124 else
125 arch_spin_lock(&die_lock);
126 }
127 die_nest_count++;
128 die_owner = cpu;
129 console_verbose();
130 bust_spinlocks(1);
131 if (machine_is(powermac))
132 pmac_backlight_unblank();
133 return flags;
134 }
135
136 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
137 int signr)
138 {
139 bust_spinlocks(0);
140 die_owner = -1;
141 add_taint(TAINT_DIE);
142 die_nest_count--;
143 oops_exit();
144 printk("\n");
145 if (!die_nest_count)
146 /* Nest count reaches zero, release the lock. */
147 arch_spin_unlock(&die_lock);
148 raw_local_irq_restore(flags);
149
150 crash_fadump(regs, "die oops");
151
152 /*
153 * A system reset (0x100) is a request to dump, so we always send
154 * it through the crashdump code.
155 */
156 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
157 crash_kexec(regs);
158
159 /*
160 * We aren't the primary crash CPU. We need to send it
161 * to a holding pattern to avoid it ending up in the panic
162 * code.
163 */
164 crash_kexec_secondary(regs);
165 }
166
167 if (!signr)
168 return;
169
170 /*
171 * While our oops output is serialised by a spinlock, output
172 * from panic() called below can race and corrupt it. If we
173 * know we are going to panic, delay for 1 second so we have a
174 * chance to get clean backtraces from all CPUs that are oopsing.
175 */
176 if (in_interrupt() || panic_on_oops || !current->pid ||
177 is_global_init(current)) {
178 mdelay(MSEC_PER_SEC);
179 }
180
181 if (in_interrupt())
182 panic("Fatal exception in interrupt");
183 if (panic_on_oops)
184 panic("Fatal exception");
185 do_exit(signr);
186 }
187
188 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
189 {
190 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
191 #ifdef CONFIG_PREEMPT
192 printk("PREEMPT ");
193 #endif
194 #ifdef CONFIG_SMP
195 printk("SMP NR_CPUS=%d ", NR_CPUS);
196 #endif
197 #ifdef CONFIG_DEBUG_PAGEALLOC
198 printk("DEBUG_PAGEALLOC ");
199 #endif
200 #ifdef CONFIG_NUMA
201 printk("NUMA ");
202 #endif
203 printk("%s\n", ppc_md.name ? ppc_md.name : "");
204
205 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
206 return 1;
207
208 print_modules();
209 show_regs(regs);
210
211 return 0;
212 }
213
214 void die(const char *str, struct pt_regs *regs, long err)
215 {
216 unsigned long flags = oops_begin(regs);
217
218 if (__die(str, regs, err))
219 err = 0;
220 oops_end(flags, regs, err);
221 }
222
223 void user_single_step_siginfo(struct task_struct *tsk,
224 struct pt_regs *regs, siginfo_t *info)
225 {
226 memset(info, 0, sizeof(*info));
227 info->si_signo = SIGTRAP;
228 info->si_code = TRAP_TRACE;
229 info->si_addr = (void __user *)regs->nip;
230 }
231
232 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
233 {
234 siginfo_t info;
235 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
236 "at %08lx nip %08lx lr %08lx code %x\n";
237 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
238 "at %016lx nip %016lx lr %016lx code %x\n";
239
240 if (!user_mode(regs)) {
241 die("Exception in kernel mode", regs, signr);
242 return;
243 }
244
245 if (show_unhandled_signals && unhandled_signal(current, signr)) {
246 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
247 current->comm, current->pid, signr,
248 addr, regs->nip, regs->link, code);
249 }
250
251 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
252 local_irq_enable();
253
254 memset(&info, 0, sizeof(info));
255 info.si_signo = signr;
256 info.si_code = code;
257 info.si_addr = (void __user *) addr;
258 force_sig_info(signr, &info, current);
259 }
260
261 #ifdef CONFIG_PPC64
262 void system_reset_exception(struct pt_regs *regs)
263 {
264 /* See if any machine dependent calls */
265 if (ppc_md.system_reset_exception) {
266 if (ppc_md.system_reset_exception(regs))
267 return;
268 }
269
270 die("System Reset", regs, SIGABRT);
271
272 /* Must die if the interrupt is not recoverable */
273 if (!(regs->msr & MSR_RI))
274 panic("Unrecoverable System Reset");
275
276 /* What should we do here? We could issue a shutdown or hard reset. */
277 }
278 #endif
279
280 /*
281 * I/O accesses can cause machine checks on powermacs.
282 * Check if the NIP corresponds to the address of a sync
283 * instruction for which there is an entry in the exception
284 * table.
285 * Note that the 601 only takes a machine check on TEA
286 * (transfer error ack) signal assertion, and does not
287 * set any of the top 16 bits of SRR1.
288 * -- paulus.
289 */
290 static inline int check_io_access(struct pt_regs *regs)
291 {
292 #ifdef CONFIG_PPC32
293 unsigned long msr = regs->msr;
294 const struct exception_table_entry *entry;
295 unsigned int *nip = (unsigned int *)regs->nip;
296
297 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
298 && (entry = search_exception_tables(regs->nip)) != NULL) {
299 /*
300 * Check that it's a sync instruction, or somewhere
301 * in the twi; isync; nop sequence that inb/inw/inl uses.
302 * As the address is in the exception table
303 * we should be able to read the instr there.
304 * For the debug message, we look at the preceding
305 * load or store.
306 */
307 if (*nip == 0x60000000) /* nop */
308 nip -= 2;
309 else if (*nip == 0x4c00012c) /* isync */
310 --nip;
311 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
312 /* sync or twi */
313 unsigned int rb;
314
315 --nip;
316 rb = (*nip >> 11) & 0x1f;
317 printk(KERN_DEBUG "%s bad port %lx at %p\n",
318 (*nip & 0x100)? "OUT to": "IN from",
319 regs->gpr[rb] - _IO_BASE, nip);
320 regs->msr |= MSR_RI;
321 regs->nip = entry->fixup;
322 return 1;
323 }
324 }
325 #endif /* CONFIG_PPC32 */
326 return 0;
327 }
328
329 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
330 /* On 4xx, the reason for the machine check or program exception
331 is in the ESR. */
332 #define get_reason(regs) ((regs)->dsisr)
333 #ifndef CONFIG_FSL_BOOKE
334 #define get_mc_reason(regs) ((regs)->dsisr)
335 #else
336 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
337 #endif
338 #define REASON_FP ESR_FP
339 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
340 #define REASON_PRIVILEGED ESR_PPR
341 #define REASON_TRAP ESR_PTR
342
343 /* single-step stuff */
344 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
345 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
346
347 #else
348 /* On non-4xx, the reason for the machine check or program
349 exception is in the MSR. */
350 #define get_reason(regs) ((regs)->msr)
351 #define get_mc_reason(regs) ((regs)->msr)
352 #define REASON_FP 0x100000
353 #define REASON_ILLEGAL 0x80000
354 #define REASON_PRIVILEGED 0x40000
355 #define REASON_TRAP 0x20000
356
357 #define single_stepping(regs) ((regs)->msr & MSR_SE)
358 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
359 #endif
360
361 #if defined(CONFIG_4xx)
362 int machine_check_4xx(struct pt_regs *regs)
363 {
364 unsigned long reason = get_mc_reason(regs);
365
366 if (reason & ESR_IMCP) {
367 printk("Instruction");
368 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
369 } else
370 printk("Data");
371 printk(" machine check in kernel mode.\n");
372
373 return 0;
374 }
375
376 int machine_check_440A(struct pt_regs *regs)
377 {
378 unsigned long reason = get_mc_reason(regs);
379
380 printk("Machine check in kernel mode.\n");
381 if (reason & ESR_IMCP){
382 printk("Instruction Synchronous Machine Check exception\n");
383 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
384 }
385 else {
386 u32 mcsr = mfspr(SPRN_MCSR);
387 if (mcsr & MCSR_IB)
388 printk("Instruction Read PLB Error\n");
389 if (mcsr & MCSR_DRB)
390 printk("Data Read PLB Error\n");
391 if (mcsr & MCSR_DWB)
392 printk("Data Write PLB Error\n");
393 if (mcsr & MCSR_TLBP)
394 printk("TLB Parity Error\n");
395 if (mcsr & MCSR_ICP){
396 flush_instruction_cache();
397 printk("I-Cache Parity Error\n");
398 }
399 if (mcsr & MCSR_DCSP)
400 printk("D-Cache Search Parity Error\n");
401 if (mcsr & MCSR_DCFP)
402 printk("D-Cache Flush Parity Error\n");
403 if (mcsr & MCSR_IMPE)
404 printk("Machine Check exception is imprecise\n");
405
406 /* Clear MCSR */
407 mtspr(SPRN_MCSR, mcsr);
408 }
409 return 0;
410 }
411
412 int machine_check_47x(struct pt_regs *regs)
413 {
414 unsigned long reason = get_mc_reason(regs);
415 u32 mcsr;
416
417 printk(KERN_ERR "Machine check in kernel mode.\n");
418 if (reason & ESR_IMCP) {
419 printk(KERN_ERR
420 "Instruction Synchronous Machine Check exception\n");
421 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
422 return 0;
423 }
424 mcsr = mfspr(SPRN_MCSR);
425 if (mcsr & MCSR_IB)
426 printk(KERN_ERR "Instruction Read PLB Error\n");
427 if (mcsr & MCSR_DRB)
428 printk(KERN_ERR "Data Read PLB Error\n");
429 if (mcsr & MCSR_DWB)
430 printk(KERN_ERR "Data Write PLB Error\n");
431 if (mcsr & MCSR_TLBP)
432 printk(KERN_ERR "TLB Parity Error\n");
433 if (mcsr & MCSR_ICP) {
434 flush_instruction_cache();
435 printk(KERN_ERR "I-Cache Parity Error\n");
436 }
437 if (mcsr & MCSR_DCSP)
438 printk(KERN_ERR "D-Cache Search Parity Error\n");
439 if (mcsr & PPC47x_MCSR_GPR)
440 printk(KERN_ERR "GPR Parity Error\n");
441 if (mcsr & PPC47x_MCSR_FPR)
442 printk(KERN_ERR "FPR Parity Error\n");
443 if (mcsr & PPC47x_MCSR_IPR)
444 printk(KERN_ERR "Machine Check exception is imprecise\n");
445
446 /* Clear MCSR */
447 mtspr(SPRN_MCSR, mcsr);
448
449 return 0;
450 }
451 #elif defined(CONFIG_E500)
452 int machine_check_e500mc(struct pt_regs *regs)
453 {
454 unsigned long mcsr = mfspr(SPRN_MCSR);
455 unsigned long reason = mcsr;
456 int recoverable = 1;
457
458 if (reason & MCSR_LD) {
459 recoverable = fsl_rio_mcheck_exception(regs);
460 if (recoverable == 1)
461 goto silent_out;
462 }
463
464 printk("Machine check in kernel mode.\n");
465 printk("Caused by (from MCSR=%lx): ", reason);
466
467 if (reason & MCSR_MCP)
468 printk("Machine Check Signal\n");
469
470 if (reason & MCSR_ICPERR) {
471 printk("Instruction Cache Parity Error\n");
472
473 /*
474 * This is recoverable by invalidating the i-cache.
475 */
476 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
477 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
478 ;
479
480 /*
481 * This will generally be accompanied by an instruction
482 * fetch error report -- only treat MCSR_IF as fatal
483 * if it wasn't due to an L1 parity error.
484 */
485 reason &= ~MCSR_IF;
486 }
487
488 if (reason & MCSR_DCPERR_MC) {
489 printk("Data Cache Parity Error\n");
490
491 /*
492 * In write shadow mode we auto-recover from the error, but it
493 * may still get logged and cause a machine check. We should
494 * only treat the non-write shadow case as non-recoverable.
495 */
496 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
497 recoverable = 0;
498 }
499
500 if (reason & MCSR_L2MMU_MHIT) {
501 printk("Hit on multiple TLB entries\n");
502 recoverable = 0;
503 }
504
505 if (reason & MCSR_NMI)
506 printk("Non-maskable interrupt\n");
507
508 if (reason & MCSR_IF) {
509 printk("Instruction Fetch Error Report\n");
510 recoverable = 0;
511 }
512
513 if (reason & MCSR_LD) {
514 printk("Load Error Report\n");
515 recoverable = 0;
516 }
517
518 if (reason & MCSR_ST) {
519 printk("Store Error Report\n");
520 recoverable = 0;
521 }
522
523 if (reason & MCSR_LDG) {
524 printk("Guarded Load Error Report\n");
525 recoverable = 0;
526 }
527
528 if (reason & MCSR_TLBSYNC)
529 printk("Simultaneous tlbsync operations\n");
530
531 if (reason & MCSR_BSL2_ERR) {
532 printk("Level 2 Cache Error\n");
533 recoverable = 0;
534 }
535
536 if (reason & MCSR_MAV) {
537 u64 addr;
538
539 addr = mfspr(SPRN_MCAR);
540 addr |= (u64)mfspr(SPRN_MCARU) << 32;
541
542 printk("Machine Check %s Address: %#llx\n",
543 reason & MCSR_MEA ? "Effective" : "Physical", addr);
544 }
545
546 silent_out:
547 mtspr(SPRN_MCSR, mcsr);
548 return mfspr(SPRN_MCSR) == 0 && recoverable;
549 }
550
551 int machine_check_e500(struct pt_regs *regs)
552 {
553 unsigned long reason = get_mc_reason(regs);
554
555 if (reason & MCSR_BUS_RBERR) {
556 if (fsl_rio_mcheck_exception(regs))
557 return 1;
558 }
559
560 printk("Machine check in kernel mode.\n");
561 printk("Caused by (from MCSR=%lx): ", reason);
562
563 if (reason & MCSR_MCP)
564 printk("Machine Check Signal\n");
565 if (reason & MCSR_ICPERR)
566 printk("Instruction Cache Parity Error\n");
567 if (reason & MCSR_DCP_PERR)
568 printk("Data Cache Push Parity Error\n");
569 if (reason & MCSR_DCPERR)
570 printk("Data Cache Parity Error\n");
571 if (reason & MCSR_BUS_IAERR)
572 printk("Bus - Instruction Address Error\n");
573 if (reason & MCSR_BUS_RAERR)
574 printk("Bus - Read Address Error\n");
575 if (reason & MCSR_BUS_WAERR)
576 printk("Bus - Write Address Error\n");
577 if (reason & MCSR_BUS_IBERR)
578 printk("Bus - Instruction Data Error\n");
579 if (reason & MCSR_BUS_RBERR)
580 printk("Bus - Read Data Bus Error\n");
581 if (reason & MCSR_BUS_WBERR)
582 printk("Bus - Read Data Bus Error\n");
583 if (reason & MCSR_BUS_IPERR)
584 printk("Bus - Instruction Parity Error\n");
585 if (reason & MCSR_BUS_RPERR)
586 printk("Bus - Read Parity Error\n");
587
588 return 0;
589 }
590
591 int machine_check_generic(struct pt_regs *regs)
592 {
593 return 0;
594 }
595 #elif defined(CONFIG_E200)
596 int machine_check_e200(struct pt_regs *regs)
597 {
598 unsigned long reason = get_mc_reason(regs);
599
600 printk("Machine check in kernel mode.\n");
601 printk("Caused by (from MCSR=%lx): ", reason);
602
603 if (reason & MCSR_MCP)
604 printk("Machine Check Signal\n");
605 if (reason & MCSR_CP_PERR)
606 printk("Cache Push Parity Error\n");
607 if (reason & MCSR_CPERR)
608 printk("Cache Parity Error\n");
609 if (reason & MCSR_EXCP_ERR)
610 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
611 if (reason & MCSR_BUS_IRERR)
612 printk("Bus - Read Bus Error on instruction fetch\n");
613 if (reason & MCSR_BUS_DRERR)
614 printk("Bus - Read Bus Error on data load\n");
615 if (reason & MCSR_BUS_WRERR)
616 printk("Bus - Write Bus Error on buffered store or cache line push\n");
617
618 return 0;
619 }
620 #else
621 int machine_check_generic(struct pt_regs *regs)
622 {
623 unsigned long reason = get_mc_reason(regs);
624
625 printk("Machine check in kernel mode.\n");
626 printk("Caused by (from SRR1=%lx): ", reason);
627 switch (reason & 0x601F0000) {
628 case 0x80000:
629 printk("Machine check signal\n");
630 break;
631 case 0: /* for 601 */
632 case 0x40000:
633 case 0x140000: /* 7450 MSS error and TEA */
634 printk("Transfer error ack signal\n");
635 break;
636 case 0x20000:
637 printk("Data parity error signal\n");
638 break;
639 case 0x10000:
640 printk("Address parity error signal\n");
641 break;
642 case 0x20000000:
643 printk("L1 Data Cache error\n");
644 break;
645 case 0x40000000:
646 printk("L1 Instruction Cache error\n");
647 break;
648 case 0x00100000:
649 printk("L2 data cache parity error\n");
650 break;
651 default:
652 printk("Unknown values in msr\n");
653 }
654 return 0;
655 }
656 #endif /* everything else */
657
658 void machine_check_exception(struct pt_regs *regs)
659 {
660 int recover = 0;
661
662 __get_cpu_var(irq_stat).mce_exceptions++;
663
664 /* See if any machine dependent calls. In theory, we would want
665 * to call the CPU first, and call the ppc_md. one if the CPU
666 * one returns a positive number. However there is existing code
667 * that assumes the board gets a first chance, so let's keep it
668 * that way for now and fix things later. --BenH.
669 */
670 if (ppc_md.machine_check_exception)
671 recover = ppc_md.machine_check_exception(regs);
672 else if (cur_cpu_spec->machine_check)
673 recover = cur_cpu_spec->machine_check(regs);
674
675 if (recover > 0)
676 return;
677
678 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
679 /* the qspan pci read routines can cause machine checks -- Cort
680 *
681 * yuck !!! that totally needs to go away ! There are better ways
682 * to deal with that than having a wart in the mcheck handler.
683 * -- BenH
684 */
685 bad_page_fault(regs, regs->dar, SIGBUS);
686 return;
687 #endif
688
689 if (debugger_fault_handler(regs))
690 return;
691
692 if (check_io_access(regs))
693 return;
694
695 die("Machine check", regs, SIGBUS);
696
697 /* Must die if the interrupt is not recoverable */
698 if (!(regs->msr & MSR_RI))
699 panic("Unrecoverable Machine check");
700 }
701
702 void SMIException(struct pt_regs *regs)
703 {
704 die("System Management Interrupt", regs, SIGABRT);
705 }
706
707 void unknown_exception(struct pt_regs *regs)
708 {
709 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
710 regs->nip, regs->msr, regs->trap);
711
712 _exception(SIGTRAP, regs, 0, 0);
713 }
714
715 void instruction_breakpoint_exception(struct pt_regs *regs)
716 {
717 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
718 5, SIGTRAP) == NOTIFY_STOP)
719 return;
720 if (debugger_iabr_match(regs))
721 return;
722 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
723 }
724
725 void RunModeException(struct pt_regs *regs)
726 {
727 _exception(SIGTRAP, regs, 0, 0);
728 }
729
730 void __kprobes single_step_exception(struct pt_regs *regs)
731 {
732 clear_single_step(regs);
733
734 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
735 5, SIGTRAP) == NOTIFY_STOP)
736 return;
737 if (debugger_sstep(regs))
738 return;
739
740 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
741 }
742
743 /*
744 * After we have successfully emulated an instruction, we have to
745 * check if the instruction was being single-stepped, and if so,
746 * pretend we got a single-step exception. This was pointed out
747 * by Kumar Gala. -- paulus
748 */
749 static void emulate_single_step(struct pt_regs *regs)
750 {
751 if (single_stepping(regs))
752 single_step_exception(regs);
753 }
754
755 static inline int __parse_fpscr(unsigned long fpscr)
756 {
757 int ret = 0;
758
759 /* Invalid operation */
760 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
761 ret = FPE_FLTINV;
762
763 /* Overflow */
764 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
765 ret = FPE_FLTOVF;
766
767 /* Underflow */
768 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
769 ret = FPE_FLTUND;
770
771 /* Divide by zero */
772 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
773 ret = FPE_FLTDIV;
774
775 /* Inexact result */
776 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
777 ret = FPE_FLTRES;
778
779 return ret;
780 }
781
782 static void parse_fpe(struct pt_regs *regs)
783 {
784 int code = 0;
785
786 flush_fp_to_thread(current);
787
788 code = __parse_fpscr(current->thread.fpscr.val);
789
790 _exception(SIGFPE, regs, code, regs->nip);
791 }
792
793 /*
794 * Illegal instruction emulation support. Originally written to
795 * provide the PVR to user applications using the mfspr rd, PVR.
796 * Return non-zero if we can't emulate, or -EFAULT if the associated
797 * memory access caused an access fault. Return zero on success.
798 *
799 * There are a couple of ways to do this, either "decode" the instruction
800 * or directly match lots of bits. In this case, matching lots of
801 * bits is faster and easier.
802 *
803 */
804 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
805 {
806 u8 rT = (instword >> 21) & 0x1f;
807 u8 rA = (instword >> 16) & 0x1f;
808 u8 NB_RB = (instword >> 11) & 0x1f;
809 u32 num_bytes;
810 unsigned long EA;
811 int pos = 0;
812
813 /* Early out if we are an invalid form of lswx */
814 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
815 if ((rT == rA) || (rT == NB_RB))
816 return -EINVAL;
817
818 EA = (rA == 0) ? 0 : regs->gpr[rA];
819
820 switch (instword & PPC_INST_STRING_MASK) {
821 case PPC_INST_LSWX:
822 case PPC_INST_STSWX:
823 EA += NB_RB;
824 num_bytes = regs->xer & 0x7f;
825 break;
826 case PPC_INST_LSWI:
827 case PPC_INST_STSWI:
828 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 while (num_bytes != 0)
835 {
836 u8 val;
837 u32 shift = 8 * (3 - (pos & 0x3));
838
839 switch ((instword & PPC_INST_STRING_MASK)) {
840 case PPC_INST_LSWX:
841 case PPC_INST_LSWI:
842 if (get_user(val, (u8 __user *)EA))
843 return -EFAULT;
844 /* first time updating this reg,
845 * zero it out */
846 if (pos == 0)
847 regs->gpr[rT] = 0;
848 regs->gpr[rT] |= val << shift;
849 break;
850 case PPC_INST_STSWI:
851 case PPC_INST_STSWX:
852 val = regs->gpr[rT] >> shift;
853 if (put_user(val, (u8 __user *)EA))
854 return -EFAULT;
855 break;
856 }
857 /* move EA to next address */
858 EA += 1;
859 num_bytes--;
860
861 /* manage our position within the register */
862 if (++pos == 4) {
863 pos = 0;
864 if (++rT == 32)
865 rT = 0;
866 }
867 }
868
869 return 0;
870 }
871
872 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
873 {
874 u32 ra,rs;
875 unsigned long tmp;
876
877 ra = (instword >> 16) & 0x1f;
878 rs = (instword >> 21) & 0x1f;
879
880 tmp = regs->gpr[rs];
881 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
882 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
883 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
884 regs->gpr[ra] = tmp;
885
886 return 0;
887 }
888
889 static int emulate_isel(struct pt_regs *regs, u32 instword)
890 {
891 u8 rT = (instword >> 21) & 0x1f;
892 u8 rA = (instword >> 16) & 0x1f;
893 u8 rB = (instword >> 11) & 0x1f;
894 u8 BC = (instword >> 6) & 0x1f;
895 u8 bit;
896 unsigned long tmp;
897
898 tmp = (rA == 0) ? 0 : regs->gpr[rA];
899 bit = (regs->ccr >> (31 - BC)) & 0x1;
900
901 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
902
903 return 0;
904 }
905
906 static int emulate_instruction(struct pt_regs *regs)
907 {
908 u32 instword;
909 u32 rd;
910
911 if (!user_mode(regs) || (regs->msr & MSR_LE))
912 return -EINVAL;
913 CHECK_FULL_REGS(regs);
914
915 if (get_user(instword, (u32 __user *)(regs->nip)))
916 return -EFAULT;
917
918 /* Emulate the mfspr rD, PVR. */
919 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
920 PPC_WARN_EMULATED(mfpvr, regs);
921 rd = (instword >> 21) & 0x1f;
922 regs->gpr[rd] = mfspr(SPRN_PVR);
923 return 0;
924 }
925
926 /* Emulating the dcba insn is just a no-op. */
927 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
928 PPC_WARN_EMULATED(dcba, regs);
929 return 0;
930 }
931
932 /* Emulate the mcrxr insn. */
933 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
934 int shift = (instword >> 21) & 0x1c;
935 unsigned long msk = 0xf0000000UL >> shift;
936
937 PPC_WARN_EMULATED(mcrxr, regs);
938 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
939 regs->xer &= ~0xf0000000UL;
940 return 0;
941 }
942
943 /* Emulate load/store string insn. */
944 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
945 PPC_WARN_EMULATED(string, regs);
946 return emulate_string_inst(regs, instword);
947 }
948
949 /* Emulate the popcntb (Population Count Bytes) instruction. */
950 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
951 PPC_WARN_EMULATED(popcntb, regs);
952 return emulate_popcntb_inst(regs, instword);
953 }
954
955 /* Emulate isel (Integer Select) instruction */
956 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
957 PPC_WARN_EMULATED(isel, regs);
958 return emulate_isel(regs, instword);
959 }
960
961 #ifdef CONFIG_PPC64
962 /* Emulate the mfspr rD, DSCR. */
963 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
964 cpu_has_feature(CPU_FTR_DSCR)) {
965 PPC_WARN_EMULATED(mfdscr, regs);
966 rd = (instword >> 21) & 0x1f;
967 regs->gpr[rd] = mfspr(SPRN_DSCR);
968 return 0;
969 }
970 /* Emulate the mtspr DSCR, rD. */
971 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
972 cpu_has_feature(CPU_FTR_DSCR)) {
973 PPC_WARN_EMULATED(mtdscr, regs);
974 rd = (instword >> 21) & 0x1f;
975 current->thread.dscr = regs->gpr[rd];
976 current->thread.dscr_inherit = 1;
977 mtspr(SPRN_DSCR, current->thread.dscr);
978 return 0;
979 }
980 #endif
981
982 return -EINVAL;
983 }
984
985 int is_valid_bugaddr(unsigned long addr)
986 {
987 return is_kernel_addr(addr);
988 }
989
990 void __kprobes program_check_exception(struct pt_regs *regs)
991 {
992 unsigned int reason = get_reason(regs);
993 extern int do_mathemu(struct pt_regs *regs);
994
995 /* We can now get here via a FP Unavailable exception if the core
996 * has no FPU, in that case the reason flags will be 0 */
997
998 if (reason & REASON_FP) {
999 /* IEEE FP exception */
1000 parse_fpe(regs);
1001 return;
1002 }
1003 if (reason & REASON_TRAP) {
1004 /* Debugger is first in line to stop recursive faults in
1005 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1006 if (debugger_bpt(regs))
1007 return;
1008
1009 /* trap exception */
1010 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1011 == NOTIFY_STOP)
1012 return;
1013
1014 if (!(regs->msr & MSR_PR) && /* not user-mode */
1015 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1016 regs->nip += 4;
1017 return;
1018 }
1019 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1020 return;
1021 }
1022
1023 /* We restore the interrupt state now */
1024 if (!arch_irq_disabled_regs(regs))
1025 local_irq_enable();
1026
1027 #ifdef CONFIG_MATH_EMULATION
1028 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1029 * but there seems to be a hardware bug on the 405GP (RevD)
1030 * that means ESR is sometimes set incorrectly - either to
1031 * ESR_DST (!?) or 0. In the process of chasing this with the
1032 * hardware people - not sure if it can happen on any illegal
1033 * instruction or only on FP instructions, whether there is a
1034 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1035 switch (do_mathemu(regs)) {
1036 case 0:
1037 emulate_single_step(regs);
1038 return;
1039 case 1: {
1040 int code = 0;
1041 code = __parse_fpscr(current->thread.fpscr.val);
1042 _exception(SIGFPE, regs, code, regs->nip);
1043 return;
1044 }
1045 case -EFAULT:
1046 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1047 return;
1048 }
1049 /* fall through on any other errors */
1050 #endif /* CONFIG_MATH_EMULATION */
1051
1052 /* Try to emulate it if we should. */
1053 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1054 switch (emulate_instruction(regs)) {
1055 case 0:
1056 regs->nip += 4;
1057 emulate_single_step(regs);
1058 return;
1059 case -EFAULT:
1060 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1061 return;
1062 }
1063 }
1064
1065 if (reason & REASON_PRIVILEGED)
1066 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1067 else
1068 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1069 }
1070
1071 void alignment_exception(struct pt_regs *regs)
1072 {
1073 int sig, code, fixed = 0;
1074
1075 /* We restore the interrupt state now */
1076 if (!arch_irq_disabled_regs(regs))
1077 local_irq_enable();
1078
1079 /* we don't implement logging of alignment exceptions */
1080 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1081 fixed = fix_alignment(regs);
1082
1083 if (fixed == 1) {
1084 regs->nip += 4; /* skip over emulated instruction */
1085 emulate_single_step(regs);
1086 return;
1087 }
1088
1089 /* Operand address was bad */
1090 if (fixed == -EFAULT) {
1091 sig = SIGSEGV;
1092 code = SEGV_ACCERR;
1093 } else {
1094 sig = SIGBUS;
1095 code = BUS_ADRALN;
1096 }
1097 if (user_mode(regs))
1098 _exception(sig, regs, code, regs->dar);
1099 else
1100 bad_page_fault(regs, regs->dar, sig);
1101 }
1102
1103 void StackOverflow(struct pt_regs *regs)
1104 {
1105 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1106 current, regs->gpr[1]);
1107 debugger(regs);
1108 show_regs(regs);
1109 panic("kernel stack overflow");
1110 }
1111
1112 void nonrecoverable_exception(struct pt_regs *regs)
1113 {
1114 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1115 regs->nip, regs->msr);
1116 debugger(regs);
1117 die("nonrecoverable exception", regs, SIGKILL);
1118 }
1119
1120 void trace_syscall(struct pt_regs *regs)
1121 {
1122 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1123 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1124 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1125 }
1126
1127 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1128 {
1129 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1130 "%lx at %lx\n", regs->trap, regs->nip);
1131 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1132 }
1133
1134 void altivec_unavailable_exception(struct pt_regs *regs)
1135 {
1136 if (user_mode(regs)) {
1137 /* A user program has executed an altivec instruction,
1138 but this kernel doesn't support altivec. */
1139 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1140 return;
1141 }
1142
1143 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1144 "%lx at %lx\n", regs->trap, regs->nip);
1145 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1146 }
1147
1148 void vsx_unavailable_exception(struct pt_regs *regs)
1149 {
1150 if (user_mode(regs)) {
1151 /* A user program has executed an vsx instruction,
1152 but this kernel doesn't support vsx. */
1153 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1154 return;
1155 }
1156
1157 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1158 "%lx at %lx\n", regs->trap, regs->nip);
1159 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1160 }
1161
1162 void performance_monitor_exception(struct pt_regs *regs)
1163 {
1164 __get_cpu_var(irq_stat).pmu_irqs++;
1165
1166 perf_irq(regs);
1167 }
1168
1169 #ifdef CONFIG_8xx
1170 void SoftwareEmulation(struct pt_regs *regs)
1171 {
1172 extern int do_mathemu(struct pt_regs *);
1173 extern int Soft_emulate_8xx(struct pt_regs *);
1174 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1175 int errcode;
1176 #endif
1177
1178 CHECK_FULL_REGS(regs);
1179
1180 if (!user_mode(regs)) {
1181 debugger(regs);
1182 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1183 }
1184
1185 #ifdef CONFIG_MATH_EMULATION
1186 errcode = do_mathemu(regs);
1187 if (errcode >= 0)
1188 PPC_WARN_EMULATED(math, regs);
1189
1190 switch (errcode) {
1191 case 0:
1192 emulate_single_step(regs);
1193 return;
1194 case 1: {
1195 int code = 0;
1196 code = __parse_fpscr(current->thread.fpscr.val);
1197 _exception(SIGFPE, regs, code, regs->nip);
1198 return;
1199 }
1200 case -EFAULT:
1201 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1202 return;
1203 default:
1204 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1205 return;
1206 }
1207
1208 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1209 errcode = Soft_emulate_8xx(regs);
1210 if (errcode >= 0)
1211 PPC_WARN_EMULATED(8xx, regs);
1212
1213 switch (errcode) {
1214 case 0:
1215 emulate_single_step(regs);
1216 return;
1217 case 1:
1218 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1219 return;
1220 case -EFAULT:
1221 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1222 return;
1223 }
1224 #else
1225 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1226 #endif
1227 }
1228 #endif /* CONFIG_8xx */
1229
1230 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1231 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1232 {
1233 int changed = 0;
1234 /*
1235 * Determine the cause of the debug event, clear the
1236 * event flags and send a trap to the handler. Torez
1237 */
1238 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1239 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1240 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1241 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1242 #endif
1243 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1244 5);
1245 changed |= 0x01;
1246 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1247 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1248 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1249 6);
1250 changed |= 0x01;
1251 } else if (debug_status & DBSR_IAC1) {
1252 current->thread.dbcr0 &= ~DBCR0_IAC1;
1253 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1254 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1255 1);
1256 changed |= 0x01;
1257 } else if (debug_status & DBSR_IAC2) {
1258 current->thread.dbcr0 &= ~DBCR0_IAC2;
1259 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1260 2);
1261 changed |= 0x01;
1262 } else if (debug_status & DBSR_IAC3) {
1263 current->thread.dbcr0 &= ~DBCR0_IAC3;
1264 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1265 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1266 3);
1267 changed |= 0x01;
1268 } else if (debug_status & DBSR_IAC4) {
1269 current->thread.dbcr0 &= ~DBCR0_IAC4;
1270 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1271 4);
1272 changed |= 0x01;
1273 }
1274 /*
1275 * At the point this routine was called, the MSR(DE) was turned off.
1276 * Check all other debug flags and see if that bit needs to be turned
1277 * back on or not.
1278 */
1279 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1280 regs->msr |= MSR_DE;
1281 else
1282 /* Make sure the IDM flag is off */
1283 current->thread.dbcr0 &= ~DBCR0_IDM;
1284
1285 if (changed & 0x01)
1286 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1287 }
1288
1289 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1290 {
1291 current->thread.dbsr = debug_status;
1292
1293 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1294 * on server, it stops on the target of the branch. In order to simulate
1295 * the server behaviour, we thus restart right away with a single step
1296 * instead of stopping here when hitting a BT
1297 */
1298 if (debug_status & DBSR_BT) {
1299 regs->msr &= ~MSR_DE;
1300
1301 /* Disable BT */
1302 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1303 /* Clear the BT event */
1304 mtspr(SPRN_DBSR, DBSR_BT);
1305
1306 /* Do the single step trick only when coming from userspace */
1307 if (user_mode(regs)) {
1308 current->thread.dbcr0 &= ~DBCR0_BT;
1309 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1310 regs->msr |= MSR_DE;
1311 return;
1312 }
1313
1314 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1315 5, SIGTRAP) == NOTIFY_STOP) {
1316 return;
1317 }
1318 if (debugger_sstep(regs))
1319 return;
1320 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1321 regs->msr &= ~MSR_DE;
1322
1323 /* Disable instruction completion */
1324 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1325 /* Clear the instruction completion event */
1326 mtspr(SPRN_DBSR, DBSR_IC);
1327
1328 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1329 5, SIGTRAP) == NOTIFY_STOP) {
1330 return;
1331 }
1332
1333 if (debugger_sstep(regs))
1334 return;
1335
1336 if (user_mode(regs)) {
1337 current->thread.dbcr0 &= ~DBCR0_IC;
1338 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1339 current->thread.dbcr1))
1340 regs->msr |= MSR_DE;
1341 else
1342 /* Make sure the IDM bit is off */
1343 current->thread.dbcr0 &= ~DBCR0_IDM;
1344 }
1345
1346 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1347 } else
1348 handle_debug(regs, debug_status);
1349 }
1350 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1351
1352 #if !defined(CONFIG_TAU_INT)
1353 void TAUException(struct pt_regs *regs)
1354 {
1355 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1356 regs->nip, regs->msr, regs->trap, print_tainted());
1357 }
1358 #endif /* CONFIG_INT_TAU */
1359
1360 #ifdef CONFIG_ALTIVEC
1361 void altivec_assist_exception(struct pt_regs *regs)
1362 {
1363 int err;
1364
1365 if (!user_mode(regs)) {
1366 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1367 " at %lx\n", regs->nip);
1368 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1369 }
1370
1371 flush_altivec_to_thread(current);
1372
1373 PPC_WARN_EMULATED(altivec, regs);
1374 err = emulate_altivec(regs);
1375 if (err == 0) {
1376 regs->nip += 4; /* skip emulated instruction */
1377 emulate_single_step(regs);
1378 return;
1379 }
1380
1381 if (err == -EFAULT) {
1382 /* got an error reading the instruction */
1383 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1384 } else {
1385 /* didn't recognize the instruction */
1386 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1387 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1388 "in %s at %lx\n", current->comm, regs->nip);
1389 current->thread.vscr.u[3] |= 0x10000;
1390 }
1391 }
1392 #endif /* CONFIG_ALTIVEC */
1393
1394 #ifdef CONFIG_VSX
1395 void vsx_assist_exception(struct pt_regs *regs)
1396 {
1397 if (!user_mode(regs)) {
1398 printk(KERN_EMERG "VSX assist exception in kernel mode"
1399 " at %lx\n", regs->nip);
1400 die("Kernel VSX assist exception", regs, SIGILL);
1401 }
1402
1403 flush_vsx_to_thread(current);
1404 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1405 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1406 }
1407 #endif /* CONFIG_VSX */
1408
1409 #ifdef CONFIG_FSL_BOOKE
1410 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1411 unsigned long error_code)
1412 {
1413 /* We treat cache locking instructions from the user
1414 * as priv ops, in the future we could try to do
1415 * something smarter
1416 */
1417 if (error_code & (ESR_DLK|ESR_ILK))
1418 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1419 return;
1420 }
1421 #endif /* CONFIG_FSL_BOOKE */
1422
1423 #ifdef CONFIG_SPE
1424 void SPEFloatingPointException(struct pt_regs *regs)
1425 {
1426 extern int do_spe_mathemu(struct pt_regs *regs);
1427 unsigned long spefscr;
1428 int fpexc_mode;
1429 int code = 0;
1430 int err;
1431
1432 flush_spe_to_thread(current);
1433
1434 spefscr = current->thread.spefscr;
1435 fpexc_mode = current->thread.fpexc_mode;
1436
1437 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1438 code = FPE_FLTOVF;
1439 }
1440 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1441 code = FPE_FLTUND;
1442 }
1443 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1444 code = FPE_FLTDIV;
1445 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1446 code = FPE_FLTINV;
1447 }
1448 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1449 code = FPE_FLTRES;
1450
1451 err = do_spe_mathemu(regs);
1452 if (err == 0) {
1453 regs->nip += 4; /* skip emulated instruction */
1454 emulate_single_step(regs);
1455 return;
1456 }
1457
1458 if (err == -EFAULT) {
1459 /* got an error reading the instruction */
1460 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1461 } else if (err == -EINVAL) {
1462 /* didn't recognize the instruction */
1463 printk(KERN_ERR "unrecognized spe instruction "
1464 "in %s at %lx\n", current->comm, regs->nip);
1465 } else {
1466 _exception(SIGFPE, regs, code, regs->nip);
1467 }
1468
1469 return;
1470 }
1471
1472 void SPEFloatingPointRoundException(struct pt_regs *regs)
1473 {
1474 extern int speround_handler(struct pt_regs *regs);
1475 int err;
1476
1477 preempt_disable();
1478 if (regs->msr & MSR_SPE)
1479 giveup_spe(current);
1480 preempt_enable();
1481
1482 regs->nip -= 4;
1483 err = speround_handler(regs);
1484 if (err == 0) {
1485 regs->nip += 4; /* skip emulated instruction */
1486 emulate_single_step(regs);
1487 return;
1488 }
1489
1490 if (err == -EFAULT) {
1491 /* got an error reading the instruction */
1492 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1493 } else if (err == -EINVAL) {
1494 /* didn't recognize the instruction */
1495 printk(KERN_ERR "unrecognized spe instruction "
1496 "in %s at %lx\n", current->comm, regs->nip);
1497 } else {
1498 _exception(SIGFPE, regs, 0, regs->nip);
1499 return;
1500 }
1501 }
1502 #endif
1503
1504 /*
1505 * We enter here if we get an unrecoverable exception, that is, one
1506 * that happened at a point where the RI (recoverable interrupt) bit
1507 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1508 * we therefore lost state by taking this exception.
1509 */
1510 void unrecoverable_exception(struct pt_regs *regs)
1511 {
1512 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1513 regs->trap, regs->nip);
1514 die("Unrecoverable exception", regs, SIGABRT);
1515 }
1516
1517 #ifdef CONFIG_BOOKE_WDT
1518 /*
1519 * Default handler for a Watchdog exception,
1520 * spins until a reboot occurs
1521 */
1522 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1523 {
1524 /* Generic WatchdogHandler, implement your own */
1525 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1526 return;
1527 }
1528
1529 void WatchdogException(struct pt_regs *regs)
1530 {
1531 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1532 WatchdogHandler(regs);
1533 }
1534 #endif
1535
1536 /*
1537 * We enter here if we discover during exception entry that we are
1538 * running in supervisor mode with a userspace value in the stack pointer.
1539 */
1540 void kernel_bad_stack(struct pt_regs *regs)
1541 {
1542 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1543 regs->gpr[1], regs->nip);
1544 die("Bad kernel stack pointer", regs, SIGABRT);
1545 }
1546
1547 void __init trap_init(void)
1548 {
1549 }
1550
1551
1552 #ifdef CONFIG_PPC_EMULATED_STATS
1553
1554 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1555
1556 struct ppc_emulated ppc_emulated = {
1557 #ifdef CONFIG_ALTIVEC
1558 WARN_EMULATED_SETUP(altivec),
1559 #endif
1560 WARN_EMULATED_SETUP(dcba),
1561 WARN_EMULATED_SETUP(dcbz),
1562 WARN_EMULATED_SETUP(fp_pair),
1563 WARN_EMULATED_SETUP(isel),
1564 WARN_EMULATED_SETUP(mcrxr),
1565 WARN_EMULATED_SETUP(mfpvr),
1566 WARN_EMULATED_SETUP(multiple),
1567 WARN_EMULATED_SETUP(popcntb),
1568 WARN_EMULATED_SETUP(spe),
1569 WARN_EMULATED_SETUP(string),
1570 WARN_EMULATED_SETUP(unaligned),
1571 #ifdef CONFIG_MATH_EMULATION
1572 WARN_EMULATED_SETUP(math),
1573 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1574 WARN_EMULATED_SETUP(8xx),
1575 #endif
1576 #ifdef CONFIG_VSX
1577 WARN_EMULATED_SETUP(vsx),
1578 #endif
1579 #ifdef CONFIG_PPC64
1580 WARN_EMULATED_SETUP(mfdscr),
1581 WARN_EMULATED_SETUP(mtdscr),
1582 #endif
1583 };
1584
1585 u32 ppc_warn_emulated;
1586
1587 void ppc_warn_emulated_print(const char *type)
1588 {
1589 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1590 type);
1591 }
1592
1593 static int __init ppc_warn_emulated_init(void)
1594 {
1595 struct dentry *dir, *d;
1596 unsigned int i;
1597 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1598
1599 if (!powerpc_debugfs_root)
1600 return -ENODEV;
1601
1602 dir = debugfs_create_dir("emulated_instructions",
1603 powerpc_debugfs_root);
1604 if (!dir)
1605 return -ENOMEM;
1606
1607 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1608 &ppc_warn_emulated);
1609 if (!d)
1610 goto fail;
1611
1612 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1613 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1614 (u32 *)&entries[i].val.counter);
1615 if (!d)
1616 goto fail;
1617 }
1618
1619 return 0;
1620
1621 fail:
1622 debugfs_remove_recursive(dir);
1623 return -ENOMEM;
1624 }
1625
1626 device_initcall(ppc_warn_emulated_init);
1627
1628 #endif /* CONFIG_PPC_EMULATED_STATS */
Linux ARM platform port for MOXA ART SoC