arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/serial_sci.h>
  18 #include <generated/machtypes.h>
  19
  20 static struct resource rtc_resources[] = {
  21         [0] = {
  22                 .start  = 0xffc80000,
  23                 .end    = 0xffc80000 + 0x58 - 1,
  24                 .flags  = IORESOURCE_IO,
  25         },
  26         [1] = {
  27                 /* Shared Period/Carry/Alarm IRQ */
  28                 .start  = evt2irq(0x480),
  29                 .flags  = IORESOURCE_IRQ,
  30         },
  31 };
  32
  33 static struct platform_device rtc_device = {
  34         .name           = "sh-rtc",
  35         .id             = -1,
  36         .num_resources  = ARRAY_SIZE(rtc_resources),
  37         .resource       = rtc_resources,
  38 };
  39
  40 static struct plat_sci_port sci_platform_data = {
  41         .mapbase        = 0xffe00000,
  42         .port_reg       = 0xffe0001C,
  43         .flags          = UPF_BOOT_AUTOCONF,
  44         .scscr          = SCSCR_TE | SCSCR_RE,
  45         .scbrr_algo_id  = SCBRR_ALGO_2,
  46         .type           = PORT_SCI,
  47         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
  48         .regshift       = 2,
  49 };
  50
  51 static struct platform_device sci_device = {
  52         .name           = "sh-sci",
  53         .id             = 0,
  54         .dev            = {
  55                 .platform_data  = &sci_platform_data,
  56         },
  57 };
  58
  59 static struct plat_sci_port scif_platform_data = {
  60         .mapbase        = 0xffe80000,
  61         .flags          = UPF_BOOT_AUTOCONF,
  62         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
  63         .scbrr_algo_id  = SCBRR_ALGO_2,
  64         .type           = PORT_SCIF,
  65         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
  66 };
  67
  68 static struct platform_device scif_device = {
  69         .name           = "sh-sci",
  70         .id             = 1,
  71         .dev            = {
  72                 .platform_data  = &scif_platform_data,
  73         },
  74 };
  75
  76 static struct sh_timer_config tmu0_platform_data = {
  77         .channel_offset = 0x04,
  78         .timer_bit = 0,
  79         .clockevent_rating = 200,
  80 };
  81
  82 static struct resource tmu0_resources[] = {
  83         [0] = {
  84                 .start  = 0xffd80008,
  85                 .end    = 0xffd80013,
  86                 .flags  = IORESOURCE_MEM,
  87         },
  88         [1] = {
  89                 .start  = evt2irq(0x400),
  90                 .flags  = IORESOURCE_IRQ,
  91         },
  92 };
  93
  94 static struct platform_device tmu0_device = {
  95         .name           = "sh_tmu",
  96         .id             = 0,
  97         .dev = {
  98                 .platform_data  = &tmu0_platform_data,
  99         },
 100         .resource       = tmu0_resources,
 101         .num_resources  = ARRAY_SIZE(tmu0_resources),
 102 };
 103
 104 static struct sh_timer_config tmu1_platform_data = {
 105         .channel_offset = 0x10,
 106         .timer_bit = 1,
 107         .clocksource_rating = 200,
 108 };
 109
 110 static struct resource tmu1_resources[] = {
 111         [0] = {
 112                 .start  = 0xffd80014,
 113                 .end    = 0xffd8001f,
 114                 .flags  = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start  = evt2irq(0x420),
 118                 .flags  = IORESOURCE_IRQ,
 119         },
 120 };
 121
 122 static struct platform_device tmu1_device = {
 123         .name           = "sh_tmu",
 124         .id             = 1,
 125         .dev = {
 126                 .platform_data  = &tmu1_platform_data,
 127         },
 128         .resource       = tmu1_resources,
 129         .num_resources  = ARRAY_SIZE(tmu1_resources),
 130 };
 131
 132 static struct sh_timer_config tmu2_platform_data = {
 133         .channel_offset = 0x1c,
 134         .timer_bit = 2,
 135 };
 136
 137 static struct resource tmu2_resources[] = {
 138         [0] = {
 139                 .start  = 0xffd80020,
 140                 .end    = 0xffd8002f,
 141                 .flags  = IORESOURCE_MEM,
 142         },
 143         [1] = {
 144                 .start  = evt2irq(0x440),
 145                 .flags  = IORESOURCE_IRQ,
 146         },
 147 };
 148
 149 static struct platform_device tmu2_device = {
 150         .name           = "sh_tmu",
 151         .id             = 2,
 152         .dev = {
 153                 .platform_data  = &tmu2_platform_data,
 154         },
 155         .resource       = tmu2_resources,
 156         .num_resources  = ARRAY_SIZE(tmu2_resources),
 157 };
 158
 159 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 160 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 161         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 162         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 163
 164 static struct sh_timer_config tmu3_platform_data = {
 165         .channel_offset = 0x04,
 166         .timer_bit = 0,
 167 };
 168
 169 static struct resource tmu3_resources[] = {
 170         [0] = {
 171                 .start  = 0xfe100008,
 172                 .end    = 0xfe100013,
 173                 .flags  = IORESOURCE_MEM,
 174         },
 175         [1] = {
 176                 .start  = evt2irq(0xb00),
 177                 .flags  = IORESOURCE_IRQ,
 178         },
 179 };
 180
 181 static struct platform_device tmu3_device = {
 182         .name           = "sh_tmu",
 183         .id             = 3,
 184         .dev = {
 185                 .platform_data  = &tmu3_platform_data,
 186         },
 187         .resource       = tmu3_resources,
 188         .num_resources  = ARRAY_SIZE(tmu3_resources),
 189 };
 190
 191 static struct sh_timer_config tmu4_platform_data = {
 192         .channel_offset = 0x10,
 193         .timer_bit = 1,
 194 };
 195
 196 static struct resource tmu4_resources[] = {
 197         [0] = {
 198                 .start  = 0xfe100014,
 199                 .end    = 0xfe10001f,
 200                 .flags  = IORESOURCE_MEM,
 201         },
 202         [1] = {
 203                 .start  = evt2irq(0xb80),
 204                 .flags  = IORESOURCE_IRQ,
 205         },
 206 };
 207
 208 static struct platform_device tmu4_device = {
 209         .name           = "sh_tmu",
 210         .id             = 4,
 211         .dev = {
 212                 .platform_data  = &tmu4_platform_data,
 213         },
 214         .resource       = tmu4_resources,
 215         .num_resources  = ARRAY_SIZE(tmu4_resources),
 216 };
 217
 218 #endif
 219
 220 static struct platform_device *sh7750_devices[] __initdata = {
 221         &rtc_device,
 222         &tmu0_device,
 223         &tmu1_device,
 224         &tmu2_device,
 225 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 226         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 227         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 228         &tmu3_device,
 229         &tmu4_device,
 230 #endif
 231 };
 232
 233 static int __init sh7750_devices_setup(void)
 234 {
 235         if (mach_is_rts7751r2d()) {
 236                 platform_device_register(&scif_device);
 237         } else {
 238                 platform_device_register(&sci_device);
 239                 platform_device_register(&scif_device);
 240         }
 241
 242         return platform_add_devices(sh7750_devices,
 243                                     ARRAY_SIZE(sh7750_devices));
 244 }
 245 arch_initcall(sh7750_devices_setup);
 246
 247 static struct platform_device *sh7750_early_devices[] __initdata = {
 248         &tmu0_device,
 249         &tmu1_device,
 250         &tmu2_device,
 251 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 252         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 253         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 254         &tmu3_device,
 255         &tmu4_device,
 256 #endif
 257 };
 258
 259 void __init plat_early_device_setup(void)
 260 {
 261         struct platform_device *dev[1];
 262
 263         if (mach_is_rts7751r2d()) {
 264                 scif_platform_data.scscr |= SCSCR_CKE1;
 265                 dev[0] = &scif_device;
 266                 early_platform_add_devices(dev, 1);
 267         } else {
 268                 dev[0] = &sci_device;
 269                 early_platform_add_devices(dev, 1);
 270                 dev[0] = &scif_device;
 271                 early_platform_add_devices(dev, 1);
 272         }
 273
 274         early_platform_add_devices(sh7750_early_devices,
 275                                    ARRAY_SIZE(sh7750_early_devices));
 276 }
 277
 278 enum {
 279         UNUSED = 0,
 280
 281         /* interrupt sources */
 282         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 283         HUDI, GPIOI, DMAC,
 284         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 285         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 286         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 287
 288         /* interrupt groups */
 289         PCIC1,
 290 };
 291
 292 static struct intc_vect vectors[] __initdata = {
 293         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 294         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 295         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 296         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 297         INTC_VECT(RTC, 0x4c0),
 298         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 299         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 300         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 301         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 302         INTC_VECT(WDT, 0x560),
 303         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 304 };
 305
 306 static struct intc_prio_reg prio_registers[] __initdata = {
 307         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 308         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 309         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 310         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 311         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 312                                                  TMU4, TMU3,
 313                                                  PCIC1, PCIC0_PCISERR } },
 314 };
 315
 316 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 317                          NULL, prio_registers, NULL);
 318
 319 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 320 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 321         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 322         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 323         defined(CONFIG_CPU_SUBTYPE_SH7091)
 324 static struct intc_vect vectors_dma4[] __initdata = {
 325         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 326         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 327         INTC_VECT(DMAC, 0x6c0),
 328 };
 329
 330 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 331                          vectors_dma4, NULL,
 332                          NULL, prio_registers, NULL);
 333 #endif
 334
 335 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 336 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 337 static struct intc_vect vectors_dma8[] __initdata = {
 338         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 339         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 340         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 341         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 342         INTC_VECT(DMAC, 0x6c0),
 343 };
 344
 345 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 346                          vectors_dma8, NULL,
 347                          NULL, prio_registers, NULL);
 348 #endif
 349
 350 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 351 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 352         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 353         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 354 static struct intc_vect vectors_tmu34[] __initdata = {
 355         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 356 };
 357
 358 static struct intc_mask_reg mask_registers[] __initdata = {
 359         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 360           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 361             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 362             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 363             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 364             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 365 };
 366
 367 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 368                          vectors_tmu34, NULL,
 369                          mask_registers, prio_registers, NULL);
 370 #endif
 371
 372 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 373 static struct intc_vect vectors_irlm[] __initdata = {
 374         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 375         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 376 };
 377
 378 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 379                          NULL, prio_registers, NULL);
 380
 381 /* SH7751 and SH7751R both have PCI */
 382 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 383 static struct intc_vect vectors_pci[] __initdata = {
 384         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 385         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 386         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 387         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 388 };
 389
 390 static struct intc_group groups_pci[] __initdata = {
 391         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 392                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 393 };
 394
 395 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 396                          mask_registers, prio_registers, NULL);
 397 #endif
 398
 399 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 400         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 401         defined(CONFIG_CPU_SUBTYPE_SH7091)
 402 void __init plat_irq_setup(void)
 403 {
 404         /*
 405          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 406          * see below..
 407          */
 408         register_intc_controller(&intc_desc);
 409         register_intc_controller(&intc_desc_dma4);
 410 }
 411 #endif
 412
 413 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 414 void __init plat_irq_setup(void)
 415 {
 416         register_intc_controller(&intc_desc);
 417         register_intc_controller(&intc_desc_dma8);
 418         register_intc_controller(&intc_desc_tmu34);
 419 }
 420 #endif
 421
 422 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 423 void __init plat_irq_setup(void)
 424 {
 425         register_intc_controller(&intc_desc);
 426         register_intc_controller(&intc_desc_dma4);
 427         register_intc_controller(&intc_desc_tmu34);
 428         register_intc_controller(&intc_desc_pci);
 429 }
 430 #endif
 431
 432 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 433 void __init plat_irq_setup(void)
 434 {
 435         register_intc_controller(&intc_desc);
 436         register_intc_controller(&intc_desc_dma8);
 437         register_intc_controller(&intc_desc_tmu34);
 438         register_intc_controller(&intc_desc_pci);
 439 }
 440 #endif
 441
 442 #define INTC_ICR        0xffd00000UL
 443 #define INTC_ICR_IRLM   (1<<7)
 444
 445 void __init plat_irq_setup_pins(int mode)
 446 {
 447 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 448         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 449         return;
 450 #endif
 451
 452         switch (mode) {
 453         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 454                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 455                 register_intc_controller(&intc_desc_irlm);
 456                 break;
 457         default:
 458                 BUG();
 459         }
 460 }