arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/acpi.h>
  16 #include <linux/sfi_acpi.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/dmi.h>
  19 #include <linux/slab.h>
  20 #include <linux/mutex.h>
  21 #include <linux/rculist.h>
  22 #include <asm/e820.h>
  23 #include <asm/pci_x86.h>
  24 #include <asm/acpi.h>
  25
  26 #define PREFIX "PCI: "
  27
  28 /* Indicate if the mmcfg resources have been placed into the resource table. */
  29 static bool pci_mmcfg_running_state;
  30 static bool pci_mmcfg_arch_init_failed;
  31 static DEFINE_MUTEX(pci_mmcfg_lock);
  32
  33 LIST_HEAD(pci_mmcfg_list);
  34
  35 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
  36 {
  37         if (cfg->res.parent)
  38                 release_resource(&cfg->res);
  39         list_del(&cfg->list);
  40         kfree(cfg);
  41 }
  42
  43 static __init void free_all_mmcfg(void)
  44 {
  45         struct pci_mmcfg_region *cfg, *tmp;
  46
  47         pci_mmcfg_arch_free();
  48         list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
  49                 pci_mmconfig_remove(cfg);
  50 }
  51
  52 static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
  53 {
  54         struct pci_mmcfg_region *cfg;
  55
  56         /* keep list sorted by segment and starting bus number */
  57         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
  58                 if (cfg->segment > new->segment ||
  59                     (cfg->segment == new->segment &&
  60                      cfg->start_bus >= new->start_bus)) {
  61                         list_add_tail_rcu(&new->list, &cfg->list);
  62                         return;
  63                 }
  64         }
  65         list_add_tail_rcu(&new->list, &pci_mmcfg_list);
  66 }
  67
  68 static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
  69                                                              int start,
  70                                                              int end, u64 addr)
  71 {
  72         struct pci_mmcfg_region *new;
  73         struct resource *res;
  74
  75         if (addr == 0)
  76                 return NULL;
  77
  78         new = kzalloc(sizeof(*new), GFP_KERNEL);
  79         if (!new)
  80                 return NULL;
  81
  82         new->address = addr;
  83         new->segment = segment;
  84         new->start_bus = start;
  85         new->end_bus = end;
  86
  87         res = &new->res;
  88         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
  89         res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
  90         res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  91         snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
  92                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
  93         res->name = new->name;
  94
  95         return new;
  96 }
  97
  98 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
  99                                                         int end, u64 addr)
 100 {
 101         struct pci_mmcfg_region *new;
 102
 103         new = pci_mmconfig_alloc(segment, start, end, addr);
 104         if (new) {
 105                 mutex_lock(&pci_mmcfg_lock);
 106                 list_add_sorted(new);
 107                 mutex_unlock(&pci_mmcfg_lock);
 108
 109                 pr_info(PREFIX
 110                        "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
 111                        "(base %#lx)\n",
 112                        segment, start, end, &new->res, (unsigned long)addr);
 113         }
 114
 115         return new;
 116 }
 117
 118 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 119 {
 120         struct pci_mmcfg_region *cfg;
 121
 122         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 123                 if (cfg->segment == segment &&
 124                     cfg->start_bus <= bus && bus <= cfg->end_bus)
 125                         return cfg;
 126
 127         return NULL;
 128 }
 129
 130 static const char __init *pci_mmcfg_e7520(void)
 131 {
 132         u32 win;
 133         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
 134
 135         win = win & 0xf000;
 136         if (win == 0x0000 || win == 0xf000)
 137                 return NULL;
 138
 139         if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
 140                 return NULL;
 141
 142         return "Intel Corporation E7520 Memory Controller Hub";
 143 }
 144
 145 static const char __init *pci_mmcfg_intel_945(void)
 146 {
 147         u32 pciexbar, mask = 0, len = 0;
 148
 149         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 150
 151         /* Enable bit */
 152         if (!(pciexbar & 1))
 153                 return NULL;
 154
 155         /* Size bits */
 156         switch ((pciexbar >> 1) & 3) {
 157         case 0:
 158                 mask = 0xf0000000U;
 159                 len  = 0x10000000U;
 160                 break;
 161         case 1:
 162                 mask = 0xf8000000U;
 163                 len  = 0x08000000U;
 164                 break;
 165         case 2:
 166                 mask = 0xfc000000U;
 167                 len  = 0x04000000U;
 168                 break;
 169         default:
 170                 return NULL;
 171         }
 172
 173         /* Errata #2, things break when not aligned on a 256Mb boundary */
 174         /* Can only happen in 64M/128M mode */
 175
 176         if ((pciexbar & mask) & 0x0fffffffU)
 177                 return NULL;
 178
 179         /* Don't hit the APIC registers and their friends */
 180         if ((pciexbar & mask) >= 0xf0000000U)
 181                 return NULL;
 182
 183         if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 184                 return NULL;
 185
 186         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 187 }
 188
 189 static const char __init *pci_mmcfg_amd_fam10h(void)
 190 {
 191         u32 low, high, address;
 192         u64 base, msr;
 193         int i;
 194         unsigned segnbits = 0, busnbits, end_bus;
 195
 196         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 197                 return NULL;
 198
 199         address = MSR_FAM10H_MMIO_CONF_BASE;
 200         if (rdmsr_safe(address, &low, &high))
 201                 return NULL;
 202
 203         msr = high;
 204         msr <<= 32;
 205         msr |= low;
 206
 207         /* mmconfig is not enable */
 208         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 209                 return NULL;
 210
 211         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 212
 213         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 214                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 215
 216         /*
 217          * only handle bus 0 ?
 218          * need to skip it
 219          */
 220         if (!busnbits)
 221                 return NULL;
 222
 223         if (busnbits > 8) {
 224                 segnbits = busnbits - 8;
 225                 busnbits = 8;
 226         }
 227
 228         end_bus = (1 << busnbits) - 1;
 229         for (i = 0; i < (1 << segnbits); i++)
 230                 if (pci_mmconfig_add(i, 0, end_bus,
 231                                      base + (1<<28) * i) == NULL) {
 232                         free_all_mmcfg();
 233                         return NULL;
 234                 }
 235
 236         return "AMD Family 10h NB";
 237 }
 238
 239 static bool __initdata mcp55_checked;
 240 static const char __init *pci_mmcfg_nvidia_mcp55(void)
 241 {
 242         int bus;
 243         int mcp55_mmconf_found = 0;
 244
 245         static const u32 extcfg_regnum          = 0x90;
 246         static const u32 extcfg_regsize         = 4;
 247         static const u32 extcfg_enable_mask     = 1<<31;
 248         static const u32 extcfg_start_mask      = 0xff<<16;
 249         static const int extcfg_start_shift     = 16;
 250         static const u32 extcfg_size_mask       = 0x3<<28;
 251         static const int extcfg_size_shift      = 28;
 252         static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
 253         static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
 254         static const int extcfg_base_lshift     = 25;
 255
 256         /*
 257          * do check if amd fam10h already took over
 258          */
 259         if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
 260                 return NULL;
 261
 262         mcp55_checked = true;
 263         for (bus = 0; bus < 256; bus++) {
 264                 u64 base;
 265                 u32 l, extcfg;
 266                 u16 vendor, device;
 267                 int start, size_index, end;
 268
 269                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 270                 vendor = l & 0xffff;
 271                 device = (l >> 16) & 0xffff;
 272
 273                 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 274                         continue;
 275
 276                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 277                                   extcfg_regsize, &extcfg);
 278
 279                 if (!(extcfg & extcfg_enable_mask))
 280                         continue;
 281
 282                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 283                 base = extcfg & extcfg_base_mask[size_index];
 284                 /* base could > 4G */
 285                 base <<= extcfg_base_lshift;
 286                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 287                 end = start + extcfg_sizebus[size_index] - 1;
 288                 if (pci_mmconfig_add(0, start, end, base) == NULL)
 289                         continue;
 290                 mcp55_mmconf_found++;
 291         }
 292
 293         if (!mcp55_mmconf_found)
 294                 return NULL;
 295
 296         return "nVidia MCP55";
 297 }
 298
 299 struct pci_mmcfg_hostbridge_probe {
 300         u32 bus;
 301         u32 devfn;
 302         u32 vendor;
 303         u32 device;
 304         const char *(*probe)(void);
 305 };
 306
 307 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 308         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 309           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 310         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 311           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 312         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 313           0x1200, pci_mmcfg_amd_fam10h },
 314         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 315           0x1200, pci_mmcfg_amd_fam10h },
 316         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 317           0x0369, pci_mmcfg_nvidia_mcp55 },
 318 };
 319
 320 static void __init pci_mmcfg_check_end_bus_number(void)
 321 {
 322         struct pci_mmcfg_region *cfg, *cfgx;
 323
 324         /* Fixup overlaps */
 325         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 326                 if (cfg->end_bus < cfg->start_bus)
 327                         cfg->end_bus = 255;
 328
 329                 /* Don't access the list head ! */
 330                 if (cfg->list.next == &pci_mmcfg_list)
 331                         break;
 332
 333                 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
 334                 if (cfg->end_bus >= cfgx->start_bus)
 335                         cfg->end_bus = cfgx->start_bus - 1;
 336         }
 337 }
 338
 339 static int __init pci_mmcfg_check_hostbridge(void)
 340 {
 341         u32 l;
 342         u32 bus, devfn;
 343         u16 vendor, device;
 344         int i;
 345         const char *name;
 346
 347         if (!raw_pci_ops)
 348                 return 0;
 349
 350         free_all_mmcfg();
 351
 352         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 353                 bus =  pci_mmcfg_probes[i].bus;
 354                 devfn = pci_mmcfg_probes[i].devfn;
 355                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 356                 vendor = l & 0xffff;
 357                 device = (l >> 16) & 0xffff;
 358
 359                 name = NULL;
 360                 if (pci_mmcfg_probes[i].vendor == vendor &&
 361                     pci_mmcfg_probes[i].device == device)
 362                         name = pci_mmcfg_probes[i].probe();
 363
 364                 if (name)
 365                         pr_info(PREFIX "%s with MMCONFIG support\n", name);
 366         }
 367
 368         /* some end_bus_number is crazy, fix it */
 369         pci_mmcfg_check_end_bus_number();
 370
 371         return !list_empty(&pci_mmcfg_list);
 372 }
 373
 374 static acpi_status __devinit check_mcfg_resource(struct acpi_resource *res,
 375                                                  void *data)
 376 {
 377         struct resource *mcfg_res = data;
 378         struct acpi_resource_address64 address;
 379         acpi_status status;
 380
 381         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 382                 struct acpi_resource_fixed_memory32 *fixmem32 =
 383                         &res->data.fixed_memory32;
 384                 if (!fixmem32)
 385                         return AE_OK;
 386                 if ((mcfg_res->start >= fixmem32->address) &&
 387                     (mcfg_res->end < (fixmem32->address +
 388                                       fixmem32->address_length))) {
 389                         mcfg_res->flags = 1;
 390                         return AE_CTRL_TERMINATE;
 391                 }
 392         }
 393         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 394             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 395                 return AE_OK;
 396
 397         status = acpi_resource_to_address64(res, &address);
 398         if (ACPI_FAILURE(status) ||
 399            (address.address_length <= 0) ||
 400            (address.resource_type != ACPI_MEMORY_RANGE))
 401                 return AE_OK;
 402
 403         if ((mcfg_res->start >= address.minimum) &&
 404             (mcfg_res->end < (address.minimum + address.address_length))) {
 405                 mcfg_res->flags = 1;
 406                 return AE_CTRL_TERMINATE;
 407         }
 408         return AE_OK;
 409 }
 410
 411 static acpi_status __devinit find_mboard_resource(acpi_handle handle, u32 lvl,
 412                                                   void *context, void **rv)
 413 {
 414         struct resource *mcfg_res = context;
 415
 416         acpi_walk_resources(handle, METHOD_NAME__CRS,
 417                             check_mcfg_resource, context);
 418
 419         if (mcfg_res->flags)
 420                 return AE_CTRL_TERMINATE;
 421
 422         return AE_OK;
 423 }
 424
 425 static int __devinit is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 426 {
 427         struct resource mcfg_res;
 428
 429         mcfg_res.start = start;
 430         mcfg_res.end = end - 1;
 431         mcfg_res.flags = 0;
 432
 433         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 434
 435         if (!mcfg_res.flags)
 436                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 437                                  NULL);
 438
 439         return mcfg_res.flags;
 440 }
 441
 442 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 443
 444 static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
 445                                     struct pci_mmcfg_region *cfg,
 446                                     struct device *dev, int with_e820)
 447 {
 448         u64 addr = cfg->res.start;
 449         u64 size = resource_size(&cfg->res);
 450         u64 old_size = size;
 451         int num_buses;
 452         char *method = with_e820 ? "E820" : "ACPI motherboard resources";
 453
 454         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
 455                 size >>= 1;
 456                 if (size < (16UL<<20))
 457                         break;
 458         }
 459
 460         if (size < (16UL<<20) && size != old_size)
 461                 return 0;
 462
 463         if (dev)
 464                 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
 465                          &cfg->res, method);
 466         else
 467                 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
 468                        &cfg->res, method);
 469
 470         if (old_size != size) {
 471                 /* update end_bus */
 472                 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
 473                 num_buses = cfg->end_bus - cfg->start_bus + 1;
 474                 cfg->res.end = cfg->res.start +
 475                     PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
 476                 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
 477                          "PCI MMCONFIG %04x [bus %02x-%02x]",
 478                          cfg->segment, cfg->start_bus, cfg->end_bus);
 479
 480                 if (dev)
 481                         dev_info(dev,
 482                                 "MMCONFIG "
 483                                 "at %pR (base %#lx) (size reduced!)\n",
 484                                 &cfg->res, (unsigned long) cfg->address);
 485                 else
 486                         pr_info(PREFIX
 487                                 "MMCONFIG for %04x [bus%02x-%02x] "
 488                                 "at %pR (base %#lx) (size reduced!)\n",
 489                                 cfg->segment, cfg->start_bus, cfg->end_bus,
 490                                 &cfg->res, (unsigned long) cfg->address);
 491         }
 492
 493         return 1;
 494 }
 495
 496 static int __ref pci_mmcfg_check_reserved(struct device *dev,
 497                   struct pci_mmcfg_region *cfg, int early)
 498 {
 499         if (!early && !acpi_disabled) {
 500                 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
 501                         return 1;
 502
 503                 if (dev)
 504                         dev_info(dev, FW_INFO
 505                                  "MMCONFIG at %pR not reserved in "
 506                                  "ACPI motherboard resources\n",
 507                                  &cfg->res);
 508                 else
 509                         pr_info(FW_INFO PREFIX
 510                                "MMCONFIG at %pR not reserved in "
 511                                "ACPI motherboard resources\n",
 512                                &cfg->res);
 513         }
 514
 515         /*
 516          * e820_all_mapped() is marked as __init.
 517          * All entries from ACPI MCFG table have been checked at boot time.
 518          * For MCFG information constructed from hotpluggable host bridge's
 519          * _CBA method, just assume it's reserved.
 520          */
 521         if (pci_mmcfg_running_state)
 522                 return 1;
 523
 524         /* Don't try to do this check unless configuration
 525            type 1 is available. how about type 2 ?*/
 526         if (raw_pci_ops)
 527                 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
 528
 529         return 0;
 530 }
 531
 532 static void __init pci_mmcfg_reject_broken(int early)
 533 {
 534         struct pci_mmcfg_region *cfg;
 535
 536         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 537                 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
 538                         pr_info(PREFIX "not using MMCONFIG\n");
 539                         free_all_mmcfg();
 540                         return;
 541                 }
 542         }
 543 }
 544
 545 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 546                                         struct acpi_mcfg_allocation *cfg)
 547 {
 548         int year;
 549
 550         if (cfg->address < 0xFFFFFFFF)
 551                 return 0;
 552
 553         if (!strcmp(mcfg->header.oem_id, "SGI") ||
 554                         !strcmp(mcfg->header.oem_id, "SGI2"))
 555                 return 0;
 556
 557         if (mcfg->header.revision >= 1) {
 558                 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 559                     year >= 2010)
 560                         return 0;
 561         }
 562
 563         pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
 564                "is above 4GB, ignored\n", cfg->pci_segment,
 565                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 566         return -EINVAL;
 567 }
 568
 569 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 570 {
 571         struct acpi_table_mcfg *mcfg;
 572         struct acpi_mcfg_allocation *cfg_table, *cfg;
 573         unsigned long i;
 574         int entries;
 575
 576         if (!header)
 577                 return -EINVAL;
 578
 579         mcfg = (struct acpi_table_mcfg *)header;
 580
 581         /* how many config structures do we have */
 582         free_all_mmcfg();
 583         entries = 0;
 584         i = header->length - sizeof(struct acpi_table_mcfg);
 585         while (i >= sizeof(struct acpi_mcfg_allocation)) {
 586                 entries++;
 587                 i -= sizeof(struct acpi_mcfg_allocation);
 588         };
 589         if (entries == 0) {
 590                 pr_err(PREFIX "MMCONFIG has no entries\n");
 591                 return -ENODEV;
 592         }
 593
 594         cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 595         for (i = 0; i < entries; i++) {
 596                 cfg = &cfg_table[i];
 597                 if (acpi_mcfg_check_entry(mcfg, cfg)) {
 598                         free_all_mmcfg();
 599                         return -ENODEV;
 600                 }
 601
 602                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 603                                    cfg->end_bus_number, cfg->address) == NULL) {
 604                         pr_warn(PREFIX "no memory for MCFG entries\n");
 605                         free_all_mmcfg();
 606                         return -ENOMEM;
 607                 }
 608         }
 609
 610         return 0;
 611 }
 612
 613 static void __init __pci_mmcfg_init(int early)
 614 {
 615         pci_mmcfg_reject_broken(early);
 616         if (list_empty(&pci_mmcfg_list))
 617                 return;
 618
 619         if (pcibios_last_bus < 0) {
 620                 const struct pci_mmcfg_region *cfg;
 621
 622                 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
 623                         if (cfg->segment)
 624                                 break;
 625                         pcibios_last_bus = cfg->end_bus;
 626                 }
 627         }
 628
 629         if (pci_mmcfg_arch_init())
 630                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 631         else {
 632                 free_all_mmcfg();
 633                 pci_mmcfg_arch_init_failed = true;
 634         }
 635 }
 636
 637 static int __initdata known_bridge;
 638
 639 void __init pci_mmcfg_early_init(void)
 640 {
 641         if (pci_probe & PCI_PROBE_MMCONF) {
 642                 if (pci_mmcfg_check_hostbridge())
 643                         known_bridge = 1;
 644                 else
 645                         acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 646                 __pci_mmcfg_init(1);
 647         }
 648 }
 649
 650 void __init pci_mmcfg_late_init(void)
 651 {
 652         /* MMCONFIG disabled */
 653         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 654                 return;
 655
 656         if (known_bridge)
 657                 return;
 658
 659         /* MMCONFIG hasn't been enabled yet, try again */
 660         if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
 661                 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 662                 __pci_mmcfg_init(0);
 663         }
 664 }
 665
 666 static int __init pci_mmcfg_late_insert_resources(void)
 667 {
 668         struct pci_mmcfg_region *cfg;
 669
 670         pci_mmcfg_running_state = true;
 671
 672         /* If we are not using MMCONFIG, don't insert the resources. */
 673         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 674                 return 1;
 675
 676         /*
 677          * Attempt to insert the mmcfg resources but not with the busy flag
 678          * marked so it won't cause request errors when __request_region is
 679          * called.
 680          */
 681         list_for_each_entry(cfg, &pci_mmcfg_list, list)
 682                 if (!cfg->res.parent)
 683                         insert_resource(&iomem_resource, &cfg->res);
 684
 685         return 0;
 686 }
 687
 688 /*
 689  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 690  * misprogrammed MCFG tables that state larger sizes but actually conflict
 691  * with other system resources.
 692  */
 693 late_initcall(pci_mmcfg_late_insert_resources);
 694
 695 /* Add MMCFG information for host bridges */
 696 int __devinit pci_mmconfig_insert(struct device *dev,
 697                                   u16 seg, u8 start, u8 end,
 698                                   phys_addr_t addr)
 699 {
 700         int rc;
 701         struct resource *tmp = NULL;
 702         struct pci_mmcfg_region *cfg;
 703
 704         if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
 705                 return -ENODEV;
 706
 707         if (start > end)
 708                 return -EINVAL;
 709
 710         mutex_lock(&pci_mmcfg_lock);
 711         cfg = pci_mmconfig_lookup(seg, start);
 712         if (cfg) {
 713                 if (cfg->end_bus < end)
 714                         dev_info(dev, FW_INFO
 715                                  "MMCONFIG for "
 716                                  "domain %04x [bus %02x-%02x] "
 717                                  "only partially covers this bridge\n",
 718                                   cfg->segment, cfg->start_bus, cfg->end_bus);
 719                 mutex_unlock(&pci_mmcfg_lock);
 720                 return -EEXIST;
 721         }
 722
 723         if (!addr) {
 724                 mutex_unlock(&pci_mmcfg_lock);
 725                 return -EINVAL;
 726         }
 727
 728         rc = -EBUSY;
 729         cfg = pci_mmconfig_alloc(seg, start, end, addr);
 730         if (cfg == NULL) {
 731                 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
 732                 rc = -ENOMEM;
 733         } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
 734                 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
 735                          &cfg->res);
 736         } else {
 737                 /* Insert resource if it's not in boot stage */
 738                 if (pci_mmcfg_running_state)
 739                         tmp = insert_resource_conflict(&iomem_resource,
 740                                                        &cfg->res);
 741
 742                 if (tmp) {
 743                         dev_warn(dev,
 744                                  "MMCONFIG %pR conflicts with "
 745                                  "%s %pR\n",
 746                                  &cfg->res, tmp->name, tmp);
 747                 } else if (pci_mmcfg_arch_map(cfg)) {
 748                         dev_warn(dev, "fail to map MMCONFIG %pR.\n",
 749                                  &cfg->res);
 750                 } else {
 751                         list_add_sorted(cfg);
 752                         dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
 753                                  &cfg->res, (unsigned long)addr);
 754                         cfg = NULL;
 755                         rc = 0;
 756                 }
 757         }
 758
 759         if (cfg) {
 760                 if (cfg->res.parent)
 761                         release_resource(&cfg->res);
 762                 kfree(cfg);
 763         }
 764
 765         mutex_unlock(&pci_mmcfg_lock);
 766
 767         return rc;
 768 }
 769
 770 /* Delete MMCFG information for host bridges */
 771 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
 772 {
 773         struct pci_mmcfg_region *cfg;
 774
 775         mutex_lock(&pci_mmcfg_lock);
 776         list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
 777                 if (cfg->segment == seg && cfg->start_bus == start &&
 778                     cfg->end_bus == end) {
 779                         list_del_rcu(&cfg->list);
 780                         synchronize_rcu();
 781                         pci_mmcfg_arch_unmap(cfg);
 782                         if (cfg->res.parent)
 783                                 release_resource(&cfg->res);
 784                         mutex_unlock(&pci_mmcfg_lock);
 785                         kfree(cfg);
 786                         return 0;
 787                 }
 788         mutex_unlock(&pci_mmcfg_lock);
 789
 790         return -ENOENT;
 791 }