drivers/gpu/drm/gma500/cdv_device.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #include <linux/backlight.h>
  21 #include <drm/drmP.h>
  22 #include <drm/drm.h>
  23 #include "gma_drm.h"
  24 #include "psb_drv.h"
  25 #include "psb_reg.h"
  26 #include "psb_intel_reg.h"
  27 #include "intel_bios.h"
  28 #include "cdv_device.h"
  29
  30 #define VGA_SR_INDEX            0x3c4
  31 #define VGA_SR_DATA             0x3c5
  32
  33 static void cdv_disable_vga(struct drm_device *dev)
  34 {
  35         u8 sr1;
  36         u32 vga_reg;
  37
  38         vga_reg = VGACNTRL;
  39
  40         outb(1, VGA_SR_INDEX);
  41         sr1 = inb(VGA_SR_DATA);
  42         outb(sr1 | 1<<5, VGA_SR_DATA);
  43         udelay(300);
  44
  45         REG_WRITE(vga_reg, VGA_DISP_DISABLE);
  46         REG_READ(vga_reg);
  47 }
  48
  49 static int cdv_output_init(struct drm_device *dev)
  50 {
  51         struct drm_psb_private *dev_priv = dev->dev_private;
  52
  53         drm_mode_create_scaling_mode_property(dev);
  54
  55         cdv_disable_vga(dev);
  56
  57         cdv_intel_crt_init(dev, &dev_priv->mode_dev);
  58         cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
  59
  60         /* These bits indicate HDMI not SDVO on CDV */
  61         if (REG_READ(SDVOB) & SDVO_DETECTED)
  62                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
  63         if (REG_READ(SDVOC) & SDVO_DETECTED)
  64                 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
  65         return 0;
  66 }
  67
  68 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  69
  70 /*
  71  *      Cedartrail Backlght Interfaces
  72  */
  73
  74 static struct backlight_device *cdv_backlight_device;
  75
  76 static int cdv_backlight_combination_mode(struct drm_device *dev)
  77 {
  78         return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
  79 }
  80
  81 static u32 cdv_get_max_backlight(struct drm_device *dev)
  82 {
  83         u32 max = REG_READ(BLC_PWM_CTL);
  84
  85         if (max == 0) {
  86                 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
  87                 /* i915 does this, I believe which means that we should not
  88                  * smash PWM control as firmware will take control of it. */
  89                 return 1;
  90         }
  91
  92         max >>= 16;
  93         if (cdv_backlight_combination_mode(dev))
  94                 max *= 0xff;
  95         return max;
  96 }
  97
  98 static int cdv_get_brightness(struct backlight_device *bd)
  99 {
 100         struct drm_device *dev = bl_get_data(bd);
 101         u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 102
 103         if (cdv_backlight_combination_mode(dev)) {
 104                 u8 lbpc;
 105
 106                 val &= ~1;
 107                 pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
 108                 val *= lbpc;
 109         }
 110         return (val * 100)/cdv_get_max_backlight(dev);
 111
 112 }
 113
 114 static int cdv_set_brightness(struct backlight_device *bd)
 115 {
 116         struct drm_device *dev = bl_get_data(bd);
 117         int level = bd->props.brightness;
 118         u32 blc_pwm_ctl;
 119
 120         /* Percentage 1-100% being valid */
 121         if (level < 1)
 122                 level = 1;
 123
 124         level *= cdv_get_max_backlight(dev);
 125         level /= 100;
 126
 127         if (cdv_backlight_combination_mode(dev)) {
 128                 u32 max = cdv_get_max_backlight(dev);
 129                 u8 lbpc;
 130
 131                 lbpc = level * 0xfe / max + 1;
 132                 level /= lbpc;
 133
 134                 pci_write_config_byte(dev->pdev, 0xF4, lbpc);
 135         }
 136
 137         blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 138         REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
 139                                 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
 140         return 0;
 141 }
 142
 143 static const struct backlight_ops cdv_ops = {
 144         .get_brightness = cdv_get_brightness,
 145         .update_status  = cdv_set_brightness,
 146 };
 147
 148 static int cdv_backlight_init(struct drm_device *dev)
 149 {
 150         struct drm_psb_private *dev_priv = dev->dev_private;
 151         struct backlight_properties props;
 152
 153         memset(&props, 0, sizeof(struct backlight_properties));
 154         props.max_brightness = 100;
 155         props.type = BACKLIGHT_PLATFORM;
 156
 157         cdv_backlight_device = backlight_device_register("psb-bl",
 158                                         NULL, (void *)dev, &cdv_ops, &props);
 159         if (IS_ERR(cdv_backlight_device))
 160                 return PTR_ERR(cdv_backlight_device);
 161
 162         cdv_backlight_device->props.brightness =
 163                         cdv_get_brightness(cdv_backlight_device);
 164         backlight_update_status(cdv_backlight_device);
 165         dev_priv->backlight_device = cdv_backlight_device;
 166         return 0;
 167 }
 168
 169 #endif
 170
 171 /*
 172  *      Provide the Cedarview specific chip logic and low level methods
 173  *      for power management
 174  *
 175  *      FIXME: we need to implement the apm/ospm base management bits
 176  *      for this and the MID devices.
 177  */
 178
 179 static inline u32 CDV_MSG_READ32(uint port, uint offset)
 180 {
 181         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 182         uint32_t ret_val = 0;
 183         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 184         pci_write_config_dword(pci_root, 0xD0, mcr);
 185         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 186         pci_dev_put(pci_root);
 187         return ret_val;
 188 }
 189
 190 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
 191 {
 192         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 193         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 194         pci_write_config_dword(pci_root, 0xD4, value);
 195         pci_write_config_dword(pci_root, 0xD0, mcr);
 196         pci_dev_put(pci_root);
 197 }
 198
 199 #define PSB_PM_SSC                      0x20
 200 #define PSB_PM_SSS                      0x30
 201 #define PSB_PWRGT_GFX_ON                0x02
 202 #define PSB_PWRGT_GFX_OFF               0x01
 203 #define PSB_PWRGT_GFX_D0                0x00
 204 #define PSB_PWRGT_GFX_D3                0x03
 205
 206 static void cdv_init_pm(struct drm_device *dev)
 207 {
 208         struct drm_psb_private *dev_priv = dev->dev_private;
 209         u32 pwr_cnt;
 210         int i;
 211
 212         dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 213                                                         PSB_APMBA) & 0xFFFF;
 214         dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
 215                                                         PSB_OSPMBA) & 0xFFFF;
 216
 217         /* Power status */
 218         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 219
 220         /* Enable the GPU */
 221         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 222         pwr_cnt |= PSB_PWRGT_GFX_ON;
 223         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 224
 225         /* Wait for the GPU power */
 226         for (i = 0; i < 5; i++) {
 227                 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 228                 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
 229                         return;
 230                 udelay(10);
 231         }
 232         dev_err(dev->dev, "GPU: power management timed out.\n");
 233 }
 234
 235 static void cdv_errata(struct drm_device *dev)
 236 {
 237         /* Disable bonus launch.
 238          *      CPU and GPU competes for memory and display misses updates and
 239          *      flickers. Worst with dual core, dual displays.
 240          *
 241          *      Fixes were done to Win 7 gfx driver to disable a feature called
 242          *      Bonus Launch to work around the issue, by degrading
 243          *      performance.
 244          */
 245          CDV_MSG_WRITE32(3, 0x30, 0x08027108);
 246 }
 247
 248 /**
 249  *      cdv_save_display_registers      -       save registers lost on suspend
 250  *      @dev: our DRM device
 251  *
 252  *      Save the state we need in order to be able to restore the interface
 253  *      upon resume from suspend
 254  */
 255 static int cdv_save_display_registers(struct drm_device *dev)
 256 {
 257         struct drm_psb_private *dev_priv = dev->dev_private;
 258         struct psb_save_area *regs = &dev_priv->regs;
 259         struct drm_connector *connector;
 260
 261         dev_dbg(dev->dev, "Saving GPU registers.\n");
 262
 263         pci_read_config_byte(dev->pdev, 0xF4, &regs->cdv.saveLBB);
 264
 265         regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
 266         regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
 267
 268         regs->cdv.saveDSPARB = REG_READ(DSPARB);
 269         regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
 270         regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
 271         regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
 272         regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
 273         regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
 274         regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
 275
 276         regs->cdv.saveADPA = REG_READ(ADPA);
 277
 278         regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
 279         regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
 280         regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
 281         regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
 282         regs->cdv.saveLVDS = REG_READ(LVDS);
 283
 284         regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
 285
 286         regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
 287         regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
 288         regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
 289
 290         regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
 291
 292         regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
 293         regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
 294
 295         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 296                 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
 297
 298         return 0;
 299 }
 300
 301 /**
 302  *      cdv_restore_display_registers   -       restore lost register state
 303  *      @dev: our DRM device
 304  *
 305  *      Restore register state that was lost during suspend and resume.
 306  *
 307  *      FIXME: review
 308  */
 309 static int cdv_restore_display_registers(struct drm_device *dev)
 310 {
 311         struct drm_psb_private *dev_priv = dev->dev_private;
 312         struct psb_save_area *regs = &dev_priv->regs;
 313         struct drm_connector *connector;
 314         u32 temp;
 315
 316         pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
 317
 318         REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
 319         REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
 320
 321         /* BIOS does below anyway */
 322         REG_WRITE(DPIO_CFG, 0);
 323         REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
 324
 325         temp = REG_READ(DPLL_A);
 326         if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
 327                 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
 328                 REG_READ(DPLL_A);
 329         }
 330
 331         temp = REG_READ(DPLL_B);
 332         if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
 333                 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
 334                 REG_READ(DPLL_B);
 335         }
 336
 337         udelay(500);
 338
 339         REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
 340         REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
 341         REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
 342         REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
 343         REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
 344         REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
 345
 346         REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
 347         REG_WRITE(ADPA, regs->cdv.saveADPA);
 348
 349         REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
 350         REG_WRITE(LVDS, regs->cdv.saveLVDS);
 351         REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
 352         REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
 353         REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
 354         REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
 355         REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
 356         REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
 357         REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
 358
 359         REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
 360
 361         REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
 362         REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
 363
 364         /* Fix arbitration bug */
 365         cdv_errata(dev);
 366
 367         drm_mode_config_reset(dev);
 368
 369         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 370                 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
 371
 372         /* Resume the modeset for every activated CRTC */
 373         drm_helper_resume_force_mode(dev);
 374         return 0;
 375 }
 376
 377 static int cdv_power_down(struct drm_device *dev)
 378 {
 379         struct drm_psb_private *dev_priv = dev->dev_private;
 380         u32 pwr_cnt, pwr_mask, pwr_sts;
 381         int tries = 5;
 382
 383         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 384         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 385         pwr_cnt |= PSB_PWRGT_GFX_OFF;
 386         pwr_mask = PSB_PWRGT_GFX_MASK;
 387
 388         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 389
 390         while (tries--) {
 391                 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 392                 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
 393                         return 0;
 394                 udelay(10);
 395         }
 396         return 0;
 397 }
 398
 399 static int cdv_power_up(struct drm_device *dev)
 400 {
 401         struct drm_psb_private *dev_priv = dev->dev_private;
 402         u32 pwr_cnt, pwr_mask, pwr_sts;
 403         int tries = 5;
 404
 405         pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
 406         pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
 407         pwr_cnt |= PSB_PWRGT_GFX_ON;
 408         pwr_mask = PSB_PWRGT_GFX_MASK;
 409
 410         outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
 411
 412         while (tries--) {
 413                 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
 414                 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
 415                         return 0;
 416                 udelay(10);
 417         }
 418         return 0;
 419 }
 420
 421 /* FIXME ? - shared with Poulsbo */
 422 static void cdv_get_core_freq(struct drm_device *dev)
 423 {
 424         uint32_t clock;
 425         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 426         struct drm_psb_private *dev_priv = dev->dev_private;
 427
 428         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 429         pci_read_config_dword(pci_root, 0xD4, &clock);
 430         pci_dev_put(pci_root);
 431
 432         switch (clock & 0x07) {
 433         case 0:
 434                 dev_priv->core_freq = 100;
 435                 break;
 436         case 1:
 437                 dev_priv->core_freq = 133;
 438                 break;
 439         case 2:
 440                 dev_priv->core_freq = 150;
 441                 break;
 442         case 3:
 443                 dev_priv->core_freq = 178;
 444                 break;
 445         case 4:
 446                 dev_priv->core_freq = 200;
 447                 break;
 448         case 5:
 449         case 6:
 450         case 7:
 451                 dev_priv->core_freq = 266;
 452         default:
 453                 dev_priv->core_freq = 0;
 454         }
 455 }
 456
 457 static void cdv_hotplug_work_func(struct work_struct *work)
 458 {
 459         struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
 460                                                         hotplug_work);
 461         struct drm_device *dev = dev_priv->dev;
 462
 463         /* Just fire off a uevent and let userspace tell us what to do */
 464         drm_helper_hpd_irq_event(dev);
 465 }
 466
 467 /* The core driver has received a hotplug IRQ. We are in IRQ context
 468    so extract the needed information and kick off queued processing */
 469
 470 static int cdv_hotplug_event(struct drm_device *dev)
 471 {
 472         struct drm_psb_private *dev_priv = dev->dev_private;
 473         schedule_work(&dev_priv->hotplug_work);
 474         REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 475         return 1;
 476 }
 477
 478 static void cdv_hotplug_enable(struct drm_device *dev, bool on)
 479 {
 480         if (on) {
 481                 u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
 482                 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
 483                            HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
 484                 REG_WRITE(PORT_HOTPLUG_EN, hotplug);
 485         }  else {
 486                 REG_WRITE(PORT_HOTPLUG_EN, 0);
 487                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 488         }
 489 }
 490
 491 /* Cedarview */
 492 static const struct psb_offset cdv_regmap[2] = {
 493         {
 494                 .fp0 = FPA0,
 495                 .fp1 = FPA1,
 496                 .cntr = DSPACNTR,
 497                 .conf = PIPEACONF,
 498                 .src = PIPEASRC,
 499                 .dpll = DPLL_A,
 500                 .dpll_md = DPLL_A_MD,
 501                 .htotal = HTOTAL_A,
 502                 .hblank = HBLANK_A,
 503                 .hsync = HSYNC_A,
 504                 .vtotal = VTOTAL_A,
 505                 .vblank = VBLANK_A,
 506                 .vsync = VSYNC_A,
 507                 .stride = DSPASTRIDE,
 508                 .size = DSPASIZE,
 509                 .pos = DSPAPOS,
 510                 .base = DSPABASE,
 511                 .surf = DSPASURF,
 512                 .addr = DSPABASE,
 513                 .status = PIPEASTAT,
 514                 .linoff = DSPALINOFF,
 515                 .tileoff = DSPATILEOFF,
 516                 .palette = PALETTE_A,
 517         },
 518         {
 519                 .fp0 = FPB0,
 520                 .fp1 = FPB1,
 521                 .cntr = DSPBCNTR,
 522                 .conf = PIPEBCONF,
 523                 .src = PIPEBSRC,
 524                 .dpll = DPLL_B,
 525                 .dpll_md = DPLL_B_MD,
 526                 .htotal = HTOTAL_B,
 527                 .hblank = HBLANK_B,
 528                 .hsync = HSYNC_B,
 529                 .vtotal = VTOTAL_B,
 530                 .vblank = VBLANK_B,
 531                 .vsync = VSYNC_B,
 532                 .stride = DSPBSTRIDE,
 533                 .size = DSPBSIZE,
 534                 .pos = DSPBPOS,
 535                 .base = DSPBBASE,
 536                 .surf = DSPBSURF,
 537                 .addr = DSPBBASE,
 538                 .status = PIPEBSTAT,
 539                 .linoff = DSPBLINOFF,
 540                 .tileoff = DSPBTILEOFF,
 541                 .palette = PALETTE_B,
 542         }
 543 };
 544
 545 static int cdv_chip_setup(struct drm_device *dev)
 546 {
 547         struct drm_psb_private *dev_priv = dev->dev_private;
 548         INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
 549
 550         if (pci_enable_msi(dev->pdev))
 551                 dev_warn(dev->dev, "Enabling MSI failed!\n");
 552         dev_priv->regmap = cdv_regmap;
 553         cdv_get_core_freq(dev);
 554         psb_intel_opregion_init(dev);
 555         psb_intel_init_bios(dev);
 556         cdv_hotplug_enable(dev, false);
 557         return 0;
 558 }
 559
 560 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
 561
 562 const struct psb_ops cdv_chip_ops = {
 563         .name = "GMA3600/3650",
 564         .accel_2d = 0,
 565         .pipes = 2,
 566         .crtcs = 2,
 567         .hdmi_mask = (1 << 0) | (1 << 1),
 568         .lvds_mask = (1 << 1),
 569         .cursor_needs_phys = 0,
 570         .sgx_offset = MRST_SGX_OFFSET,
 571         .chip_setup = cdv_chip_setup,
 572         .errata = cdv_errata,
 573
 574         .crtc_helper = &cdv_intel_helper_funcs,
 575         .crtc_funcs = &cdv_intel_crtc_funcs,
 576
 577         .output_init = cdv_output_init,
 578         .hotplug = cdv_hotplug_event,
 579         .hotplug_enable = cdv_hotplug_enable,
 580
 581 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 582         .backlight_init = cdv_backlight_init,
 583 #endif
 584
 585         .init_pm = cdv_init_pm,
 586         .save_regs = cdv_save_display_registers,
 587         .restore_regs = cdv_restore_display_registers,
 588         .power_down = cdv_power_down,
 589         .power_up = cdv_power_up,
 590 };