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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / i915 / i915_dma.c
blob0969a7cbbba3bbca750a122ef30c515983dbbda4
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc_helper.h"
34 #include "drm_fb_helper.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include <linux/pci.h>
40 #include <linux/vgaarb.h>
41 #include <linux/acpi.h>
42 #include <linux/pnp.h>
43 #include <linux/vga_switcheroo.h>
44 #include <linux/slab.h>
45 #include <acpi/video.h>
46 #include <asm/pat.h>
47
48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
49
50 #define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
52
53 #define OUT_RING(x) \
54 intel_ring_emit(LP_RING(dev_priv), x)
55
56 #define ADVANCE_LP_RING() \
57 intel_ring_advance(LP_RING(dev_priv))
58
59 /**
60 * Lock test for when it's just for synchronization of ring access.
61 *
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
64 */
65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
68 } while (0)
69
70 static inline u32
71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
72 {
73 if (I915_NEED_GFX_HWS(dev_priv->dev))
74 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
75 else
76 return intel_read_status_page(LP_RING(dev_priv), reg);
77 }
78
79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81 #define I915_BREADCRUMB_INDEX 0x21
82
83 void i915_update_dri1_breadcrumb(struct drm_device *dev)
84 {
85 drm_i915_private_t *dev_priv = dev->dev_private;
86 struct drm_i915_master_private *master_priv;
87
88 if (dev->primary->master) {
89 master_priv = dev->primary->master->driver_priv;
90 if (master_priv->sarea_priv)
91 master_priv->sarea_priv->last_dispatch =
92 READ_BREADCRUMB(dev_priv);
93 }
94 }
95
96 static void i915_write_hws_pga(struct drm_device *dev)
97 {
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 u32 addr;
100
101 addr = dev_priv->status_page_dmah->busaddr;
102 if (INTEL_INFO(dev)->gen >= 4)
103 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
104 I915_WRITE(HWS_PGA, addr);
105 }
106
107 /**
108 * Sets up the hardware status page for devices that need a physical address
109 * in the register.
110 */
111 static int i915_init_phys_hws(struct drm_device *dev)
112 {
113 drm_i915_private_t *dev_priv = dev->dev_private;
114
115 /* Program Hardware Status Page */
116 dev_priv->status_page_dmah =
117 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
118
119 if (!dev_priv->status_page_dmah) {
120 DRM_ERROR("Can not allocate hardware status page\n");
121 return -ENOMEM;
122 }
123
124 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
125 0, PAGE_SIZE);
126
127 i915_write_hws_pga(dev);
128
129 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
130 return 0;
131 }
132
133 /**
134 * Frees the hardware status page, whether it's a physical address or a virtual
135 * address set up by the X Server.
136 */
137 static void i915_free_hws(struct drm_device *dev)
138 {
139 drm_i915_private_t *dev_priv = dev->dev_private;
140 struct intel_ring_buffer *ring = LP_RING(dev_priv);
141
142 if (dev_priv->status_page_dmah) {
143 drm_pci_free(dev, dev_priv->status_page_dmah);
144 dev_priv->status_page_dmah = NULL;
145 }
146
147 if (ring->status_page.gfx_addr) {
148 ring->status_page.gfx_addr = 0;
149 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
150 }
151
152 /* Need to rewrite hardware status page */
153 I915_WRITE(HWS_PGA, 0x1ffff000);
154 }
155
156 void i915_kernel_lost_context(struct drm_device * dev)
157 {
158 drm_i915_private_t *dev_priv = dev->dev_private;
159 struct drm_i915_master_private *master_priv;
160 struct intel_ring_buffer *ring = LP_RING(dev_priv);
161
162 /*
163 * We should never lose context on the ring with modesetting
164 * as we don't expose it to userspace
165 */
166 if (drm_core_check_feature(dev, DRIVER_MODESET))
167 return;
168
169 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
170 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
171 ring->space = ring->head - (ring->tail + 8);
172 if (ring->space < 0)
173 ring->space += ring->size;
174
175 if (!dev->primary->master)
176 return;
177
178 master_priv = dev->primary->master->driver_priv;
179 if (ring->head == ring->tail && master_priv->sarea_priv)
180 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
181 }
182
183 static int i915_dma_cleanup(struct drm_device * dev)
184 {
185 drm_i915_private_t *dev_priv = dev->dev_private;
186 int i;
187
188 /* Make sure interrupts are disabled here because the uninstall ioctl
189 * may not have been called from userspace and after dev_private
190 * is freed, it's too late.
191 */
192 if (dev->irq_enabled)
193 drm_irq_uninstall(dev);
194
195 mutex_lock(&dev->struct_mutex);
196 for (i = 0; i < I915_NUM_RINGS; i++)
197 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
198 mutex_unlock(&dev->struct_mutex);
199
200 /* Clear the HWS virtual address at teardown */
201 if (I915_NEED_GFX_HWS(dev))
202 i915_free_hws(dev);
203
204 return 0;
205 }
206
207 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
208 {
209 drm_i915_private_t *dev_priv = dev->dev_private;
210 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
211 int ret;
212
213 master_priv->sarea = drm_getsarea(dev);
214 if (master_priv->sarea) {
215 master_priv->sarea_priv = (drm_i915_sarea_t *)
216 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
217 } else {
218 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
219 }
220
221 if (init->ring_size != 0) {
222 if (LP_RING(dev_priv)->obj != NULL) {
223 i915_dma_cleanup(dev);
224 DRM_ERROR("Client tried to initialize ringbuffer in "
225 "GEM mode\n");
226 return -EINVAL;
227 }
228
229 ret = intel_render_ring_init_dri(dev,
230 init->ring_start,
231 init->ring_size);
232 if (ret) {
233 i915_dma_cleanup(dev);
234 return ret;
235 }
236 }
237
238 dev_priv->cpp = init->cpp;
239 dev_priv->back_offset = init->back_offset;
240 dev_priv->front_offset = init->front_offset;
241 dev_priv->current_page = 0;
242 if (master_priv->sarea_priv)
243 master_priv->sarea_priv->pf_current_page = 0;
244
245 /* Allow hardware batchbuffers unless told otherwise.
246 */
247 dev_priv->dri1.allow_batchbuffer = 1;
248
249 return 0;
250 }
251
252 static int i915_dma_resume(struct drm_device * dev)
253 {
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
255 struct intel_ring_buffer *ring = LP_RING(dev_priv);
256
257 DRM_DEBUG_DRIVER("%s\n", __func__);
258
259 if (ring->virtual_start == NULL) {
260 DRM_ERROR("can not ioremap virtual address for"
261 " ring buffer\n");
262 return -ENOMEM;
263 }
264
265 /* Program Hardware Status Page */
266 if (!ring->status_page.page_addr) {
267 DRM_ERROR("Can not find hardware status page\n");
268 return -EINVAL;
269 }
270 DRM_DEBUG_DRIVER("hw status page @ %p\n",
271 ring->status_page.page_addr);
272 if (ring->status_page.gfx_addr != 0)
273 intel_ring_setup_status_page(ring);
274 else
275 i915_write_hws_pga(dev);
276
277 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
278
279 return 0;
280 }
281
282 static int i915_dma_init(struct drm_device *dev, void *data,
283 struct drm_file *file_priv)
284 {
285 drm_i915_init_t *init = data;
286 int retcode = 0;
287
288 if (drm_core_check_feature(dev, DRIVER_MODESET))
289 return -ENODEV;
290
291 switch (init->func) {
292 case I915_INIT_DMA:
293 retcode = i915_initialize(dev, init);
294 break;
295 case I915_CLEANUP_DMA:
296 retcode = i915_dma_cleanup(dev);
297 break;
298 case I915_RESUME_DMA:
299 retcode = i915_dma_resume(dev);
300 break;
301 default:
302 retcode = -EINVAL;
303 break;
304 }
305
306 return retcode;
307 }
308
309 /* Implement basically the same security restrictions as hardware does
310 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
311 *
312 * Most of the calculations below involve calculating the size of a
313 * particular instruction. It's important to get the size right as
314 * that tells us where the next instruction to check is. Any illegal
315 * instruction detected will be given a size of zero, which is a
316 * signal to abort the rest of the buffer.
317 */
318 static int validate_cmd(int cmd)
319 {
320 switch (((cmd >> 29) & 0x7)) {
321 case 0x0:
322 switch ((cmd >> 23) & 0x3f) {
323 case 0x0:
324 return 1; /* MI_NOOP */
325 case 0x4:
326 return 1; /* MI_FLUSH */
327 default:
328 return 0; /* disallow everything else */
329 }
330 break;
331 case 0x1:
332 return 0; /* reserved */
333 case 0x2:
334 return (cmd & 0xff) + 2; /* 2d commands */
335 case 0x3:
336 if (((cmd >> 24) & 0x1f) <= 0x18)
337 return 1;
338
339 switch ((cmd >> 24) & 0x1f) {
340 case 0x1c:
341 return 1;
342 case 0x1d:
343 switch ((cmd >> 16) & 0xff) {
344 case 0x3:
345 return (cmd & 0x1f) + 2;
346 case 0x4:
347 return (cmd & 0xf) + 2;
348 default:
349 return (cmd & 0xffff) + 2;
350 }
351 case 0x1e:
352 if (cmd & (1 << 23))
353 return (cmd & 0xffff) + 1;
354 else
355 return 1;
356 case 0x1f:
357 if ((cmd & (1 << 23)) == 0) /* inline vertices */
358 return (cmd & 0x1ffff) + 2;
359 else if (cmd & (1 << 17)) /* indirect random */
360 if ((cmd & 0xffff) == 0)
361 return 0; /* unknown length, too hard */
362 else
363 return (((cmd & 0xffff) + 1) / 2) + 1;
364 else
365 return 2; /* indirect sequential */
366 default:
367 return 0;
368 }
369 default:
370 return 0;
371 }
372
373 return 0;
374 }
375
376 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
377 {
378 drm_i915_private_t *dev_priv = dev->dev_private;
379 int i, ret;
380
381 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
382 return -EINVAL;
383
384 for (i = 0; i < dwords;) {
385 int sz = validate_cmd(buffer[i]);
386 if (sz == 0 || i + sz > dwords)
387 return -EINVAL;
388 i += sz;
389 }
390
391 ret = BEGIN_LP_RING((dwords+1)&~1);
392 if (ret)
393 return ret;
394
395 for (i = 0; i < dwords; i++)
396 OUT_RING(buffer[i]);
397 if (dwords & 1)
398 OUT_RING(0);
399
400 ADVANCE_LP_RING();
401
402 return 0;
403 }
404
405 int
406 i915_emit_box(struct drm_device *dev,
407 struct drm_clip_rect *box,
408 int DR1, int DR4)
409 {
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 int ret;
412
413 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
414 box->y2 <= 0 || box->x2 <= 0) {
415 DRM_ERROR("Bad box %d,%d..%d,%d\n",
416 box->x1, box->y1, box->x2, box->y2);
417 return -EINVAL;
418 }
419
420 if (INTEL_INFO(dev)->gen >= 4) {
421 ret = BEGIN_LP_RING(4);
422 if (ret)
423 return ret;
424
425 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
426 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
427 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
428 OUT_RING(DR4);
429 } else {
430 ret = BEGIN_LP_RING(6);
431 if (ret)
432 return ret;
433
434 OUT_RING(GFX_OP_DRAWRECT_INFO);
435 OUT_RING(DR1);
436 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
437 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
438 OUT_RING(DR4);
439 OUT_RING(0);
440 }
441 ADVANCE_LP_RING();
442
443 return 0;
444 }
445
446 /* XXX: Emitting the counter should really be moved to part of the IRQ
447 * emit. For now, do it in both places:
448 */
449
450 static void i915_emit_breadcrumb(struct drm_device *dev)
451 {
452 drm_i915_private_t *dev_priv = dev->dev_private;
453 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
454
455 dev_priv->counter++;
456 if (dev_priv->counter > 0x7FFFFFFFUL)
457 dev_priv->counter = 0;
458 if (master_priv->sarea_priv)
459 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
460
461 if (BEGIN_LP_RING(4) == 0) {
462 OUT_RING(MI_STORE_DWORD_INDEX);
463 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
464 OUT_RING(dev_priv->counter);
465 OUT_RING(0);
466 ADVANCE_LP_RING();
467 }
468 }
469
470 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
471 drm_i915_cmdbuffer_t *cmd,
472 struct drm_clip_rect *cliprects,
473 void *cmdbuf)
474 {
475 int nbox = cmd->num_cliprects;
476 int i = 0, count, ret;
477
478 if (cmd->sz & 0x3) {
479 DRM_ERROR("alignment");
480 return -EINVAL;
481 }
482
483 i915_kernel_lost_context(dev);
484
485 count = nbox ? nbox : 1;
486
487 for (i = 0; i < count; i++) {
488 if (i < nbox) {
489 ret = i915_emit_box(dev, &cliprects[i],
490 cmd->DR1, cmd->DR4);
491 if (ret)
492 return ret;
493 }
494
495 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
496 if (ret)
497 return ret;
498 }
499
500 i915_emit_breadcrumb(dev);
501 return 0;
502 }
503
504 static int i915_dispatch_batchbuffer(struct drm_device * dev,
505 drm_i915_batchbuffer_t * batch,
506 struct drm_clip_rect *cliprects)
507 {
508 struct drm_i915_private *dev_priv = dev->dev_private;
509 int nbox = batch->num_cliprects;
510 int i, count, ret;
511
512 if ((batch->start | batch->used) & 0x7) {
513 DRM_ERROR("alignment");
514 return -EINVAL;
515 }
516
517 i915_kernel_lost_context(dev);
518
519 count = nbox ? nbox : 1;
520 for (i = 0; i < count; i++) {
521 if (i < nbox) {
522 ret = i915_emit_box(dev, &cliprects[i],
523 batch->DR1, batch->DR4);
524 if (ret)
525 return ret;
526 }
527
528 if (!IS_I830(dev) && !IS_845G(dev)) {
529 ret = BEGIN_LP_RING(2);
530 if (ret)
531 return ret;
532
533 if (INTEL_INFO(dev)->gen >= 4) {
534 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
535 OUT_RING(batch->start);
536 } else {
537 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
538 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
539 }
540 } else {
541 ret = BEGIN_LP_RING(4);
542 if (ret)
543 return ret;
544
545 OUT_RING(MI_BATCH_BUFFER);
546 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
547 OUT_RING(batch->start + batch->used - 4);
548 OUT_RING(0);
549 }
550 ADVANCE_LP_RING();
551 }
552
553
554 if (IS_G4X(dev) || IS_GEN5(dev)) {
555 if (BEGIN_LP_RING(2) == 0) {
556 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
557 OUT_RING(MI_NOOP);
558 ADVANCE_LP_RING();
559 }
560 }
561
562 i915_emit_breadcrumb(dev);
563 return 0;
564 }
565
566 static int i915_dispatch_flip(struct drm_device * dev)
567 {
568 drm_i915_private_t *dev_priv = dev->dev_private;
569 struct drm_i915_master_private *master_priv =
570 dev->primary->master->driver_priv;
571 int ret;
572
573 if (!master_priv->sarea_priv)
574 return -EINVAL;
575
576 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
577 __func__,
578 dev_priv->current_page,
579 master_priv->sarea_priv->pf_current_page);
580
581 i915_kernel_lost_context(dev);
582
583 ret = BEGIN_LP_RING(10);
584 if (ret)
585 return ret;
586
587 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
588 OUT_RING(0);
589
590 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
591 OUT_RING(0);
592 if (dev_priv->current_page == 0) {
593 OUT_RING(dev_priv->back_offset);
594 dev_priv->current_page = 1;
595 } else {
596 OUT_RING(dev_priv->front_offset);
597 dev_priv->current_page = 0;
598 }
599 OUT_RING(0);
600
601 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
602 OUT_RING(0);
603
604 ADVANCE_LP_RING();
605
606 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
607
608 if (BEGIN_LP_RING(4) == 0) {
609 OUT_RING(MI_STORE_DWORD_INDEX);
610 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
611 OUT_RING(dev_priv->counter);
612 OUT_RING(0);
613 ADVANCE_LP_RING();
614 }
615
616 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
617 return 0;
618 }
619
620 static int i915_quiescent(struct drm_device *dev)
621 {
622 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
623
624 i915_kernel_lost_context(dev);
625 return intel_wait_ring_idle(ring);
626 }
627
628 static int i915_flush_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *file_priv)
630 {
631 int ret;
632
633 if (drm_core_check_feature(dev, DRIVER_MODESET))
634 return -ENODEV;
635
636 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
637
638 mutex_lock(&dev->struct_mutex);
639 ret = i915_quiescent(dev);
640 mutex_unlock(&dev->struct_mutex);
641
642 return ret;
643 }
644
645 static int i915_batchbuffer(struct drm_device *dev, void *data,
646 struct drm_file *file_priv)
647 {
648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
649 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
650 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
651 master_priv->sarea_priv;
652 drm_i915_batchbuffer_t *batch = data;
653 int ret;
654 struct drm_clip_rect *cliprects = NULL;
655
656 if (drm_core_check_feature(dev, DRIVER_MODESET))
657 return -ENODEV;
658
659 if (!dev_priv->dri1.allow_batchbuffer) {
660 DRM_ERROR("Batchbuffer ioctl disabled\n");
661 return -EINVAL;
662 }
663
664 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
665 batch->start, batch->used, batch->num_cliprects);
666
667 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
668
669 if (batch->num_cliprects < 0)
670 return -EINVAL;
671
672 if (batch->num_cliprects) {
673 cliprects = kcalloc(batch->num_cliprects,
674 sizeof(struct drm_clip_rect),
675 GFP_KERNEL);
676 if (cliprects == NULL)
677 return -ENOMEM;
678
679 ret = copy_from_user(cliprects, batch->cliprects,
680 batch->num_cliprects *
681 sizeof(struct drm_clip_rect));
682 if (ret != 0) {
683 ret = -EFAULT;
684 goto fail_free;
685 }
686 }
687
688 mutex_lock(&dev->struct_mutex);
689 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
690 mutex_unlock(&dev->struct_mutex);
691
692 if (sarea_priv)
693 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
694
695 fail_free:
696 kfree(cliprects);
697
698 return ret;
699 }
700
701 static int i915_cmdbuffer(struct drm_device *dev, void *data,
702 struct drm_file *file_priv)
703 {
704 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
705 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
706 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
707 master_priv->sarea_priv;
708 drm_i915_cmdbuffer_t *cmdbuf = data;
709 struct drm_clip_rect *cliprects = NULL;
710 void *batch_data;
711 int ret;
712
713 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
714 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
715
716 if (drm_core_check_feature(dev, DRIVER_MODESET))
717 return -ENODEV;
718
719 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
720
721 if (cmdbuf->num_cliprects < 0)
722 return -EINVAL;
723
724 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
725 if (batch_data == NULL)
726 return -ENOMEM;
727
728 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
729 if (ret != 0) {
730 ret = -EFAULT;
731 goto fail_batch_free;
732 }
733
734 if (cmdbuf->num_cliprects) {
735 cliprects = kcalloc(cmdbuf->num_cliprects,
736 sizeof(struct drm_clip_rect), GFP_KERNEL);
737 if (cliprects == NULL) {
738 ret = -ENOMEM;
739 goto fail_batch_free;
740 }
741
742 ret = copy_from_user(cliprects, cmdbuf->cliprects,
743 cmdbuf->num_cliprects *
744 sizeof(struct drm_clip_rect));
745 if (ret != 0) {
746 ret = -EFAULT;
747 goto fail_clip_free;
748 }
749 }
750
751 mutex_lock(&dev->struct_mutex);
752 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
753 mutex_unlock(&dev->struct_mutex);
754 if (ret) {
755 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
756 goto fail_clip_free;
757 }
758
759 if (sarea_priv)
760 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
761
762 fail_clip_free:
763 kfree(cliprects);
764 fail_batch_free:
765 kfree(batch_data);
766
767 return ret;
768 }
769
770 static int i915_emit_irq(struct drm_device * dev)
771 {
772 drm_i915_private_t *dev_priv = dev->dev_private;
773 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
774
775 i915_kernel_lost_context(dev);
776
777 DRM_DEBUG_DRIVER("\n");
778
779 dev_priv->counter++;
780 if (dev_priv->counter > 0x7FFFFFFFUL)
781 dev_priv->counter = 1;
782 if (master_priv->sarea_priv)
783 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
784
785 if (BEGIN_LP_RING(4) == 0) {
786 OUT_RING(MI_STORE_DWORD_INDEX);
787 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
788 OUT_RING(dev_priv->counter);
789 OUT_RING(MI_USER_INTERRUPT);
790 ADVANCE_LP_RING();
791 }
792
793 return dev_priv->counter;
794 }
795
796 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
797 {
798 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
799 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
800 int ret = 0;
801 struct intel_ring_buffer *ring = LP_RING(dev_priv);
802
803 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
804 READ_BREADCRUMB(dev_priv));
805
806 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
807 if (master_priv->sarea_priv)
808 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
809 return 0;
810 }
811
812 if (master_priv->sarea_priv)
813 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
814
815 if (ring->irq_get(ring)) {
816 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
817 READ_BREADCRUMB(dev_priv) >= irq_nr);
818 ring->irq_put(ring);
819 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
820 ret = -EBUSY;
821
822 if (ret == -EBUSY) {
823 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
824 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
825 }
826
827 return ret;
828 }
829
830 /* Needs the lock as it touches the ring.
831 */
832 static int i915_irq_emit(struct drm_device *dev, void *data,
833 struct drm_file *file_priv)
834 {
835 drm_i915_private_t *dev_priv = dev->dev_private;
836 drm_i915_irq_emit_t *emit = data;
837 int result;
838
839 if (drm_core_check_feature(dev, DRIVER_MODESET))
840 return -ENODEV;
841
842 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
843 DRM_ERROR("called with no initialization\n");
844 return -EINVAL;
845 }
846
847 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
848
849 mutex_lock(&dev->struct_mutex);
850 result = i915_emit_irq(dev);
851 mutex_unlock(&dev->struct_mutex);
852
853 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
854 DRM_ERROR("copy_to_user\n");
855 return -EFAULT;
856 }
857
858 return 0;
859 }
860
861 /* Doesn't need the hardware lock.
862 */
863 static int i915_irq_wait(struct drm_device *dev, void *data,
864 struct drm_file *file_priv)
865 {
866 drm_i915_private_t *dev_priv = dev->dev_private;
867 drm_i915_irq_wait_t *irqwait = data;
868
869 if (drm_core_check_feature(dev, DRIVER_MODESET))
870 return -ENODEV;
871
872 if (!dev_priv) {
873 DRM_ERROR("called with no initialization\n");
874 return -EINVAL;
875 }
876
877 return i915_wait_irq(dev, irqwait->irq_seq);
878 }
879
880 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
882 {
883 drm_i915_private_t *dev_priv = dev->dev_private;
884 drm_i915_vblank_pipe_t *pipe = data;
885
886 if (drm_core_check_feature(dev, DRIVER_MODESET))
887 return -ENODEV;
888
889 if (!dev_priv) {
890 DRM_ERROR("called with no initialization\n");
891 return -EINVAL;
892 }
893
894 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
895
896 return 0;
897 }
898
899 /**
900 * Schedule buffer swap at given vertical blank.
901 */
902 static int i915_vblank_swap(struct drm_device *dev, void *data,
903 struct drm_file *file_priv)
904 {
905 /* The delayed swap mechanism was fundamentally racy, and has been
906 * removed. The model was that the client requested a delayed flip/swap
907 * from the kernel, then waited for vblank before continuing to perform
908 * rendering. The problem was that the kernel might wake the client
909 * up before it dispatched the vblank swap (since the lock has to be
910 * held while touching the ringbuffer), in which case the client would
911 * clear and start the next frame before the swap occurred, and
912 * flicker would occur in addition to likely missing the vblank.
913 *
914 * In the absence of this ioctl, userland falls back to a correct path
915 * of waiting for a vblank, then dispatching the swap on its own.
916 * Context switching to userland and back is plenty fast enough for
917 * meeting the requirements of vblank swapping.
918 */
919 return -EINVAL;
920 }
921
922 static int i915_flip_bufs(struct drm_device *dev, void *data,
923 struct drm_file *file_priv)
924 {
925 int ret;
926
927 if (drm_core_check_feature(dev, DRIVER_MODESET))
928 return -ENODEV;
929
930 DRM_DEBUG_DRIVER("%s\n", __func__);
931
932 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
933
934 mutex_lock(&dev->struct_mutex);
935 ret = i915_dispatch_flip(dev);
936 mutex_unlock(&dev->struct_mutex);
937
938 return ret;
939 }
940
941 static int i915_getparam(struct drm_device *dev, void *data,
942 struct drm_file *file_priv)
943 {
944 drm_i915_private_t *dev_priv = dev->dev_private;
945 drm_i915_getparam_t *param = data;
946 int value;
947
948 if (!dev_priv) {
949 DRM_ERROR("called with no initialization\n");
950 return -EINVAL;
951 }
952
953 switch (param->param) {
954 case I915_PARAM_IRQ_ACTIVE:
955 value = dev->pdev->irq ? 1 : 0;
956 break;
957 case I915_PARAM_ALLOW_BATCHBUFFER:
958 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
959 break;
960 case I915_PARAM_LAST_DISPATCH:
961 value = READ_BREADCRUMB(dev_priv);
962 break;
963 case I915_PARAM_CHIPSET_ID:
964 value = dev->pci_device;
965 break;
966 case I915_PARAM_HAS_GEM:
967 value = 1;
968 break;
969 case I915_PARAM_NUM_FENCES_AVAIL:
970 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
971 break;
972 case I915_PARAM_HAS_OVERLAY:
973 value = dev_priv->overlay ? 1 : 0;
974 break;
975 case I915_PARAM_HAS_PAGEFLIPPING:
976 value = 1;
977 break;
978 case I915_PARAM_HAS_EXECBUF2:
979 /* depends on GEM */
980 value = 1;
981 break;
982 case I915_PARAM_HAS_BSD:
983 value = intel_ring_initialized(&dev_priv->ring[VCS]);
984 break;
985 case I915_PARAM_HAS_BLT:
986 value = intel_ring_initialized(&dev_priv->ring[BCS]);
987 break;
988 case I915_PARAM_HAS_RELAXED_FENCING:
989 value = 1;
990 break;
991 case I915_PARAM_HAS_COHERENT_RINGS:
992 value = 1;
993 break;
994 case I915_PARAM_HAS_EXEC_CONSTANTS:
995 value = INTEL_INFO(dev)->gen >= 4;
996 break;
997 case I915_PARAM_HAS_RELAXED_DELTA:
998 value = 1;
999 break;
1000 case I915_PARAM_HAS_GEN7_SOL_RESET:
1001 value = 1;
1002 break;
1003 case I915_PARAM_HAS_LLC:
1004 value = HAS_LLC(dev);
1005 break;
1006 case I915_PARAM_HAS_ALIASING_PPGTT:
1007 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1008 break;
1009 case I915_PARAM_HAS_WAIT_TIMEOUT:
1010 value = 1;
1011 break;
1012 default:
1013 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1014 param->param);
1015 return -EINVAL;
1016 }
1017
1018 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1019 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1020 return -EFAULT;
1021 }
1022
1023 return 0;
1024 }
1025
1026 static int i915_setparam(struct drm_device *dev, void *data,
1027 struct drm_file *file_priv)
1028 {
1029 drm_i915_private_t *dev_priv = dev->dev_private;
1030 drm_i915_setparam_t *param = data;
1031
1032 if (!dev_priv) {
1033 DRM_ERROR("called with no initialization\n");
1034 return -EINVAL;
1035 }
1036
1037 switch (param->param) {
1038 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1039 break;
1040 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1041 break;
1042 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1043 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1044 break;
1045 case I915_SETPARAM_NUM_USED_FENCES:
1046 if (param->value > dev_priv->num_fence_regs ||
1047 param->value < 0)
1048 return -EINVAL;
1049 /* Userspace can use first N regs */
1050 dev_priv->fence_reg_start = param->value;
1051 break;
1052 default:
1053 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1054 param->param);
1055 return -EINVAL;
1056 }
1057
1058 return 0;
1059 }
1060
1061 static int i915_set_status_page(struct drm_device *dev, void *data,
1062 struct drm_file *file_priv)
1063 {
1064 drm_i915_private_t *dev_priv = dev->dev_private;
1065 drm_i915_hws_addr_t *hws = data;
1066 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1067
1068 if (drm_core_check_feature(dev, DRIVER_MODESET))
1069 return -ENODEV;
1070
1071 if (!I915_NEED_GFX_HWS(dev))
1072 return -EINVAL;
1073
1074 if (!dev_priv) {
1075 DRM_ERROR("called with no initialization\n");
1076 return -EINVAL;
1077 }
1078
1079 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1080 WARN(1, "tried to set status page when mode setting active\n");
1081 return 0;
1082 }
1083
1084 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1085
1086 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1087
1088 dev_priv->dri1.gfx_hws_cpu_addr =
1089 ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1090 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1091 i915_dma_cleanup(dev);
1092 ring->status_page.gfx_addr = 0;
1093 DRM_ERROR("can not ioremap virtual address for"
1094 " G33 hw status page\n");
1095 return -ENOMEM;
1096 }
1097
1098 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1099 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1100
1101 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1102 ring->status_page.gfx_addr);
1103 DRM_DEBUG_DRIVER("load hws at %p\n",
1104 ring->status_page.page_addr);
1105 return 0;
1106 }
1107
1108 static int i915_get_bridge_dev(struct drm_device *dev)
1109 {
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111
1112 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1113 if (!dev_priv->bridge_dev) {
1114 DRM_ERROR("bridge device not found\n");
1115 return -1;
1116 }
1117 return 0;
1118 }
1119
1120 #define MCHBAR_I915 0x44
1121 #define MCHBAR_I965 0x48
1122 #define MCHBAR_SIZE (4*4096)
1123
1124 #define DEVEN_REG 0x54
1125 #define DEVEN_MCHBAR_EN (1 << 28)
1126
1127 /* Allocate space for the MCH regs if needed, return nonzero on error */
1128 static int
1129 intel_alloc_mchbar_resource(struct drm_device *dev)
1130 {
1131 drm_i915_private_t *dev_priv = dev->dev_private;
1132 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1133 u32 temp_lo, temp_hi = 0;
1134 u64 mchbar_addr;
1135 int ret;
1136
1137 if (INTEL_INFO(dev)->gen >= 4)
1138 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1139 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1140 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1141
1142 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1143 #ifdef CONFIG_PNP
1144 if (mchbar_addr &&
1145 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1146 return 0;
1147 #endif
1148
1149 /* Get some space for it */
1150 dev_priv->mch_res.name = "i915 MCHBAR";
1151 dev_priv->mch_res.flags = IORESOURCE_MEM;
1152 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1153 &dev_priv->mch_res,
1154 MCHBAR_SIZE, MCHBAR_SIZE,
1155 PCIBIOS_MIN_MEM,
1156 0, pcibios_align_resource,
1157 dev_priv->bridge_dev);
1158 if (ret) {
1159 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1160 dev_priv->mch_res.start = 0;
1161 return ret;
1162 }
1163
1164 if (INTEL_INFO(dev)->gen >= 4)
1165 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1166 upper_32_bits(dev_priv->mch_res.start));
1167
1168 pci_write_config_dword(dev_priv->bridge_dev, reg,
1169 lower_32_bits(dev_priv->mch_res.start));
1170 return 0;
1171 }
1172
1173 /* Setup MCHBAR if possible, return true if we should disable it again */
1174 static void
1175 intel_setup_mchbar(struct drm_device *dev)
1176 {
1177 drm_i915_private_t *dev_priv = dev->dev_private;
1178 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1179 u32 temp;
1180 bool enabled;
1181
1182 dev_priv->mchbar_need_disable = false;
1183
1184 if (IS_I915G(dev) || IS_I915GM(dev)) {
1185 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1186 enabled = !!(temp & DEVEN_MCHBAR_EN);
1187 } else {
1188 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1189 enabled = temp & 1;
1190 }
1191
1192 /* If it's already enabled, don't have to do anything */
1193 if (enabled)
1194 return;
1195
1196 if (intel_alloc_mchbar_resource(dev))
1197 return;
1198
1199 dev_priv->mchbar_need_disable = true;
1200
1201 /* Space is allocated or reserved, so enable it. */
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1204 temp | DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1208 }
1209 }
1210
1211 static void
1212 intel_teardown_mchbar(struct drm_device *dev)
1213 {
1214 drm_i915_private_t *dev_priv = dev->dev_private;
1215 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1216 u32 temp;
1217
1218 if (dev_priv->mchbar_need_disable) {
1219 if (IS_I915G(dev) || IS_I915GM(dev)) {
1220 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1221 temp &= ~DEVEN_MCHBAR_EN;
1222 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1223 } else {
1224 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1225 temp &= ~1;
1226 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1227 }
1228 }
1229
1230 if (dev_priv->mch_res.start)
1231 release_resource(&dev_priv->mch_res);
1232 }
1233
1234 /* true = enable decode, false = disable decoder */
1235 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1236 {
1237 struct drm_device *dev = cookie;
1238
1239 intel_modeset_vga_set_state(dev, state);
1240 if (state)
1241 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1242 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1243 else
1244 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1245 }
1246
1247 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1248 {
1249 struct drm_device *dev = pci_get_drvdata(pdev);
1250 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1251 if (state == VGA_SWITCHEROO_ON) {
1252 pr_info("switched on\n");
1253 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1254 /* i915 resume handler doesn't set to D0 */
1255 pci_set_power_state(dev->pdev, PCI_D0);
1256 i915_resume(dev);
1257 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1258 } else {
1259 pr_err("switched off\n");
1260 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1261 i915_suspend(dev, pmm);
1262 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1263 }
1264 }
1265
1266 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1267 {
1268 struct drm_device *dev = pci_get_drvdata(pdev);
1269 bool can_switch;
1270
1271 spin_lock(&dev->count_lock);
1272 can_switch = (dev->open_count == 0);
1273 spin_unlock(&dev->count_lock);
1274 return can_switch;
1275 }
1276
1277 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1278 .set_gpu_state = i915_switcheroo_set_state,
1279 .reprobe = NULL,
1280 .can_switch = i915_switcheroo_can_switch,
1281 };
1282
1283 static int i915_load_modeset_init(struct drm_device *dev)
1284 {
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 int ret;
1287
1288 ret = intel_parse_bios(dev);
1289 if (ret)
1290 DRM_INFO("failed to find VBIOS tables\n");
1291
1292 /* If we have > 1 VGA cards, then we need to arbitrate access
1293 * to the common VGA resources.
1294 *
1295 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1296 * then we do not take part in VGA arbitration and the
1297 * vga_client_register() fails with -ENODEV.
1298 */
1299 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1300 if (ret && ret != -ENODEV)
1301 goto out;
1302
1303 intel_register_dsm_handler();
1304
1305 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1306 if (ret)
1307 goto cleanup_vga_client;
1308
1309 /* Initialise stolen first so that we may reserve preallocated
1310 * objects for the BIOS to KMS transition.
1311 */
1312 ret = i915_gem_init_stolen(dev);
1313 if (ret)
1314 goto cleanup_vga_switcheroo;
1315
1316 intel_modeset_init(dev);
1317
1318 ret = i915_gem_init(dev);
1319 if (ret)
1320 goto cleanup_gem_stolen;
1321
1322 intel_modeset_gem_init(dev);
1323
1324 ret = drm_irq_install(dev);
1325 if (ret)
1326 goto cleanup_gem;
1327
1328 /* Always safe in the mode setting case. */
1329 /* FIXME: do pre/post-mode set stuff in core KMS code */
1330 dev->vblank_disable_allowed = 1;
1331
1332 ret = intel_fbdev_init(dev);
1333 if (ret)
1334 goto cleanup_irq;
1335
1336 drm_kms_helper_poll_init(dev);
1337
1338 /* We're off and running w/KMS */
1339 dev_priv->mm.suspended = 0;
1340
1341 return 0;
1342
1343 cleanup_irq:
1344 drm_irq_uninstall(dev);
1345 cleanup_gem:
1346 mutex_lock(&dev->struct_mutex);
1347 i915_gem_cleanup_ringbuffer(dev);
1348 mutex_unlock(&dev->struct_mutex);
1349 i915_gem_cleanup_aliasing_ppgtt(dev);
1350 cleanup_gem_stolen:
1351 i915_gem_cleanup_stolen(dev);
1352 cleanup_vga_switcheroo:
1353 vga_switcheroo_unregister_client(dev->pdev);
1354 cleanup_vga_client:
1355 vga_client_register(dev->pdev, NULL, NULL, NULL);
1356 out:
1357 return ret;
1358 }
1359
1360 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1361 {
1362 struct drm_i915_master_private *master_priv;
1363
1364 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1365 if (!master_priv)
1366 return -ENOMEM;
1367
1368 master->driver_priv = master_priv;
1369 return 0;
1370 }
1371
1372 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1373 {
1374 struct drm_i915_master_private *master_priv = master->driver_priv;
1375
1376 if (!master_priv)
1377 return;
1378
1379 kfree(master_priv);
1380
1381 master->driver_priv = NULL;
1382 }
1383
1384 static void
1385 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1386 unsigned long size)
1387 {
1388 dev_priv->mm.gtt_mtrr = -1;
1389
1390 #if defined(CONFIG_X86_PAT)
1391 if (cpu_has_pat)
1392 return;
1393 #endif
1394
1395 /* Set up a WC MTRR for non-PAT systems. This is more common than
1396 * one would think, because the kernel disables PAT on first
1397 * generation Core chips because WC PAT gets overridden by a UC
1398 * MTRR if present. Even if a UC MTRR isn't present.
1399 */
1400 dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1401 if (dev_priv->mm.gtt_mtrr < 0) {
1402 DRM_INFO("MTRR allocation failed. Graphics "
1403 "performance may suffer.\n");
1404 }
1405 }
1406
1407 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1408 {
1409 struct apertures_struct *ap;
1410 struct pci_dev *pdev = dev_priv->dev->pdev;
1411 bool primary;
1412
1413 ap = alloc_apertures(1);
1414 if (!ap)
1415 return;
1416
1417 ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1418 ap->ranges[0].size =
1419 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1420 primary =
1421 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1422
1423 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1424
1425 kfree(ap);
1426 }
1427
1428 /**
1429 * i915_driver_load - setup chip and create an initial config
1430 * @dev: DRM device
1431 * @flags: startup flags
1432 *
1433 * The driver load routine has to do several things:
1434 * - drive output discovery via intel_modeset_init()
1435 * - initialize the memory manager
1436 * - allocate initial config memory
1437 * - setup the DRM framebuffer with the allocated memory
1438 */
1439 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1440 {
1441 struct drm_i915_private *dev_priv;
1442 struct intel_device_info *info;
1443 int ret = 0, mmio_bar;
1444 uint32_t aperture_size;
1445
1446 info = (struct intel_device_info *) flags;
1447
1448 /* Refuse to load on gen6+ without kms enabled. */
1449 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1450 return -ENODEV;
1451
1452
1453 /* i915 has 4 more counters */
1454 dev->counters += 4;
1455 dev->types[6] = _DRM_STAT_IRQ;
1456 dev->types[7] = _DRM_STAT_PRIMARY;
1457 dev->types[8] = _DRM_STAT_SECONDARY;
1458 dev->types[9] = _DRM_STAT_DMA;
1459
1460 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1461 if (dev_priv == NULL)
1462 return -ENOMEM;
1463
1464 dev->dev_private = (void *)dev_priv;
1465 dev_priv->dev = dev;
1466 dev_priv->info = info;
1467
1468 if (i915_get_bridge_dev(dev)) {
1469 ret = -EIO;
1470 goto free_priv;
1471 }
1472
1473 ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
1474 if (!ret) {
1475 DRM_ERROR("failed to set up gmch\n");
1476 ret = -EIO;
1477 goto put_bridge;
1478 }
1479
1480 dev_priv->mm.gtt = intel_gtt_get();
1481 if (!dev_priv->mm.gtt) {
1482 DRM_ERROR("Failed to initialize GTT\n");
1483 ret = -ENODEV;
1484 goto put_gmch;
1485 }
1486
1487 if (drm_core_check_feature(dev, DRIVER_MODESET))
1488 i915_kick_out_firmware_fb(dev_priv);
1489
1490 pci_set_master(dev->pdev);
1491
1492 /* overlay on gen2 is broken and can't address above 1G */
1493 if (IS_GEN2(dev))
1494 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1495
1496 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1497 * using 32bit addressing, overwriting memory if HWS is located
1498 * above 4GB.
1499 *
1500 * The documentation also mentions an issue with undefined
1501 * behaviour if any general state is accessed within a page above 4GB,
1502 * which also needs to be handled carefully.
1503 */
1504 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1505 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1506
1507 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1508 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1509 if (!dev_priv->regs) {
1510 DRM_ERROR("failed to map registers\n");
1511 ret = -EIO;
1512 goto put_gmch;
1513 }
1514
1515 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1516 dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1517
1518 dev_priv->mm.gtt_mapping =
1519 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1520 aperture_size);
1521 if (dev_priv->mm.gtt_mapping == NULL) {
1522 ret = -EIO;
1523 goto out_rmmap;
1524 }
1525
1526 i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1527 aperture_size);
1528
1529 /* The i915 workqueue is primarily used for batched retirement of
1530 * requests (and thus managing bo) once the task has been completed
1531 * by the GPU. i915_gem_retire_requests() is called directly when we
1532 * need high-priority retirement, such as waiting for an explicit
1533 * bo.
1534 *
1535 * It is also used for periodic low-priority events, such as
1536 * idle-timers and recording error state.
1537 *
1538 * All tasks on the workqueue are expected to acquire the dev mutex
1539 * so there is no point in running more than one instance of the
1540 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1541 */
1542 dev_priv->wq = alloc_workqueue("i915",
1543 WQ_UNBOUND | WQ_NON_REENTRANT,
1544 1);
1545 if (dev_priv->wq == NULL) {
1546 DRM_ERROR("Failed to create our workqueue.\n");
1547 ret = -ENOMEM;
1548 goto out_mtrrfree;
1549 }
1550
1551 /* This must be called before any calls to HAS_PCH_* */
1552 intel_detect_pch(dev);
1553
1554 intel_irq_init(dev);
1555 intel_gt_init(dev);
1556
1557 /* Try to make sure MCHBAR is enabled before poking at it */
1558 intel_setup_mchbar(dev);
1559 intel_setup_gmbus(dev);
1560 intel_opregion_setup(dev);
1561
1562 /* Make sure the bios did its job and set up vital registers */
1563 intel_setup_bios(dev);
1564
1565 i915_gem_load(dev);
1566
1567 /* Init HWS */
1568 if (!I915_NEED_GFX_HWS(dev)) {
1569 ret = i915_init_phys_hws(dev);
1570 if (ret)
1571 goto out_gem_unload;
1572 }
1573
1574 /* On the 945G/GM, the chipset reports the MSI capability on the
1575 * integrated graphics even though the support isn't actually there
1576 * according to the published specs. It doesn't appear to function
1577 * correctly in testing on 945G.
1578 * This may be a side effect of MSI having been made available for PEG
1579 * and the registers being closely associated.
1580 *
1581 * According to chipset errata, on the 965GM, MSI interrupts may
1582 * be lost or delayed, but we use them anyways to avoid
1583 * stuck interrupts on some machines.
1584 */
1585 if (!IS_I945G(dev) && !IS_I945GM(dev))
1586 pci_enable_msi(dev->pdev);
1587
1588 spin_lock_init(&dev_priv->irq_lock);
1589 spin_lock_init(&dev_priv->error_lock);
1590 spin_lock_init(&dev_priv->rps_lock);
1591 spin_lock_init(&dev_priv->dpio_lock);
1592
1593 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1594 dev_priv->num_pipe = 3;
1595 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1596 dev_priv->num_pipe = 2;
1597 else
1598 dev_priv->num_pipe = 1;
1599
1600 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1601 if (ret)
1602 goto out_gem_unload;
1603
1604 /* Start out suspended */
1605 dev_priv->mm.suspended = 1;
1606
1607 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1608 ret = i915_load_modeset_init(dev);
1609 if (ret < 0) {
1610 DRM_ERROR("failed to init modeset\n");
1611 goto out_gem_unload;
1612 }
1613 }
1614
1615 i915_setup_sysfs(dev);
1616
1617 /* Must be done after probing outputs */
1618 intel_opregion_init(dev);
1619 acpi_video_register();
1620
1621 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1622 (unsigned long) dev);
1623
1624 if (IS_GEN5(dev))
1625 intel_gpu_ips_init(dev_priv);
1626
1627 return 0;
1628
1629 out_gem_unload:
1630 if (dev_priv->mm.inactive_shrinker.shrink)
1631 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1632
1633 if (dev->pdev->msi_enabled)
1634 pci_disable_msi(dev->pdev);
1635
1636 intel_teardown_gmbus(dev);
1637 intel_teardown_mchbar(dev);
1638 destroy_workqueue(dev_priv->wq);
1639 out_mtrrfree:
1640 if (dev_priv->mm.gtt_mtrr >= 0) {
1641 mtrr_del(dev_priv->mm.gtt_mtrr,
1642 dev_priv->mm.gtt_base_addr,
1643 aperture_size);
1644 dev_priv->mm.gtt_mtrr = -1;
1645 }
1646 io_mapping_free(dev_priv->mm.gtt_mapping);
1647 out_rmmap:
1648 pci_iounmap(dev->pdev, dev_priv->regs);
1649 put_gmch:
1650 intel_gmch_remove();
1651 put_bridge:
1652 pci_dev_put(dev_priv->bridge_dev);
1653 free_priv:
1654 kfree(dev_priv);
1655 return ret;
1656 }
1657
1658 int i915_driver_unload(struct drm_device *dev)
1659 {
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int ret;
1662
1663 intel_gpu_ips_teardown();
1664
1665 i915_teardown_sysfs(dev);
1666
1667 if (dev_priv->mm.inactive_shrinker.shrink)
1668 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1669
1670 mutex_lock(&dev->struct_mutex);
1671 ret = i915_gpu_idle(dev);
1672 if (ret)
1673 DRM_ERROR("failed to idle hardware: %d\n", ret);
1674 i915_gem_retire_requests(dev);
1675 mutex_unlock(&dev->struct_mutex);
1676
1677 /* Cancel the retire work handler, which should be idle now. */
1678 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1679
1680 io_mapping_free(dev_priv->mm.gtt_mapping);
1681 if (dev_priv->mm.gtt_mtrr >= 0) {
1682 mtrr_del(dev_priv->mm.gtt_mtrr,
1683 dev_priv->mm.gtt_base_addr,
1684 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1685 dev_priv->mm.gtt_mtrr = -1;
1686 }
1687
1688 acpi_video_unregister();
1689
1690 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1691 intel_fbdev_fini(dev);
1692 intel_modeset_cleanup(dev);
1693
1694 /*
1695 * free the memory space allocated for the child device
1696 * config parsed from VBT
1697 */
1698 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1699 kfree(dev_priv->child_dev);
1700 dev_priv->child_dev = NULL;
1701 dev_priv->child_dev_num = 0;
1702 }
1703
1704 vga_switcheroo_unregister_client(dev->pdev);
1705 vga_client_register(dev->pdev, NULL, NULL, NULL);
1706 }
1707
1708 /* Free error state after interrupts are fully disabled. */
1709 del_timer_sync(&dev_priv->hangcheck_timer);
1710 cancel_work_sync(&dev_priv->error_work);
1711 i915_destroy_error_state(dev);
1712
1713 if (dev->pdev->msi_enabled)
1714 pci_disable_msi(dev->pdev);
1715
1716 intel_opregion_fini(dev);
1717
1718 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1719 /* Flush any outstanding unpin_work. */
1720 flush_workqueue(dev_priv->wq);
1721
1722 mutex_lock(&dev->struct_mutex);
1723 i915_gem_free_all_phys_object(dev);
1724 i915_gem_cleanup_ringbuffer(dev);
1725 i915_gem_context_fini(dev);
1726 mutex_unlock(&dev->struct_mutex);
1727 i915_gem_cleanup_aliasing_ppgtt(dev);
1728 i915_gem_cleanup_stolen(dev);
1729 drm_mm_takedown(&dev_priv->mm.stolen);
1730
1731 intel_cleanup_overlay(dev);
1732
1733 if (!I915_NEED_GFX_HWS(dev))
1734 i915_free_hws(dev);
1735 }
1736
1737 if (dev_priv->regs != NULL)
1738 pci_iounmap(dev->pdev, dev_priv->regs);
1739
1740 intel_teardown_gmbus(dev);
1741 intel_teardown_mchbar(dev);
1742
1743 destroy_workqueue(dev_priv->wq);
1744
1745 pci_dev_put(dev_priv->bridge_dev);
1746 kfree(dev->dev_private);
1747
1748 return 0;
1749 }
1750
1751 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1752 {
1753 struct drm_i915_file_private *file_priv;
1754
1755 DRM_DEBUG_DRIVER("\n");
1756 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1757 if (!file_priv)
1758 return -ENOMEM;
1759
1760 file->driver_priv = file_priv;
1761
1762 spin_lock_init(&file_priv->mm.lock);
1763 INIT_LIST_HEAD(&file_priv->mm.request_list);
1764
1765 idr_init(&file_priv->context_idr);
1766
1767 return 0;
1768 }
1769
1770 /**
1771 * i915_driver_lastclose - clean up after all DRM clients have exited
1772 * @dev: DRM device
1773 *
1774 * Take care of cleaning up after all DRM clients have exited. In the
1775 * mode setting case, we want to restore the kernel's initial mode (just
1776 * in case the last client left us in a bad state).
1777 *
1778 * Additionally, in the non-mode setting case, we'll tear down the GTT
1779 * and DMA structures, since the kernel won't be using them, and clea
1780 * up any GEM state.
1781 */
1782 void i915_driver_lastclose(struct drm_device * dev)
1783 {
1784 drm_i915_private_t *dev_priv = dev->dev_private;
1785
1786 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1787 * goes right around and calls lastclose. Check for this and don't clean
1788 * up anything. */
1789 if (!dev_priv)
1790 return;
1791
1792 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1793 intel_fb_restore_mode(dev);
1794 vga_switcheroo_process_delayed_switch();
1795 return;
1796 }
1797
1798 i915_gem_lastclose(dev);
1799
1800 i915_dma_cleanup(dev);
1801 }
1802
1803 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1804 {
1805 i915_gem_context_close(dev, file_priv);
1806 i915_gem_release(dev, file_priv);
1807 }
1808
1809 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1810 {
1811 struct drm_i915_file_private *file_priv = file->driver_priv;
1812
1813 kfree(file_priv);
1814 }
1815
1816 struct drm_ioctl_desc i915_ioctls[] = {
1817 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1818 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1819 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1820 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1821 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1822 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1823 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1824 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1825 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1826 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1827 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1828 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1829 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1830 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1831 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1832 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1833 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1834 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1835 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1836 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1837 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1838 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1839 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1840 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1841 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1842 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1843 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1844 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1845 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1846 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1847 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1848 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1849 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1850 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1851 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1852 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1853 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1854 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1855 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1856 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1857 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1858 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1859 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1860 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1861 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1862 };
1863
1864 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1865
1866 /*
1867 * This is really ugly: Because old userspace abused the linux agp interface to
1868 * manage the gtt, we need to claim that all intel devices are agp. For
1869 * otherwise the drm core refuses to initialize the agp support code.
1870 */
1871 int i915_driver_device_is_agp(struct drm_device * dev)
1872 {
1873 return 1;
1874 }
Linux ARM platform port for MOXA ART SoC