?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / i915 / intel_display.c
blobb634f6ff25cc75e693a3752dc02b4df3162e0c60
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1381 "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386 {
1387 u32 val = I915_READ(reg);
1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390 reg, pipe_name(pipe));
1391
1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1394 "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 int reg;
1401 u32 val;
1402
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 pipe_name(pipe));
1412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 pipe_name(pipe));
1418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
1434 */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518 out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525 unsigned long flags;
1526 u32 value = 0;
1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552 }
1553
1554 /**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1566 int reg;
1567 u32 val;
1568
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
1598
1599 pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606 int reg;
1607 u32 val;
1608
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
1616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623 return;
1624 }
1625
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636 reg = pll->pll_reg;
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
1642
1643 pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648 {
1649 int reg;
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1680 }
1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699 {
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
1735 {
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778 {
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806 enum plane plane)
1807 {
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822 {
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849 {
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1865 {
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1870 }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875 {
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1881 }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 alignment;
1923 int ret;
1924
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948 if (ret)
1949 goto err_interruptible;
1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
1956 ret = i915_gem_object_get_fence(obj);
1957 if (ret)
1958 goto err_unpin;
1959
1960 i915_gem_object_pin_fence(obj);
1961
1962 dev_priv->mm.interruptible = true;
1963 return 0;
1964
1965 err_unpin:
1966 i915_gem_object_unpin(obj);
1967 err_interruptible:
1968 dev_priv->mm.interruptible = true;
1969 return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983 {
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
1996 {
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2004 u32 dspcntr;
2005 u32 reg;
2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039 return -EINVAL;
2040 }
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
2048 I915_WRITE(reg, dspcntr);
2049
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
2059 intel_crtc->dspaddr_offset = linear_offset;
2060 }
2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072 POSTING_READ(reg);
2073
2074 return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079 {
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 case 2:
2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
2147
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2155 POSTING_READ(reg);
2156
2157 return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2171
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
2205 {
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 int ret;
2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
2214 DRM_ERROR("No FB bound\n");
2215 return 0;
2216 }
2217
2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
2222 return -EINVAL;
2223 }
2224
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2228 NULL);
2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2232 return ret;
2233 }
2234
2235 if (old_fb)
2236 intel_finish_fb(old_fb);
2237
2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239 if (ret) {
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2243 return ret;
2244 }
2245
2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249 }
2250
2251 intel_update_fbc(dev);
2252 mutex_unlock(&dev->struct_mutex);
2253
2254 if (!dev->primary->master)
2255 return 0;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return 0;
2260
2261 if (intel_crtc->pipe) {
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
2305 POSTING_READ(DP_A);
2306 udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 if (IS_IVYBRIDGE(dev)) {
2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326 }
2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2371
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
2384 udelay(150);
2385
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
2402 udelay(150);
2403
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
2410
2411 reg = FDI_RX_IIR(pipe);
2412 for (tries = 0; tries < 5; tries++) {
2413 temp = I915_READ(reg);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419 break;
2420 }
2421 }
2422 if (tries == 5)
2423 DRM_ERROR("FDI train 1 fail!\n");
2424
2425 /* Train 2 */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 I915_WRITE(reg, temp);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
2439 udelay(150);
2440
2441 reg = FDI_RX_IIR(pipe);
2442 for (tries = 0; tries < 5; tries++) {
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
2451 }
2452 if (tries == 5)
2453 DRM_ERROR("FDI train 2 fail!\n");
2454
2455 DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 u32 reg, temp, i, retry;
2474
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
2484 udelay(150);
2485
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
2510 udelay(150);
2511
2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
2515 for (i = 0; i < 4; i++) {
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(500);
2524
2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
2535 }
2536 if (retry < 5)
2537 break;
2538 }
2539 if (i == 4)
2540 DRM_ERROR("FDI train 1 fail!\n");
2541
2542 /* Train 2 */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
2552 I915_WRITE(reg, temp);
2553
2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
2588 }
2589 if (retry < 5)
2590 break;
2591 }
2592 if (i == 4)
2593 DRM_ERROR("FDI train 2 fail!\n");
2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 temp |= FDI_COMPOSITE_SYNC;
2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 temp |= FDI_COMPOSITE_SYNC;
2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2713 {
2714 struct drm_device *dev = crtc->dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717 int pipe = intel_crtc->pipe;
2718 u32 reg, temp;
2719
2720 /* Write the TU size bits so error detection works */
2721 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2722 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2723
2724 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~((0x7 << 19) | (0x7 << 16));
2728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2730 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2731
2732 POSTING_READ(reg);
2733 udelay(200);
2734
2735 /* Switch from Rawclk to PCDclk */
2736 temp = I915_READ(reg);
2737 I915_WRITE(reg, temp | FDI_PCDCLK);
2738
2739 POSTING_READ(reg);
2740 udelay(200);
2741
2742 /* On Haswell, the PLL configuration for ports and pipes is handled
2743 * separately, as part of DDI setup */
2744 if (!IS_HASWELL(dev)) {
2745 /* Enable CPU FDI TX PLL, always on for Ironlake */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2749 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753 }
2754 }
2755 }
2756
2757 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2758 {
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 u32 flags = I915_READ(SOUTH_CHICKEN1);
2761
2762 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2763 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2764 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2765 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2766 POSTING_READ(SOUTH_CHICKEN1);
2767 }
2768 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2769 {
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 int pipe = intel_crtc->pipe;
2774 u32 reg, temp;
2775
2776 /* disable CPU FDI tx and PCH FDI rx */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2780 POSTING_READ(reg);
2781
2782 reg = FDI_RX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~(0x7 << 16);
2785 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2786 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2787
2788 POSTING_READ(reg);
2789 udelay(100);
2790
2791 /* Ironlake workaround, disable clock pointer after downing FDI */
2792 if (HAS_PCH_IBX(dev)) {
2793 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2794 I915_WRITE(FDI_RX_CHICKEN(pipe),
2795 I915_READ(FDI_RX_CHICKEN(pipe) &
2796 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2797 } else if (HAS_PCH_CPT(dev)) {
2798 cpt_phase_pointer_disable(dev, pipe);
2799 }
2800
2801 /* still set train pattern 1 */
2802 reg = FDI_TX_CTL(pipe);
2803 temp = I915_READ(reg);
2804 temp &= ~FDI_LINK_TRAIN_NONE;
2805 temp |= FDI_LINK_TRAIN_PATTERN_1;
2806 I915_WRITE(reg, temp);
2807
2808 reg = FDI_RX_CTL(pipe);
2809 temp = I915_READ(reg);
2810 if (HAS_PCH_CPT(dev)) {
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813 } else {
2814 temp &= ~FDI_LINK_TRAIN_NONE;
2815 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816 }
2817 /* BPC in FDI rx is consistent with that in PIPECONF */
2818 temp &= ~(0x07 << 16);
2819 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820 I915_WRITE(reg, temp);
2821
2822 POSTING_READ(reg);
2823 udelay(100);
2824 }
2825
2826 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2827 {
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 unsigned long flags;
2831 bool pending;
2832
2833 if (atomic_read(&dev_priv->mm.wedged))
2834 return false;
2835
2836 spin_lock_irqsave(&dev->event_lock, flags);
2837 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2838 spin_unlock_irqrestore(&dev->event_lock, flags);
2839
2840 return pending;
2841 }
2842
2843 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844 {
2845 struct drm_device *dev = crtc->dev;
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
2851 wait_event(dev_priv->pending_flip_queue,
2852 !intel_crtc_has_pending_flip(crtc));
2853
2854 mutex_lock(&dev->struct_mutex);
2855 intel_finish_fb(crtc->fb);
2856 mutex_unlock(&dev->struct_mutex);
2857 }
2858
2859 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2860 {
2861 struct drm_device *dev = crtc->dev;
2862 struct intel_encoder *encoder;
2863
2864 /*
2865 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2866 * must be driven by its own crtc; no sharing is possible.
2867 */
2868 for_each_encoder_on_crtc(dev, crtc, encoder) {
2869
2870 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2871 * CPU handles all others */
2872 if (IS_HASWELL(dev)) {
2873 /* It is still unclear how this will work on PPT, so throw up a warning */
2874 WARN_ON(!HAS_PCH_LPT(dev));
2875
2876 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2877 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2878 return true;
2879 } else {
2880 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2881 encoder->type);
2882 return false;
2883 }
2884 }
2885
2886 switch (encoder->type) {
2887 case INTEL_OUTPUT_EDP:
2888 if (!intel_encoder_is_pch_edp(&encoder->base))
2889 return false;
2890 continue;
2891 }
2892 }
2893
2894 return true;
2895 }
2896
2897 /* Program iCLKIP clock to the desired frequency */
2898 static void lpt_program_iclkip(struct drm_crtc *crtc)
2899 {
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2903 u32 temp;
2904
2905 /* It is necessary to ungate the pixclk gate prior to programming
2906 * the divisors, and gate it back when it is done.
2907 */
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2909
2910 /* Disable SSCCTL */
2911 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2912 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2913 SBI_SSCCTL_DISABLE);
2914
2915 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2916 if (crtc->mode.clock == 20000) {
2917 auxdiv = 1;
2918 divsel = 0x41;
2919 phaseinc = 0x20;
2920 } else {
2921 /* The iCLK virtual clock root frequency is in MHz,
2922 * but the crtc->mode.clock in in KHz. To get the divisors,
2923 * it is necessary to divide one by another, so we
2924 * convert the virtual clock precision to KHz here for higher
2925 * precision.
2926 */
2927 u32 iclk_virtual_root_freq = 172800 * 1000;
2928 u32 iclk_pi_range = 64;
2929 u32 desired_divisor, msb_divisor_value, pi_value;
2930
2931 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2932 msb_divisor_value = desired_divisor / iclk_pi_range;
2933 pi_value = desired_divisor % iclk_pi_range;
2934
2935 auxdiv = 0;
2936 divsel = msb_divisor_value - 2;
2937 phaseinc = pi_value;
2938 }
2939
2940 /* This should not happen with any sane values */
2941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2945
2946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2947 crtc->mode.clock,
2948 auxdiv,
2949 divsel,
2950 phasedir,
2951 phaseinc);
2952
2953 /* Program SSCDIVINTPHASE6 */
2954 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2955 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2956 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2957 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2958 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2959 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2960 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2961
2962 intel_sbi_write(dev_priv,
2963 SBI_SSCDIVINTPHASE6,
2964 temp);
2965
2966 /* Program SSCAUXDIV */
2967 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2968 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2969 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2970 intel_sbi_write(dev_priv,
2971 SBI_SSCAUXDIV6,
2972 temp);
2973
2974
2975 /* Enable modulator and associated divider */
2976 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2977 temp &= ~SBI_SSCCTL_DISABLE;
2978 intel_sbi_write(dev_priv,
2979 SBI_SSCCTL6,
2980 temp);
2981
2982 /* Wait for initialization time */
2983 udelay(24);
2984
2985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2986 }
2987
2988 /*
2989 * Enable PCH resources required for PCH ports:
2990 * - PCH PLLs
2991 * - FDI training & RX/TX
2992 * - update transcoder timings
2993 * - DP transcoding bits
2994 * - transcoder
2995 */
2996 static void ironlake_pch_enable(struct drm_crtc *crtc)
2997 {
2998 struct drm_device *dev = crtc->dev;
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3001 int pipe = intel_crtc->pipe;
3002 u32 reg, temp;
3003
3004 assert_transcoder_disabled(dev_priv, pipe);
3005
3006 /* For PCH output, training FDI link */
3007 dev_priv->display.fdi_link_train(crtc);
3008
3009 intel_enable_pch_pll(intel_crtc);
3010
3011 if (HAS_PCH_LPT(dev)) {
3012 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3013 lpt_program_iclkip(crtc);
3014 } else if (HAS_PCH_CPT(dev)) {
3015 u32 sel;
3016
3017 temp = I915_READ(PCH_DPLL_SEL);
3018 switch (pipe) {
3019 default:
3020 case 0:
3021 temp |= TRANSA_DPLL_ENABLE;
3022 sel = TRANSA_DPLLB_SEL;
3023 break;
3024 case 1:
3025 temp |= TRANSB_DPLL_ENABLE;
3026 sel = TRANSB_DPLLB_SEL;
3027 break;
3028 case 2:
3029 temp |= TRANSC_DPLL_ENABLE;
3030 sel = TRANSC_DPLLB_SEL;
3031 break;
3032 }
3033 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3034 temp |= sel;
3035 else
3036 temp &= ~sel;
3037 I915_WRITE(PCH_DPLL_SEL, temp);
3038 }
3039
3040 /* set transcoder timing, panel must allow it */
3041 assert_panel_unlocked(dev_priv, pipe);
3042 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3043 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3044 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3045
3046 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3047 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3048 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3049 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3050
3051 if (!IS_HASWELL(dev))
3052 intel_fdi_normal_train(crtc);
3053
3054 /* For PCH DP, enable TRANS_DP_CTL */
3055 if (HAS_PCH_CPT(dev) &&
3056 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3057 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3058 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3059 reg = TRANS_DP_CTL(pipe);
3060 temp = I915_READ(reg);
3061 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3062 TRANS_DP_SYNC_MASK |
3063 TRANS_DP_BPC_MASK);
3064 temp |= (TRANS_DP_OUTPUT_ENABLE |
3065 TRANS_DP_ENH_FRAMING);
3066 temp |= bpc << 9; /* same format but at 11:9 */
3067
3068 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3069 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3070 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3071 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3072
3073 switch (intel_trans_dp_port_sel(crtc)) {
3074 case PCH_DP_B:
3075 temp |= TRANS_DP_PORT_SEL_B;
3076 break;
3077 case PCH_DP_C:
3078 temp |= TRANS_DP_PORT_SEL_C;
3079 break;
3080 case PCH_DP_D:
3081 temp |= TRANS_DP_PORT_SEL_D;
3082 break;
3083 default:
3084 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3085 temp |= TRANS_DP_PORT_SEL_B;
3086 break;
3087 }
3088
3089 I915_WRITE(reg, temp);
3090 }
3091
3092 intel_enable_transcoder(dev_priv, pipe);
3093 }
3094
3095 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3096 {
3097 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3098
3099 if (pll == NULL)
3100 return;
3101
3102 if (pll->refcount == 0) {
3103 WARN(1, "bad PCH PLL refcount\n");
3104 return;
3105 }
3106
3107 --pll->refcount;
3108 intel_crtc->pch_pll = NULL;
3109 }
3110
3111 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3112 {
3113 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3114 struct intel_pch_pll *pll;
3115 int i;
3116
3117 pll = intel_crtc->pch_pll;
3118 if (pll) {
3119 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3120 intel_crtc->base.base.id, pll->pll_reg);
3121 goto prepare;
3122 }
3123
3124 if (HAS_PCH_IBX(dev_priv->dev)) {
3125 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3126 i = intel_crtc->pipe;
3127 pll = &dev_priv->pch_plls[i];
3128
3129 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3130 intel_crtc->base.base.id, pll->pll_reg);
3131
3132 goto found;
3133 }
3134
3135 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3136 pll = &dev_priv->pch_plls[i];
3137
3138 /* Only want to check enabled timings first */
3139 if (pll->refcount == 0)
3140 continue;
3141
3142 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3143 fp == I915_READ(pll->fp0_reg)) {
3144 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3145 intel_crtc->base.base.id,
3146 pll->pll_reg, pll->refcount, pll->active);
3147
3148 goto found;
3149 }
3150 }
3151
3152 /* Ok no matching timings, maybe there's a free one? */
3153 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3154 pll = &dev_priv->pch_plls[i];
3155 if (pll->refcount == 0) {
3156 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3157 intel_crtc->base.base.id, pll->pll_reg);
3158 goto found;
3159 }
3160 }
3161
3162 return NULL;
3163
3164 found:
3165 intel_crtc->pch_pll = pll;
3166 pll->refcount++;
3167 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3168 prepare: /* separate function? */
3169 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3170
3171 /* Wait for the clocks to stabilize before rewriting the regs */
3172 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3173 POSTING_READ(pll->pll_reg);
3174 udelay(150);
3175
3176 I915_WRITE(pll->fp0_reg, fp);
3177 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3178 pll->on = false;
3179 return pll;
3180 }
3181
3182 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3183 {
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3186 u32 temp;
3187
3188 temp = I915_READ(dslreg);
3189 udelay(500);
3190 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3191 /* Without this, mode sets may fail silently on FDI */
3192 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3193 udelay(250);
3194 I915_WRITE(tc2reg, 0);
3195 if (wait_for(I915_READ(dslreg) != temp, 5))
3196 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3197 }
3198 }
3199
3200 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3201 {
3202 struct drm_device *dev = crtc->dev;
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205 int pipe = intel_crtc->pipe;
3206 int plane = intel_crtc->plane;
3207 u32 temp;
3208 bool is_pch_port;
3209
3210 if (intel_crtc->active)
3211 return;
3212
3213 intel_crtc->active = true;
3214 intel_update_watermarks(dev);
3215
3216 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3217 temp = I915_READ(PCH_LVDS);
3218 if ((temp & LVDS_PORT_EN) == 0)
3219 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3220 }
3221
3222 is_pch_port = intel_crtc_driving_pch(crtc);
3223
3224 if (is_pch_port)
3225 ironlake_fdi_pll_enable(crtc);
3226 else
3227 ironlake_fdi_disable(crtc);
3228
3229 /* Enable panel fitting for LVDS */
3230 if (dev_priv->pch_pf_size &&
3231 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3232 /* Force use of hard-coded filter coefficients
3233 * as some pre-programmed values are broken,
3234 * e.g. x201.
3235 */
3236 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3237 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3238 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3239 }
3240
3241 /*
3242 * On ILK+ LUT must be loaded before the pipe is running but with
3243 * clocks enabled
3244 */
3245 intel_crtc_load_lut(crtc);
3246
3247 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3248 intel_enable_plane(dev_priv, plane, pipe);
3249
3250 if (is_pch_port)
3251 ironlake_pch_enable(crtc);
3252
3253 mutex_lock(&dev->struct_mutex);
3254 intel_update_fbc(dev);
3255 mutex_unlock(&dev->struct_mutex);
3256
3257 intel_crtc_update_cursor(crtc, true);
3258 }
3259
3260 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3261 {
3262 struct drm_device *dev = crtc->dev;
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3265 int pipe = intel_crtc->pipe;
3266 int plane = intel_crtc->plane;
3267 u32 reg, temp;
3268
3269 if (!intel_crtc->active)
3270 return;
3271
3272 intel_crtc_wait_for_pending_flips(crtc);
3273 drm_vblank_off(dev, pipe);
3274 intel_crtc_update_cursor(crtc, false);
3275
3276 intel_disable_plane(dev_priv, plane, pipe);
3277
3278 if (dev_priv->cfb_plane == plane)
3279 intel_disable_fbc(dev);
3280
3281 intel_disable_pipe(dev_priv, pipe);
3282
3283 /* Disable PF */
3284 I915_WRITE(PF_CTL(pipe), 0);
3285 I915_WRITE(PF_WIN_SZ(pipe), 0);
3286
3287 ironlake_fdi_disable(crtc);
3288
3289 /* This is a horrible layering violation; we should be doing this in
3290 * the connector/encoder ->prepare instead, but we don't always have
3291 * enough information there about the config to know whether it will
3292 * actually be necessary or just cause undesired flicker.
3293 */
3294 intel_disable_pch_ports(dev_priv, pipe);
3295
3296 intel_disable_transcoder(dev_priv, pipe);
3297
3298 if (HAS_PCH_CPT(dev)) {
3299 /* disable TRANS_DP_CTL */
3300 reg = TRANS_DP_CTL(pipe);
3301 temp = I915_READ(reg);
3302 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3303 temp |= TRANS_DP_PORT_SEL_NONE;
3304 I915_WRITE(reg, temp);
3305
3306 /* disable DPLL_SEL */
3307 temp = I915_READ(PCH_DPLL_SEL);
3308 switch (pipe) {
3309 case 0:
3310 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3311 break;
3312 case 1:
3313 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3314 break;
3315 case 2:
3316 /* C shares PLL A or B */
3317 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3318 break;
3319 default:
3320 BUG(); /* wtf */
3321 }
3322 I915_WRITE(PCH_DPLL_SEL, temp);
3323 }
3324
3325 /* disable PCH DPLL */
3326 intel_disable_pch_pll(intel_crtc);
3327
3328 /* Switch from PCDclk to Rawclk */
3329 reg = FDI_RX_CTL(pipe);
3330 temp = I915_READ(reg);
3331 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3332
3333 /* Disable CPU FDI TX PLL */
3334 reg = FDI_TX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3337
3338 POSTING_READ(reg);
3339 udelay(100);
3340
3341 reg = FDI_RX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3344
3345 /* Wait for the clocks to turn off. */
3346 POSTING_READ(reg);
3347 udelay(100);
3348
3349 intel_crtc->active = false;
3350 intel_update_watermarks(dev);
3351
3352 mutex_lock(&dev->struct_mutex);
3353 intel_update_fbc(dev);
3354 mutex_unlock(&dev->struct_mutex);
3355 }
3356
3357 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3358 {
3359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360 int pipe = intel_crtc->pipe;
3361 int plane = intel_crtc->plane;
3362
3363 /* XXX: When our outputs are all unaware of DPMS modes other than off
3364 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3365 */
3366 switch (mode) {
3367 case DRM_MODE_DPMS_ON:
3368 case DRM_MODE_DPMS_STANDBY:
3369 case DRM_MODE_DPMS_SUSPEND:
3370 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3371 ironlake_crtc_enable(crtc);
3372 break;
3373
3374 case DRM_MODE_DPMS_OFF:
3375 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3376 ironlake_crtc_disable(crtc);
3377 break;
3378 }
3379 }
3380
3381 static void ironlake_crtc_off(struct drm_crtc *crtc)
3382 {
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384 intel_put_pch_pll(intel_crtc);
3385 }
3386
3387 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3388 {
3389 if (!enable && intel_crtc->overlay) {
3390 struct drm_device *dev = intel_crtc->base.dev;
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392
3393 mutex_lock(&dev->struct_mutex);
3394 dev_priv->mm.interruptible = false;
3395 (void) intel_overlay_switch_off(intel_crtc->overlay);
3396 dev_priv->mm.interruptible = true;
3397 mutex_unlock(&dev->struct_mutex);
3398 }
3399
3400 /* Let userspace switch the overlay on again. In most cases userspace
3401 * has to recompute where to put it anyway.
3402 */
3403 }
3404
3405 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3406 {
3407 struct drm_device *dev = crtc->dev;
3408 struct drm_i915_private *dev_priv = dev->dev_private;
3409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3410 int pipe = intel_crtc->pipe;
3411 int plane = intel_crtc->plane;
3412
3413 if (intel_crtc->active)
3414 return;
3415
3416 intel_crtc->active = true;
3417 intel_update_watermarks(dev);
3418
3419 intel_enable_pll(dev_priv, pipe);
3420 intel_enable_pipe(dev_priv, pipe, false);
3421 intel_enable_plane(dev_priv, plane, pipe);
3422
3423 intel_crtc_load_lut(crtc);
3424 intel_update_fbc(dev);
3425
3426 /* Give the overlay scaler a chance to enable if it's on this pipe */
3427 intel_crtc_dpms_overlay(intel_crtc, true);
3428 intel_crtc_update_cursor(crtc, true);
3429 }
3430
3431 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3432 {
3433 struct drm_device *dev = crtc->dev;
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436 int pipe = intel_crtc->pipe;
3437 int plane = intel_crtc->plane;
3438
3439 if (!intel_crtc->active)
3440 return;
3441
3442 /* Give the overlay scaler a chance to disable if it's on this pipe */
3443 intel_crtc_wait_for_pending_flips(crtc);
3444 drm_vblank_off(dev, pipe);
3445 intel_crtc_dpms_overlay(intel_crtc, false);
3446 intel_crtc_update_cursor(crtc, false);
3447
3448 if (dev_priv->cfb_plane == plane)
3449 intel_disable_fbc(dev);
3450
3451 intel_disable_plane(dev_priv, plane, pipe);
3452 intel_disable_pipe(dev_priv, pipe);
3453 intel_disable_pll(dev_priv, pipe);
3454
3455 intel_crtc->active = false;
3456 intel_update_fbc(dev);
3457 intel_update_watermarks(dev);
3458 }
3459
3460 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3461 {
3462 /* XXX: When our outputs are all unaware of DPMS modes other than off
3463 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3464 */
3465 switch (mode) {
3466 case DRM_MODE_DPMS_ON:
3467 case DRM_MODE_DPMS_STANDBY:
3468 case DRM_MODE_DPMS_SUSPEND:
3469 i9xx_crtc_enable(crtc);
3470 break;
3471 case DRM_MODE_DPMS_OFF:
3472 i9xx_crtc_disable(crtc);
3473 break;
3474 }
3475 }
3476
3477 static void i9xx_crtc_off(struct drm_crtc *crtc)
3478 {
3479 }
3480
3481 /**
3482 * Sets the power management mode of the pipe and plane.
3483 */
3484 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3485 {
3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 struct drm_i915_master_private *master_priv;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 int pipe = intel_crtc->pipe;
3491 bool enabled;
3492
3493 if (intel_crtc->dpms_mode == mode)
3494 return;
3495
3496 intel_crtc->dpms_mode = mode;
3497
3498 dev_priv->display.dpms(crtc, mode);
3499
3500 if (!dev->primary->master)
3501 return;
3502
3503 master_priv = dev->primary->master->driver_priv;
3504 if (!master_priv->sarea_priv)
3505 return;
3506
3507 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3508
3509 switch (pipe) {
3510 case 0:
3511 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3512 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3513 break;
3514 case 1:
3515 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3516 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3517 break;
3518 default:
3519 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3520 break;
3521 }
3522 }
3523
3524 static void intel_crtc_disable(struct drm_crtc *crtc)
3525 {
3526 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3527 struct drm_device *dev = crtc->dev;
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529
3530 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3531 dev_priv->display.off(crtc);
3532
3533 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3534 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3535
3536 if (crtc->fb) {
3537 mutex_lock(&dev->struct_mutex);
3538 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3539 mutex_unlock(&dev->struct_mutex);
3540 }
3541 }
3542
3543 /* Prepare for a mode set.
3544 *
3545 * Note we could be a lot smarter here. We need to figure out which outputs
3546 * will be enabled, which disabled (in short, how the config will changes)
3547 * and perform the minimum necessary steps to accomplish that, e.g. updating
3548 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3549 * panel fitting is in the proper state, etc.
3550 */
3551 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3552 {
3553 i9xx_crtc_disable(crtc);
3554 }
3555
3556 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3557 {
3558 i9xx_crtc_enable(crtc);
3559 }
3560
3561 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3562 {
3563 ironlake_crtc_disable(crtc);
3564 }
3565
3566 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3567 {
3568 ironlake_crtc_enable(crtc);
3569 }
3570
3571 void intel_encoder_prepare(struct drm_encoder *encoder)
3572 {
3573 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3574 /* lvds has its own version of prepare see intel_lvds_prepare */
3575 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3576 }
3577
3578 void intel_encoder_commit(struct drm_encoder *encoder)
3579 {
3580 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3581 struct drm_device *dev = encoder->dev;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3583
3584 /* lvds has its own version of commit see intel_lvds_commit */
3585 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3586
3587 if (HAS_PCH_CPT(dev))
3588 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3589 }
3590
3591 void intel_encoder_destroy(struct drm_encoder *encoder)
3592 {
3593 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3594
3595 drm_encoder_cleanup(encoder);
3596 kfree(intel_encoder);
3597 }
3598
3599 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3600 const struct drm_display_mode *mode,
3601 struct drm_display_mode *adjusted_mode)
3602 {
3603 struct drm_device *dev = crtc->dev;
3604
3605 if (HAS_PCH_SPLIT(dev)) {
3606 /* FDI link clock is fixed at 2.7G */
3607 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3608 return false;
3609 }
3610
3611 /* All interlaced capable intel hw wants timings in frames. Note though
3612 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3613 * timings, so we need to be careful not to clobber these.*/
3614 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3615 drm_mode_set_crtcinfo(adjusted_mode, 0);
3616
3617 return true;
3618 }
3619
3620 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3621 {
3622 return 400000; /* FIXME */
3623 }
3624
3625 static int i945_get_display_clock_speed(struct drm_device *dev)
3626 {
3627 return 400000;
3628 }
3629
3630 static int i915_get_display_clock_speed(struct drm_device *dev)
3631 {
3632 return 333000;
3633 }
3634
3635 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3636 {
3637 return 200000;
3638 }
3639
3640 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3641 {
3642 u16 gcfgc = 0;
3643
3644 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3645
3646 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3647 return 133000;
3648 else {
3649 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3650 case GC_DISPLAY_CLOCK_333_MHZ:
3651 return 333000;
3652 default:
3653 case GC_DISPLAY_CLOCK_190_200_MHZ:
3654 return 190000;
3655 }
3656 }
3657 }
3658
3659 static int i865_get_display_clock_speed(struct drm_device *dev)
3660 {
3661 return 266000;
3662 }
3663
3664 static int i855_get_display_clock_speed(struct drm_device *dev)
3665 {
3666 u16 hpllcc = 0;
3667 /* Assume that the hardware is in the high speed state. This
3668 * should be the default.
3669 */
3670 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3671 case GC_CLOCK_133_200:
3672 case GC_CLOCK_100_200:
3673 return 200000;
3674 case GC_CLOCK_166_250:
3675 return 250000;
3676 case GC_CLOCK_100_133:
3677 return 133000;
3678 }
3679
3680 /* Shouldn't happen */
3681 return 0;
3682 }
3683
3684 static int i830_get_display_clock_speed(struct drm_device *dev)
3685 {
3686 return 133000;
3687 }
3688
3689 struct fdi_m_n {
3690 u32 tu;
3691 u32 gmch_m;
3692 u32 gmch_n;
3693 u32 link_m;
3694 u32 link_n;
3695 };
3696
3697 static void
3698 fdi_reduce_ratio(u32 *num, u32 *den)
3699 {
3700 while (*num > 0xffffff || *den > 0xffffff) {
3701 *num >>= 1;
3702 *den >>= 1;
3703 }
3704 }
3705
3706 static void
3707 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3708 int link_clock, struct fdi_m_n *m_n)
3709 {
3710 m_n->tu = 64; /* default size */
3711
3712 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3713 m_n->gmch_m = bits_per_pixel * pixel_clock;
3714 m_n->gmch_n = link_clock * nlanes * 8;
3715 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3716
3717 m_n->link_m = pixel_clock;
3718 m_n->link_n = link_clock;
3719 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3720 }
3721
3722 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3723 {
3724 if (i915_panel_use_ssc >= 0)
3725 return i915_panel_use_ssc != 0;
3726 return dev_priv->lvds_use_ssc
3727 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3728 }
3729
3730 /**
3731 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3732 * @crtc: CRTC structure
3733 * @mode: requested mode
3734 *
3735 * A pipe may be connected to one or more outputs. Based on the depth of the
3736 * attached framebuffer, choose a good color depth to use on the pipe.
3737 *
3738 * If possible, match the pipe depth to the fb depth. In some cases, this
3739 * isn't ideal, because the connected output supports a lesser or restricted
3740 * set of depths. Resolve that here:
3741 * LVDS typically supports only 6bpc, so clamp down in that case
3742 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3743 * Displays may support a restricted set as well, check EDID and clamp as
3744 * appropriate.
3745 * DP may want to dither down to 6bpc to fit larger modes
3746 *
3747 * RETURNS:
3748 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3749 * true if they don't match).
3750 */
3751 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3752 unsigned int *pipe_bpp,
3753 struct drm_display_mode *mode)
3754 {
3755 struct drm_device *dev = crtc->dev;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 struct drm_connector *connector;
3758 struct intel_encoder *intel_encoder;
3759 unsigned int display_bpc = UINT_MAX, bpc;
3760
3761 /* Walk the encoders & connectors on this crtc, get min bpc */
3762 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3763
3764 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3765 unsigned int lvds_bpc;
3766
3767 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3768 LVDS_A3_POWER_UP)
3769 lvds_bpc = 8;
3770 else
3771 lvds_bpc = 6;
3772
3773 if (lvds_bpc < display_bpc) {
3774 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3775 display_bpc = lvds_bpc;
3776 }
3777 continue;
3778 }
3779
3780 /* Not one of the known troublemakers, check the EDID */
3781 list_for_each_entry(connector, &dev->mode_config.connector_list,
3782 head) {
3783 if (connector->encoder != &intel_encoder->base)
3784 continue;
3785
3786 /* Don't use an invalid EDID bpc value */
3787 if (connector->display_info.bpc &&
3788 connector->display_info.bpc < display_bpc) {
3789 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3790 display_bpc = connector->display_info.bpc;
3791 }
3792 }
3793
3794 /*
3795 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3796 * through, clamp it down. (Note: >12bpc will be caught below.)
3797 */
3798 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3799 if (display_bpc > 8 && display_bpc < 12) {
3800 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3801 display_bpc = 12;
3802 } else {
3803 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3804 display_bpc = 8;
3805 }
3806 }
3807 }
3808
3809 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3810 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3811 display_bpc = 6;
3812 }
3813
3814 /*
3815 * We could just drive the pipe at the highest bpc all the time and
3816 * enable dithering as needed, but that costs bandwidth. So choose
3817 * the minimum value that expresses the full color range of the fb but
3818 * also stays within the max display bpc discovered above.
3819 */
3820
3821 switch (crtc->fb->depth) {
3822 case 8:
3823 bpc = 8; /* since we go through a colormap */
3824 break;
3825 case 15:
3826 case 16:
3827 bpc = 6; /* min is 18bpp */
3828 break;
3829 case 24:
3830 bpc = 8;
3831 break;
3832 case 30:
3833 bpc = 10;
3834 break;
3835 case 48:
3836 bpc = 12;
3837 break;
3838 default:
3839 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3840 bpc = min((unsigned int)8, display_bpc);
3841 break;
3842 }
3843
3844 display_bpc = min(display_bpc, bpc);
3845
3846 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3847 bpc, display_bpc);
3848
3849 *pipe_bpp = display_bpc * 3;
3850
3851 return display_bpc != bpc;
3852 }
3853
3854 static int vlv_get_refclk(struct drm_crtc *crtc)
3855 {
3856 struct drm_device *dev = crtc->dev;
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 int refclk = 27000; /* for DP & HDMI */
3859
3860 return 100000; /* only one validated so far */
3861
3862 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3863 refclk = 96000;
3864 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3865 if (intel_panel_use_ssc(dev_priv))
3866 refclk = 100000;
3867 else
3868 refclk = 96000;
3869 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3870 refclk = 100000;
3871 }
3872
3873 return refclk;
3874 }
3875
3876 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3877 {
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 int refclk;
3881
3882 if (IS_VALLEYVIEW(dev)) {
3883 refclk = vlv_get_refclk(crtc);
3884 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3885 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3886 refclk = dev_priv->lvds_ssc_freq * 1000;
3887 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3888 refclk / 1000);
3889 } else if (!IS_GEN2(dev)) {
3890 refclk = 96000;
3891 } else {
3892 refclk = 48000;
3893 }
3894
3895 return refclk;
3896 }
3897
3898 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3899 intel_clock_t *clock)
3900 {
3901 /* SDVO TV has fixed PLL values depend on its clock range,
3902 this mirrors vbios setting. */
3903 if (adjusted_mode->clock >= 100000
3904 && adjusted_mode->clock < 140500) {
3905 clock->p1 = 2;
3906 clock->p2 = 10;
3907 clock->n = 3;
3908 clock->m1 = 16;
3909 clock->m2 = 8;
3910 } else if (adjusted_mode->clock >= 140500
3911 && adjusted_mode->clock <= 200000) {
3912 clock->p1 = 1;
3913 clock->p2 = 10;
3914 clock->n = 6;
3915 clock->m1 = 12;
3916 clock->m2 = 8;
3917 }
3918 }
3919
3920 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3921 intel_clock_t *clock,
3922 intel_clock_t *reduced_clock)
3923 {
3924 struct drm_device *dev = crtc->dev;
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3927 int pipe = intel_crtc->pipe;
3928 u32 fp, fp2 = 0;
3929
3930 if (IS_PINEVIEW(dev)) {
3931 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3932 if (reduced_clock)
3933 fp2 = (1 << reduced_clock->n) << 16 |
3934 reduced_clock->m1 << 8 | reduced_clock->m2;
3935 } else {
3936 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3937 if (reduced_clock)
3938 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3939 reduced_clock->m2;
3940 }
3941
3942 I915_WRITE(FP0(pipe), fp);
3943
3944 intel_crtc->lowfreq_avail = false;
3945 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3946 reduced_clock && i915_powersave) {
3947 I915_WRITE(FP1(pipe), fp2);
3948 intel_crtc->lowfreq_avail = true;
3949 } else {
3950 I915_WRITE(FP1(pipe), fp);
3951 }
3952 }
3953
3954 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3955 struct drm_display_mode *adjusted_mode)
3956 {
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 int pipe = intel_crtc->pipe;
3961 u32 temp;
3962
3963 temp = I915_READ(LVDS);
3964 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3965 if (pipe == 1) {
3966 temp |= LVDS_PIPEB_SELECT;
3967 } else {
3968 temp &= ~LVDS_PIPEB_SELECT;
3969 }
3970 /* set the corresponsding LVDS_BORDER bit */
3971 temp |= dev_priv->lvds_border_bits;
3972 /* Set the B0-B3 data pairs corresponding to whether we're going to
3973 * set the DPLLs for dual-channel mode or not.
3974 */
3975 if (clock->p2 == 7)
3976 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3977 else
3978 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3979
3980 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3981 * appropriately here, but we need to look more thoroughly into how
3982 * panels behave in the two modes.
3983 */
3984 /* set the dithering flag on LVDS as needed */
3985 if (INTEL_INFO(dev)->gen >= 4) {
3986 if (dev_priv->lvds_dither)
3987 temp |= LVDS_ENABLE_DITHER;
3988 else
3989 temp &= ~LVDS_ENABLE_DITHER;
3990 }
3991 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3992 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3993 temp |= LVDS_HSYNC_POLARITY;
3994 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3995 temp |= LVDS_VSYNC_POLARITY;
3996 I915_WRITE(LVDS, temp);
3997 }
3998
3999 static void vlv_update_pll(struct drm_crtc *crtc,
4000 struct drm_display_mode *mode,
4001 struct drm_display_mode *adjusted_mode,
4002 intel_clock_t *clock, intel_clock_t *reduced_clock,
4003 int refclk, int num_connectors)
4004 {
4005 struct drm_device *dev = crtc->dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
4007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4008 int pipe = intel_crtc->pipe;
4009 u32 dpll, mdiv, pdiv;
4010 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4011 bool is_hdmi;
4012
4013 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4014
4015 bestn = clock->n;
4016 bestm1 = clock->m1;
4017 bestm2 = clock->m2;
4018 bestp1 = clock->p1;
4019 bestp2 = clock->p2;
4020
4021 /* Enable DPIO clock input */
4022 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4023 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4024 I915_WRITE(DPLL(pipe), dpll);
4025 POSTING_READ(DPLL(pipe));
4026
4027 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4028 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4029 mdiv |= ((bestn << DPIO_N_SHIFT));
4030 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4031 mdiv |= (1 << DPIO_K_SHIFT);
4032 mdiv |= DPIO_ENABLE_CALIBRATION;
4033 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4034
4035 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4036
4037 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4038 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4039 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4040 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4041
4042 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4043
4044 dpll |= DPLL_VCO_ENABLE;
4045 I915_WRITE(DPLL(pipe), dpll);
4046 POSTING_READ(DPLL(pipe));
4047 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4048 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4049
4050 if (is_hdmi) {
4051 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4052
4053 if (temp > 1)
4054 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4055 else
4056 temp = 0;
4057
4058 I915_WRITE(DPLL_MD(pipe), temp);
4059 POSTING_READ(DPLL_MD(pipe));
4060 }
4061
4062 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4063 }
4064
4065 static void i9xx_update_pll(struct drm_crtc *crtc,
4066 struct drm_display_mode *mode,
4067 struct drm_display_mode *adjusted_mode,
4068 intel_clock_t *clock, intel_clock_t *reduced_clock,
4069 int num_connectors)
4070 {
4071 struct drm_device *dev = crtc->dev;
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074 int pipe = intel_crtc->pipe;
4075 u32 dpll;
4076 bool is_sdvo;
4077
4078 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4079 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4080
4081 dpll = DPLL_VGA_MODE_DIS;
4082
4083 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4084 dpll |= DPLLB_MODE_LVDS;
4085 else
4086 dpll |= DPLLB_MODE_DAC_SERIAL;
4087 if (is_sdvo) {
4088 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4089 if (pixel_multiplier > 1) {
4090 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4091 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4092 }
4093 dpll |= DPLL_DVO_HIGH_SPEED;
4094 }
4095 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4096 dpll |= DPLL_DVO_HIGH_SPEED;
4097
4098 /* compute bitmask from p1 value */
4099 if (IS_PINEVIEW(dev))
4100 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4101 else {
4102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4103 if (IS_G4X(dev) && reduced_clock)
4104 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4105 }
4106 switch (clock->p2) {
4107 case 5:
4108 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4109 break;
4110 case 7:
4111 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4112 break;
4113 case 10:
4114 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4115 break;
4116 case 14:
4117 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4118 break;
4119 }
4120 if (INTEL_INFO(dev)->gen >= 4)
4121 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4122
4123 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4124 dpll |= PLL_REF_INPUT_TVCLKINBC;
4125 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4126 /* XXX: just matching BIOS for now */
4127 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4128 dpll |= 3;
4129 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4130 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4131 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4132 else
4133 dpll |= PLL_REF_INPUT_DREFCLK;
4134
4135 dpll |= DPLL_VCO_ENABLE;
4136 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4137 POSTING_READ(DPLL(pipe));
4138 udelay(150);
4139
4140 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4141 * This is an exception to the general rule that mode_set doesn't turn
4142 * things on.
4143 */
4144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4145 intel_update_lvds(crtc, clock, adjusted_mode);
4146
4147 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4148 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4149
4150 I915_WRITE(DPLL(pipe), dpll);
4151
4152 /* Wait for the clocks to stabilize. */
4153 POSTING_READ(DPLL(pipe));
4154 udelay(150);
4155
4156 if (INTEL_INFO(dev)->gen >= 4) {
4157 u32 temp = 0;
4158 if (is_sdvo) {
4159 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4160 if (temp > 1)
4161 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4162 else
4163 temp = 0;
4164 }
4165 I915_WRITE(DPLL_MD(pipe), temp);
4166 } else {
4167 /* The pixel multiplier can only be updated once the
4168 * DPLL is enabled and the clocks are stable.
4169 *
4170 * So write it again.
4171 */
4172 I915_WRITE(DPLL(pipe), dpll);
4173 }
4174 }
4175
4176 static void i8xx_update_pll(struct drm_crtc *crtc,
4177 struct drm_display_mode *adjusted_mode,
4178 intel_clock_t *clock,
4179 int num_connectors)
4180 {
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 int pipe = intel_crtc->pipe;
4185 u32 dpll;
4186
4187 dpll = DPLL_VGA_MODE_DIS;
4188
4189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4190 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4191 } else {
4192 if (clock->p1 == 2)
4193 dpll |= PLL_P1_DIVIDE_BY_TWO;
4194 else
4195 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4196 if (clock->p2 == 4)
4197 dpll |= PLL_P2_DIVIDE_BY_4;
4198 }
4199
4200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4201 /* XXX: just matching BIOS for now */
4202 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4203 dpll |= 3;
4204 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4205 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4206 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4207 else
4208 dpll |= PLL_REF_INPUT_DREFCLK;
4209
4210 dpll |= DPLL_VCO_ENABLE;
4211 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4212 POSTING_READ(DPLL(pipe));
4213 udelay(150);
4214
4215 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4216 * This is an exception to the general rule that mode_set doesn't turn
4217 * things on.
4218 */
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4220 intel_update_lvds(crtc, clock, adjusted_mode);
4221
4222 I915_WRITE(DPLL(pipe), dpll);
4223
4224 /* Wait for the clocks to stabilize. */
4225 POSTING_READ(DPLL(pipe));
4226 udelay(150);
4227
4228 /* The pixel multiplier can only be updated once the
4229 * DPLL is enabled and the clocks are stable.
4230 *
4231 * So write it again.
4232 */
4233 I915_WRITE(DPLL(pipe), dpll);
4234 }
4235
4236 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4237 struct drm_display_mode *mode,
4238 struct drm_display_mode *adjusted_mode,
4239 int x, int y,
4240 struct drm_framebuffer *old_fb)
4241 {
4242 struct drm_device *dev = crtc->dev;
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245 int pipe = intel_crtc->pipe;
4246 int plane = intel_crtc->plane;
4247 int refclk, num_connectors = 0;
4248 intel_clock_t clock, reduced_clock;
4249 u32 dspcntr, pipeconf, vsyncshift;
4250 bool ok, has_reduced_clock = false, is_sdvo = false;
4251 bool is_lvds = false, is_tv = false, is_dp = false;
4252 struct intel_encoder *encoder;
4253 const intel_limit_t *limit;
4254 int ret;
4255
4256 for_each_encoder_on_crtc(dev, crtc, encoder) {
4257 switch (encoder->type) {
4258 case INTEL_OUTPUT_LVDS:
4259 is_lvds = true;
4260 break;
4261 case INTEL_OUTPUT_SDVO:
4262 case INTEL_OUTPUT_HDMI:
4263 is_sdvo = true;
4264 if (encoder->needs_tv_clock)
4265 is_tv = true;
4266 break;
4267 case INTEL_OUTPUT_TVOUT:
4268 is_tv = true;
4269 break;
4270 case INTEL_OUTPUT_DISPLAYPORT:
4271 is_dp = true;
4272 break;
4273 }
4274
4275 num_connectors++;
4276 }
4277
4278 refclk = i9xx_get_refclk(crtc, num_connectors);
4279
4280 /*
4281 * Returns a set of divisors for the desired target clock with the given
4282 * refclk, or FALSE. The returned values represent the clock equation:
4283 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4284 */
4285 limit = intel_limit(crtc, refclk);
4286 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4287 &clock);
4288 if (!ok) {
4289 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4290 return -EINVAL;
4291 }
4292
4293 /* Ensure that the cursor is valid for the new mode before changing... */
4294 intel_crtc_update_cursor(crtc, true);
4295
4296 if (is_lvds && dev_priv->lvds_downclock_avail) {
4297 /*
4298 * Ensure we match the reduced clock's P to the target clock.
4299 * If the clocks don't match, we can't switch the display clock
4300 * by using the FP0/FP1. In such case we will disable the LVDS
4301 * downclock feature.
4302 */
4303 has_reduced_clock = limit->find_pll(limit, crtc,
4304 dev_priv->lvds_downclock,
4305 refclk,
4306 &clock,
4307 &reduced_clock);
4308 }
4309
4310 if (is_sdvo && is_tv)
4311 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4312
4313 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4314 &reduced_clock : NULL);
4315
4316 if (IS_GEN2(dev))
4317 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4318 else if (IS_VALLEYVIEW(dev))
4319 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4320 refclk, num_connectors);
4321 else
4322 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4323 has_reduced_clock ? &reduced_clock : NULL,
4324 num_connectors);
4325
4326 /* setup pipeconf */
4327 pipeconf = I915_READ(PIPECONF(pipe));
4328
4329 /* Set up the display plane register */
4330 dspcntr = DISPPLANE_GAMMA_ENABLE;
4331
4332 if (pipe == 0)
4333 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4334 else
4335 dspcntr |= DISPPLANE_SEL_PIPE_B;
4336
4337 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4338 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4339 * core speed.
4340 *
4341 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4342 * pipe == 0 check?
4343 */
4344 if (mode->clock >
4345 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4346 pipeconf |= PIPECONF_DOUBLE_WIDE;
4347 else
4348 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4349 }
4350
4351 /* default to 8bpc */
4352 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4353 if (is_dp) {
4354 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4355 pipeconf |= PIPECONF_BPP_6 |
4356 PIPECONF_DITHER_EN |
4357 PIPECONF_DITHER_TYPE_SP;
4358 }
4359 }
4360
4361 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4362 drm_mode_debug_printmodeline(mode);
4363
4364 if (HAS_PIPE_CXSR(dev)) {
4365 if (intel_crtc->lowfreq_avail) {
4366 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4367 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4368 } else {
4369 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4370 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4371 }
4372 }
4373
4374 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4375 if (!IS_GEN2(dev) &&
4376 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4377 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4378 /* the chip adds 2 halflines automatically */
4379 adjusted_mode->crtc_vtotal -= 1;
4380 adjusted_mode->crtc_vblank_end -= 1;
4381 vsyncshift = adjusted_mode->crtc_hsync_start
4382 - adjusted_mode->crtc_htotal/2;
4383 } else {
4384 pipeconf |= PIPECONF_PROGRESSIVE;
4385 vsyncshift = 0;
4386 }
4387
4388 if (!IS_GEN3(dev))
4389 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4390
4391 I915_WRITE(HTOTAL(pipe),
4392 (adjusted_mode->crtc_hdisplay - 1) |
4393 ((adjusted_mode->crtc_htotal - 1) << 16));
4394 I915_WRITE(HBLANK(pipe),
4395 (adjusted_mode->crtc_hblank_start - 1) |
4396 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4397 I915_WRITE(HSYNC(pipe),
4398 (adjusted_mode->crtc_hsync_start - 1) |
4399 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4400
4401 I915_WRITE(VTOTAL(pipe),
4402 (adjusted_mode->crtc_vdisplay - 1) |
4403 ((adjusted_mode->crtc_vtotal - 1) << 16));
4404 I915_WRITE(VBLANK(pipe),
4405 (adjusted_mode->crtc_vblank_start - 1) |
4406 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4407 I915_WRITE(VSYNC(pipe),
4408 (adjusted_mode->crtc_vsync_start - 1) |
4409 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4410
4411 /* pipesrc and dspsize control the size that is scaled from,
4412 * which should always be the user's requested size.
4413 */
4414 I915_WRITE(DSPSIZE(plane),
4415 ((mode->vdisplay - 1) << 16) |
4416 (mode->hdisplay - 1));
4417 I915_WRITE(DSPPOS(plane), 0);
4418 I915_WRITE(PIPESRC(pipe),
4419 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4420
4421 I915_WRITE(PIPECONF(pipe), pipeconf);
4422 POSTING_READ(PIPECONF(pipe));
4423 intel_enable_pipe(dev_priv, pipe, false);
4424
4425 intel_wait_for_vblank(dev, pipe);
4426
4427 I915_WRITE(DSPCNTR(plane), dspcntr);
4428 POSTING_READ(DSPCNTR(plane));
4429
4430 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4431
4432 intel_update_watermarks(dev);
4433
4434 return ret;
4435 }
4436
4437 /*
4438 * Initialize reference clocks when the driver loads
4439 */
4440 void ironlake_init_pch_refclk(struct drm_device *dev)
4441 {
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 struct drm_mode_config *mode_config = &dev->mode_config;
4444 struct intel_encoder *encoder;
4445 u32 temp;
4446 bool has_lvds = false;
4447 bool has_cpu_edp = false;
4448 bool has_pch_edp = false;
4449 bool has_panel = false;
4450 bool has_ck505 = false;
4451 bool can_ssc = false;
4452
4453 /* We need to take the global config into account */
4454 list_for_each_entry(encoder, &mode_config->encoder_list,
4455 base.head) {
4456 switch (encoder->type) {
4457 case INTEL_OUTPUT_LVDS:
4458 has_panel = true;
4459 has_lvds = true;
4460 break;
4461 case INTEL_OUTPUT_EDP:
4462 has_panel = true;
4463 if (intel_encoder_is_pch_edp(&encoder->base))
4464 has_pch_edp = true;
4465 else
4466 has_cpu_edp = true;
4467 break;
4468 }
4469 }
4470
4471 if (HAS_PCH_IBX(dev)) {
4472 has_ck505 = dev_priv->display_clock_mode;
4473 can_ssc = has_ck505;
4474 } else {
4475 has_ck505 = false;
4476 can_ssc = true;
4477 }
4478
4479 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4480 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4481 has_ck505);
4482
4483 /* Ironlake: try to setup display ref clock before DPLL
4484 * enabling. This is only under driver's control after
4485 * PCH B stepping, previous chipset stepping should be
4486 * ignoring this setting.
4487 */
4488 temp = I915_READ(PCH_DREF_CONTROL);
4489 /* Always enable nonspread source */
4490 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4491
4492 if (has_ck505)
4493 temp |= DREF_NONSPREAD_CK505_ENABLE;
4494 else
4495 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4496
4497 if (has_panel) {
4498 temp &= ~DREF_SSC_SOURCE_MASK;
4499 temp |= DREF_SSC_SOURCE_ENABLE;
4500
4501 /* SSC must be turned on before enabling the CPU output */
4502 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4503 DRM_DEBUG_KMS("Using SSC on panel\n");
4504 temp |= DREF_SSC1_ENABLE;
4505 } else
4506 temp &= ~DREF_SSC1_ENABLE;
4507
4508 /* Get SSC going before enabling the outputs */
4509 I915_WRITE(PCH_DREF_CONTROL, temp);
4510 POSTING_READ(PCH_DREF_CONTROL);
4511 udelay(200);
4512
4513 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4514
4515 /* Enable CPU source on CPU attached eDP */
4516 if (has_cpu_edp) {
4517 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4518 DRM_DEBUG_KMS("Using SSC on eDP\n");
4519 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4520 }
4521 else
4522 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4523 } else
4524 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4525
4526 I915_WRITE(PCH_DREF_CONTROL, temp);
4527 POSTING_READ(PCH_DREF_CONTROL);
4528 udelay(200);
4529 } else {
4530 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4531
4532 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4533
4534 /* Turn off CPU output */
4535 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4536
4537 I915_WRITE(PCH_DREF_CONTROL, temp);
4538 POSTING_READ(PCH_DREF_CONTROL);
4539 udelay(200);
4540
4541 /* Turn off the SSC source */
4542 temp &= ~DREF_SSC_SOURCE_MASK;
4543 temp |= DREF_SSC_SOURCE_DISABLE;
4544
4545 /* Turn off SSC1 */
4546 temp &= ~ DREF_SSC1_ENABLE;
4547
4548 I915_WRITE(PCH_DREF_CONTROL, temp);
4549 POSTING_READ(PCH_DREF_CONTROL);
4550 udelay(200);
4551 }
4552 }
4553
4554 static int ironlake_get_refclk(struct drm_crtc *crtc)
4555 {
4556 struct drm_device *dev = crtc->dev;
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 struct intel_encoder *encoder;
4559 struct intel_encoder *edp_encoder = NULL;
4560 int num_connectors = 0;
4561 bool is_lvds = false;
4562
4563 for_each_encoder_on_crtc(dev, crtc, encoder) {
4564 switch (encoder->type) {
4565 case INTEL_OUTPUT_LVDS:
4566 is_lvds = true;
4567 break;
4568 case INTEL_OUTPUT_EDP:
4569 edp_encoder = encoder;
4570 break;
4571 }
4572 num_connectors++;
4573 }
4574
4575 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4576 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4577 dev_priv->lvds_ssc_freq);
4578 return dev_priv->lvds_ssc_freq * 1000;
4579 }
4580
4581 return 120000;
4582 }
4583
4584 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4585 struct drm_display_mode *mode,
4586 struct drm_display_mode *adjusted_mode,
4587 int x, int y,
4588 struct drm_framebuffer *old_fb)
4589 {
4590 struct drm_device *dev = crtc->dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593 int pipe = intel_crtc->pipe;
4594 int plane = intel_crtc->plane;
4595 int refclk, num_connectors = 0;
4596 intel_clock_t clock, reduced_clock;
4597 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4598 bool ok, has_reduced_clock = false, is_sdvo = false;
4599 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4600 struct intel_encoder *encoder, *edp_encoder = NULL;
4601 const intel_limit_t *limit;
4602 int ret;
4603 struct fdi_m_n m_n = {0};
4604 u32 temp;
4605 int target_clock, pixel_multiplier, lane, link_bw, factor;
4606 unsigned int pipe_bpp;
4607 bool dither;
4608 bool is_cpu_edp = false, is_pch_edp = false;
4609
4610 for_each_encoder_on_crtc(dev, crtc, encoder) {
4611 switch (encoder->type) {
4612 case INTEL_OUTPUT_LVDS:
4613 is_lvds = true;
4614 break;
4615 case INTEL_OUTPUT_SDVO:
4616 case INTEL_OUTPUT_HDMI:
4617 is_sdvo = true;
4618 if (encoder->needs_tv_clock)
4619 is_tv = true;
4620 break;
4621 case INTEL_OUTPUT_TVOUT:
4622 is_tv = true;
4623 break;
4624 case INTEL_OUTPUT_ANALOG:
4625 is_crt = true;
4626 break;
4627 case INTEL_OUTPUT_DISPLAYPORT:
4628 is_dp = true;
4629 break;
4630 case INTEL_OUTPUT_EDP:
4631 is_dp = true;
4632 if (intel_encoder_is_pch_edp(&encoder->base))
4633 is_pch_edp = true;
4634 else
4635 is_cpu_edp = true;
4636 edp_encoder = encoder;
4637 break;
4638 }
4639
4640 num_connectors++;
4641 }
4642
4643 refclk = ironlake_get_refclk(crtc);
4644
4645 /*
4646 * Returns a set of divisors for the desired target clock with the given
4647 * refclk, or FALSE. The returned values represent the clock equation:
4648 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4649 */
4650 limit = intel_limit(crtc, refclk);
4651 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4652 &clock);
4653 if (!ok) {
4654 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4655 return -EINVAL;
4656 }
4657
4658 /* Ensure that the cursor is valid for the new mode before changing... */
4659 intel_crtc_update_cursor(crtc, true);
4660
4661 if (is_lvds && dev_priv->lvds_downclock_avail) {
4662 /*
4663 * Ensure we match the reduced clock's P to the target clock.
4664 * If the clocks don't match, we can't switch the display clock
4665 * by using the FP0/FP1. In such case we will disable the LVDS
4666 * downclock feature.
4667 */
4668 has_reduced_clock = limit->find_pll(limit, crtc,
4669 dev_priv->lvds_downclock,
4670 refclk,
4671 &clock,
4672 &reduced_clock);
4673 }
4674
4675 if (is_sdvo && is_tv)
4676 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4677
4678
4679 /* FDI link */
4680 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4681 lane = 0;
4682 /* CPU eDP doesn't require FDI link, so just set DP M/N
4683 according to current link config */
4684 if (is_cpu_edp) {
4685 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4686 } else {
4687 /* FDI is a binary signal running at ~2.7GHz, encoding
4688 * each output octet as 10 bits. The actual frequency
4689 * is stored as a divider into a 100MHz clock, and the
4690 * mode pixel clock is stored in units of 1KHz.
4691 * Hence the bw of each lane in terms of the mode signal
4692 * is:
4693 */
4694 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4695 }
4696
4697 /* [e]DP over FDI requires target mode clock instead of link clock. */
4698 if (edp_encoder)
4699 target_clock = intel_edp_target_clock(edp_encoder, mode);
4700 else if (is_dp)
4701 target_clock = mode->clock;
4702 else
4703 target_clock = adjusted_mode->clock;
4704
4705 /* determine panel color depth */
4706 temp = I915_READ(PIPECONF(pipe));
4707 temp &= ~PIPE_BPC_MASK;
4708 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
4709 switch (pipe_bpp) {
4710 case 18:
4711 temp |= PIPE_6BPC;
4712 break;
4713 case 24:
4714 temp |= PIPE_8BPC;
4715 break;
4716 case 30:
4717 temp |= PIPE_10BPC;
4718 break;
4719 case 36:
4720 temp |= PIPE_12BPC;
4721 break;
4722 default:
4723 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4724 pipe_bpp);
4725 temp |= PIPE_8BPC;
4726 pipe_bpp = 24;
4727 break;
4728 }
4729
4730 intel_crtc->bpp = pipe_bpp;
4731 I915_WRITE(PIPECONF(pipe), temp);
4732
4733 if (!lane) {
4734 /*
4735 * Account for spread spectrum to avoid
4736 * oversubscribing the link. Max center spread
4737 * is 2.5%; use 5% for safety's sake.
4738 */
4739 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4740 lane = bps / (link_bw * 8) + 1;
4741 }
4742
4743 intel_crtc->fdi_lanes = lane;
4744
4745 if (pixel_multiplier > 1)
4746 link_bw *= pixel_multiplier;
4747 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4748 &m_n);
4749
4750 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4751 if (has_reduced_clock)
4752 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4753 reduced_clock.m2;
4754
4755 /* Enable autotuning of the PLL clock (if permissible) */
4756 factor = 21;
4757 if (is_lvds) {
4758 if ((intel_panel_use_ssc(dev_priv) &&
4759 dev_priv->lvds_ssc_freq == 100) ||
4760 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4761 factor = 25;
4762 } else if (is_sdvo && is_tv)
4763 factor = 20;
4764
4765 if (clock.m < factor * clock.n)
4766 fp |= FP_CB_TUNE;
4767
4768 dpll = 0;
4769
4770 if (is_lvds)
4771 dpll |= DPLLB_MODE_LVDS;
4772 else
4773 dpll |= DPLLB_MODE_DAC_SERIAL;
4774 if (is_sdvo) {
4775 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4776 if (pixel_multiplier > 1) {
4777 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4778 }
4779 dpll |= DPLL_DVO_HIGH_SPEED;
4780 }
4781 if (is_dp && !is_cpu_edp)
4782 dpll |= DPLL_DVO_HIGH_SPEED;
4783
4784 /* compute bitmask from p1 value */
4785 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4786 /* also FPA1 */
4787 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4788
4789 switch (clock.p2) {
4790 case 5:
4791 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4792 break;
4793 case 7:
4794 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4795 break;
4796 case 10:
4797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4798 break;
4799 case 14:
4800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4801 break;
4802 }
4803
4804 if (is_sdvo && is_tv)
4805 dpll |= PLL_REF_INPUT_TVCLKINBC;
4806 else if (is_tv)
4807 /* XXX: just matching BIOS for now */
4808 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4809 dpll |= 3;
4810 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4812 else
4813 dpll |= PLL_REF_INPUT_DREFCLK;
4814
4815 /* setup pipeconf */
4816 pipeconf = I915_READ(PIPECONF(pipe));
4817
4818 /* Set up the display plane register */
4819 dspcntr = DISPPLANE_GAMMA_ENABLE;
4820
4821 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4822 drm_mode_debug_printmodeline(mode);
4823
4824 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4825 * pre-Haswell/LPT generation */
4826 if (HAS_PCH_LPT(dev)) {
4827 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4828 pipe);
4829 } else if (!is_cpu_edp) {
4830 struct intel_pch_pll *pll;
4831
4832 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4833 if (pll == NULL) {
4834 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4835 pipe);
4836 return -EINVAL;
4837 }
4838 } else
4839 intel_put_pch_pll(intel_crtc);
4840
4841 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4842 * This is an exception to the general rule that mode_set doesn't turn
4843 * things on.
4844 */
4845 if (is_lvds) {
4846 temp = I915_READ(PCH_LVDS);
4847 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4848 if (HAS_PCH_CPT(dev)) {
4849 temp &= ~PORT_TRANS_SEL_MASK;
4850 temp |= PORT_TRANS_SEL_CPT(pipe);
4851 } else {
4852 if (pipe == 1)
4853 temp |= LVDS_PIPEB_SELECT;
4854 else
4855 temp &= ~LVDS_PIPEB_SELECT;
4856 }
4857
4858 /* set the corresponsding LVDS_BORDER bit */
4859 temp |= dev_priv->lvds_border_bits;
4860 /* Set the B0-B3 data pairs corresponding to whether we're going to
4861 * set the DPLLs for dual-channel mode or not.
4862 */
4863 if (clock.p2 == 7)
4864 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4865 else
4866 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4867
4868 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4869 * appropriately here, but we need to look more thoroughly into how
4870 * panels behave in the two modes.
4871 */
4872 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4873 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4874 temp |= LVDS_HSYNC_POLARITY;
4875 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4876 temp |= LVDS_VSYNC_POLARITY;
4877 I915_WRITE(PCH_LVDS, temp);
4878 }
4879
4880 pipeconf &= ~PIPECONF_DITHER_EN;
4881 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4882 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4883 pipeconf |= PIPECONF_DITHER_EN;
4884 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4885 }
4886 if (is_dp && !is_cpu_edp) {
4887 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4888 } else {
4889 /* For non-DP output, clear any trans DP clock recovery setting.*/
4890 I915_WRITE(TRANSDATA_M1(pipe), 0);
4891 I915_WRITE(TRANSDATA_N1(pipe), 0);
4892 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4893 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4894 }
4895
4896 if (intel_crtc->pch_pll) {
4897 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4898
4899 /* Wait for the clocks to stabilize. */
4900 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4901 udelay(150);
4902
4903 /* The pixel multiplier can only be updated once the
4904 * DPLL is enabled and the clocks are stable.
4905 *
4906 * So write it again.
4907 */
4908 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4909 }
4910
4911 intel_crtc->lowfreq_avail = false;
4912 if (intel_crtc->pch_pll) {
4913 if (is_lvds && has_reduced_clock && i915_powersave) {
4914 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4915 intel_crtc->lowfreq_avail = true;
4916 } else {
4917 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4918 }
4919 }
4920
4921 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4922 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4923 pipeconf |= PIPECONF_INTERLACED_ILK;
4924 /* the chip adds 2 halflines automatically */
4925 adjusted_mode->crtc_vtotal -= 1;
4926 adjusted_mode->crtc_vblank_end -= 1;
4927 I915_WRITE(VSYNCSHIFT(pipe),
4928 adjusted_mode->crtc_hsync_start
4929 - adjusted_mode->crtc_htotal/2);
4930 } else {
4931 pipeconf |= PIPECONF_PROGRESSIVE;
4932 I915_WRITE(VSYNCSHIFT(pipe), 0);
4933 }
4934
4935 I915_WRITE(HTOTAL(pipe),
4936 (adjusted_mode->crtc_hdisplay - 1) |
4937 ((adjusted_mode->crtc_htotal - 1) << 16));
4938 I915_WRITE(HBLANK(pipe),
4939 (adjusted_mode->crtc_hblank_start - 1) |
4940 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4941 I915_WRITE(HSYNC(pipe),
4942 (adjusted_mode->crtc_hsync_start - 1) |
4943 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4944
4945 I915_WRITE(VTOTAL(pipe),
4946 (adjusted_mode->crtc_vdisplay - 1) |
4947 ((adjusted_mode->crtc_vtotal - 1) << 16));
4948 I915_WRITE(VBLANK(pipe),
4949 (adjusted_mode->crtc_vblank_start - 1) |
4950 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4951 I915_WRITE(VSYNC(pipe),
4952 (adjusted_mode->crtc_vsync_start - 1) |
4953 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4954
4955 /* pipesrc controls the size that is scaled from, which should
4956 * always be the user's requested size.
4957 */
4958 I915_WRITE(PIPESRC(pipe),
4959 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4960
4961 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4962 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4963 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4964 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4965
4966 if (is_cpu_edp)
4967 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4968
4969 I915_WRITE(PIPECONF(pipe), pipeconf);
4970 POSTING_READ(PIPECONF(pipe));
4971
4972 intel_wait_for_vblank(dev, pipe);
4973
4974 I915_WRITE(DSPCNTR(plane), dspcntr);
4975 POSTING_READ(DSPCNTR(plane));
4976
4977 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4978
4979 intel_update_watermarks(dev);
4980
4981 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4982
4983 return ret;
4984 }
4985
4986 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4987 struct drm_display_mode *mode,
4988 struct drm_display_mode *adjusted_mode,
4989 int x, int y,
4990 struct drm_framebuffer *old_fb)
4991 {
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995 int pipe = intel_crtc->pipe;
4996 int ret;
4997
4998 drm_vblank_pre_modeset(dev, pipe);
4999
5000 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5001 x, y, old_fb);
5002 drm_vblank_post_modeset(dev, pipe);
5003
5004 if (ret)
5005 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5006 else
5007 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5008
5009 return ret;
5010 }
5011
5012 static bool intel_eld_uptodate(struct drm_connector *connector,
5013 int reg_eldv, uint32_t bits_eldv,
5014 int reg_elda, uint32_t bits_elda,
5015 int reg_edid)
5016 {
5017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5018 uint8_t *eld = connector->eld;
5019 uint32_t i;
5020
5021 i = I915_READ(reg_eldv);
5022 i &= bits_eldv;
5023
5024 if (!eld[0])
5025 return !i;
5026
5027 if (!i)
5028 return false;
5029
5030 i = I915_READ(reg_elda);
5031 i &= ~bits_elda;
5032 I915_WRITE(reg_elda, i);
5033
5034 for (i = 0; i < eld[2]; i++)
5035 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5036 return false;
5037
5038 return true;
5039 }
5040
5041 static void g4x_write_eld(struct drm_connector *connector,
5042 struct drm_crtc *crtc)
5043 {
5044 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5045 uint8_t *eld = connector->eld;
5046 uint32_t eldv;
5047 uint32_t len;
5048 uint32_t i;
5049
5050 i = I915_READ(G4X_AUD_VID_DID);
5051
5052 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5053 eldv = G4X_ELDV_DEVCL_DEVBLC;
5054 else
5055 eldv = G4X_ELDV_DEVCTG;
5056
5057 if (intel_eld_uptodate(connector,
5058 G4X_AUD_CNTL_ST, eldv,
5059 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5060 G4X_HDMIW_HDMIEDID))
5061 return;
5062
5063 i = I915_READ(G4X_AUD_CNTL_ST);
5064 i &= ~(eldv | G4X_ELD_ADDR);
5065 len = (i >> 9) & 0x1f; /* ELD buffer size */
5066 I915_WRITE(G4X_AUD_CNTL_ST, i);
5067
5068 if (!eld[0])
5069 return;
5070
5071 len = min_t(uint8_t, eld[2], len);
5072 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5073 for (i = 0; i < len; i++)
5074 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5075
5076 i = I915_READ(G4X_AUD_CNTL_ST);
5077 i |= eldv;
5078 I915_WRITE(G4X_AUD_CNTL_ST, i);
5079 }
5080
5081 static void ironlake_write_eld(struct drm_connector *connector,
5082 struct drm_crtc *crtc)
5083 {
5084 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5085 uint8_t *eld = connector->eld;
5086 uint32_t eldv;
5087 uint32_t i;
5088 int len;
5089 int hdmiw_hdmiedid;
5090 int aud_config;
5091 int aud_cntl_st;
5092 int aud_cntrl_st2;
5093
5094 if (HAS_PCH_IBX(connector->dev)) {
5095 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
5096 aud_config = IBX_AUD_CONFIG_A;
5097 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5098 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5099 } else {
5100 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
5101 aud_config = CPT_AUD_CONFIG_A;
5102 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5103 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5104 }
5105
5106 i = to_intel_crtc(crtc)->pipe;
5107 hdmiw_hdmiedid += i * 0x100;
5108 aud_cntl_st += i * 0x100;
5109 aud_config += i * 0x100;
5110
5111 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5112
5113 i = I915_READ(aud_cntl_st);
5114 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5115 if (!i) {
5116 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5117 /* operate blindly on all ports */
5118 eldv = IBX_ELD_VALIDB;
5119 eldv |= IBX_ELD_VALIDB << 4;
5120 eldv |= IBX_ELD_VALIDB << 8;
5121 } else {
5122 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5123 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5124 }
5125
5126 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5127 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5128 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5129 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5130 } else
5131 I915_WRITE(aud_config, 0);
5132
5133 if (intel_eld_uptodate(connector,
5134 aud_cntrl_st2, eldv,
5135 aud_cntl_st, IBX_ELD_ADDRESS,
5136 hdmiw_hdmiedid))
5137 return;
5138
5139 i = I915_READ(aud_cntrl_st2);
5140 i &= ~eldv;
5141 I915_WRITE(aud_cntrl_st2, i);
5142
5143 if (!eld[0])
5144 return;
5145
5146 i = I915_READ(aud_cntl_st);
5147 i &= ~IBX_ELD_ADDRESS;
5148 I915_WRITE(aud_cntl_st, i);
5149
5150 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5151 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5152 for (i = 0; i < len; i++)
5153 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5154
5155 i = I915_READ(aud_cntrl_st2);
5156 i |= eldv;
5157 I915_WRITE(aud_cntrl_st2, i);
5158 }
5159
5160 void intel_write_eld(struct drm_encoder *encoder,
5161 struct drm_display_mode *mode)
5162 {
5163 struct drm_crtc *crtc = encoder->crtc;
5164 struct drm_connector *connector;
5165 struct drm_device *dev = encoder->dev;
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167
5168 connector = drm_select_eld(encoder, mode);
5169 if (!connector)
5170 return;
5171
5172 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5173 connector->base.id,
5174 drm_get_connector_name(connector),
5175 connector->encoder->base.id,
5176 drm_get_encoder_name(connector->encoder));
5177
5178 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5179
5180 if (dev_priv->display.write_eld)
5181 dev_priv->display.write_eld(connector, crtc);
5182 }
5183
5184 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5185 void intel_crtc_load_lut(struct drm_crtc *crtc)
5186 {
5187 struct drm_device *dev = crtc->dev;
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5190 int palreg = PALETTE(intel_crtc->pipe);
5191 int i;
5192
5193 /* The clocks have to be on to load the palette. */
5194 if (!crtc->enabled || !intel_crtc->active)
5195 return;
5196
5197 /* use legacy palette for Ironlake */
5198 if (HAS_PCH_SPLIT(dev))
5199 palreg = LGC_PALETTE(intel_crtc->pipe);
5200
5201 for (i = 0; i < 256; i++) {
5202 I915_WRITE(palreg + 4 * i,
5203 (intel_crtc->lut_r[i] << 16) |
5204 (intel_crtc->lut_g[i] << 8) |
5205 intel_crtc->lut_b[i]);
5206 }
5207 }
5208
5209 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5210 {
5211 struct drm_device *dev = crtc->dev;
5212 struct drm_i915_private *dev_priv = dev->dev_private;
5213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5214 bool visible = base != 0;
5215 u32 cntl;
5216
5217 if (intel_crtc->cursor_visible == visible)
5218 return;
5219
5220 cntl = I915_READ(_CURACNTR);
5221 if (visible) {
5222 /* On these chipsets we can only modify the base whilst
5223 * the cursor is disabled.
5224 */
5225 I915_WRITE(_CURABASE, base);
5226
5227 cntl &= ~(CURSOR_FORMAT_MASK);
5228 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5229 cntl |= CURSOR_ENABLE |
5230 CURSOR_GAMMA_ENABLE |
5231 CURSOR_FORMAT_ARGB;
5232 } else
5233 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5234 I915_WRITE(_CURACNTR, cntl);
5235
5236 intel_crtc->cursor_visible = visible;
5237 }
5238
5239 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5240 {
5241 struct drm_device *dev = crtc->dev;
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5244 int pipe = intel_crtc->pipe;
5245 bool visible = base != 0;
5246
5247 if (intel_crtc->cursor_visible != visible) {
5248 uint32_t cntl = I915_READ(CURCNTR(pipe));
5249 if (base) {
5250 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5251 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5252 cntl |= pipe << 28; /* Connect to correct pipe */
5253 } else {
5254 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5255 cntl |= CURSOR_MODE_DISABLE;
5256 }
5257 I915_WRITE(CURCNTR(pipe), cntl);
5258
5259 intel_crtc->cursor_visible = visible;
5260 }
5261 /* and commit changes on next vblank */
5262 I915_WRITE(CURBASE(pipe), base);
5263 }
5264
5265 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5266 {
5267 struct drm_device *dev = crtc->dev;
5268 struct drm_i915_private *dev_priv = dev->dev_private;
5269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5270 int pipe = intel_crtc->pipe;
5271 bool visible = base != 0;
5272
5273 if (intel_crtc->cursor_visible != visible) {
5274 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5275 if (base) {
5276 cntl &= ~CURSOR_MODE;
5277 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5278 } else {
5279 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5280 cntl |= CURSOR_MODE_DISABLE;
5281 }
5282 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5283
5284 intel_crtc->cursor_visible = visible;
5285 }
5286 /* and commit changes on next vblank */
5287 I915_WRITE(CURBASE_IVB(pipe), base);
5288 }
5289
5290 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5291 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5292 bool on)
5293 {
5294 struct drm_device *dev = crtc->dev;
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297 int pipe = intel_crtc->pipe;
5298 int x = intel_crtc->cursor_x;
5299 int y = intel_crtc->cursor_y;
5300 u32 base, pos;
5301 bool visible;
5302
5303 pos = 0;
5304
5305 if (on && crtc->enabled && crtc->fb) {
5306 base = intel_crtc->cursor_addr;
5307 if (x > (int) crtc->fb->width)
5308 base = 0;
5309
5310 if (y > (int) crtc->fb->height)
5311 base = 0;
5312 } else
5313 base = 0;
5314
5315 if (x < 0) {
5316 if (x + intel_crtc->cursor_width < 0)
5317 base = 0;
5318
5319 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5320 x = -x;
5321 }
5322 pos |= x << CURSOR_X_SHIFT;
5323
5324 if (y < 0) {
5325 if (y + intel_crtc->cursor_height < 0)
5326 base = 0;
5327
5328 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5329 y = -y;
5330 }
5331 pos |= y << CURSOR_Y_SHIFT;
5332
5333 visible = base != 0;
5334 if (!visible && !intel_crtc->cursor_visible)
5335 return;
5336
5337 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5338 I915_WRITE(CURPOS_IVB(pipe), pos);
5339 ivb_update_cursor(crtc, base);
5340 } else {
5341 I915_WRITE(CURPOS(pipe), pos);
5342 if (IS_845G(dev) || IS_I865G(dev))
5343 i845_update_cursor(crtc, base);
5344 else
5345 i9xx_update_cursor(crtc, base);
5346 }
5347 }
5348
5349 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5350 struct drm_file *file,
5351 uint32_t handle,
5352 uint32_t width, uint32_t height)
5353 {
5354 struct drm_device *dev = crtc->dev;
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5357 struct drm_i915_gem_object *obj;
5358 uint32_t addr;
5359 int ret;
5360
5361 DRM_DEBUG_KMS("\n");
5362
5363 /* if we want to turn off the cursor ignore width and height */
5364 if (!handle) {
5365 DRM_DEBUG_KMS("cursor off\n");
5366 addr = 0;
5367 obj = NULL;
5368 mutex_lock(&dev->struct_mutex);
5369 goto finish;
5370 }
5371
5372 /* Currently we only support 64x64 cursors */
5373 if (width != 64 || height != 64) {
5374 DRM_ERROR("we currently only support 64x64 cursors\n");
5375 return -EINVAL;
5376 }
5377
5378 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5379 if (&obj->base == NULL)
5380 return -ENOENT;
5381
5382 if (obj->base.size < width * height * 4) {
5383 DRM_ERROR("buffer is to small\n");
5384 ret = -ENOMEM;
5385 goto fail;
5386 }
5387
5388 /* we only need to pin inside GTT if cursor is non-phy */
5389 mutex_lock(&dev->struct_mutex);
5390 if (!dev_priv->info->cursor_needs_physical) {
5391 if (obj->tiling_mode) {
5392 DRM_ERROR("cursor cannot be tiled\n");
5393 ret = -EINVAL;
5394 goto fail_locked;
5395 }
5396
5397 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5398 if (ret) {
5399 DRM_ERROR("failed to move cursor bo into the GTT\n");
5400 goto fail_locked;
5401 }
5402
5403 ret = i915_gem_object_put_fence(obj);
5404 if (ret) {
5405 DRM_ERROR("failed to release fence for cursor");
5406 goto fail_unpin;
5407 }
5408
5409 addr = obj->gtt_offset;
5410 } else {
5411 int align = IS_I830(dev) ? 16 * 1024 : 256;
5412 ret = i915_gem_attach_phys_object(dev, obj,
5413 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5414 align);
5415 if (ret) {
5416 DRM_ERROR("failed to attach phys object\n");
5417 goto fail_locked;
5418 }
5419 addr = obj->phys_obj->handle->busaddr;
5420 }
5421
5422 if (IS_GEN2(dev))
5423 I915_WRITE(CURSIZE, (height << 12) | width);
5424
5425 finish:
5426 if (intel_crtc->cursor_bo) {
5427 if (dev_priv->info->cursor_needs_physical) {
5428 if (intel_crtc->cursor_bo != obj)
5429 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5430 } else
5431 i915_gem_object_unpin(intel_crtc->cursor_bo);
5432 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5433 }
5434
5435 mutex_unlock(&dev->struct_mutex);
5436
5437 intel_crtc->cursor_addr = addr;
5438 intel_crtc->cursor_bo = obj;
5439 intel_crtc->cursor_width = width;
5440 intel_crtc->cursor_height = height;
5441
5442 intel_crtc_update_cursor(crtc, true);
5443
5444 return 0;
5445 fail_unpin:
5446 i915_gem_object_unpin(obj);
5447 fail_locked:
5448 mutex_unlock(&dev->struct_mutex);
5449 fail:
5450 drm_gem_object_unreference_unlocked(&obj->base);
5451 return ret;
5452 }
5453
5454 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5455 {
5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5457
5458 intel_crtc->cursor_x = x;
5459 intel_crtc->cursor_y = y;
5460
5461 intel_crtc_update_cursor(crtc, true);
5462
5463 return 0;
5464 }
5465
5466 /** Sets the color ramps on behalf of RandR */
5467 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5468 u16 blue, int regno)
5469 {
5470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5471
5472 intel_crtc->lut_r[regno] = red >> 8;
5473 intel_crtc->lut_g[regno] = green >> 8;
5474 intel_crtc->lut_b[regno] = blue >> 8;
5475 }
5476
5477 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5478 u16 *blue, int regno)
5479 {
5480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5481
5482 *red = intel_crtc->lut_r[regno] << 8;
5483 *green = intel_crtc->lut_g[regno] << 8;
5484 *blue = intel_crtc->lut_b[regno] << 8;
5485 }
5486
5487 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5488 u16 *blue, uint32_t start, uint32_t size)
5489 {
5490 int end = (start + size > 256) ? 256 : start + size, i;
5491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5492
5493 for (i = start; i < end; i++) {
5494 intel_crtc->lut_r[i] = red[i] >> 8;
5495 intel_crtc->lut_g[i] = green[i] >> 8;
5496 intel_crtc->lut_b[i] = blue[i] >> 8;
5497 }
5498
5499 intel_crtc_load_lut(crtc);
5500 }
5501
5502 /**
5503 * Get a pipe with a simple mode set on it for doing load-based monitor
5504 * detection.
5505 *
5506 * It will be up to the load-detect code to adjust the pipe as appropriate for
5507 * its requirements. The pipe will be connected to no other encoders.
5508 *
5509 * Currently this code will only succeed if there is a pipe with no encoders
5510 * configured for it. In the future, it could choose to temporarily disable
5511 * some outputs to free up a pipe for its use.
5512 *
5513 * \return crtc, or NULL if no pipes are available.
5514 */
5515
5516 /* VESA 640x480x72Hz mode to set on the pipe */
5517 static struct drm_display_mode load_detect_mode = {
5518 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5519 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5520 };
5521
5522 static struct drm_framebuffer *
5523 intel_framebuffer_create(struct drm_device *dev,
5524 struct drm_mode_fb_cmd2 *mode_cmd,
5525 struct drm_i915_gem_object *obj)
5526 {
5527 struct intel_framebuffer *intel_fb;
5528 int ret;
5529
5530 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5531 if (!intel_fb) {
5532 drm_gem_object_unreference_unlocked(&obj->base);
5533 return ERR_PTR(-ENOMEM);
5534 }
5535
5536 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5537 if (ret) {
5538 drm_gem_object_unreference_unlocked(&obj->base);
5539 kfree(intel_fb);
5540 return ERR_PTR(ret);
5541 }
5542
5543 return &intel_fb->base;
5544 }
5545
5546 static u32
5547 intel_framebuffer_pitch_for_width(int width, int bpp)
5548 {
5549 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5550 return ALIGN(pitch, 64);
5551 }
5552
5553 static u32
5554 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5555 {
5556 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5557 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5558 }
5559
5560 static struct drm_framebuffer *
5561 intel_framebuffer_create_for_mode(struct drm_device *dev,
5562 struct drm_display_mode *mode,
5563 int depth, int bpp)
5564 {
5565 struct drm_i915_gem_object *obj;
5566 struct drm_mode_fb_cmd2 mode_cmd;
5567
5568 obj = i915_gem_alloc_object(dev,
5569 intel_framebuffer_size_for_mode(mode, bpp));
5570 if (obj == NULL)
5571 return ERR_PTR(-ENOMEM);
5572
5573 mode_cmd.width = mode->hdisplay;
5574 mode_cmd.height = mode->vdisplay;
5575 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5576 bpp);
5577 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5578
5579 return intel_framebuffer_create(dev, &mode_cmd, obj);
5580 }
5581
5582 static struct drm_framebuffer *
5583 mode_fits_in_fbdev(struct drm_device *dev,
5584 struct drm_display_mode *mode)
5585 {
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 struct drm_i915_gem_object *obj;
5588 struct drm_framebuffer *fb;
5589
5590 if (dev_priv->fbdev == NULL)
5591 return NULL;
5592
5593 obj = dev_priv->fbdev->ifb.obj;
5594 if (obj == NULL)
5595 return NULL;
5596
5597 fb = &dev_priv->fbdev->ifb.base;
5598 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5599 fb->bits_per_pixel))
5600 return NULL;
5601
5602 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5603 return NULL;
5604
5605 return fb;
5606 }
5607
5608 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5609 struct drm_connector *connector,
5610 struct drm_display_mode *mode,
5611 struct intel_load_detect_pipe *old)
5612 {
5613 struct intel_crtc *intel_crtc;
5614 struct drm_crtc *possible_crtc;
5615 struct drm_encoder *encoder = &intel_encoder->base;
5616 struct drm_crtc *crtc = NULL;
5617 struct drm_device *dev = encoder->dev;
5618 struct drm_framebuffer *old_fb;
5619 int i = -1;
5620
5621 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5622 connector->base.id, drm_get_connector_name(connector),
5623 encoder->base.id, drm_get_encoder_name(encoder));
5624
5625 /*
5626 * Algorithm gets a little messy:
5627 *
5628 * - if the connector already has an assigned crtc, use it (but make
5629 * sure it's on first)
5630 *
5631 * - try to find the first unused crtc that can drive this connector,
5632 * and use that if we find one
5633 */
5634
5635 /* See if we already have a CRTC for this connector */
5636 if (encoder->crtc) {
5637 crtc = encoder->crtc;
5638
5639 intel_crtc = to_intel_crtc(crtc);
5640 old->dpms_mode = intel_crtc->dpms_mode;
5641 old->load_detect_temp = false;
5642
5643 /* Make sure the crtc and connector are running */
5644 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5645 struct drm_encoder_helper_funcs *encoder_funcs;
5646 struct drm_crtc_helper_funcs *crtc_funcs;
5647
5648 crtc_funcs = crtc->helper_private;
5649 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5650
5651 encoder_funcs = encoder->helper_private;
5652 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5653 }
5654
5655 return true;
5656 }
5657
5658 /* Find an unused one (if possible) */
5659 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5660 i++;
5661 if (!(encoder->possible_crtcs & (1 << i)))
5662 continue;
5663 if (!possible_crtc->enabled) {
5664 crtc = possible_crtc;
5665 break;
5666 }
5667 }
5668
5669 /*
5670 * If we didn't find an unused CRTC, don't use any.
5671 */
5672 if (!crtc) {
5673 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5674 return false;
5675 }
5676
5677 encoder->crtc = crtc;
5678 connector->encoder = encoder;
5679
5680 intel_crtc = to_intel_crtc(crtc);
5681 old->dpms_mode = intel_crtc->dpms_mode;
5682 old->load_detect_temp = true;
5683 old->release_fb = NULL;
5684
5685 if (!mode)
5686 mode = &load_detect_mode;
5687
5688 old_fb = crtc->fb;
5689
5690 /* We need a framebuffer large enough to accommodate all accesses
5691 * that the plane may generate whilst we perform load detection.
5692 * We can not rely on the fbcon either being present (we get called
5693 * during its initialisation to detect all boot displays, or it may
5694 * not even exist) or that it is large enough to satisfy the
5695 * requested mode.
5696 */
5697 crtc->fb = mode_fits_in_fbdev(dev, mode);
5698 if (crtc->fb == NULL) {
5699 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5700 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5701 old->release_fb = crtc->fb;
5702 } else
5703 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5704 if (IS_ERR(crtc->fb)) {
5705 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5706 crtc->fb = old_fb;
5707 return false;
5708 }
5709
5710 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5711 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5712 if (old->release_fb)
5713 old->release_fb->funcs->destroy(old->release_fb);
5714 crtc->fb = old_fb;
5715 return false;
5716 }
5717
5718 /* let the connector get through one full cycle before testing */
5719 intel_wait_for_vblank(dev, intel_crtc->pipe);
5720
5721 return true;
5722 }
5723
5724 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5725 struct drm_connector *connector,
5726 struct intel_load_detect_pipe *old)
5727 {
5728 struct drm_encoder *encoder = &intel_encoder->base;
5729 struct drm_device *dev = encoder->dev;
5730 struct drm_crtc *crtc = encoder->crtc;
5731 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5732 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5733
5734 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5735 connector->base.id, drm_get_connector_name(connector),
5736 encoder->base.id, drm_get_encoder_name(encoder));
5737
5738 if (old->load_detect_temp) {
5739 connector->encoder = NULL;
5740 drm_helper_disable_unused_functions(dev);
5741
5742 if (old->release_fb)
5743 old->release_fb->funcs->destroy(old->release_fb);
5744
5745 return;
5746 }
5747
5748 /* Switch crtc and encoder back off if necessary */
5749 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5750 encoder_funcs->dpms(encoder, old->dpms_mode);
5751 crtc_funcs->dpms(crtc, old->dpms_mode);
5752 }
5753 }
5754
5755 /* Returns the clock of the currently programmed mode of the given pipe. */
5756 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5757 {
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 int pipe = intel_crtc->pipe;
5761 u32 dpll = I915_READ(DPLL(pipe));
5762 u32 fp;
5763 intel_clock_t clock;
5764
5765 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5766 fp = I915_READ(FP0(pipe));
5767 else
5768 fp = I915_READ(FP1(pipe));
5769
5770 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5771 if (IS_PINEVIEW(dev)) {
5772 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5773 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5774 } else {
5775 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5776 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5777 }
5778
5779 if (!IS_GEN2(dev)) {
5780 if (IS_PINEVIEW(dev))
5781 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5782 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5783 else
5784 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5785 DPLL_FPA01_P1_POST_DIV_SHIFT);
5786
5787 switch (dpll & DPLL_MODE_MASK) {
5788 case DPLLB_MODE_DAC_SERIAL:
5789 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5790 5 : 10;
5791 break;
5792 case DPLLB_MODE_LVDS:
5793 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5794 7 : 14;
5795 break;
5796 default:
5797 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5798 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5799 return 0;
5800 }
5801
5802 /* XXX: Handle the 100Mhz refclk */
5803 intel_clock(dev, 96000, &clock);
5804 } else {
5805 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5806
5807 if (is_lvds) {
5808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5809 DPLL_FPA01_P1_POST_DIV_SHIFT);
5810 clock.p2 = 14;
5811
5812 if ((dpll & PLL_REF_INPUT_MASK) ==
5813 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5814 /* XXX: might not be 66MHz */
5815 intel_clock(dev, 66000, &clock);
5816 } else
5817 intel_clock(dev, 48000, &clock);
5818 } else {
5819 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5820 clock.p1 = 2;
5821 else {
5822 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5823 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5824 }
5825 if (dpll & PLL_P2_DIVIDE_BY_4)
5826 clock.p2 = 4;
5827 else
5828 clock.p2 = 2;
5829
5830 intel_clock(dev, 48000, &clock);
5831 }
5832 }
5833
5834 /* XXX: It would be nice to validate the clocks, but we can't reuse
5835 * i830PllIsValid() because it relies on the xf86_config connector
5836 * configuration being accurate, which it isn't necessarily.
5837 */
5838
5839 return clock.dot;
5840 }
5841
5842 /** Returns the currently programmed mode of the given pipe. */
5843 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5844 struct drm_crtc *crtc)
5845 {
5846 struct drm_i915_private *dev_priv = dev->dev_private;
5847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848 int pipe = intel_crtc->pipe;
5849 struct drm_display_mode *mode;
5850 int htot = I915_READ(HTOTAL(pipe));
5851 int hsync = I915_READ(HSYNC(pipe));
5852 int vtot = I915_READ(VTOTAL(pipe));
5853 int vsync = I915_READ(VSYNC(pipe));
5854
5855 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5856 if (!mode)
5857 return NULL;
5858
5859 mode->clock = intel_crtc_clock_get(dev, crtc);
5860 mode->hdisplay = (htot & 0xffff) + 1;
5861 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5862 mode->hsync_start = (hsync & 0xffff) + 1;
5863 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5864 mode->vdisplay = (vtot & 0xffff) + 1;
5865 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5866 mode->vsync_start = (vsync & 0xffff) + 1;
5867 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5868
5869 drm_mode_set_name(mode);
5870
5871 return mode;
5872 }
5873
5874 #define GPU_IDLE_TIMEOUT 500 /* ms */
5875
5876 /* When this timer fires, we've been idle for awhile */
5877 static void intel_gpu_idle_timer(unsigned long arg)
5878 {
5879 struct drm_device *dev = (struct drm_device *)arg;
5880 drm_i915_private_t *dev_priv = dev->dev_private;
5881
5882 if (!list_empty(&dev_priv->mm.active_list)) {
5883 /* Still processing requests, so just re-arm the timer. */
5884 mod_timer(&dev_priv->idle_timer, jiffies +
5885 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5886 return;
5887 }
5888
5889 dev_priv->busy = false;
5890 queue_work(dev_priv->wq, &dev_priv->idle_work);
5891 }
5892
5893 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5894
5895 static void intel_crtc_idle_timer(unsigned long arg)
5896 {
5897 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5898 struct drm_crtc *crtc = &intel_crtc->base;
5899 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5900 struct intel_framebuffer *intel_fb;
5901
5902 intel_fb = to_intel_framebuffer(crtc->fb);
5903 if (intel_fb && intel_fb->obj->active) {
5904 /* The framebuffer is still being accessed by the GPU. */
5905 mod_timer(&intel_crtc->idle_timer, jiffies +
5906 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5907 return;
5908 }
5909
5910 intel_crtc->busy = false;
5911 queue_work(dev_priv->wq, &dev_priv->idle_work);
5912 }
5913
5914 static void intel_increase_pllclock(struct drm_crtc *crtc)
5915 {
5916 struct drm_device *dev = crtc->dev;
5917 drm_i915_private_t *dev_priv = dev->dev_private;
5918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5919 int pipe = intel_crtc->pipe;
5920 int dpll_reg = DPLL(pipe);
5921 int dpll;
5922
5923 if (HAS_PCH_SPLIT(dev))
5924 return;
5925
5926 if (!dev_priv->lvds_downclock_avail)
5927 return;
5928
5929 dpll = I915_READ(dpll_reg);
5930 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5931 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5932
5933 assert_panel_unlocked(dev_priv, pipe);
5934
5935 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5936 I915_WRITE(dpll_reg, dpll);
5937 intel_wait_for_vblank(dev, pipe);
5938
5939 dpll = I915_READ(dpll_reg);
5940 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5941 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5942 }
5943
5944 /* Schedule downclock */
5945 mod_timer(&intel_crtc->idle_timer, jiffies +
5946 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5947 }
5948
5949 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5950 {
5951 struct drm_device *dev = crtc->dev;
5952 drm_i915_private_t *dev_priv = dev->dev_private;
5953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5954
5955 if (HAS_PCH_SPLIT(dev))
5956 return;
5957
5958 if (!dev_priv->lvds_downclock_avail)
5959 return;
5960
5961 /*
5962 * Since this is called by a timer, we should never get here in
5963 * the manual case.
5964 */
5965 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5966 int pipe = intel_crtc->pipe;
5967 int dpll_reg = DPLL(pipe);
5968 int dpll;
5969
5970 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5971
5972 assert_panel_unlocked(dev_priv, pipe);
5973
5974 dpll = I915_READ(dpll_reg);
5975 dpll |= DISPLAY_RATE_SELECT_FPA1;
5976 I915_WRITE(dpll_reg, dpll);
5977 intel_wait_for_vblank(dev, pipe);
5978 dpll = I915_READ(dpll_reg);
5979 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5980 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5981 }
5982
5983 }
5984
5985 /**
5986 * intel_idle_update - adjust clocks for idleness
5987 * @work: work struct
5988 *
5989 * Either the GPU or display (or both) went idle. Check the busy status
5990 * here and adjust the CRTC and GPU clocks as necessary.
5991 */
5992 static void intel_idle_update(struct work_struct *work)
5993 {
5994 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5995 idle_work);
5996 struct drm_device *dev = dev_priv->dev;
5997 struct drm_crtc *crtc;
5998 struct intel_crtc *intel_crtc;
5999
6000 if (!i915_powersave)
6001 return;
6002
6003 mutex_lock(&dev->struct_mutex);
6004
6005 i915_update_gfx_val(dev_priv);
6006
6007 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6008 /* Skip inactive CRTCs */
6009 if (!crtc->fb)
6010 continue;
6011
6012 intel_crtc = to_intel_crtc(crtc);
6013 if (!intel_crtc->busy)
6014 intel_decrease_pllclock(crtc);
6015 }
6016
6017
6018 mutex_unlock(&dev->struct_mutex);
6019 }
6020
6021 /**
6022 * intel_mark_busy - mark the GPU and possibly the display busy
6023 * @dev: drm device
6024 * @obj: object we're operating on
6025 *
6026 * Callers can use this function to indicate that the GPU is busy processing
6027 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6028 * buffer), we'll also mark the display as busy, so we know to increase its
6029 * clock frequency.
6030 */
6031 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6032 {
6033 drm_i915_private_t *dev_priv = dev->dev_private;
6034 struct drm_crtc *crtc = NULL;
6035 struct intel_framebuffer *intel_fb;
6036 struct intel_crtc *intel_crtc;
6037
6038 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6039 return;
6040
6041 if (!dev_priv->busy) {
6042 intel_sanitize_pm(dev);
6043 dev_priv->busy = true;
6044 } else
6045 mod_timer(&dev_priv->idle_timer, jiffies +
6046 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6047
6048 if (obj == NULL)
6049 return;
6050
6051 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6052 if (!crtc->fb)
6053 continue;
6054
6055 intel_crtc = to_intel_crtc(crtc);
6056 intel_fb = to_intel_framebuffer(crtc->fb);
6057 if (intel_fb->obj == obj) {
6058 if (!intel_crtc->busy) {
6059 /* Non-busy -> busy, upclock */
6060 intel_increase_pllclock(crtc);
6061 intel_crtc->busy = true;
6062 } else {
6063 /* Busy -> busy, put off timer */
6064 mod_timer(&intel_crtc->idle_timer, jiffies +
6065 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6066 }
6067 }
6068 }
6069 }
6070
6071 static void intel_crtc_destroy(struct drm_crtc *crtc)
6072 {
6073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074 struct drm_device *dev = crtc->dev;
6075 struct intel_unpin_work *work;
6076 unsigned long flags;
6077
6078 spin_lock_irqsave(&dev->event_lock, flags);
6079 work = intel_crtc->unpin_work;
6080 intel_crtc->unpin_work = NULL;
6081 spin_unlock_irqrestore(&dev->event_lock, flags);
6082
6083 if (work) {
6084 cancel_work_sync(&work->work);
6085 kfree(work);
6086 }
6087
6088 drm_crtc_cleanup(crtc);
6089
6090 kfree(intel_crtc);
6091 }
6092
6093 static void intel_unpin_work_fn(struct work_struct *__work)
6094 {
6095 struct intel_unpin_work *work =
6096 container_of(__work, struct intel_unpin_work, work);
6097
6098 mutex_lock(&work->dev->struct_mutex);
6099 intel_unpin_fb_obj(work->old_fb_obj);
6100 drm_gem_object_unreference(&work->pending_flip_obj->base);
6101 drm_gem_object_unreference(&work->old_fb_obj->base);
6102
6103 intel_update_fbc(work->dev);
6104 mutex_unlock(&work->dev->struct_mutex);
6105 kfree(work);
6106 }
6107
6108 static void do_intel_finish_page_flip(struct drm_device *dev,
6109 struct drm_crtc *crtc)
6110 {
6111 drm_i915_private_t *dev_priv = dev->dev_private;
6112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6113 struct intel_unpin_work *work;
6114 struct drm_i915_gem_object *obj;
6115 struct drm_pending_vblank_event *e;
6116 struct timeval tnow, tvbl;
6117 unsigned long flags;
6118
6119 /* Ignore early vblank irqs */
6120 if (intel_crtc == NULL)
6121 return;
6122
6123 do_gettimeofday(&tnow);
6124
6125 spin_lock_irqsave(&dev->event_lock, flags);
6126 work = intel_crtc->unpin_work;
6127 if (work == NULL || !work->pending) {
6128 spin_unlock_irqrestore(&dev->event_lock, flags);
6129 return;
6130 }
6131
6132 intel_crtc->unpin_work = NULL;
6133
6134 if (work->event) {
6135 e = work->event;
6136 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6137
6138 /* Called before vblank count and timestamps have
6139 * been updated for the vblank interval of flip
6140 * completion? Need to increment vblank count and
6141 * add one videorefresh duration to returned timestamp
6142 * to account for this. We assume this happened if we
6143 * get called over 0.9 frame durations after the last
6144 * timestamped vblank.
6145 *
6146 * This calculation can not be used with vrefresh rates
6147 * below 5Hz (10Hz to be on the safe side) without
6148 * promoting to 64 integers.
6149 */
6150 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6151 9 * crtc->framedur_ns) {
6152 e->event.sequence++;
6153 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6154 crtc->framedur_ns);
6155 }
6156
6157 e->event.tv_sec = tvbl.tv_sec;
6158 e->event.tv_usec = tvbl.tv_usec;
6159
6160 list_add_tail(&e->base.link,
6161 &e->base.file_priv->event_list);
6162 wake_up_interruptible(&e->base.file_priv->event_wait);
6163 }
6164
6165 drm_vblank_put(dev, intel_crtc->pipe);
6166
6167 spin_unlock_irqrestore(&dev->event_lock, flags);
6168
6169 obj = work->old_fb_obj;
6170
6171 atomic_clear_mask(1 << intel_crtc->plane,
6172 &obj->pending_flip.counter);
6173
6174 wake_up(&dev_priv->pending_flip_queue);
6175 schedule_work(&work->work);
6176
6177 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6178 }
6179
6180 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6181 {
6182 drm_i915_private_t *dev_priv = dev->dev_private;
6183 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6184
6185 do_intel_finish_page_flip(dev, crtc);
6186 }
6187
6188 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6189 {
6190 drm_i915_private_t *dev_priv = dev->dev_private;
6191 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6192
6193 do_intel_finish_page_flip(dev, crtc);
6194 }
6195
6196 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6197 {
6198 drm_i915_private_t *dev_priv = dev->dev_private;
6199 struct intel_crtc *intel_crtc =
6200 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6201 unsigned long flags;
6202
6203 spin_lock_irqsave(&dev->event_lock, flags);
6204 if (intel_crtc->unpin_work) {
6205 if ((++intel_crtc->unpin_work->pending) > 1)
6206 DRM_ERROR("Prepared flip multiple times\n");
6207 } else {
6208 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6209 }
6210 spin_unlock_irqrestore(&dev->event_lock, flags);
6211 }
6212
6213 static int intel_gen2_queue_flip(struct drm_device *dev,
6214 struct drm_crtc *crtc,
6215 struct drm_framebuffer *fb,
6216 struct drm_i915_gem_object *obj)
6217 {
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6220 u32 flip_mask;
6221 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6222 int ret;
6223
6224 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6225 if (ret)
6226 goto err;
6227
6228 ret = intel_ring_begin(ring, 6);
6229 if (ret)
6230 goto err_unpin;
6231
6232 /* Can't queue multiple flips, so wait for the previous
6233 * one to finish before executing the next.
6234 */
6235 if (intel_crtc->plane)
6236 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6237 else
6238 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6239 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6240 intel_ring_emit(ring, MI_NOOP);
6241 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6242 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6243 intel_ring_emit(ring, fb->pitches[0]);
6244 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6245 intel_ring_emit(ring, 0); /* aux display base address, unused */
6246 intel_ring_advance(ring);
6247 return 0;
6248
6249 err_unpin:
6250 intel_unpin_fb_obj(obj);
6251 err:
6252 return ret;
6253 }
6254
6255 static int intel_gen3_queue_flip(struct drm_device *dev,
6256 struct drm_crtc *crtc,
6257 struct drm_framebuffer *fb,
6258 struct drm_i915_gem_object *obj)
6259 {
6260 struct drm_i915_private *dev_priv = dev->dev_private;
6261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262 u32 flip_mask;
6263 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6264 int ret;
6265
6266 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6267 if (ret)
6268 goto err;
6269
6270 ret = intel_ring_begin(ring, 6);
6271 if (ret)
6272 goto err_unpin;
6273
6274 if (intel_crtc->plane)
6275 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6276 else
6277 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6278 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6279 intel_ring_emit(ring, MI_NOOP);
6280 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6281 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6282 intel_ring_emit(ring, fb->pitches[0]);
6283 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6284 intel_ring_emit(ring, MI_NOOP);
6285
6286 intel_ring_advance(ring);
6287 return 0;
6288
6289 err_unpin:
6290 intel_unpin_fb_obj(obj);
6291 err:
6292 return ret;
6293 }
6294
6295 static int intel_gen4_queue_flip(struct drm_device *dev,
6296 struct drm_crtc *crtc,
6297 struct drm_framebuffer *fb,
6298 struct drm_i915_gem_object *obj)
6299 {
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6302 uint32_t pf, pipesrc;
6303 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6304 int ret;
6305
6306 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6307 if (ret)
6308 goto err;
6309
6310 ret = intel_ring_begin(ring, 4);
6311 if (ret)
6312 goto err_unpin;
6313
6314 /* i965+ uses the linear or tiled offsets from the
6315 * Display Registers (which do not change across a page-flip)
6316 * so we need only reprogram the base address.
6317 */
6318 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6319 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6320 intel_ring_emit(ring, fb->pitches[0]);
6321 intel_ring_emit(ring,
6322 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6323 obj->tiling_mode);
6324
6325 /* XXX Enabling the panel-fitter across page-flip is so far
6326 * untested on non-native modes, so ignore it for now.
6327 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6328 */
6329 pf = 0;
6330 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6331 intel_ring_emit(ring, pf | pipesrc);
6332 intel_ring_advance(ring);
6333 return 0;
6334
6335 err_unpin:
6336 intel_unpin_fb_obj(obj);
6337 err:
6338 return ret;
6339 }
6340
6341 static int intel_gen6_queue_flip(struct drm_device *dev,
6342 struct drm_crtc *crtc,
6343 struct drm_framebuffer *fb,
6344 struct drm_i915_gem_object *obj)
6345 {
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6349 uint32_t pf, pipesrc;
6350 int ret;
6351
6352 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6353 if (ret)
6354 goto err;
6355
6356 ret = intel_ring_begin(ring, 4);
6357 if (ret)
6358 goto err_unpin;
6359
6360 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6361 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6362 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6363 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6364
6365 /* Contrary to the suggestions in the documentation,
6366 * "Enable Panel Fitter" does not seem to be required when page
6367 * flipping with a non-native mode, and worse causes a normal
6368 * modeset to fail.
6369 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6370 */
6371 pf = 0;
6372 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6373 intel_ring_emit(ring, pf | pipesrc);
6374 intel_ring_advance(ring);
6375 return 0;
6376
6377 err_unpin:
6378 intel_unpin_fb_obj(obj);
6379 err:
6380 return ret;
6381 }
6382
6383 /*
6384 * On gen7 we currently use the blit ring because (in early silicon at least)
6385 * the render ring doesn't give us interrpts for page flip completion, which
6386 * means clients will hang after the first flip is queued. Fortunately the
6387 * blit ring generates interrupts properly, so use it instead.
6388 */
6389 static int intel_gen7_queue_flip(struct drm_device *dev,
6390 struct drm_crtc *crtc,
6391 struct drm_framebuffer *fb,
6392 struct drm_i915_gem_object *obj)
6393 {
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6397 uint32_t plane_bit = 0;
6398 int ret;
6399
6400 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6401 if (ret)
6402 goto err;
6403
6404 switch(intel_crtc->plane) {
6405 case PLANE_A:
6406 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6407 break;
6408 case PLANE_B:
6409 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6410 break;
6411 case PLANE_C:
6412 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6413 break;
6414 default:
6415 WARN_ONCE(1, "unknown plane in flip command\n");
6416 ret = -ENODEV;
6417 goto err_unpin;
6418 }
6419
6420 ret = intel_ring_begin(ring, 4);
6421 if (ret)
6422 goto err_unpin;
6423
6424 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6425 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6426 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6427 intel_ring_emit(ring, (MI_NOOP));
6428 intel_ring_advance(ring);
6429 return 0;
6430
6431 err_unpin:
6432 intel_unpin_fb_obj(obj);
6433 err:
6434 return ret;
6435 }
6436
6437 static int intel_default_queue_flip(struct drm_device *dev,
6438 struct drm_crtc *crtc,
6439 struct drm_framebuffer *fb,
6440 struct drm_i915_gem_object *obj)
6441 {
6442 return -ENODEV;
6443 }
6444
6445 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6446 struct drm_framebuffer *fb,
6447 struct drm_pending_vblank_event *event)
6448 {
6449 struct drm_device *dev = crtc->dev;
6450 struct drm_i915_private *dev_priv = dev->dev_private;
6451 struct intel_framebuffer *intel_fb;
6452 struct drm_i915_gem_object *obj;
6453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6454 struct intel_unpin_work *work;
6455 unsigned long flags;
6456 int ret;
6457
6458 /* Can't change pixel format via MI display flips. */
6459 if (fb->pixel_format != crtc->fb->pixel_format)
6460 return -EINVAL;
6461
6462 /*
6463 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6464 * Note that pitch changes could also affect these register.
6465 */
6466 if (INTEL_INFO(dev)->gen > 3 &&
6467 (fb->offsets[0] != crtc->fb->offsets[0] ||
6468 fb->pitches[0] != crtc->fb->pitches[0]))
6469 return -EINVAL;
6470
6471 work = kzalloc(sizeof *work, GFP_KERNEL);
6472 if (work == NULL)
6473 return -ENOMEM;
6474
6475 work->event = event;
6476 work->dev = crtc->dev;
6477 intel_fb = to_intel_framebuffer(crtc->fb);
6478 work->old_fb_obj = intel_fb->obj;
6479 INIT_WORK(&work->work, intel_unpin_work_fn);
6480
6481 ret = drm_vblank_get(dev, intel_crtc->pipe);
6482 if (ret)
6483 goto free_work;
6484
6485 /* We borrow the event spin lock for protecting unpin_work */
6486 spin_lock_irqsave(&dev->event_lock, flags);
6487 if (intel_crtc->unpin_work) {
6488 spin_unlock_irqrestore(&dev->event_lock, flags);
6489 kfree(work);
6490 drm_vblank_put(dev, intel_crtc->pipe);
6491
6492 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6493 return -EBUSY;
6494 }
6495 intel_crtc->unpin_work = work;
6496 spin_unlock_irqrestore(&dev->event_lock, flags);
6497
6498 intel_fb = to_intel_framebuffer(fb);
6499 obj = intel_fb->obj;
6500
6501 ret = i915_mutex_lock_interruptible(dev);
6502 if (ret)
6503 goto cleanup;
6504
6505 /* Reference the objects for the scheduled work. */
6506 drm_gem_object_reference(&work->old_fb_obj->base);
6507 drm_gem_object_reference(&obj->base);
6508
6509 crtc->fb = fb;
6510
6511 work->pending_flip_obj = obj;
6512
6513 work->enable_stall_check = true;
6514
6515 /* Block clients from rendering to the new back buffer until
6516 * the flip occurs and the object is no longer visible.
6517 */
6518 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6519
6520 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6521 if (ret)
6522 goto cleanup_pending;
6523
6524 intel_disable_fbc(dev);
6525 intel_mark_busy(dev, obj);
6526 mutex_unlock(&dev->struct_mutex);
6527
6528 trace_i915_flip_request(intel_crtc->plane, obj);
6529
6530 return 0;
6531
6532 cleanup_pending:
6533 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6534 drm_gem_object_unreference(&work->old_fb_obj->base);
6535 drm_gem_object_unreference(&obj->base);
6536 mutex_unlock(&dev->struct_mutex);
6537
6538 cleanup:
6539 spin_lock_irqsave(&dev->event_lock, flags);
6540 intel_crtc->unpin_work = NULL;
6541 spin_unlock_irqrestore(&dev->event_lock, flags);
6542
6543 drm_vblank_put(dev, intel_crtc->pipe);
6544 free_work:
6545 kfree(work);
6546
6547 return ret;
6548 }
6549
6550 static void intel_sanitize_modesetting(struct drm_device *dev,
6551 int pipe, int plane)
6552 {
6553 struct drm_i915_private *dev_priv = dev->dev_private;
6554 u32 reg, val;
6555 int i;
6556
6557 /* Clear any frame start delays used for debugging left by the BIOS */
6558 for_each_pipe(i) {
6559 reg = PIPECONF(i);
6560 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6561 }
6562
6563 if (HAS_PCH_SPLIT(dev))
6564 return;
6565
6566 /* Who knows what state these registers were left in by the BIOS or
6567 * grub?
6568 *
6569 * If we leave the registers in a conflicting state (e.g. with the
6570 * display plane reading from the other pipe than the one we intend
6571 * to use) then when we attempt to teardown the active mode, we will
6572 * not disable the pipes and planes in the correct order -- leaving
6573 * a plane reading from a disabled pipe and possibly leading to
6574 * undefined behaviour.
6575 */
6576
6577 reg = DSPCNTR(plane);
6578 val = I915_READ(reg);
6579
6580 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6581 return;
6582 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6583 return;
6584
6585 /* This display plane is active and attached to the other CPU pipe. */
6586 pipe = !pipe;
6587
6588 /* Disable the plane and wait for it to stop reading from the pipe. */
6589 intel_disable_plane(dev_priv, plane, pipe);
6590 intel_disable_pipe(dev_priv, pipe);
6591 }
6592
6593 static void intel_crtc_reset(struct drm_crtc *crtc)
6594 {
6595 struct drm_device *dev = crtc->dev;
6596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6597
6598 /* Reset flags back to the 'unknown' status so that they
6599 * will be correctly set on the initial modeset.
6600 */
6601 intel_crtc->dpms_mode = -1;
6602
6603 /* We need to fix up any BIOS configuration that conflicts with
6604 * our expectations.
6605 */
6606 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6607 }
6608
6609 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6610 .dpms = intel_crtc_dpms,
6611 .mode_fixup = intel_crtc_mode_fixup,
6612 .mode_set = intel_crtc_mode_set,
6613 .mode_set_base = intel_pipe_set_base,
6614 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6615 .load_lut = intel_crtc_load_lut,
6616 .disable = intel_crtc_disable,
6617 };
6618
6619 static const struct drm_crtc_funcs intel_crtc_funcs = {
6620 .reset = intel_crtc_reset,
6621 .cursor_set = intel_crtc_cursor_set,
6622 .cursor_move = intel_crtc_cursor_move,
6623 .gamma_set = intel_crtc_gamma_set,
6624 .set_config = drm_crtc_helper_set_config,
6625 .destroy = intel_crtc_destroy,
6626 .page_flip = intel_crtc_page_flip,
6627 };
6628
6629 static void intel_pch_pll_init(struct drm_device *dev)
6630 {
6631 drm_i915_private_t *dev_priv = dev->dev_private;
6632 int i;
6633
6634 if (dev_priv->num_pch_pll == 0) {
6635 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6636 return;
6637 }
6638
6639 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6640 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6641 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6642 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6643 }
6644 }
6645
6646 static void intel_crtc_init(struct drm_device *dev, int pipe)
6647 {
6648 drm_i915_private_t *dev_priv = dev->dev_private;
6649 struct intel_crtc *intel_crtc;
6650 int i;
6651
6652 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6653 if (intel_crtc == NULL)
6654 return;
6655
6656 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6657
6658 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6659 for (i = 0; i < 256; i++) {
6660 intel_crtc->lut_r[i] = i;
6661 intel_crtc->lut_g[i] = i;
6662 intel_crtc->lut_b[i] = i;
6663 }
6664
6665 /* Swap pipes & planes for FBC on pre-965 */
6666 intel_crtc->pipe = pipe;
6667 intel_crtc->plane = pipe;
6668 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6669 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6670 intel_crtc->plane = !pipe;
6671 }
6672
6673 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6674 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6675 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6676 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6677
6678 intel_crtc_reset(&intel_crtc->base);
6679 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6680 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6681
6682 if (HAS_PCH_SPLIT(dev)) {
6683 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6684 intel_helper_funcs.commit = ironlake_crtc_commit;
6685 } else {
6686 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6687 intel_helper_funcs.commit = i9xx_crtc_commit;
6688 }
6689
6690 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6691
6692 intel_crtc->busy = false;
6693
6694 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6695 (unsigned long)intel_crtc);
6696 }
6697
6698 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6699 struct drm_file *file)
6700 {
6701 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6702 struct drm_mode_object *drmmode_obj;
6703 struct intel_crtc *crtc;
6704
6705 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6706 return -ENODEV;
6707
6708 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6709 DRM_MODE_OBJECT_CRTC);
6710
6711 if (!drmmode_obj) {
6712 DRM_ERROR("no such CRTC id\n");
6713 return -EINVAL;
6714 }
6715
6716 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6717 pipe_from_crtc_id->pipe = crtc->pipe;
6718
6719 return 0;
6720 }
6721
6722 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6723 {
6724 struct intel_encoder *encoder;
6725 int index_mask = 0;
6726 int entry = 0;
6727
6728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6729 if (type_mask & encoder->clone_mask)
6730 index_mask |= (1 << entry);
6731 entry++;
6732 }
6733
6734 return index_mask;
6735 }
6736
6737 static bool has_edp_a(struct drm_device *dev)
6738 {
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740
6741 if (!IS_MOBILE(dev))
6742 return false;
6743
6744 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6745 return false;
6746
6747 if (IS_GEN5(dev) &&
6748 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6749 return false;
6750
6751 return true;
6752 }
6753
6754 static void intel_setup_outputs(struct drm_device *dev)
6755 {
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 struct intel_encoder *encoder;
6758 bool dpd_is_edp = false;
6759 bool has_lvds;
6760
6761 has_lvds = intel_lvds_init(dev);
6762 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6763 /* disable the panel fitter on everything but LVDS */
6764 I915_WRITE(PFIT_CONTROL, 0);
6765 }
6766
6767 if (HAS_PCH_SPLIT(dev)) {
6768 dpd_is_edp = intel_dpd_is_edp(dev);
6769
6770 if (has_edp_a(dev))
6771 intel_dp_init(dev, DP_A);
6772
6773 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6774 intel_dp_init(dev, PCH_DP_D);
6775 }
6776
6777 intel_crt_init(dev);
6778
6779 if (IS_HASWELL(dev)) {
6780 int found;
6781
6782 /* Haswell uses DDI functions to detect digital outputs */
6783 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6784 /* DDI A only supports eDP */
6785 if (found)
6786 intel_ddi_init(dev, PORT_A);
6787
6788 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6789 * register */
6790 found = I915_READ(SFUSE_STRAP);
6791
6792 if (found & SFUSE_STRAP_DDIB_DETECTED)
6793 intel_ddi_init(dev, PORT_B);
6794 if (found & SFUSE_STRAP_DDIC_DETECTED)
6795 intel_ddi_init(dev, PORT_C);
6796 if (found & SFUSE_STRAP_DDID_DETECTED)
6797 intel_ddi_init(dev, PORT_D);
6798 } else if (HAS_PCH_SPLIT(dev)) {
6799 int found;
6800
6801 if (I915_READ(HDMIB) & PORT_DETECTED) {
6802 /* PCH SDVOB multiplex with HDMIB */
6803 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6804 if (!found)
6805 intel_hdmi_init(dev, HDMIB);
6806 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6807 intel_dp_init(dev, PCH_DP_B);
6808 }
6809
6810 if (I915_READ(HDMIC) & PORT_DETECTED)
6811 intel_hdmi_init(dev, HDMIC);
6812
6813 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6814 intel_hdmi_init(dev, HDMID);
6815
6816 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6817 intel_dp_init(dev, PCH_DP_C);
6818
6819 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6820 intel_dp_init(dev, PCH_DP_D);
6821 } else if (IS_VALLEYVIEW(dev)) {
6822 int found;
6823
6824 if (I915_READ(SDVOB) & PORT_DETECTED) {
6825 /* SDVOB multiplex with HDMIB */
6826 found = intel_sdvo_init(dev, SDVOB, true);
6827 if (!found)
6828 intel_hdmi_init(dev, SDVOB);
6829 if (!found && (I915_READ(DP_B) & DP_DETECTED))
6830 intel_dp_init(dev, DP_B);
6831 }
6832
6833 if (I915_READ(SDVOC) & PORT_DETECTED)
6834 intel_hdmi_init(dev, SDVOC);
6835
6836 /* Shares lanes with HDMI on SDVOC */
6837 if (I915_READ(DP_C) & DP_DETECTED)
6838 intel_dp_init(dev, DP_C);
6839 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6840 bool found = false;
6841
6842 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6843 DRM_DEBUG_KMS("probing SDVOB\n");
6844 found = intel_sdvo_init(dev, SDVOB, true);
6845 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6846 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6847 intel_hdmi_init(dev, SDVOB);
6848 }
6849
6850 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6851 DRM_DEBUG_KMS("probing DP_B\n");
6852 intel_dp_init(dev, DP_B);
6853 }
6854 }
6855
6856 /* Before G4X SDVOC doesn't have its own detect register */
6857
6858 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6859 DRM_DEBUG_KMS("probing SDVOC\n");
6860 found = intel_sdvo_init(dev, SDVOC, false);
6861 }
6862
6863 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6864
6865 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6866 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6867 intel_hdmi_init(dev, SDVOC);
6868 }
6869 if (SUPPORTS_INTEGRATED_DP(dev)) {
6870 DRM_DEBUG_KMS("probing DP_C\n");
6871 intel_dp_init(dev, DP_C);
6872 }
6873 }
6874
6875 if (SUPPORTS_INTEGRATED_DP(dev) &&
6876 (I915_READ(DP_D) & DP_DETECTED)) {
6877 DRM_DEBUG_KMS("probing DP_D\n");
6878 intel_dp_init(dev, DP_D);
6879 }
6880 } else if (IS_GEN2(dev))
6881 intel_dvo_init(dev);
6882
6883 if (SUPPORTS_TV(dev))
6884 intel_tv_init(dev);
6885
6886 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6887 encoder->base.possible_crtcs = encoder->crtc_mask;
6888 encoder->base.possible_clones =
6889 intel_encoder_clones(dev, encoder->clone_mask);
6890 }
6891
6892 /* disable all the possible outputs/crtcs before entering KMS mode */
6893 drm_helper_disable_unused_functions(dev);
6894
6895 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6896 ironlake_init_pch_refclk(dev);
6897 }
6898
6899 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6900 {
6901 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6902
6903 drm_framebuffer_cleanup(fb);
6904 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6905
6906 kfree(intel_fb);
6907 }
6908
6909 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6910 struct drm_file *file,
6911 unsigned int *handle)
6912 {
6913 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6914 struct drm_i915_gem_object *obj = intel_fb->obj;
6915
6916 return drm_gem_handle_create(file, &obj->base, handle);
6917 }
6918
6919 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6920 .destroy = intel_user_framebuffer_destroy,
6921 .create_handle = intel_user_framebuffer_create_handle,
6922 };
6923
6924 int intel_framebuffer_init(struct drm_device *dev,
6925 struct intel_framebuffer *intel_fb,
6926 struct drm_mode_fb_cmd2 *mode_cmd,
6927 struct drm_i915_gem_object *obj)
6928 {
6929 int ret;
6930
6931 if (obj->tiling_mode == I915_TILING_Y)
6932 return -EINVAL;
6933
6934 if (mode_cmd->pitches[0] & 63)
6935 return -EINVAL;
6936
6937 switch (mode_cmd->pixel_format) {
6938 case DRM_FORMAT_RGB332:
6939 case DRM_FORMAT_RGB565:
6940 case DRM_FORMAT_XRGB8888:
6941 case DRM_FORMAT_XBGR8888:
6942 case DRM_FORMAT_ARGB8888:
6943 case DRM_FORMAT_XRGB2101010:
6944 case DRM_FORMAT_ARGB2101010:
6945 /* RGB formats are common across chipsets */
6946 break;
6947 case DRM_FORMAT_YUYV:
6948 case DRM_FORMAT_UYVY:
6949 case DRM_FORMAT_YVYU:
6950 case DRM_FORMAT_VYUY:
6951 break;
6952 default:
6953 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6954 mode_cmd->pixel_format);
6955 return -EINVAL;
6956 }
6957
6958 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6959 if (ret) {
6960 DRM_ERROR("framebuffer init failed %d\n", ret);
6961 return ret;
6962 }
6963
6964 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6965 intel_fb->obj = obj;
6966 return 0;
6967 }
6968
6969 static struct drm_framebuffer *
6970 intel_user_framebuffer_create(struct drm_device *dev,
6971 struct drm_file *filp,
6972 struct drm_mode_fb_cmd2 *mode_cmd)
6973 {
6974 struct drm_i915_gem_object *obj;
6975
6976 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6977 mode_cmd->handles[0]));
6978 if (&obj->base == NULL)
6979 return ERR_PTR(-ENOENT);
6980
6981 return intel_framebuffer_create(dev, mode_cmd, obj);
6982 }
6983
6984 static const struct drm_mode_config_funcs intel_mode_funcs = {
6985 .fb_create = intel_user_framebuffer_create,
6986 .output_poll_changed = intel_fb_output_poll_changed,
6987 };
6988
6989 /* Set up chip specific display functions */
6990 static void intel_init_display(struct drm_device *dev)
6991 {
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993
6994 /* We always want a DPMS function */
6995 if (HAS_PCH_SPLIT(dev)) {
6996 dev_priv->display.dpms = ironlake_crtc_dpms;
6997 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6998 dev_priv->display.off = ironlake_crtc_off;
6999 dev_priv->display.update_plane = ironlake_update_plane;
7000 } else {
7001 dev_priv->display.dpms = i9xx_crtc_dpms;
7002 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7003 dev_priv->display.off = i9xx_crtc_off;
7004 dev_priv->display.update_plane = i9xx_update_plane;
7005 }
7006
7007 /* Returns the core display clock speed */
7008 if (IS_VALLEYVIEW(dev))
7009 dev_priv->display.get_display_clock_speed =
7010 valleyview_get_display_clock_speed;
7011 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7012 dev_priv->display.get_display_clock_speed =
7013 i945_get_display_clock_speed;
7014 else if (IS_I915G(dev))
7015 dev_priv->display.get_display_clock_speed =
7016 i915_get_display_clock_speed;
7017 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7018 dev_priv->display.get_display_clock_speed =
7019 i9xx_misc_get_display_clock_speed;
7020 else if (IS_I915GM(dev))
7021 dev_priv->display.get_display_clock_speed =
7022 i915gm_get_display_clock_speed;
7023 else if (IS_I865G(dev))
7024 dev_priv->display.get_display_clock_speed =
7025 i865_get_display_clock_speed;
7026 else if (IS_I85X(dev))
7027 dev_priv->display.get_display_clock_speed =
7028 i855_get_display_clock_speed;
7029 else /* 852, 830 */
7030 dev_priv->display.get_display_clock_speed =
7031 i830_get_display_clock_speed;
7032
7033 if (HAS_PCH_SPLIT(dev)) {
7034 if (IS_GEN5(dev)) {
7035 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7036 dev_priv->display.write_eld = ironlake_write_eld;
7037 } else if (IS_GEN6(dev)) {
7038 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7039 dev_priv->display.write_eld = ironlake_write_eld;
7040 } else if (IS_IVYBRIDGE(dev)) {
7041 /* FIXME: detect B0+ stepping and use auto training */
7042 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7043 dev_priv->display.write_eld = ironlake_write_eld;
7044 } else if (IS_HASWELL(dev)) {
7045 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7046 dev_priv->display.write_eld = ironlake_write_eld;
7047 } else
7048 dev_priv->display.update_wm = NULL;
7049 } else if (IS_G4X(dev)) {
7050 dev_priv->display.write_eld = g4x_write_eld;
7051 }
7052
7053 /* Default just returns -ENODEV to indicate unsupported */
7054 dev_priv->display.queue_flip = intel_default_queue_flip;
7055
7056 switch (INTEL_INFO(dev)->gen) {
7057 case 2:
7058 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7059 break;
7060
7061 case 3:
7062 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7063 break;
7064
7065 case 4:
7066 case 5:
7067 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7068 break;
7069
7070 case 6:
7071 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7072 break;
7073 case 7:
7074 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7075 break;
7076 }
7077 }
7078
7079 /*
7080 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7081 * resume, or other times. This quirk makes sure that's the case for
7082 * affected systems.
7083 */
7084 static void quirk_pipea_force(struct drm_device *dev)
7085 {
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087
7088 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7089 DRM_INFO("applying pipe a force quirk\n");
7090 }
7091
7092 /*
7093 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7094 */
7095 static void quirk_ssc_force_disable(struct drm_device *dev)
7096 {
7097 struct drm_i915_private *dev_priv = dev->dev_private;
7098 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7099 DRM_INFO("applying lvds SSC disable quirk\n");
7100 }
7101
7102 /*
7103 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7104 * brightness value
7105 */
7106 static void quirk_invert_brightness(struct drm_device *dev)
7107 {
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7110 DRM_INFO("applying inverted panel brightness quirk\n");
7111 }
7112
7113 struct intel_quirk {
7114 int device;
7115 int subsystem_vendor;
7116 int subsystem_device;
7117 void (*hook)(struct drm_device *dev);
7118 };
7119
7120 static struct intel_quirk intel_quirks[] = {
7121 /* HP Mini needs pipe A force quirk (LP: #322104) */
7122 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7123
7124 /* Thinkpad R31 needs pipe A force quirk */
7125 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7126 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7127 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7128
7129 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7130 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7131 /* ThinkPad X40 needs pipe A force quirk */
7132
7133 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7134 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7135
7136 /* 855 & before need to leave pipe A & dpll A up */
7137 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7138 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7139
7140 /* Lenovo U160 cannot use SSC on LVDS */
7141 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7142
7143 /* Sony Vaio Y cannot use SSC on LVDS */
7144 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7145
7146 /* Acer Aspire 5734Z must invert backlight brightness */
7147 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7148 };
7149
7150 static void intel_init_quirks(struct drm_device *dev)
7151 {
7152 struct pci_dev *d = dev->pdev;
7153 int i;
7154
7155 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7156 struct intel_quirk *q = &intel_quirks[i];
7157
7158 if (d->device == q->device &&
7159 (d->subsystem_vendor == q->subsystem_vendor ||
7160 q->subsystem_vendor == PCI_ANY_ID) &&
7161 (d->subsystem_device == q->subsystem_device ||
7162 q->subsystem_device == PCI_ANY_ID))
7163 q->hook(dev);
7164 }
7165 }
7166
7167 /* Disable the VGA plane that we never use */
7168 static void i915_disable_vga(struct drm_device *dev)
7169 {
7170 struct drm_i915_private *dev_priv = dev->dev_private;
7171 u8 sr1;
7172 u32 vga_reg;
7173
7174 if (HAS_PCH_SPLIT(dev))
7175 vga_reg = CPU_VGACNTRL;
7176 else
7177 vga_reg = VGACNTRL;
7178
7179 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7180 outb(SR01, VGA_SR_INDEX);
7181 sr1 = inb(VGA_SR_DATA);
7182 outb(sr1 | 1<<5, VGA_SR_DATA);
7183 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7184 udelay(300);
7185
7186 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7187 POSTING_READ(vga_reg);
7188 }
7189
7190 void intel_modeset_init_hw(struct drm_device *dev)
7191 {
7192 /* We attempt to init the necessary power wells early in the initialization
7193 * time, so the subsystems that expect power to be enabled can work.
7194 */
7195 intel_init_power_wells(dev);
7196
7197 intel_prepare_ddi(dev);
7198
7199 intel_init_clock_gating(dev);
7200
7201 mutex_lock(&dev->struct_mutex);
7202 intel_enable_gt_powersave(dev);
7203 mutex_unlock(&dev->struct_mutex);
7204 }
7205
7206 void intel_modeset_init(struct drm_device *dev)
7207 {
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 int i, ret;
7210
7211 drm_mode_config_init(dev);
7212
7213 dev->mode_config.min_width = 0;
7214 dev->mode_config.min_height = 0;
7215
7216 dev->mode_config.preferred_depth = 24;
7217 dev->mode_config.prefer_shadow = 1;
7218
7219 dev->mode_config.funcs = &intel_mode_funcs;
7220
7221 intel_init_quirks(dev);
7222
7223 intel_init_pm(dev);
7224
7225 intel_init_display(dev);
7226
7227 if (IS_GEN2(dev)) {
7228 dev->mode_config.max_width = 2048;
7229 dev->mode_config.max_height = 2048;
7230 } else if (IS_GEN3(dev)) {
7231 dev->mode_config.max_width = 4096;
7232 dev->mode_config.max_height = 4096;
7233 } else {
7234 dev->mode_config.max_width = 8192;
7235 dev->mode_config.max_height = 8192;
7236 }
7237 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7238
7239 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7240 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7241
7242 for (i = 0; i < dev_priv->num_pipe; i++) {
7243 intel_crtc_init(dev, i);
7244 ret = intel_plane_init(dev, i);
7245 if (ret)
7246 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7247 }
7248
7249 intel_pch_pll_init(dev);
7250
7251 /* Just disable it once at startup */
7252 i915_disable_vga(dev);
7253 intel_setup_outputs(dev);
7254
7255 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7256 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7257 (unsigned long)dev);
7258 }
7259
7260 void intel_modeset_gem_init(struct drm_device *dev)
7261 {
7262 intel_modeset_init_hw(dev);
7263
7264 intel_setup_overlay(dev);
7265 }
7266
7267 void intel_modeset_cleanup(struct drm_device *dev)
7268 {
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 struct drm_crtc *crtc;
7271 struct intel_crtc *intel_crtc;
7272
7273 drm_kms_helper_poll_fini(dev);
7274 mutex_lock(&dev->struct_mutex);
7275
7276 intel_unregister_dsm_handler();
7277
7278
7279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7280 /* Skip inactive CRTCs */
7281 if (!crtc->fb)
7282 continue;
7283
7284 intel_crtc = to_intel_crtc(crtc);
7285 intel_increase_pllclock(crtc);
7286 }
7287
7288 intel_disable_fbc(dev);
7289
7290 intel_disable_gt_powersave(dev);
7291
7292 ironlake_teardown_rc6(dev);
7293
7294 if (IS_VALLEYVIEW(dev))
7295 vlv_init_dpio(dev);
7296
7297 mutex_unlock(&dev->struct_mutex);
7298
7299 /* Disable the irq before mode object teardown, for the irq might
7300 * enqueue unpin/hotplug work. */
7301 drm_irq_uninstall(dev);
7302 cancel_work_sync(&dev_priv->hotplug_work);
7303 cancel_work_sync(&dev_priv->rps_work);
7304
7305 /* flush any delayed tasks or pending work */
7306 flush_scheduled_work();
7307
7308 /* Shut off idle work before the crtcs get freed. */
7309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7310 intel_crtc = to_intel_crtc(crtc);
7311 del_timer_sync(&intel_crtc->idle_timer);
7312 }
7313 del_timer_sync(&dev_priv->idle_timer);
7314 cancel_work_sync(&dev_priv->idle_work);
7315
7316 drm_mode_config_cleanup(dev);
7317 }
7318
7319 /*
7320 * Return which encoder is currently attached for connector.
7321 */
7322 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7323 {
7324 return &intel_attached_encoder(connector)->base;
7325 }
7326
7327 void intel_connector_attach_encoder(struct intel_connector *connector,
7328 struct intel_encoder *encoder)
7329 {
7330 connector->encoder = encoder;
7331 drm_mode_connector_attach_encoder(&connector->base,
7332 &encoder->base);
7333 }
7334
7335 /*
7336 * set vga decode state - true == enable VGA decode
7337 */
7338 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7339 {
7340 struct drm_i915_private *dev_priv = dev->dev_private;
7341 u16 gmch_ctrl;
7342
7343 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7344 if (state)
7345 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7346 else
7347 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7348 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7349 return 0;
7350 }
7351
7352 #ifdef CONFIG_DEBUG_FS
7353 #include <linux/seq_file.h>
7354
7355 struct intel_display_error_state {
7356 struct intel_cursor_error_state {
7357 u32 control;
7358 u32 position;
7359 u32 base;
7360 u32 size;
7361 } cursor[2];
7362
7363 struct intel_pipe_error_state {
7364 u32 conf;
7365 u32 source;
7366
7367 u32 htotal;
7368 u32 hblank;
7369 u32 hsync;
7370 u32 vtotal;
7371 u32 vblank;
7372 u32 vsync;
7373 } pipe[2];
7374
7375 struct intel_plane_error_state {
7376 u32 control;
7377 u32 stride;
7378 u32 size;
7379 u32 pos;
7380 u32 addr;
7381 u32 surface;
7382 u32 tile_offset;
7383 } plane[2];
7384 };
7385
7386 struct intel_display_error_state *
7387 intel_display_capture_error_state(struct drm_device *dev)
7388 {
7389 drm_i915_private_t *dev_priv = dev->dev_private;
7390 struct intel_display_error_state *error;
7391 int i;
7392
7393 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7394 if (error == NULL)
7395 return NULL;
7396
7397 for (i = 0; i < 2; i++) {
7398 error->cursor[i].control = I915_READ(CURCNTR(i));
7399 error->cursor[i].position = I915_READ(CURPOS(i));
7400 error->cursor[i].base = I915_READ(CURBASE(i));
7401
7402 error->plane[i].control = I915_READ(DSPCNTR(i));
7403 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7404 error->plane[i].size = I915_READ(DSPSIZE(i));
7405 error->plane[i].pos = I915_READ(DSPPOS(i));
7406 error->plane[i].addr = I915_READ(DSPADDR(i));
7407 if (INTEL_INFO(dev)->gen >= 4) {
7408 error->plane[i].surface = I915_READ(DSPSURF(i));
7409 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7410 }
7411
7412 error->pipe[i].conf = I915_READ(PIPECONF(i));
7413 error->pipe[i].source = I915_READ(PIPESRC(i));
7414 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7415 error->pipe[i].hblank = I915_READ(HBLANK(i));
7416 error->pipe[i].hsync = I915_READ(HSYNC(i));
7417 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7418 error->pipe[i].vblank = I915_READ(VBLANK(i));
7419 error->pipe[i].vsync = I915_READ(VSYNC(i));
7420 }
7421
7422 return error;
7423 }
7424
7425 void
7426 intel_display_print_error_state(struct seq_file *m,
7427 struct drm_device *dev,
7428 struct intel_display_error_state *error)
7429 {
7430 int i;
7431
7432 for (i = 0; i < 2; i++) {
7433 seq_printf(m, "Pipe [%d]:\n", i);
7434 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7435 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7436 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7437 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7438 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7439 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7440 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7441 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7442
7443 seq_printf(m, "Plane [%d]:\n", i);
7444 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7445 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7446 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7447 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7448 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7449 if (INTEL_INFO(dev)->gen >= 4) {
7450 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7451 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7452 }
7453
7454 seq_printf(m, "Cursor [%d]:\n", i);
7455 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7456 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7457 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7458 }
7459 }
7460 #endif
Linux ARM platform port for MOXA ART SoC