drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_crtc.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 static void
  41 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  42 {
  43         struct drm_device *dev = intel_hdmi->base.base.dev;
  44         struct drm_i915_private *dev_priv = dev->dev_private;
  45         uint32_t enabled_bits;
  46
  47         enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  48
  49         WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  50              "HDMI port enabled, expecting disabled\n");
  51 }
  52
  53 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  54 {
  55         return container_of(encoder, struct intel_hdmi, base.base);
  56 }
  57
  58 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  59 {
  60         return container_of(intel_attached_encoder(connector),
  61                             struct intel_hdmi, base);
  62 }
  63
  64 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  65 {
  66         uint8_t *data = (uint8_t *)frame;
  67         uint8_t sum = 0;
  68         unsigned i;
  69
  70         frame->checksum = 0;
  71         frame->ecc = 0;
  72
  73         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  74                 sum += data[i];
  75
  76         frame->checksum = 0x100 - sum;
  77 }
  78
  79 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  80 {
  81         switch (frame->type) {
  82         case DIP_TYPE_AVI:
  83                 return VIDEO_DIP_SELECT_AVI;
  84         case DIP_TYPE_SPD:
  85                 return VIDEO_DIP_SELECT_SPD;
  86         default:
  87                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  88                 return 0;
  89         }
  90 }
  91
  92 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  93 {
  94         switch (frame->type) {
  95         case DIP_TYPE_AVI:
  96                 return VIDEO_DIP_ENABLE_AVI;
  97         case DIP_TYPE_SPD:
  98                 return VIDEO_DIP_ENABLE_SPD;
  99         default:
 100                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 101                 return 0;
 102         }
 103 }
 104
 105 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 106 {
 107         switch (frame->type) {
 108         case DIP_TYPE_AVI:
 109                 return VIDEO_DIP_ENABLE_AVI_HSW;
 110         case DIP_TYPE_SPD:
 111                 return VIDEO_DIP_ENABLE_SPD_HSW;
 112         default:
 113                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 114                 return 0;
 115         }
 116 }
 117
 118 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
 119 {
 120         switch (frame->type) {
 121         case DIP_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
 123         case DIP_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 127                 return 0;
 128         }
 129 }
 130
 131 static void g4x_write_infoframe(struct drm_encoder *encoder,
 132                                 struct dip_infoframe *frame)
 133 {
 134         uint32_t *data = (uint32_t *)frame;
 135         struct drm_device *dev = encoder->dev;
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         u32 val = I915_READ(VIDEO_DIP_CTL);
 138         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 139
 140         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 141
 142         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 143         val |= g4x_infoframe_index(frame);
 144
 145         val &= ~g4x_infoframe_enable(frame);
 146
 147         I915_WRITE(VIDEO_DIP_CTL, val);
 148
 149         mmiowb();
 150         for (i = 0; i < len; i += 4) {
 151                 I915_WRITE(VIDEO_DIP_DATA, *data);
 152                 data++;
 153         }
 154         /* Write every possible data byte to force correct ECC calculation. */
 155         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 156                 I915_WRITE(VIDEO_DIP_DATA, 0);
 157         mmiowb();
 158
 159         val |= g4x_infoframe_enable(frame);
 160         val &= ~VIDEO_DIP_FREQ_MASK;
 161         val |= VIDEO_DIP_FREQ_VSYNC;
 162
 163         I915_WRITE(VIDEO_DIP_CTL, val);
 164         POSTING_READ(VIDEO_DIP_CTL);
 165 }
 166
 167 static void ibx_write_infoframe(struct drm_encoder *encoder,
 168                                 struct dip_infoframe *frame)
 169 {
 170         uint32_t *data = (uint32_t *)frame;
 171         struct drm_device *dev = encoder->dev;
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 174         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 175         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 176         u32 val = I915_READ(reg);
 177
 178         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 179
 180         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 181         val |= g4x_infoframe_index(frame);
 182
 183         val &= ~g4x_infoframe_enable(frame);
 184
 185         I915_WRITE(reg, val);
 186
 187         mmiowb();
 188         for (i = 0; i < len; i += 4) {
 189                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 190                 data++;
 191         }
 192         /* Write every possible data byte to force correct ECC calculation. */
 193         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 194                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 195         mmiowb();
 196
 197         val |= g4x_infoframe_enable(frame);
 198         val &= ~VIDEO_DIP_FREQ_MASK;
 199         val |= VIDEO_DIP_FREQ_VSYNC;
 200
 201         I915_WRITE(reg, val);
 202         POSTING_READ(reg);
 203 }
 204
 205 static void cpt_write_infoframe(struct drm_encoder *encoder,
 206                                 struct dip_infoframe *frame)
 207 {
 208         uint32_t *data = (uint32_t *)frame;
 209         struct drm_device *dev = encoder->dev;
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 212         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 213         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 214         u32 val = I915_READ(reg);
 215
 216         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 217
 218         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 219         val |= g4x_infoframe_index(frame);
 220
 221         /* The DIP control register spec says that we need to update the AVI
 222          * infoframe without clearing its enable bit */
 223         if (frame->type != DIP_TYPE_AVI)
 224                 val &= ~g4x_infoframe_enable(frame);
 225
 226         I915_WRITE(reg, val);
 227
 228         mmiowb();
 229         for (i = 0; i < len; i += 4) {
 230                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 231                 data++;
 232         }
 233         /* Write every possible data byte to force correct ECC calculation. */
 234         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 236         mmiowb();
 237
 238         val |= g4x_infoframe_enable(frame);
 239         val &= ~VIDEO_DIP_FREQ_MASK;
 240         val |= VIDEO_DIP_FREQ_VSYNC;
 241
 242         I915_WRITE(reg, val);
 243         POSTING_READ(reg);
 244 }
 245
 246 static void vlv_write_infoframe(struct drm_encoder *encoder,
 247                                      struct dip_infoframe *frame)
 248 {
 249         uint32_t *data = (uint32_t *)frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 253         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 254         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 255         u32 val = I915_READ(reg);
 256
 257         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 258
 259         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 260         val |= g4x_infoframe_index(frame);
 261
 262         val &= ~g4x_infoframe_enable(frame);
 263
 264         I915_WRITE(reg, val);
 265
 266         mmiowb();
 267         for (i = 0; i < len; i += 4) {
 268                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 269                 data++;
 270         }
 271         /* Write every possible data byte to force correct ECC calculation. */
 272         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 273                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 274         mmiowb();
 275
 276         val |= g4x_infoframe_enable(frame);
 277         val &= ~VIDEO_DIP_FREQ_MASK;
 278         val |= VIDEO_DIP_FREQ_VSYNC;
 279
 280         I915_WRITE(reg, val);
 281         POSTING_READ(reg);
 282 }
 283
 284 static void hsw_write_infoframe(struct drm_encoder *encoder,
 285                                 struct dip_infoframe *frame)
 286 {
 287         uint32_t *data = (uint32_t *)frame;
 288         struct drm_device *dev = encoder->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 291         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 292         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
 293         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 294         u32 val = I915_READ(ctl_reg);
 295
 296         if (data_reg == 0)
 297                 return;
 298
 299         val &= ~hsw_infoframe_enable(frame);
 300         I915_WRITE(ctl_reg, val);
 301
 302         mmiowb();
 303         for (i = 0; i < len; i += 4) {
 304                 I915_WRITE(data_reg + i, *data);
 305                 data++;
 306         }
 307         /* Write every possible data byte to force correct ECC calculation. */
 308         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 309                 I915_WRITE(data_reg + i, 0);
 310         mmiowb();
 311
 312         val |= hsw_infoframe_enable(frame);
 313         I915_WRITE(ctl_reg, val);
 314         POSTING_READ(ctl_reg);
 315 }
 316
 317 static void intel_set_infoframe(struct drm_encoder *encoder,
 318                                 struct dip_infoframe *frame)
 319 {
 320         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 321
 322         intel_dip_infoframe_csum(frame);
 323         intel_hdmi->write_infoframe(encoder, frame);
 324 }
 325
 326 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 327                                          struct drm_display_mode *adjusted_mode)
 328 {
 329         struct dip_infoframe avi_if = {
 330                 .type = DIP_TYPE_AVI,
 331                 .ver = DIP_VERSION_AVI,
 332                 .len = DIP_LEN_AVI,
 333         };
 334
 335         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 336                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 337
 338         intel_set_infoframe(encoder, &avi_if);
 339 }
 340
 341 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 342 {
 343         struct dip_infoframe spd_if;
 344
 345         memset(&spd_if, 0, sizeof(spd_if));
 346         spd_if.type = DIP_TYPE_SPD;
 347         spd_if.ver = DIP_VERSION_SPD;
 348         spd_if.len = DIP_LEN_SPD;
 349         strcpy(spd_if.body.spd.vn, "Intel");
 350         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 351         spd_if.body.spd.sdi = DIP_SPD_PC;
 352
 353         intel_set_infoframe(encoder, &spd_if);
 354 }
 355
 356 static void g4x_set_infoframes(struct drm_encoder *encoder,
 357                                struct drm_display_mode *adjusted_mode)
 358 {
 359         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 360         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 361         u32 reg = VIDEO_DIP_CTL;
 362         u32 val = I915_READ(reg);
 363         u32 port;
 364
 365         assert_hdmi_port_disabled(intel_hdmi);
 366
 367         /* If the registers were not initialized yet, they might be zeroes,
 368          * which means we're selecting the AVI DIP and we're setting its
 369          * frequency to once. This seems to really confuse the HW and make
 370          * things stop working (the register spec says the AVI always needs to
 371          * be sent every VSync). So here we avoid writing to the register more
 372          * than we need and also explicitly select the AVI DIP and explicitly
 373          * set its frequency to every VSync. Avoiding to write it twice seems to
 374          * be enough to solve the problem, but being defensive shouldn't hurt us
 375          * either. */
 376         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 377
 378         if (!intel_hdmi->has_hdmi_sink) {
 379                 if (!(val & VIDEO_DIP_ENABLE))
 380                         return;
 381                 val &= ~VIDEO_DIP_ENABLE;
 382                 I915_WRITE(reg, val);
 383                 POSTING_READ(reg);
 384                 return;
 385         }
 386
 387         switch (intel_hdmi->sdvox_reg) {
 388         case SDVOB:
 389                 port = VIDEO_DIP_PORT_B;
 390                 break;
 391         case SDVOC:
 392                 port = VIDEO_DIP_PORT_C;
 393                 break;
 394         default:
 395                 return;
 396         }
 397
 398         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 399                 if (val & VIDEO_DIP_ENABLE) {
 400                         val &= ~VIDEO_DIP_ENABLE;
 401                         I915_WRITE(reg, val);
 402                         POSTING_READ(reg);
 403                 }
 404                 val &= ~VIDEO_DIP_PORT_MASK;
 405                 val |= port;
 406         }
 407
 408         val |= VIDEO_DIP_ENABLE;
 409         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 410
 411         I915_WRITE(reg, val);
 412         POSTING_READ(reg);
 413
 414         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 415         intel_hdmi_set_spd_infoframe(encoder);
 416 }
 417
 418 static void ibx_set_infoframes(struct drm_encoder *encoder,
 419                                struct drm_display_mode *adjusted_mode)
 420 {
 421         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 422         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 423         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 424         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 425         u32 val = I915_READ(reg);
 426         u32 port;
 427
 428         assert_hdmi_port_disabled(intel_hdmi);
 429
 430         /* See the big comment in g4x_set_infoframes() */
 431         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 432
 433         if (!intel_hdmi->has_hdmi_sink) {
 434                 if (!(val & VIDEO_DIP_ENABLE))
 435                         return;
 436                 val &= ~VIDEO_DIP_ENABLE;
 437                 I915_WRITE(reg, val);
 438                 POSTING_READ(reg);
 439                 return;
 440         }
 441
 442         switch (intel_hdmi->sdvox_reg) {
 443         case HDMIB:
 444                 port = VIDEO_DIP_PORT_B;
 445                 break;
 446         case HDMIC:
 447                 port = VIDEO_DIP_PORT_C;
 448                 break;
 449         case HDMID:
 450                 port = VIDEO_DIP_PORT_D;
 451                 break;
 452         default:
 453                 return;
 454         }
 455
 456         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 457                 if (val & VIDEO_DIP_ENABLE) {
 458                         val &= ~VIDEO_DIP_ENABLE;
 459                         I915_WRITE(reg, val);
 460                         POSTING_READ(reg);
 461                 }
 462                 val &= ~VIDEO_DIP_PORT_MASK;
 463                 val |= port;
 464         }
 465
 466         val |= VIDEO_DIP_ENABLE;
 467         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 468                  VIDEO_DIP_ENABLE_GCP);
 469
 470         I915_WRITE(reg, val);
 471         POSTING_READ(reg);
 472
 473         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 474         intel_hdmi_set_spd_infoframe(encoder);
 475 }
 476
 477 static void cpt_set_infoframes(struct drm_encoder *encoder,
 478                                struct drm_display_mode *adjusted_mode)
 479 {
 480         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 481         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 482         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 483         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 484         u32 val = I915_READ(reg);
 485
 486         assert_hdmi_port_disabled(intel_hdmi);
 487
 488         /* See the big comment in g4x_set_infoframes() */
 489         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 490
 491         if (!intel_hdmi->has_hdmi_sink) {
 492                 if (!(val & VIDEO_DIP_ENABLE))
 493                         return;
 494                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 495                 I915_WRITE(reg, val);
 496                 POSTING_READ(reg);
 497                 return;
 498         }
 499
 500         /* Set both together, unset both together: see the spec. */
 501         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 502         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 503                  VIDEO_DIP_ENABLE_GCP);
 504
 505         I915_WRITE(reg, val);
 506         POSTING_READ(reg);
 507
 508         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 509         intel_hdmi_set_spd_infoframe(encoder);
 510 }
 511
 512 static void vlv_set_infoframes(struct drm_encoder *encoder,
 513                                struct drm_display_mode *adjusted_mode)
 514 {
 515         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 516         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 517         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 518         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 519         u32 val = I915_READ(reg);
 520
 521         assert_hdmi_port_disabled(intel_hdmi);
 522
 523         /* See the big comment in g4x_set_infoframes() */
 524         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 525
 526         if (!intel_hdmi->has_hdmi_sink) {
 527                 if (!(val & VIDEO_DIP_ENABLE))
 528                         return;
 529                 val &= ~VIDEO_DIP_ENABLE;
 530                 I915_WRITE(reg, val);
 531                 POSTING_READ(reg);
 532                 return;
 533         }
 534
 535         val |= VIDEO_DIP_ENABLE;
 536         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 537                  VIDEO_DIP_ENABLE_GCP);
 538
 539         I915_WRITE(reg, val);
 540         POSTING_READ(reg);
 541
 542         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 543         intel_hdmi_set_spd_infoframe(encoder);
 544 }
 545
 546 static void hsw_set_infoframes(struct drm_encoder *encoder,
 547                                struct drm_display_mode *adjusted_mode)
 548 {
 549         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 550         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 551         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 552         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 553         u32 val = I915_READ(reg);
 554
 555         assert_hdmi_port_disabled(intel_hdmi);
 556
 557         if (!intel_hdmi->has_hdmi_sink) {
 558                 I915_WRITE(reg, 0);
 559                 POSTING_READ(reg);
 560                 return;
 561         }
 562
 563         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 564                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 565
 566         I915_WRITE(reg, val);
 567         POSTING_READ(reg);
 568
 569         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 570         intel_hdmi_set_spd_infoframe(encoder);
 571 }
 572
 573 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 574                                 struct drm_display_mode *mode,
 575                                 struct drm_display_mode *adjusted_mode)
 576 {
 577         struct drm_device *dev = encoder->dev;
 578         struct drm_i915_private *dev_priv = dev->dev_private;
 579         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 580         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 581         u32 sdvox;
 582
 583         sdvox = SDVO_ENCODING_HDMI;
 584         if (!HAS_PCH_SPLIT(dev))
 585                 sdvox |= intel_hdmi->color_range;
 586         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 587                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 588         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 589                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 590
 591         if (intel_crtc->bpp > 24)
 592                 sdvox |= COLOR_FORMAT_12bpc;
 593         else
 594                 sdvox |= COLOR_FORMAT_8bpc;
 595
 596         /* Required on CPT */
 597         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 598                 sdvox |= HDMI_MODE_SELECT;
 599
 600         if (intel_hdmi->has_audio) {
 601                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 602                                  pipe_name(intel_crtc->pipe));
 603                 sdvox |= SDVO_AUDIO_ENABLE;
 604                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 605                 intel_write_eld(encoder, adjusted_mode);
 606         }
 607
 608         if (HAS_PCH_CPT(dev))
 609                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 610         else if (intel_crtc->pipe == PIPE_B)
 611                 sdvox |= SDVO_PIPE_B_SELECT;
 612
 613         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 614         POSTING_READ(intel_hdmi->sdvox_reg);
 615
 616         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 617 }
 618
 619 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
 620 {
 621         struct drm_device *dev = encoder->dev;
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 624         u32 temp;
 625         u32 enable_bits = SDVO_ENABLE;
 626
 627         if (intel_hdmi->has_audio || mode != DRM_MODE_DPMS_ON)
 628                 enable_bits |= SDVO_AUDIO_ENABLE;
 629
 630         temp = I915_READ(intel_hdmi->sdvox_reg);
 631
 632         /* HW workaround for IBX, we need to move the port to transcoder A
 633          * before disabling it. */
 634         if (HAS_PCH_IBX(dev)) {
 635                 struct drm_crtc *crtc = encoder->crtc;
 636                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 637
 638                 if (mode != DRM_MODE_DPMS_ON) {
 639                         if (temp & SDVO_PIPE_B_SELECT) {
 640                                 temp &= ~SDVO_PIPE_B_SELECT;
 641                                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 642                                 POSTING_READ(intel_hdmi->sdvox_reg);
 643
 644                                 /* Again we need to write this twice. */
 645                                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 646                                 POSTING_READ(intel_hdmi->sdvox_reg);
 647
 648                                 /* Transcoder selection bits only update
 649                                  * effectively on vblank. */
 650                                 if (crtc)
 651                                         intel_wait_for_vblank(dev, pipe);
 652                                 else
 653                                         msleep(50);
 654                         }
 655                 } else {
 656                         /* Restore the transcoder select bit. */
 657                         if (pipe == PIPE_B)
 658                                 enable_bits |= SDVO_PIPE_B_SELECT;
 659                 }
 660         }
 661
 662         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 663          * we do this anyway which shows more stable in testing.
 664          */
 665         if (HAS_PCH_SPLIT(dev)) {
 666                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 667                 POSTING_READ(intel_hdmi->sdvox_reg);
 668         }
 669
 670         if (mode != DRM_MODE_DPMS_ON) {
 671                 temp &= ~enable_bits;
 672         } else {
 673                 temp |= enable_bits;
 674         }
 675
 676         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 677         POSTING_READ(intel_hdmi->sdvox_reg);
 678
 679         /* HW workaround, need to write this twice for issue that may result
 680          * in first write getting masked.
 681          */
 682         if (HAS_PCH_SPLIT(dev)) {
 683                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 684                 POSTING_READ(intel_hdmi->sdvox_reg);
 685         }
 686 }
 687
 688 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 689                                  struct drm_display_mode *mode)
 690 {
 691         if (mode->clock > 165000)
 692                 return MODE_CLOCK_HIGH;
 693         if (mode->clock < 20000)
 694                 return MODE_CLOCK_LOW;
 695
 696         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 697                 return MODE_NO_DBLESCAN;
 698
 699         return MODE_OK;
 700 }
 701
 702 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 703                                   const struct drm_display_mode *mode,
 704                                   struct drm_display_mode *adjusted_mode)
 705 {
 706         return true;
 707 }
 708
 709 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 710 {
 711         struct drm_device *dev = intel_hdmi->base.base.dev;
 712         struct drm_i915_private *dev_priv = dev->dev_private;
 713         uint32_t bit;
 714
 715         switch (intel_hdmi->sdvox_reg) {
 716         case SDVOB:
 717                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
 718                 break;
 719         case SDVOC:
 720                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
 721                 break;
 722         default:
 723                 bit = 0;
 724                 break;
 725         }
 726
 727         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 728 }
 729
 730 static enum drm_connector_status
 731 intel_hdmi_detect(struct drm_connector *connector, bool force)
 732 {
 733         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 734         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 735         struct edid *edid;
 736         enum drm_connector_status status = connector_status_disconnected;
 737
 738         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
 739                 return status;
 740
 741         intel_hdmi->has_hdmi_sink = false;
 742         intel_hdmi->has_audio = false;
 743         edid = drm_get_edid(connector,
 744                             intel_gmbus_get_adapter(dev_priv,
 745                                                     intel_hdmi->ddc_bus));
 746
 747         if (edid) {
 748                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 749                         status = connector_status_connected;
 750                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 751                                 intel_hdmi->has_hdmi_sink =
 752                                                 drm_detect_hdmi_monitor(edid);
 753                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 754                 }
 755                 connector->display_info.raw_edid = NULL;
 756                 kfree(edid);
 757         }
 758
 759         if (status == connector_status_connected) {
 760                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 761                         intel_hdmi->has_audio =
 762                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 763         }
 764
 765         return status;
 766 }
 767
 768 static int intel_hdmi_get_modes(struct drm_connector *connector)
 769 {
 770         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 771         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 772
 773         /* We should parse the EDID data and find out if it's an HDMI sink so
 774          * we can send audio to it.
 775          */
 776
 777         return intel_ddc_get_modes(connector,
 778                                    intel_gmbus_get_adapter(dev_priv,
 779                                                            intel_hdmi->ddc_bus));
 780 }
 781
 782 static bool
 783 intel_hdmi_detect_audio(struct drm_connector *connector)
 784 {
 785         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 786         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 787         struct edid *edid;
 788         bool has_audio = false;
 789
 790         edid = drm_get_edid(connector,
 791                             intel_gmbus_get_adapter(dev_priv,
 792                                                     intel_hdmi->ddc_bus));
 793         if (edid) {
 794                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 795                         has_audio = drm_detect_monitor_audio(edid);
 796
 797                 connector->display_info.raw_edid = NULL;
 798                 kfree(edid);
 799         }
 800
 801         return has_audio;
 802 }
 803
 804 static int
 805 intel_hdmi_set_property(struct drm_connector *connector,
 806                         struct drm_property *property,
 807                         uint64_t val)
 808 {
 809         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 810         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 811         int ret;
 812
 813         ret = drm_connector_property_set_value(connector, property, val);
 814         if (ret)
 815                 return ret;
 816
 817         if (property == dev_priv->force_audio_property) {
 818                 enum hdmi_force_audio i = val;
 819                 bool has_audio;
 820
 821                 if (i == intel_hdmi->force_audio)
 822                         return 0;
 823
 824                 intel_hdmi->force_audio = i;
 825
 826                 if (i == HDMI_AUDIO_AUTO)
 827                         has_audio = intel_hdmi_detect_audio(connector);
 828                 else
 829                         has_audio = (i == HDMI_AUDIO_ON);
 830
 831                 if (i == HDMI_AUDIO_OFF_DVI)
 832                         intel_hdmi->has_hdmi_sink = 0;
 833
 834                 intel_hdmi->has_audio = has_audio;
 835                 goto done;
 836         }
 837
 838         if (property == dev_priv->broadcast_rgb_property) {
 839                 if (val == !!intel_hdmi->color_range)
 840                         return 0;
 841
 842                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 843                 goto done;
 844         }
 845
 846         return -EINVAL;
 847
 848 done:
 849         if (intel_hdmi->base.base.crtc) {
 850                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
 851                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 852                                          crtc->x, crtc->y,
 853                                          crtc->fb);
 854         }
 855
 856         return 0;
 857 }
 858
 859 static void intel_hdmi_destroy(struct drm_connector *connector)
 860 {
 861         drm_sysfs_connector_remove(connector);
 862         drm_connector_cleanup(connector);
 863         kfree(connector);
 864 }
 865
 866 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
 867         .dpms = intel_ddi_dpms,
 868         .mode_fixup = intel_hdmi_mode_fixup,
 869         .prepare = intel_encoder_prepare,
 870         .mode_set = intel_ddi_mode_set,
 871         .commit = intel_encoder_commit,
 872 };
 873
 874 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 875         .dpms = intel_hdmi_dpms,
 876         .mode_fixup = intel_hdmi_mode_fixup,
 877         .prepare = intel_encoder_prepare,
 878         .mode_set = intel_hdmi_mode_set,
 879         .commit = intel_encoder_commit,
 880 };
 881
 882 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 883         .dpms = drm_helper_connector_dpms,
 884         .detect = intel_hdmi_detect,
 885         .fill_modes = drm_helper_probe_single_connector_modes,
 886         .set_property = intel_hdmi_set_property,
 887         .destroy = intel_hdmi_destroy,
 888 };
 889
 890 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 891         .get_modes = intel_hdmi_get_modes,
 892         .mode_valid = intel_hdmi_mode_valid,
 893         .best_encoder = intel_best_encoder,
 894 };
 895
 896 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 897         .destroy = intel_encoder_destroy,
 898 };
 899
 900 static void
 901 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 902 {
 903         intel_attach_force_audio_property(connector);
 904         intel_attach_broadcast_rgb_property(connector);
 905 }
 906
 907 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 908 {
 909         struct drm_i915_private *dev_priv = dev->dev_private;
 910         struct drm_connector *connector;
 911         struct intel_encoder *intel_encoder;
 912         struct intel_connector *intel_connector;
 913         struct intel_hdmi *intel_hdmi;
 914
 915         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
 916         if (!intel_hdmi)
 917                 return;
 918
 919         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
 920         if (!intel_connector) {
 921                 kfree(intel_hdmi);
 922                 return;
 923         }
 924
 925         intel_encoder = &intel_hdmi->base;
 926         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
 927                          DRM_MODE_ENCODER_TMDS);
 928
 929         connector = &intel_connector->base;
 930         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 931                            DRM_MODE_CONNECTOR_HDMIA);
 932         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 933
 934         intel_encoder->type = INTEL_OUTPUT_HDMI;
 935
 936         connector->polled = DRM_CONNECTOR_POLL_HPD;
 937         connector->interlace_allowed = 1;
 938         connector->doublescan_allowed = 0;
 939         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 940
 941         /* Set up the DDC bus. */
 942         if (sdvox_reg == SDVOB) {
 943                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 944                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 945                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 946         } else if (sdvox_reg == SDVOC) {
 947                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 948                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 949                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 950         } else if (sdvox_reg == HDMIB) {
 951                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 952                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 953                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 954         } else if (sdvox_reg == HDMIC) {
 955                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
 956                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 957                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 958         } else if (sdvox_reg == HDMID) {
 959                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
 960                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 961                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 962         } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
 963                 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
 964                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 965                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 966                 intel_hdmi->ddi_port = PORT_B;
 967                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 968         } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
 969                 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
 970                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 971                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 972                 intel_hdmi->ddi_port = PORT_C;
 973                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 974         } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
 975                 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
 976                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
 977                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 978                 intel_hdmi->ddi_port = PORT_D;
 979                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 980         } else {
 981                 /* If we got an unknown sdvox_reg, things are pretty much broken
 982                  * in a way that we should let the kernel know about it */
 983                 BUG();
 984         }
 985
 986         intel_hdmi->sdvox_reg = sdvox_reg;
 987
 988         if (!HAS_PCH_SPLIT(dev)) {
 989                 intel_hdmi->write_infoframe = g4x_write_infoframe;
 990                 intel_hdmi->set_infoframes = g4x_set_infoframes;
 991         } else if (IS_VALLEYVIEW(dev)) {
 992                 intel_hdmi->write_infoframe = vlv_write_infoframe;
 993                 intel_hdmi->set_infoframes = vlv_set_infoframes;
 994         } else if (IS_HASWELL(dev)) {
 995                 intel_hdmi->write_infoframe = hsw_write_infoframe;
 996                 intel_hdmi->set_infoframes = hsw_set_infoframes;
 997         } else if (HAS_PCH_IBX(dev)) {
 998                 intel_hdmi->write_infoframe = ibx_write_infoframe;
 999                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1000         } else {
1001                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1002                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1003         }
1004
1005         if (IS_HASWELL(dev))
1006                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
1007         else
1008                 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1009
1010         intel_hdmi_add_properties(intel_hdmi, connector);
1011
1012         intel_connector_attach_encoder(intel_connector, intel_encoder);
1013         drm_sysfs_connector_add(connector);
1014
1015         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1016          * 0xd.  Failure to do so will result in spurious interrupts being
1017          * generated on the port when a cable is not attached.
1018          */
1019         if (IS_G4X(dev) && !IS_GM45(dev)) {
1020                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1021                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1022         }
1023 }