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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
blobe2a73b38abe96e7dc49674d39806c5ca3cab6e51
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 ret = intel_emit_post_sync_nonzero_flush(ring);
223 if (ret)
224 return ret;
225
226 /* Just flush everything. Experiments have shown that reducing the
227 * number of bits based on the write domains has little performance
228 * impact.
229 */
230 if (flush_domains) {
231 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233 /*
234 * Ensure that any following seqno writes only happen
235 * when the render cache is indeed flushed.
236 */
237 flags |= PIPE_CONTROL_CS_STALL;
238 }
239 if (invalidate_domains) {
240 flags |= PIPE_CONTROL_TLB_INVALIDATE;
241 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
245 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
246 /*
247 * TLB invalidate requires a post-sync write.
248 */
249 flags |= PIPE_CONTROL_QW_WRITE;
250 }
251
252 ret = intel_ring_begin(ring, 4);
253 if (ret)
254 return ret;
255
256 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
257 intel_ring_emit(ring, flags);
258 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
259 intel_ring_emit(ring, 0);
260 intel_ring_advance(ring);
261
262 return 0;
263 }
264
265 static void ring_write_tail(struct intel_ring_buffer *ring,
266 u32 value)
267 {
268 drm_i915_private_t *dev_priv = ring->dev->dev_private;
269 I915_WRITE_TAIL(ring, value);
270 }
271
272 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
273 {
274 drm_i915_private_t *dev_priv = ring->dev->dev_private;
275 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
276 RING_ACTHD(ring->mmio_base) : ACTHD;
277
278 return I915_READ(acthd_reg);
279 }
280
281 static int init_ring_common(struct intel_ring_buffer *ring)
282 {
283 struct drm_device *dev = ring->dev;
284 drm_i915_private_t *dev_priv = dev->dev_private;
285 struct drm_i915_gem_object *obj = ring->obj;
286 int ret = 0;
287 u32 head;
288
289 if (HAS_FORCE_WAKE(dev))
290 gen6_gt_force_wake_get(dev_priv);
291
292 /* Stop the ring if it's running. */
293 I915_WRITE_CTL(ring, 0);
294 I915_WRITE_HEAD(ring, 0);
295 ring->write_tail(ring, 0);
296
297 head = I915_READ_HEAD(ring) & HEAD_ADDR;
298
299 /* G45 ring initialization fails to reset head to zero */
300 if (head != 0) {
301 DRM_DEBUG_KMS("%s head not reset to zero "
302 "ctl %08x head %08x tail %08x start %08x\n",
303 ring->name,
304 I915_READ_CTL(ring),
305 I915_READ_HEAD(ring),
306 I915_READ_TAIL(ring),
307 I915_READ_START(ring));
308
309 I915_WRITE_HEAD(ring, 0);
310
311 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
312 DRM_ERROR("failed to set %s head to zero "
313 "ctl %08x head %08x tail %08x start %08x\n",
314 ring->name,
315 I915_READ_CTL(ring),
316 I915_READ_HEAD(ring),
317 I915_READ_TAIL(ring),
318 I915_READ_START(ring));
319 }
320 }
321
322 /* Initialize the ring. This must happen _after_ we've cleared the ring
323 * registers with the above sequence (the readback of the HEAD registers
324 * also enforces ordering), otherwise the hw might lose the new ring
325 * register values. */
326 I915_WRITE_START(ring, obj->gtt_offset);
327 I915_WRITE_CTL(ring,
328 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
329 | RING_VALID);
330
331 /* If the head is still not zero, the ring is dead */
332 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
333 I915_READ_START(ring) == obj->gtt_offset &&
334 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
335 DRM_ERROR("%s initialization failed "
336 "ctl %08x head %08x tail %08x start %08x\n",
337 ring->name,
338 I915_READ_CTL(ring),
339 I915_READ_HEAD(ring),
340 I915_READ_TAIL(ring),
341 I915_READ_START(ring));
342 ret = -EIO;
343 goto out;
344 }
345
346 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
347 i915_kernel_lost_context(ring->dev);
348 else {
349 ring->head = I915_READ_HEAD(ring);
350 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
351 ring->space = ring_space(ring);
352 ring->last_retired_head = -1;
353 }
354
355 out:
356 if (HAS_FORCE_WAKE(dev))
357 gen6_gt_force_wake_put(dev_priv);
358
359 return ret;
360 }
361
362 static int
363 init_pipe_control(struct intel_ring_buffer *ring)
364 {
365 struct pipe_control *pc;
366 struct drm_i915_gem_object *obj;
367 int ret;
368
369 if (ring->private)
370 return 0;
371
372 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
373 if (!pc)
374 return -ENOMEM;
375
376 obj = i915_gem_alloc_object(ring->dev, 4096);
377 if (obj == NULL) {
378 DRM_ERROR("Failed to allocate seqno page\n");
379 ret = -ENOMEM;
380 goto err;
381 }
382
383 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
384
385 ret = i915_gem_object_pin(obj, 4096, true);
386 if (ret)
387 goto err_unref;
388
389 pc->gtt_offset = obj->gtt_offset;
390 pc->cpu_page = kmap(obj->pages[0]);
391 if (pc->cpu_page == NULL)
392 goto err_unpin;
393
394 pc->obj = obj;
395 ring->private = pc;
396 return 0;
397
398 err_unpin:
399 i915_gem_object_unpin(obj);
400 err_unref:
401 drm_gem_object_unreference(&obj->base);
402 err:
403 kfree(pc);
404 return ret;
405 }
406
407 static void
408 cleanup_pipe_control(struct intel_ring_buffer *ring)
409 {
410 struct pipe_control *pc = ring->private;
411 struct drm_i915_gem_object *obj;
412
413 if (!ring->private)
414 return;
415
416 obj = pc->obj;
417 kunmap(obj->pages[0]);
418 i915_gem_object_unpin(obj);
419 drm_gem_object_unreference(&obj->base);
420
421 kfree(pc);
422 ring->private = NULL;
423 }
424
425 static int init_render_ring(struct intel_ring_buffer *ring)
426 {
427 struct drm_device *dev = ring->dev;
428 struct drm_i915_private *dev_priv = dev->dev_private;
429 int ret = init_ring_common(ring);
430
431 if (INTEL_INFO(dev)->gen > 3) {
432 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
433 if (IS_GEN7(dev))
434 I915_WRITE(GFX_MODE_GEN7,
435 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
436 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
437 }
438
439 if (INTEL_INFO(dev)->gen >= 5) {
440 ret = init_pipe_control(ring);
441 if (ret)
442 return ret;
443 }
444
445 if (IS_GEN6(dev)) {
446 /* From the Sandybridge PRM, volume 1 part 3, page 24:
447 * "If this bit is set, STCunit will have LRA as replacement
448 * policy. [...] This bit must be reset. LRA replacement
449 * policy is not supported."
450 */
451 I915_WRITE(CACHE_MODE_0,
452 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
453
454 /* This is not explicitly set for GEN6, so read the register.
455 * see intel_ring_mi_set_context() for why we care.
456 * TODO: consider explicitly setting the bit for GEN5
457 */
458 ring->itlb_before_ctx_switch =
459 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
460 }
461
462 if (INTEL_INFO(dev)->gen >= 6)
463 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
464
465 if (IS_IVYBRIDGE(dev))
466 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
467
468 return ret;
469 }
470
471 static void render_ring_cleanup(struct intel_ring_buffer *ring)
472 {
473 if (!ring->private)
474 return;
475
476 cleanup_pipe_control(ring);
477 }
478
479 static void
480 update_mboxes(struct intel_ring_buffer *ring,
481 u32 seqno,
482 u32 mmio_offset)
483 {
484 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
485 MI_SEMAPHORE_GLOBAL_GTT |
486 MI_SEMAPHORE_REGISTER |
487 MI_SEMAPHORE_UPDATE);
488 intel_ring_emit(ring, seqno);
489 intel_ring_emit(ring, mmio_offset);
490 }
491
492 /**
493 * gen6_add_request - Update the semaphore mailbox registers
494 *
495 * @ring - ring that is adding a request
496 * @seqno - return seqno stuck into the ring
497 *
498 * Update the mailbox registers in the *other* rings with the current seqno.
499 * This acts like a signal in the canonical semaphore.
500 */
501 static int
502 gen6_add_request(struct intel_ring_buffer *ring,
503 u32 *seqno)
504 {
505 u32 mbox1_reg;
506 u32 mbox2_reg;
507 int ret;
508
509 ret = intel_ring_begin(ring, 10);
510 if (ret)
511 return ret;
512
513 mbox1_reg = ring->signal_mbox[0];
514 mbox2_reg = ring->signal_mbox[1];
515
516 *seqno = i915_gem_next_request_seqno(ring);
517
518 update_mboxes(ring, *seqno, mbox1_reg);
519 update_mboxes(ring, *seqno, mbox2_reg);
520 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
521 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
522 intel_ring_emit(ring, *seqno);
523 intel_ring_emit(ring, MI_USER_INTERRUPT);
524 intel_ring_advance(ring);
525
526 return 0;
527 }
528
529 /**
530 * intel_ring_sync - sync the waiter to the signaller on seqno
531 *
532 * @waiter - ring that is waiting
533 * @signaller - ring which has, or will signal
534 * @seqno - seqno which the waiter will block on
535 */
536 static int
537 gen6_ring_sync(struct intel_ring_buffer *waiter,
538 struct intel_ring_buffer *signaller,
539 u32 seqno)
540 {
541 int ret;
542 u32 dw1 = MI_SEMAPHORE_MBOX |
543 MI_SEMAPHORE_COMPARE |
544 MI_SEMAPHORE_REGISTER;
545
546 /* Throughout all of the GEM code, seqno passed implies our current
547 * seqno is >= the last seqno executed. However for hardware the
548 * comparison is strictly greater than.
549 */
550 seqno -= 1;
551
552 WARN_ON(signaller->semaphore_register[waiter->id] ==
553 MI_SEMAPHORE_SYNC_INVALID);
554
555 ret = intel_ring_begin(waiter, 4);
556 if (ret)
557 return ret;
558
559 intel_ring_emit(waiter,
560 dw1 | signaller->semaphore_register[waiter->id]);
561 intel_ring_emit(waiter, seqno);
562 intel_ring_emit(waiter, 0);
563 intel_ring_emit(waiter, MI_NOOP);
564 intel_ring_advance(waiter);
565
566 return 0;
567 }
568
569 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
570 do { \
571 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
572 PIPE_CONTROL_DEPTH_STALL); \
573 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
574 intel_ring_emit(ring__, 0); \
575 intel_ring_emit(ring__, 0); \
576 } while (0)
577
578 static int
579 pc_render_add_request(struct intel_ring_buffer *ring,
580 u32 *result)
581 {
582 u32 seqno = i915_gem_next_request_seqno(ring);
583 struct pipe_control *pc = ring->private;
584 u32 scratch_addr = pc->gtt_offset + 128;
585 int ret;
586
587 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
588 * incoherent with writes to memory, i.e. completely fubar,
589 * so we need to use PIPE_NOTIFY instead.
590 *
591 * However, we also need to workaround the qword write
592 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
593 * memory before requesting an interrupt.
594 */
595 ret = intel_ring_begin(ring, 32);
596 if (ret)
597 return ret;
598
599 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
600 PIPE_CONTROL_WRITE_FLUSH |
601 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
602 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
603 intel_ring_emit(ring, seqno);
604 intel_ring_emit(ring, 0);
605 PIPE_CONTROL_FLUSH(ring, scratch_addr);
606 scratch_addr += 128; /* write to separate cachelines */
607 PIPE_CONTROL_FLUSH(ring, scratch_addr);
608 scratch_addr += 128;
609 PIPE_CONTROL_FLUSH(ring, scratch_addr);
610 scratch_addr += 128;
611 PIPE_CONTROL_FLUSH(ring, scratch_addr);
612 scratch_addr += 128;
613 PIPE_CONTROL_FLUSH(ring, scratch_addr);
614 scratch_addr += 128;
615 PIPE_CONTROL_FLUSH(ring, scratch_addr);
616
617 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
618 PIPE_CONTROL_WRITE_FLUSH |
619 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
620 PIPE_CONTROL_NOTIFY);
621 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
622 intel_ring_emit(ring, seqno);
623 intel_ring_emit(ring, 0);
624 intel_ring_advance(ring);
625
626 *result = seqno;
627 return 0;
628 }
629
630 static u32
631 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
632 {
633 struct drm_device *dev = ring->dev;
634
635 /* Workaround to force correct ordering between irq and seqno writes on
636 * ivb (and maybe also on snb) by reading from a CS register (like
637 * ACTHD) before reading the status page. */
638 if (IS_GEN6(dev) || IS_GEN7(dev))
639 intel_ring_get_active_head(ring);
640 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
641 }
642
643 static u32
644 ring_get_seqno(struct intel_ring_buffer *ring)
645 {
646 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
647 }
648
649 static u32
650 pc_render_get_seqno(struct intel_ring_buffer *ring)
651 {
652 struct pipe_control *pc = ring->private;
653 return pc->cpu_page[0];
654 }
655
656 static bool
657 gen5_ring_get_irq(struct intel_ring_buffer *ring)
658 {
659 struct drm_device *dev = ring->dev;
660 drm_i915_private_t *dev_priv = dev->dev_private;
661 unsigned long flags;
662
663 if (!dev->irq_enabled)
664 return false;
665
666 spin_lock_irqsave(&dev_priv->irq_lock, flags);
667 if (ring->irq_refcount++ == 0) {
668 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
669 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
670 POSTING_READ(GTIMR);
671 }
672 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
673
674 return true;
675 }
676
677 static void
678 gen5_ring_put_irq(struct intel_ring_buffer *ring)
679 {
680 struct drm_device *dev = ring->dev;
681 drm_i915_private_t *dev_priv = dev->dev_private;
682 unsigned long flags;
683
684 spin_lock_irqsave(&dev_priv->irq_lock, flags);
685 if (--ring->irq_refcount == 0) {
686 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
687 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
688 POSTING_READ(GTIMR);
689 }
690 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
691 }
692
693 static bool
694 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
695 {
696 struct drm_device *dev = ring->dev;
697 drm_i915_private_t *dev_priv = dev->dev_private;
698 unsigned long flags;
699
700 if (!dev->irq_enabled)
701 return false;
702
703 spin_lock_irqsave(&dev_priv->irq_lock, flags);
704 if (ring->irq_refcount++ == 0) {
705 dev_priv->irq_mask &= ~ring->irq_enable_mask;
706 I915_WRITE(IMR, dev_priv->irq_mask);
707 POSTING_READ(IMR);
708 }
709 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
710
711 return true;
712 }
713
714 static void
715 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
716 {
717 struct drm_device *dev = ring->dev;
718 drm_i915_private_t *dev_priv = dev->dev_private;
719 unsigned long flags;
720
721 spin_lock_irqsave(&dev_priv->irq_lock, flags);
722 if (--ring->irq_refcount == 0) {
723 dev_priv->irq_mask |= ring->irq_enable_mask;
724 I915_WRITE(IMR, dev_priv->irq_mask);
725 POSTING_READ(IMR);
726 }
727 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
728 }
729
730 static bool
731 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
732 {
733 struct drm_device *dev = ring->dev;
734 drm_i915_private_t *dev_priv = dev->dev_private;
735 unsigned long flags;
736
737 if (!dev->irq_enabled)
738 return false;
739
740 spin_lock_irqsave(&dev_priv->irq_lock, flags);
741 if (ring->irq_refcount++ == 0) {
742 dev_priv->irq_mask &= ~ring->irq_enable_mask;
743 I915_WRITE16(IMR, dev_priv->irq_mask);
744 POSTING_READ16(IMR);
745 }
746 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
747
748 return true;
749 }
750
751 static void
752 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
753 {
754 struct drm_device *dev = ring->dev;
755 drm_i915_private_t *dev_priv = dev->dev_private;
756 unsigned long flags;
757
758 spin_lock_irqsave(&dev_priv->irq_lock, flags);
759 if (--ring->irq_refcount == 0) {
760 dev_priv->irq_mask |= ring->irq_enable_mask;
761 I915_WRITE16(IMR, dev_priv->irq_mask);
762 POSTING_READ16(IMR);
763 }
764 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
765 }
766
767 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
768 {
769 struct drm_device *dev = ring->dev;
770 drm_i915_private_t *dev_priv = ring->dev->dev_private;
771 u32 mmio = 0;
772
773 /* The ring status page addresses are no longer next to the rest of
774 * the ring registers as of gen7.
775 */
776 if (IS_GEN7(dev)) {
777 switch (ring->id) {
778 case RCS:
779 mmio = RENDER_HWS_PGA_GEN7;
780 break;
781 case BCS:
782 mmio = BLT_HWS_PGA_GEN7;
783 break;
784 case VCS:
785 mmio = BSD_HWS_PGA_GEN7;
786 break;
787 }
788 } else if (IS_GEN6(ring->dev)) {
789 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
790 } else {
791 mmio = RING_HWS_PGA(ring->mmio_base);
792 }
793
794 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
795 POSTING_READ(mmio);
796 }
797
798 static int
799 bsd_ring_flush(struct intel_ring_buffer *ring,
800 u32 invalidate_domains,
801 u32 flush_domains)
802 {
803 int ret;
804
805 ret = intel_ring_begin(ring, 2);
806 if (ret)
807 return ret;
808
809 intel_ring_emit(ring, MI_FLUSH);
810 intel_ring_emit(ring, MI_NOOP);
811 intel_ring_advance(ring);
812 return 0;
813 }
814
815 static int
816 i9xx_add_request(struct intel_ring_buffer *ring,
817 u32 *result)
818 {
819 u32 seqno;
820 int ret;
821
822 ret = intel_ring_begin(ring, 4);
823 if (ret)
824 return ret;
825
826 seqno = i915_gem_next_request_seqno(ring);
827
828 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
829 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
830 intel_ring_emit(ring, seqno);
831 intel_ring_emit(ring, MI_USER_INTERRUPT);
832 intel_ring_advance(ring);
833
834 *result = seqno;
835 return 0;
836 }
837
838 static bool
839 gen6_ring_get_irq(struct intel_ring_buffer *ring)
840 {
841 struct drm_device *dev = ring->dev;
842 drm_i915_private_t *dev_priv = dev->dev_private;
843 unsigned long flags;
844
845 if (!dev->irq_enabled)
846 return false;
847
848 /* It looks like we need to prevent the gt from suspending while waiting
849 * for an notifiy irq, otherwise irqs seem to get lost on at least the
850 * blt/bsd rings on ivb. */
851 gen6_gt_force_wake_get(dev_priv);
852
853 spin_lock_irqsave(&dev_priv->irq_lock, flags);
854 if (ring->irq_refcount++ == 0) {
855 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
856 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
857 GEN6_RENDER_L3_PARITY_ERROR));
858 else
859 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
860 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
861 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
862 POSTING_READ(GTIMR);
863 }
864 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
865
866 return true;
867 }
868
869 static void
870 gen6_ring_put_irq(struct intel_ring_buffer *ring)
871 {
872 struct drm_device *dev = ring->dev;
873 drm_i915_private_t *dev_priv = dev->dev_private;
874 unsigned long flags;
875
876 spin_lock_irqsave(&dev_priv->irq_lock, flags);
877 if (--ring->irq_refcount == 0) {
878 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
879 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
880 else
881 I915_WRITE_IMR(ring, ~0);
882 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
883 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
884 POSTING_READ(GTIMR);
885 }
886 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
887
888 gen6_gt_force_wake_put(dev_priv);
889 }
890
891 static int
892 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
893 {
894 int ret;
895
896 ret = intel_ring_begin(ring, 2);
897 if (ret)
898 return ret;
899
900 intel_ring_emit(ring,
901 MI_BATCH_BUFFER_START |
902 MI_BATCH_GTT |
903 MI_BATCH_NON_SECURE_I965);
904 intel_ring_emit(ring, offset);
905 intel_ring_advance(ring);
906
907 return 0;
908 }
909
910 static int
911 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
912 u32 offset, u32 len)
913 {
914 int ret;
915
916 ret = intel_ring_begin(ring, 4);
917 if (ret)
918 return ret;
919
920 intel_ring_emit(ring, MI_BATCH_BUFFER);
921 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
922 intel_ring_emit(ring, offset + len - 8);
923 intel_ring_emit(ring, 0);
924 intel_ring_advance(ring);
925
926 return 0;
927 }
928
929 static int
930 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
931 u32 offset, u32 len)
932 {
933 int ret;
934
935 ret = intel_ring_begin(ring, 2);
936 if (ret)
937 return ret;
938
939 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
940 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
941 intel_ring_advance(ring);
942
943 return 0;
944 }
945
946 static void cleanup_status_page(struct intel_ring_buffer *ring)
947 {
948 struct drm_i915_gem_object *obj;
949
950 obj = ring->status_page.obj;
951 if (obj == NULL)
952 return;
953
954 kunmap(obj->pages[0]);
955 i915_gem_object_unpin(obj);
956 drm_gem_object_unreference(&obj->base);
957 ring->status_page.obj = NULL;
958 }
959
960 static int init_status_page(struct intel_ring_buffer *ring)
961 {
962 struct drm_device *dev = ring->dev;
963 struct drm_i915_gem_object *obj;
964 int ret;
965
966 obj = i915_gem_alloc_object(dev, 4096);
967 if (obj == NULL) {
968 DRM_ERROR("Failed to allocate status page\n");
969 ret = -ENOMEM;
970 goto err;
971 }
972
973 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
974
975 ret = i915_gem_object_pin(obj, 4096, true);
976 if (ret != 0) {
977 goto err_unref;
978 }
979
980 ring->status_page.gfx_addr = obj->gtt_offset;
981 ring->status_page.page_addr = kmap(obj->pages[0]);
982 if (ring->status_page.page_addr == NULL) {
983 ret = -ENOMEM;
984 goto err_unpin;
985 }
986 ring->status_page.obj = obj;
987 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
988
989 intel_ring_setup_status_page(ring);
990 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
991 ring->name, ring->status_page.gfx_addr);
992
993 return 0;
994
995 err_unpin:
996 i915_gem_object_unpin(obj);
997 err_unref:
998 drm_gem_object_unreference(&obj->base);
999 err:
1000 return ret;
1001 }
1002
1003 static int intel_init_ring_buffer(struct drm_device *dev,
1004 struct intel_ring_buffer *ring)
1005 {
1006 struct drm_i915_gem_object *obj;
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 int ret;
1009
1010 ring->dev = dev;
1011 INIT_LIST_HEAD(&ring->active_list);
1012 INIT_LIST_HEAD(&ring->request_list);
1013 INIT_LIST_HEAD(&ring->gpu_write_list);
1014 ring->size = 32 * PAGE_SIZE;
1015
1016 init_waitqueue_head(&ring->irq_queue);
1017
1018 if (I915_NEED_GFX_HWS(dev)) {
1019 ret = init_status_page(ring);
1020 if (ret)
1021 return ret;
1022 }
1023
1024 obj = i915_gem_alloc_object(dev, ring->size);
1025 if (obj == NULL) {
1026 DRM_ERROR("Failed to allocate ringbuffer\n");
1027 ret = -ENOMEM;
1028 goto err_hws;
1029 }
1030
1031 ring->obj = obj;
1032
1033 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1034 if (ret)
1035 goto err_unref;
1036
1037 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1038 if (ret)
1039 goto err_unpin;
1040
1041 ring->virtual_start =
1042 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1043 ring->size);
1044 if (ring->virtual_start == NULL) {
1045 DRM_ERROR("Failed to map ringbuffer.\n");
1046 ret = -EINVAL;
1047 goto err_unpin;
1048 }
1049
1050 ret = ring->init(ring);
1051 if (ret)
1052 goto err_unmap;
1053
1054 /* Workaround an erratum on the i830 which causes a hang if
1055 * the TAIL pointer points to within the last 2 cachelines
1056 * of the buffer.
1057 */
1058 ring->effective_size = ring->size;
1059 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1060 ring->effective_size -= 128;
1061
1062 return 0;
1063
1064 err_unmap:
1065 iounmap(ring->virtual_start);
1066 err_unpin:
1067 i915_gem_object_unpin(obj);
1068 err_unref:
1069 drm_gem_object_unreference(&obj->base);
1070 ring->obj = NULL;
1071 err_hws:
1072 cleanup_status_page(ring);
1073 return ret;
1074 }
1075
1076 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1077 {
1078 struct drm_i915_private *dev_priv;
1079 int ret;
1080
1081 if (ring->obj == NULL)
1082 return;
1083
1084 /* Disable the ring buffer. The ring must be idle at this point */
1085 dev_priv = ring->dev->dev_private;
1086 ret = intel_wait_ring_idle(ring);
1087 if (ret)
1088 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1089 ring->name, ret);
1090
1091 I915_WRITE_CTL(ring, 0);
1092
1093 iounmap(ring->virtual_start);
1094
1095 i915_gem_object_unpin(ring->obj);
1096 drm_gem_object_unreference(&ring->obj->base);
1097 ring->obj = NULL;
1098
1099 if (ring->cleanup)
1100 ring->cleanup(ring);
1101
1102 cleanup_status_page(ring);
1103 }
1104
1105 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1106 {
1107 uint32_t __iomem *virt;
1108 int rem = ring->size - ring->tail;
1109
1110 if (ring->space < rem) {
1111 int ret = intel_wait_ring_buffer(ring, rem);
1112 if (ret)
1113 return ret;
1114 }
1115
1116 virt = ring->virtual_start + ring->tail;
1117 rem /= 4;
1118 while (rem--)
1119 iowrite32(MI_NOOP, virt++);
1120
1121 ring->tail = 0;
1122 ring->space = ring_space(ring);
1123
1124 return 0;
1125 }
1126
1127 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1128 {
1129 int ret;
1130
1131 ret = i915_wait_seqno(ring, seqno);
1132 if (!ret)
1133 i915_gem_retire_requests_ring(ring);
1134
1135 return ret;
1136 }
1137
1138 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1139 {
1140 struct drm_i915_gem_request *request;
1141 u32 seqno = 0;
1142 int ret;
1143
1144 i915_gem_retire_requests_ring(ring);
1145
1146 if (ring->last_retired_head != -1) {
1147 ring->head = ring->last_retired_head;
1148 ring->last_retired_head = -1;
1149 ring->space = ring_space(ring);
1150 if (ring->space >= n)
1151 return 0;
1152 }
1153
1154 list_for_each_entry(request, &ring->request_list, list) {
1155 int space;
1156
1157 if (request->tail == -1)
1158 continue;
1159
1160 space = request->tail - (ring->tail + 8);
1161 if (space < 0)
1162 space += ring->size;
1163 if (space >= n) {
1164 seqno = request->seqno;
1165 break;
1166 }
1167
1168 /* Consume this request in case we need more space than
1169 * is available and so need to prevent a race between
1170 * updating last_retired_head and direct reads of
1171 * I915_RING_HEAD. It also provides a nice sanity check.
1172 */
1173 request->tail = -1;
1174 }
1175
1176 if (seqno == 0)
1177 return -ENOSPC;
1178
1179 ret = intel_ring_wait_seqno(ring, seqno);
1180 if (ret)
1181 return ret;
1182
1183 if (WARN_ON(ring->last_retired_head == -1))
1184 return -ENOSPC;
1185
1186 ring->head = ring->last_retired_head;
1187 ring->last_retired_head = -1;
1188 ring->space = ring_space(ring);
1189 if (WARN_ON(ring->space < n))
1190 return -ENOSPC;
1191
1192 return 0;
1193 }
1194
1195 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1196 {
1197 struct drm_device *dev = ring->dev;
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 unsigned long end;
1200 int ret;
1201
1202 ret = intel_ring_wait_request(ring, n);
1203 if (ret != -ENOSPC)
1204 return ret;
1205
1206 trace_i915_ring_wait_begin(ring);
1207 /* With GEM the hangcheck timer should kick us out of the loop,
1208 * leaving it early runs the risk of corrupting GEM state (due
1209 * to running on almost untested codepaths). But on resume
1210 * timers don't work yet, so prevent a complete hang in that
1211 * case by choosing an insanely large timeout. */
1212 end = jiffies + 60 * HZ;
1213
1214 do {
1215 ring->head = I915_READ_HEAD(ring);
1216 ring->space = ring_space(ring);
1217 if (ring->space >= n) {
1218 trace_i915_ring_wait_end(ring);
1219 return 0;
1220 }
1221
1222 if (dev->primary->master) {
1223 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1224 if (master_priv->sarea_priv)
1225 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1226 }
1227
1228 msleep(1);
1229
1230 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1231 if (ret)
1232 return ret;
1233 } while (!time_after(jiffies, end));
1234 trace_i915_ring_wait_end(ring);
1235 return -EBUSY;
1236 }
1237
1238 int intel_ring_begin(struct intel_ring_buffer *ring,
1239 int num_dwords)
1240 {
1241 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1242 int n = 4*num_dwords;
1243 int ret;
1244
1245 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1246 if (ret)
1247 return ret;
1248
1249 if (unlikely(ring->tail + n > ring->effective_size)) {
1250 ret = intel_wrap_ring_buffer(ring);
1251 if (unlikely(ret))
1252 return ret;
1253 }
1254
1255 if (unlikely(ring->space < n)) {
1256 ret = intel_wait_ring_buffer(ring, n);
1257 if (unlikely(ret))
1258 return ret;
1259 }
1260
1261 ring->space -= n;
1262 return 0;
1263 }
1264
1265 void intel_ring_advance(struct intel_ring_buffer *ring)
1266 {
1267 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1268
1269 ring->tail &= ring->size - 1;
1270 if (dev_priv->stop_rings & intel_ring_flag(ring))
1271 return;
1272 ring->write_tail(ring, ring->tail);
1273 }
1274
1275
1276 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1277 u32 value)
1278 {
1279 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1280
1281 /* Every tail move must follow the sequence below */
1282
1283 /* Disable notification that the ring is IDLE. The GT
1284 * will then assume that it is busy and bring it out of rc6.
1285 */
1286 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1287 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1288
1289 /* Clear the context id. Here be magic! */
1290 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1291
1292 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1293 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1294 GEN6_BSD_SLEEP_INDICATOR) == 0,
1295 50))
1296 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1297
1298 /* Now that the ring is fully powered up, update the tail */
1299 I915_WRITE_TAIL(ring, value);
1300 POSTING_READ(RING_TAIL(ring->mmio_base));
1301
1302 /* Let the ring send IDLE messages to the GT again,
1303 * and so let it sleep to conserve power when idle.
1304 */
1305 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1306 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1307 }
1308
1309 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1310 u32 invalidate, u32 flush)
1311 {
1312 uint32_t cmd;
1313 int ret;
1314
1315 ret = intel_ring_begin(ring, 4);
1316 if (ret)
1317 return ret;
1318
1319 cmd = MI_FLUSH_DW;
1320 if (invalidate & I915_GEM_GPU_DOMAINS)
1321 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1322 intel_ring_emit(ring, cmd);
1323 intel_ring_emit(ring, 0);
1324 intel_ring_emit(ring, 0);
1325 intel_ring_emit(ring, MI_NOOP);
1326 intel_ring_advance(ring);
1327 return 0;
1328 }
1329
1330 static int
1331 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1332 u32 offset, u32 len)
1333 {
1334 int ret;
1335
1336 ret = intel_ring_begin(ring, 2);
1337 if (ret)
1338 return ret;
1339
1340 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1341 /* bit0-7 is the length on GEN6+ */
1342 intel_ring_emit(ring, offset);
1343 intel_ring_advance(ring);
1344
1345 return 0;
1346 }
1347
1348 /* Blitter support (SandyBridge+) */
1349
1350 static int blt_ring_flush(struct intel_ring_buffer *ring,
1351 u32 invalidate, u32 flush)
1352 {
1353 uint32_t cmd;
1354 int ret;
1355
1356 ret = intel_ring_begin(ring, 4);
1357 if (ret)
1358 return ret;
1359
1360 cmd = MI_FLUSH_DW;
1361 if (invalidate & I915_GEM_DOMAIN_RENDER)
1362 cmd |= MI_INVALIDATE_TLB;
1363 intel_ring_emit(ring, cmd);
1364 intel_ring_emit(ring, 0);
1365 intel_ring_emit(ring, 0);
1366 intel_ring_emit(ring, MI_NOOP);
1367 intel_ring_advance(ring);
1368 return 0;
1369 }
1370
1371 int intel_init_render_ring_buffer(struct drm_device *dev)
1372 {
1373 drm_i915_private_t *dev_priv = dev->dev_private;
1374 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1375
1376 ring->name = "render ring";
1377 ring->id = RCS;
1378 ring->mmio_base = RENDER_RING_BASE;
1379
1380 if (INTEL_INFO(dev)->gen >= 6) {
1381 ring->add_request = gen6_add_request;
1382 ring->flush = gen6_render_ring_flush;
1383 ring->irq_get = gen6_ring_get_irq;
1384 ring->irq_put = gen6_ring_put_irq;
1385 ring->irq_enable_mask = GT_USER_INTERRUPT;
1386 ring->get_seqno = gen6_ring_get_seqno;
1387 ring->sync_to = gen6_ring_sync;
1388 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1389 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1390 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1391 ring->signal_mbox[0] = GEN6_VRSYNC;
1392 ring->signal_mbox[1] = GEN6_BRSYNC;
1393 } else if (IS_GEN5(dev)) {
1394 ring->add_request = pc_render_add_request;
1395 ring->flush = gen4_render_ring_flush;
1396 ring->get_seqno = pc_render_get_seqno;
1397 ring->irq_get = gen5_ring_get_irq;
1398 ring->irq_put = gen5_ring_put_irq;
1399 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1400 } else {
1401 ring->add_request = i9xx_add_request;
1402 if (INTEL_INFO(dev)->gen < 4)
1403 ring->flush = gen2_render_ring_flush;
1404 else
1405 ring->flush = gen4_render_ring_flush;
1406 ring->get_seqno = ring_get_seqno;
1407 if (IS_GEN2(dev)) {
1408 ring->irq_get = i8xx_ring_get_irq;
1409 ring->irq_put = i8xx_ring_put_irq;
1410 } else {
1411 ring->irq_get = i9xx_ring_get_irq;
1412 ring->irq_put = i9xx_ring_put_irq;
1413 }
1414 ring->irq_enable_mask = I915_USER_INTERRUPT;
1415 }
1416 ring->write_tail = ring_write_tail;
1417 if (INTEL_INFO(dev)->gen >= 6)
1418 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1419 else if (INTEL_INFO(dev)->gen >= 4)
1420 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1421 else if (IS_I830(dev) || IS_845G(dev))
1422 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1423 else
1424 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1425 ring->init = init_render_ring;
1426 ring->cleanup = render_ring_cleanup;
1427
1428
1429 if (!I915_NEED_GFX_HWS(dev)) {
1430 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1431 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1432 }
1433
1434 return intel_init_ring_buffer(dev, ring);
1435 }
1436
1437 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1438 {
1439 drm_i915_private_t *dev_priv = dev->dev_private;
1440 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1441
1442 ring->name = "render ring";
1443 ring->id = RCS;
1444 ring->mmio_base = RENDER_RING_BASE;
1445
1446 if (INTEL_INFO(dev)->gen >= 6) {
1447 /* non-kms not supported on gen6+ */
1448 return -ENODEV;
1449 }
1450
1451 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1452 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1453 * the special gen5 functions. */
1454 ring->add_request = i9xx_add_request;
1455 if (INTEL_INFO(dev)->gen < 4)
1456 ring->flush = gen2_render_ring_flush;
1457 else
1458 ring->flush = gen4_render_ring_flush;
1459 ring->get_seqno = ring_get_seqno;
1460 if (IS_GEN2(dev)) {
1461 ring->irq_get = i8xx_ring_get_irq;
1462 ring->irq_put = i8xx_ring_put_irq;
1463 } else {
1464 ring->irq_get = i9xx_ring_get_irq;
1465 ring->irq_put = i9xx_ring_put_irq;
1466 }
1467 ring->irq_enable_mask = I915_USER_INTERRUPT;
1468 ring->write_tail = ring_write_tail;
1469 if (INTEL_INFO(dev)->gen >= 4)
1470 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1471 else if (IS_I830(dev) || IS_845G(dev))
1472 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1473 else
1474 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1475 ring->init = init_render_ring;
1476 ring->cleanup = render_ring_cleanup;
1477
1478 if (!I915_NEED_GFX_HWS(dev))
1479 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1480
1481 ring->dev = dev;
1482 INIT_LIST_HEAD(&ring->active_list);
1483 INIT_LIST_HEAD(&ring->request_list);
1484 INIT_LIST_HEAD(&ring->gpu_write_list);
1485
1486 ring->size = size;
1487 ring->effective_size = ring->size;
1488 if (IS_I830(ring->dev))
1489 ring->effective_size -= 128;
1490
1491 ring->virtual_start = ioremap_wc(start, size);
1492 if (ring->virtual_start == NULL) {
1493 DRM_ERROR("can not ioremap virtual address for"
1494 " ring buffer\n");
1495 return -ENOMEM;
1496 }
1497
1498 return 0;
1499 }
1500
1501 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1502 {
1503 drm_i915_private_t *dev_priv = dev->dev_private;
1504 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1505
1506 ring->name = "bsd ring";
1507 ring->id = VCS;
1508
1509 ring->write_tail = ring_write_tail;
1510 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1511 ring->mmio_base = GEN6_BSD_RING_BASE;
1512 /* gen6 bsd needs a special wa for tail updates */
1513 if (IS_GEN6(dev))
1514 ring->write_tail = gen6_bsd_ring_write_tail;
1515 ring->flush = gen6_ring_flush;
1516 ring->add_request = gen6_add_request;
1517 ring->get_seqno = gen6_ring_get_seqno;
1518 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1519 ring->irq_get = gen6_ring_get_irq;
1520 ring->irq_put = gen6_ring_put_irq;
1521 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1522 ring->sync_to = gen6_ring_sync;
1523 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1524 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1525 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1526 ring->signal_mbox[0] = GEN6_RVSYNC;
1527 ring->signal_mbox[1] = GEN6_BVSYNC;
1528 } else {
1529 ring->mmio_base = BSD_RING_BASE;
1530 ring->flush = bsd_ring_flush;
1531 ring->add_request = i9xx_add_request;
1532 ring->get_seqno = ring_get_seqno;
1533 if (IS_GEN5(dev)) {
1534 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1535 ring->irq_get = gen5_ring_get_irq;
1536 ring->irq_put = gen5_ring_put_irq;
1537 } else {
1538 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1539 ring->irq_get = i9xx_ring_get_irq;
1540 ring->irq_put = i9xx_ring_put_irq;
1541 }
1542 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1543 }
1544 ring->init = init_ring_common;
1545
1546
1547 return intel_init_ring_buffer(dev, ring);
1548 }
1549
1550 int intel_init_blt_ring_buffer(struct drm_device *dev)
1551 {
1552 drm_i915_private_t *dev_priv = dev->dev_private;
1553 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1554
1555 ring->name = "blitter ring";
1556 ring->id = BCS;
1557
1558 ring->mmio_base = BLT_RING_BASE;
1559 ring->write_tail = ring_write_tail;
1560 ring->flush = blt_ring_flush;
1561 ring->add_request = gen6_add_request;
1562 ring->get_seqno = gen6_ring_get_seqno;
1563 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1564 ring->irq_get = gen6_ring_get_irq;
1565 ring->irq_put = gen6_ring_put_irq;
1566 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1567 ring->sync_to = gen6_ring_sync;
1568 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1569 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1570 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1571 ring->signal_mbox[0] = GEN6_RBSYNC;
1572 ring->signal_mbox[1] = GEN6_VBSYNC;
1573 ring->init = init_ring_common;
1574
1575 return intel_init_ring_buffer(dev, ring);
1576 }
Linux ARM platform port for MOXA ART SoC