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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / i915 / intel_tv.c
blobbefce6c4970496a821e2a84b8b4e6bda29c04f9d
1 /*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29 /** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "drm_crtc.h"
36 #include "drm_edid.h"
37 #include "intel_drv.h"
38 #include "i915_drm.h"
39 #include "i915_drv.h"
40
41 enum tv_margin {
42 TV_MARGIN_LEFT, TV_MARGIN_TOP,
43 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
44 };
45
46 /** Private structure for the integrated TV support */
47 struct intel_tv {
48 struct intel_encoder base;
49
50 int type;
51 const char *tv_format;
52 int margin[4];
53 u32 save_TV_H_CTL_1;
54 u32 save_TV_H_CTL_2;
55 u32 save_TV_H_CTL_3;
56 u32 save_TV_V_CTL_1;
57 u32 save_TV_V_CTL_2;
58 u32 save_TV_V_CTL_3;
59 u32 save_TV_V_CTL_4;
60 u32 save_TV_V_CTL_5;
61 u32 save_TV_V_CTL_6;
62 u32 save_TV_V_CTL_7;
63 u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
64
65 u32 save_TV_CSC_Y;
66 u32 save_TV_CSC_Y2;
67 u32 save_TV_CSC_U;
68 u32 save_TV_CSC_U2;
69 u32 save_TV_CSC_V;
70 u32 save_TV_CSC_V2;
71 u32 save_TV_CLR_KNOBS;
72 u32 save_TV_CLR_LEVEL;
73 u32 save_TV_WIN_POS;
74 u32 save_TV_WIN_SIZE;
75 u32 save_TV_FILTER_CTL_1;
76 u32 save_TV_FILTER_CTL_2;
77 u32 save_TV_FILTER_CTL_3;
78
79 u32 save_TV_H_LUMA[60];
80 u32 save_TV_H_CHROMA[60];
81 u32 save_TV_V_LUMA[43];
82 u32 save_TV_V_CHROMA[43];
83
84 u32 save_TV_DAC;
85 u32 save_TV_CTL;
86 };
87
88 struct video_levels {
89 int blank, black, burst;
90 };
91
92 struct color_conversion {
93 u16 ry, gy, by, ay;
94 u16 ru, gu, bu, au;
95 u16 rv, gv, bv, av;
96 };
97
98 static const u32 filter_table[] = {
99 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
100 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
101 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
102 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
103 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
104 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
105 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
106 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
107 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
108 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
109 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
110 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
111 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
112 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
113 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
114 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
115 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
116 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
117 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
118 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
119 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
120 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
121 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
122 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
123 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
124 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
125 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
126 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
127 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
128 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
129 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
130 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
131 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
132 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
133 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
134 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
135 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
136 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
137 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
138 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
139 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
140 0x2D002CC0, 0x30003640, 0x2D0036C0,
141 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
142 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
143 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
144 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
145 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
146 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
147 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
148 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
149 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
150 0x28003100, 0x28002F00, 0x00003100,
151 };
152
153 /*
154 * Color conversion values have 3 separate fixed point formats:
155 *
156 * 10 bit fields (ay, au)
157 * 1.9 fixed point (b.bbbbbbbbb)
158 * 11 bit fields (ry, by, ru, gu, gv)
159 * exp.mantissa (ee.mmmmmmmmm)
160 * ee = 00 = 10^-1 (0.mmmmmmmmm)
161 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
162 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
163 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
164 * 12 bit fields (gy, rv, bu)
165 * exp.mantissa (eee.mmmmmmmmm)
166 * eee = 000 = 10^-1 (0.mmmmmmmmm)
167 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
168 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
169 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
170 * eee = 100 = reserved
171 * eee = 101 = reserved
172 * eee = 110 = reserved
173 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
174 *
175 * Saturation and contrast are 8 bits, with their own representation:
176 * 8 bit field (saturation, contrast)
177 * exp.mantissa (ee.mmmmmm)
178 * ee = 00 = 10^-1 (0.mmmmmm)
179 * ee = 01 = 10^0 (m.mmmmm)
180 * ee = 10 = 10^1 (mm.mmmm)
181 * ee = 11 = 10^2 (mmm.mmm)
182 *
183 * Simple conversion function:
184 *
185 * static u32
186 * float_to_csc_11(float f)
187 * {
188 * u32 exp;
189 * u32 mant;
190 * u32 ret;
191 *
192 * if (f < 0)
193 * f = -f;
194 *
195 * if (f >= 1) {
196 * exp = 0x7;
197 * mant = 1 << 8;
198 * } else {
199 * for (exp = 0; exp < 3 && f < 0.5; exp++)
200 * f *= 2.0;
201 * mant = (f * (1 << 9) + 0.5);
202 * if (mant >= (1 << 9))
203 * mant = (1 << 9) - 1;
204 * }
205 * ret = (exp << 9) | mant;
206 * return ret;
207 * }
208 */
209
210 /*
211 * Behold, magic numbers! If we plant them they might grow a big
212 * s-video cable to the sky... or something.
213 *
214 * Pre-converted to appropriate hex value.
215 */
216
217 /*
218 * PAL & NTSC values for composite & s-video connections
219 */
220 static const struct color_conversion ntsc_m_csc_composite = {
221 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
222 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
223 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
224 };
225
226 static const struct video_levels ntsc_m_levels_composite = {
227 .blank = 225, .black = 267, .burst = 113,
228 };
229
230 static const struct color_conversion ntsc_m_csc_svideo = {
231 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
232 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
233 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
234 };
235
236 static const struct video_levels ntsc_m_levels_svideo = {
237 .blank = 266, .black = 316, .burst = 133,
238 };
239
240 static const struct color_conversion ntsc_j_csc_composite = {
241 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
242 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
243 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
244 };
245
246 static const struct video_levels ntsc_j_levels_composite = {
247 .blank = 225, .black = 225, .burst = 113,
248 };
249
250 static const struct color_conversion ntsc_j_csc_svideo = {
251 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
252 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
253 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
254 };
255
256 static const struct video_levels ntsc_j_levels_svideo = {
257 .blank = 266, .black = 266, .burst = 133,
258 };
259
260 static const struct color_conversion pal_csc_composite = {
261 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
262 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
263 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
264 };
265
266 static const struct video_levels pal_levels_composite = {
267 .blank = 237, .black = 237, .burst = 118,
268 };
269
270 static const struct color_conversion pal_csc_svideo = {
271 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
272 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
273 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
274 };
275
276 static const struct video_levels pal_levels_svideo = {
277 .blank = 280, .black = 280, .burst = 139,
278 };
279
280 static const struct color_conversion pal_m_csc_composite = {
281 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
282 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
283 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
284 };
285
286 static const struct video_levels pal_m_levels_composite = {
287 .blank = 225, .black = 267, .burst = 113,
288 };
289
290 static const struct color_conversion pal_m_csc_svideo = {
291 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
292 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
293 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
294 };
295
296 static const struct video_levels pal_m_levels_svideo = {
297 .blank = 266, .black = 316, .burst = 133,
298 };
299
300 static const struct color_conversion pal_n_csc_composite = {
301 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
302 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
303 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
304 };
305
306 static const struct video_levels pal_n_levels_composite = {
307 .blank = 225, .black = 267, .burst = 118,
308 };
309
310 static const struct color_conversion pal_n_csc_svideo = {
311 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
312 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
313 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
314 };
315
316 static const struct video_levels pal_n_levels_svideo = {
317 .blank = 266, .black = 316, .burst = 139,
318 };
319
320 /*
321 * Component connections
322 */
323 static const struct color_conversion sdtv_csc_yprpb = {
324 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
325 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
326 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
327 };
328
329 static const struct color_conversion sdtv_csc_rgb = {
330 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
331 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
332 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
333 };
334
335 static const struct color_conversion hdtv_csc_yprpb = {
336 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
337 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
338 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
339 };
340
341 static const struct color_conversion hdtv_csc_rgb = {
342 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
343 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
344 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
345 };
346
347 static const struct video_levels component_levels = {
348 .blank = 279, .black = 279, .burst = 0,
349 };
350
351
352 struct tv_mode {
353 const char *name;
354 int clock;
355 int refresh; /* in millihertz (for precision) */
356 u32 oversample;
357 int hsync_end, hblank_start, hblank_end, htotal;
358 bool progressive, trilevel_sync, component_only;
359 int vsync_start_f1, vsync_start_f2, vsync_len;
360 bool veq_ena;
361 int veq_start_f1, veq_start_f2, veq_len;
362 int vi_end_f1, vi_end_f2, nbr_end;
363 bool burst_ena;
364 int hburst_start, hburst_len;
365 int vburst_start_f1, vburst_end_f1;
366 int vburst_start_f2, vburst_end_f2;
367 int vburst_start_f3, vburst_end_f3;
368 int vburst_start_f4, vburst_end_f4;
369 /*
370 * subcarrier programming
371 */
372 int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
373 u32 sc_reset;
374 bool pal_burst;
375 /*
376 * blank/black levels
377 */
378 const struct video_levels *composite_levels, *svideo_levels;
379 const struct color_conversion *composite_color, *svideo_color;
380 const u32 *filter_table;
381 int max_srcw;
382 };
383
384
385 /*
386 * Sub carrier DDA
387 *
388 * I think this works as follows:
389 *
390 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
391 *
392 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
393 *
394 * So,
395 * dda1_ideal = subcarrier/pixel * 4096
396 * dda1_inc = floor (dda1_ideal)
397 * dda2 = dda1_ideal - dda1_inc
398 *
399 * then pick a ratio for dda2 that gives the closest approximation. If
400 * you can't get close enough, you can play with dda3 as well. This
401 * seems likely to happen when dda2 is small as the jumps would be larger
402 *
403 * To invert this,
404 *
405 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
406 *
407 * The constants below were all computed using a 107.520MHz clock
408 */
409
410 /**
411 * Register programming values for TV modes.
412 *
413 * These values account for -1s required.
414 */
415
416 static const struct tv_mode tv_modes[] = {
417 {
418 .name = "NTSC-M",
419 .clock = 108000,
420 .refresh = 59940,
421 .oversample = TV_OVERSAMPLE_8X,
422 .component_only = 0,
423 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
424
425 .hsync_end = 64, .hblank_end = 124,
426 .hblank_start = 836, .htotal = 857,
427
428 .progressive = false, .trilevel_sync = false,
429
430 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
431 .vsync_len = 6,
432
433 .veq_ena = true, .veq_start_f1 = 0,
434 .veq_start_f2 = 1, .veq_len = 18,
435
436 .vi_end_f1 = 20, .vi_end_f2 = 21,
437 .nbr_end = 240,
438
439 .burst_ena = true,
440 .hburst_start = 72, .hburst_len = 34,
441 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
442 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
443 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
444 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
445
446 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
447 .dda1_inc = 135,
448 .dda2_inc = 20800, .dda2_size = 27456,
449 .dda3_inc = 0, .dda3_size = 0,
450 .sc_reset = TV_SC_RESET_EVERY_4,
451 .pal_burst = false,
452
453 .composite_levels = &ntsc_m_levels_composite,
454 .composite_color = &ntsc_m_csc_composite,
455 .svideo_levels = &ntsc_m_levels_svideo,
456 .svideo_color = &ntsc_m_csc_svideo,
457
458 .filter_table = filter_table,
459 },
460 {
461 .name = "NTSC-443",
462 .clock = 108000,
463 .refresh = 59940,
464 .oversample = TV_OVERSAMPLE_8X,
465 .component_only = 0,
466 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
467 .hsync_end = 64, .hblank_end = 124,
468 .hblank_start = 836, .htotal = 857,
469
470 .progressive = false, .trilevel_sync = false,
471
472 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
473 .vsync_len = 6,
474
475 .veq_ena = true, .veq_start_f1 = 0,
476 .veq_start_f2 = 1, .veq_len = 18,
477
478 .vi_end_f1 = 20, .vi_end_f2 = 21,
479 .nbr_end = 240,
480
481 .burst_ena = true,
482 .hburst_start = 72, .hburst_len = 34,
483 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
484 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
485 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
486 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
487
488 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
489 .dda1_inc = 168,
490 .dda2_inc = 4093, .dda2_size = 27456,
491 .dda3_inc = 310, .dda3_size = 525,
492 .sc_reset = TV_SC_RESET_NEVER,
493 .pal_burst = false,
494
495 .composite_levels = &ntsc_m_levels_composite,
496 .composite_color = &ntsc_m_csc_composite,
497 .svideo_levels = &ntsc_m_levels_svideo,
498 .svideo_color = &ntsc_m_csc_svideo,
499
500 .filter_table = filter_table,
501 },
502 {
503 .name = "NTSC-J",
504 .clock = 108000,
505 .refresh = 59940,
506 .oversample = TV_OVERSAMPLE_8X,
507 .component_only = 0,
508
509 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
510 .hsync_end = 64, .hblank_end = 124,
511 .hblank_start = 836, .htotal = 857,
512
513 .progressive = false, .trilevel_sync = false,
514
515 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
516 .vsync_len = 6,
517
518 .veq_ena = true, .veq_start_f1 = 0,
519 .veq_start_f2 = 1, .veq_len = 18,
520
521 .vi_end_f1 = 20, .vi_end_f2 = 21,
522 .nbr_end = 240,
523
524 .burst_ena = true,
525 .hburst_start = 72, .hburst_len = 34,
526 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
527 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
528 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
529 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
530
531 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
532 .dda1_inc = 135,
533 .dda2_inc = 20800, .dda2_size = 27456,
534 .dda3_inc = 0, .dda3_size = 0,
535 .sc_reset = TV_SC_RESET_EVERY_4,
536 .pal_burst = false,
537
538 .composite_levels = &ntsc_j_levels_composite,
539 .composite_color = &ntsc_j_csc_composite,
540 .svideo_levels = &ntsc_j_levels_svideo,
541 .svideo_color = &ntsc_j_csc_svideo,
542
543 .filter_table = filter_table,
544 },
545 {
546 .name = "PAL-M",
547 .clock = 108000,
548 .refresh = 59940,
549 .oversample = TV_OVERSAMPLE_8X,
550 .component_only = 0,
551
552 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
553 .hsync_end = 64, .hblank_end = 124,
554 .hblank_start = 836, .htotal = 857,
555
556 .progressive = false, .trilevel_sync = false,
557
558 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
559 .vsync_len = 6,
560
561 .veq_ena = true, .veq_start_f1 = 0,
562 .veq_start_f2 = 1, .veq_len = 18,
563
564 .vi_end_f1 = 20, .vi_end_f2 = 21,
565 .nbr_end = 240,
566
567 .burst_ena = true,
568 .hburst_start = 72, .hburst_len = 34,
569 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
570 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
571 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
572 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
573
574 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
575 .dda1_inc = 135,
576 .dda2_inc = 16704, .dda2_size = 27456,
577 .dda3_inc = 0, .dda3_size = 0,
578 .sc_reset = TV_SC_RESET_EVERY_8,
579 .pal_burst = true,
580
581 .composite_levels = &pal_m_levels_composite,
582 .composite_color = &pal_m_csc_composite,
583 .svideo_levels = &pal_m_levels_svideo,
584 .svideo_color = &pal_m_csc_svideo,
585
586 .filter_table = filter_table,
587 },
588 {
589 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
590 .name = "PAL-N",
591 .clock = 108000,
592 .refresh = 50000,
593 .oversample = TV_OVERSAMPLE_8X,
594 .component_only = 0,
595
596 .hsync_end = 64, .hblank_end = 128,
597 .hblank_start = 844, .htotal = 863,
598
599 .progressive = false, .trilevel_sync = false,
600
601
602 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
603 .vsync_len = 6,
604
605 .veq_ena = true, .veq_start_f1 = 0,
606 .veq_start_f2 = 1, .veq_len = 18,
607
608 .vi_end_f1 = 24, .vi_end_f2 = 25,
609 .nbr_end = 286,
610
611 .burst_ena = true,
612 .hburst_start = 73, .hburst_len = 34,
613 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
614 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
615 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
616 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
617
618
619 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
620 .dda1_inc = 135,
621 .dda2_inc = 23578, .dda2_size = 27648,
622 .dda3_inc = 134, .dda3_size = 625,
623 .sc_reset = TV_SC_RESET_EVERY_8,
624 .pal_burst = true,
625
626 .composite_levels = &pal_n_levels_composite,
627 .composite_color = &pal_n_csc_composite,
628 .svideo_levels = &pal_n_levels_svideo,
629 .svideo_color = &pal_n_csc_svideo,
630
631 .filter_table = filter_table,
632 },
633 {
634 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
635 .name = "PAL",
636 .clock = 108000,
637 .refresh = 50000,
638 .oversample = TV_OVERSAMPLE_8X,
639 .component_only = 0,
640
641 .hsync_end = 64, .hblank_end = 142,
642 .hblank_start = 844, .htotal = 863,
643
644 .progressive = false, .trilevel_sync = false,
645
646 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
647 .vsync_len = 5,
648
649 .veq_ena = true, .veq_start_f1 = 0,
650 .veq_start_f2 = 1, .veq_len = 15,
651
652 .vi_end_f1 = 24, .vi_end_f2 = 25,
653 .nbr_end = 286,
654
655 .burst_ena = true,
656 .hburst_start = 73, .hburst_len = 32,
657 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
658 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
659 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
660 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
661
662 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
663 .dda1_inc = 168,
664 .dda2_inc = 4122, .dda2_size = 27648,
665 .dda3_inc = 67, .dda3_size = 625,
666 .sc_reset = TV_SC_RESET_EVERY_8,
667 .pal_burst = true,
668
669 .composite_levels = &pal_levels_composite,
670 .composite_color = &pal_csc_composite,
671 .svideo_levels = &pal_levels_svideo,
672 .svideo_color = &pal_csc_svideo,
673
674 .filter_table = filter_table,
675 },
676 {
677 .name = "480p",
678 .clock = 107520,
679 .refresh = 59940,
680 .oversample = TV_OVERSAMPLE_4X,
681 .component_only = 1,
682
683 .hsync_end = 64, .hblank_end = 122,
684 .hblank_start = 842, .htotal = 857,
685
686 .progressive = true, .trilevel_sync = false,
687
688 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
689 .vsync_len = 12,
690
691 .veq_ena = false,
692
693 .vi_end_f1 = 44, .vi_end_f2 = 44,
694 .nbr_end = 479,
695
696 .burst_ena = false,
697
698 .filter_table = filter_table,
699 },
700 {
701 .name = "576p",
702 .clock = 107520,
703 .refresh = 50000,
704 .oversample = TV_OVERSAMPLE_4X,
705 .component_only = 1,
706
707 .hsync_end = 64, .hblank_end = 139,
708 .hblank_start = 859, .htotal = 863,
709
710 .progressive = true, .trilevel_sync = false,
711
712 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
713 .vsync_len = 10,
714
715 .veq_ena = false,
716
717 .vi_end_f1 = 48, .vi_end_f2 = 48,
718 .nbr_end = 575,
719
720 .burst_ena = false,
721
722 .filter_table = filter_table,
723 },
724 {
725 .name = "720p@60Hz",
726 .clock = 148800,
727 .refresh = 60000,
728 .oversample = TV_OVERSAMPLE_2X,
729 .component_only = 1,
730
731 .hsync_end = 80, .hblank_end = 300,
732 .hblank_start = 1580, .htotal = 1649,
733
734 .progressive = true, .trilevel_sync = true,
735
736 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
737 .vsync_len = 10,
738
739 .veq_ena = false,
740
741 .vi_end_f1 = 29, .vi_end_f2 = 29,
742 .nbr_end = 719,
743
744 .burst_ena = false,
745
746 .filter_table = filter_table,
747 },
748 {
749 .name = "720p@50Hz",
750 .clock = 148800,
751 .refresh = 50000,
752 .oversample = TV_OVERSAMPLE_2X,
753 .component_only = 1,
754
755 .hsync_end = 80, .hblank_end = 300,
756 .hblank_start = 1580, .htotal = 1979,
757
758 .progressive = true, .trilevel_sync = true,
759
760 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
761 .vsync_len = 10,
762
763 .veq_ena = false,
764
765 .vi_end_f1 = 29, .vi_end_f2 = 29,
766 .nbr_end = 719,
767
768 .burst_ena = false,
769
770 .filter_table = filter_table,
771 .max_srcw = 800
772 },
773 {
774 .name = "1080i@50Hz",
775 .clock = 148800,
776 .refresh = 50000,
777 .oversample = TV_OVERSAMPLE_2X,
778 .component_only = 1,
779
780 .hsync_end = 88, .hblank_end = 235,
781 .hblank_start = 2155, .htotal = 2639,
782
783 .progressive = false, .trilevel_sync = true,
784
785 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
786 .vsync_len = 10,
787
788 .veq_ena = true, .veq_start_f1 = 4,
789 .veq_start_f2 = 4, .veq_len = 10,
790
791
792 .vi_end_f1 = 21, .vi_end_f2 = 22,
793 .nbr_end = 539,
794
795 .burst_ena = false,
796
797 .filter_table = filter_table,
798 },
799 {
800 .name = "1080i@60Hz",
801 .clock = 148800,
802 .refresh = 60000,
803 .oversample = TV_OVERSAMPLE_2X,
804 .component_only = 1,
805
806 .hsync_end = 88, .hblank_end = 235,
807 .hblank_start = 2155, .htotal = 2199,
808
809 .progressive = false, .trilevel_sync = true,
810
811 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
812 .vsync_len = 10,
813
814 .veq_ena = true, .veq_start_f1 = 4,
815 .veq_start_f2 = 4, .veq_len = 10,
816
817
818 .vi_end_f1 = 21, .vi_end_f2 = 22,
819 .nbr_end = 539,
820
821 .burst_ena = false,
822
823 .filter_table = filter_table,
824 },
825 };
826
827 static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
828 {
829 return container_of(encoder, struct intel_tv, base.base);
830 }
831
832 static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
833 {
834 return container_of(intel_attached_encoder(connector),
835 struct intel_tv,
836 base);
837 }
838
839 static void
840 intel_tv_dpms(struct drm_encoder *encoder, int mode)
841 {
842 struct drm_device *dev = encoder->dev;
843 struct drm_i915_private *dev_priv = dev->dev_private;
844
845 switch (mode) {
846 case DRM_MODE_DPMS_ON:
847 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
848 break;
849 case DRM_MODE_DPMS_STANDBY:
850 case DRM_MODE_DPMS_SUSPEND:
851 case DRM_MODE_DPMS_OFF:
852 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
853 break;
854 }
855 }
856
857 static const struct tv_mode *
858 intel_tv_mode_lookup(const char *tv_format)
859 {
860 int i;
861
862 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
863 const struct tv_mode *tv_mode = &tv_modes[i];
864
865 if (!strcmp(tv_format, tv_mode->name))
866 return tv_mode;
867 }
868 return NULL;
869 }
870
871 static const struct tv_mode *
872 intel_tv_mode_find(struct intel_tv *intel_tv)
873 {
874 return intel_tv_mode_lookup(intel_tv->tv_format);
875 }
876
877 static enum drm_mode_status
878 intel_tv_mode_valid(struct drm_connector *connector,
879 struct drm_display_mode *mode)
880 {
881 struct intel_tv *intel_tv = intel_attached_tv(connector);
882 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
883
884 /* Ensure TV refresh is close to desired refresh */
885 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
886 < 1000)
887 return MODE_OK;
888
889 return MODE_CLOCK_RANGE;
890 }
891
892
893 static bool
894 intel_tv_mode_fixup(struct drm_encoder *encoder,
895 const struct drm_display_mode *mode,
896 struct drm_display_mode *adjusted_mode)
897 {
898 struct drm_device *dev = encoder->dev;
899 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
900 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
901 struct intel_encoder *other_encoder;
902
903 if (!tv_mode)
904 return false;
905
906 for_each_encoder_on_crtc(dev, encoder->crtc, other_encoder)
907 if (&other_encoder->base != encoder)
908 return false;
909
910 adjusted_mode->clock = tv_mode->clock;
911 return true;
912 }
913
914 static void
915 intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
916 struct drm_display_mode *adjusted_mode)
917 {
918 struct drm_device *dev = encoder->dev;
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 struct drm_crtc *crtc = encoder->crtc;
921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
922 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
923 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
924 u32 tv_ctl;
925 u32 hctl1, hctl2, hctl3;
926 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
927 u32 scctl1, scctl2, scctl3;
928 int i, j;
929 const struct video_levels *video_levels;
930 const struct color_conversion *color_conversion;
931 bool burst_ena;
932 int pipe = intel_crtc->pipe;
933
934 if (!tv_mode)
935 return; /* can't happen (mode_prepare prevents this) */
936
937 tv_ctl = I915_READ(TV_CTL);
938 tv_ctl &= TV_CTL_SAVE;
939
940 switch (intel_tv->type) {
941 default:
942 case DRM_MODE_CONNECTOR_Unknown:
943 case DRM_MODE_CONNECTOR_Composite:
944 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
945 video_levels = tv_mode->composite_levels;
946 color_conversion = tv_mode->composite_color;
947 burst_ena = tv_mode->burst_ena;
948 break;
949 case DRM_MODE_CONNECTOR_Component:
950 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
951 video_levels = &component_levels;
952 if (tv_mode->burst_ena)
953 color_conversion = &sdtv_csc_yprpb;
954 else
955 color_conversion = &hdtv_csc_yprpb;
956 burst_ena = false;
957 break;
958 case DRM_MODE_CONNECTOR_SVIDEO:
959 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
960 video_levels = tv_mode->svideo_levels;
961 color_conversion = tv_mode->svideo_color;
962 burst_ena = tv_mode->burst_ena;
963 break;
964 }
965 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
966 (tv_mode->htotal << TV_HTOTAL_SHIFT);
967
968 hctl2 = (tv_mode->hburst_start << 16) |
969 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
970
971 if (burst_ena)
972 hctl2 |= TV_BURST_ENA;
973
974 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
975 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
976
977 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
978 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
979 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
980
981 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
982 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
983 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
984
985 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
986 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
987 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
988
989 if (tv_mode->veq_ena)
990 vctl3 |= TV_EQUAL_ENA;
991
992 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
993 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
994
995 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
996 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
997
998 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
999 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1000
1001 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1002 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1003
1004 if (intel_crtc->pipe == 1)
1005 tv_ctl |= TV_ENC_PIPEB_SELECT;
1006 tv_ctl |= tv_mode->oversample;
1007
1008 if (tv_mode->progressive)
1009 tv_ctl |= TV_PROGRESSIVE;
1010 if (tv_mode->trilevel_sync)
1011 tv_ctl |= TV_TRILEVEL_SYNC;
1012 if (tv_mode->pal_burst)
1013 tv_ctl |= TV_PAL_BURST;
1014
1015 scctl1 = 0;
1016 if (tv_mode->dda1_inc)
1017 scctl1 |= TV_SC_DDA1_EN;
1018 if (tv_mode->dda2_inc)
1019 scctl1 |= TV_SC_DDA2_EN;
1020 if (tv_mode->dda3_inc)
1021 scctl1 |= TV_SC_DDA3_EN;
1022 scctl1 |= tv_mode->sc_reset;
1023 if (video_levels)
1024 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1025 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1026
1027 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1028 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1029
1030 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1031 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1032
1033 /* Enable two fixes for the chips that need them. */
1034 if (dev->pci_device < 0x2772)
1035 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1036
1037 I915_WRITE(TV_H_CTL_1, hctl1);
1038 I915_WRITE(TV_H_CTL_2, hctl2);
1039 I915_WRITE(TV_H_CTL_3, hctl3);
1040 I915_WRITE(TV_V_CTL_1, vctl1);
1041 I915_WRITE(TV_V_CTL_2, vctl2);
1042 I915_WRITE(TV_V_CTL_3, vctl3);
1043 I915_WRITE(TV_V_CTL_4, vctl4);
1044 I915_WRITE(TV_V_CTL_5, vctl5);
1045 I915_WRITE(TV_V_CTL_6, vctl6);
1046 I915_WRITE(TV_V_CTL_7, vctl7);
1047 I915_WRITE(TV_SC_CTL_1, scctl1);
1048 I915_WRITE(TV_SC_CTL_2, scctl2);
1049 I915_WRITE(TV_SC_CTL_3, scctl3);
1050
1051 if (color_conversion) {
1052 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1053 color_conversion->gy);
1054 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
1055 color_conversion->ay);
1056 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1057 color_conversion->gu);
1058 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1059 color_conversion->au);
1060 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1061 color_conversion->gv);
1062 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1063 color_conversion->av);
1064 }
1065
1066 if (INTEL_INFO(dev)->gen >= 4)
1067 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1068 else
1069 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1070
1071 if (video_levels)
1072 I915_WRITE(TV_CLR_LEVEL,
1073 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1074 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1075 {
1076 int pipeconf_reg = PIPECONF(pipe);
1077 int dspcntr_reg = DSPCNTR(intel_crtc->plane);
1078 int pipeconf = I915_READ(pipeconf_reg);
1079 int dspcntr = I915_READ(dspcntr_reg);
1080 int dspbase_reg = DSPADDR(intel_crtc->plane);
1081 int xpos = 0x0, ypos = 0x0;
1082 unsigned int xsize, ysize;
1083 /* Pipe must be off here */
1084 I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
1085 /* Flush the plane changes */
1086 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1087
1088 /* Wait for vblank for the disable to take effect */
1089 if (IS_GEN2(dev))
1090 intel_wait_for_vblank(dev, intel_crtc->pipe);
1091
1092 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
1093 /* Wait for vblank for the disable to take effect. */
1094 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
1095
1096 /* Filter ctl must be set before TV_WIN_SIZE */
1097 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1098 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1099 if (tv_mode->progressive)
1100 ysize = tv_mode->nbr_end + 1;
1101 else
1102 ysize = 2*tv_mode->nbr_end + 1;
1103
1104 xpos += intel_tv->margin[TV_MARGIN_LEFT];
1105 ypos += intel_tv->margin[TV_MARGIN_TOP];
1106 xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1107 intel_tv->margin[TV_MARGIN_RIGHT]);
1108 ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1109 intel_tv->margin[TV_MARGIN_BOTTOM]);
1110 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1111 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1112
1113 I915_WRITE(pipeconf_reg, pipeconf);
1114 I915_WRITE(dspcntr_reg, dspcntr);
1115 /* Flush the plane changes */
1116 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1117 }
1118
1119 j = 0;
1120 for (i = 0; i < 60; i++)
1121 I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1122 for (i = 0; i < 60; i++)
1123 I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1124 for (i = 0; i < 43; i++)
1125 I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1126 for (i = 0; i < 43; i++)
1127 I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1128 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
1129 I915_WRITE(TV_CTL, tv_ctl);
1130 }
1131
1132 static const struct drm_display_mode reported_modes[] = {
1133 {
1134 .name = "NTSC 480i",
1135 .clock = 107520,
1136 .hdisplay = 1280,
1137 .hsync_start = 1368,
1138 .hsync_end = 1496,
1139 .htotal = 1712,
1140
1141 .vdisplay = 1024,
1142 .vsync_start = 1027,
1143 .vsync_end = 1034,
1144 .vtotal = 1104,
1145 .type = DRM_MODE_TYPE_DRIVER,
1146 },
1147 };
1148
1149 /**
1150 * Detects TV presence by checking for load.
1151 *
1152 * Requires that the current pipe's DPLL is active.
1153
1154 * \return true if TV is connected.
1155 * \return false if TV is disconnected.
1156 */
1157 static int
1158 intel_tv_detect_type(struct intel_tv *intel_tv,
1159 struct drm_connector *connector)
1160 {
1161 struct drm_encoder *encoder = &intel_tv->base.base;
1162 struct drm_crtc *crtc = encoder->crtc;
1163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1164 struct drm_device *dev = encoder->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 unsigned long irqflags;
1167 u32 tv_ctl, save_tv_ctl;
1168 u32 tv_dac, save_tv_dac;
1169 int type;
1170
1171 /* Disable TV interrupts around load detect or we'll recurse */
1172 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1173 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1174 i915_disable_pipestat(dev_priv, 0,
1175 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1176 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1177 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1178 }
1179
1180 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1181 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1182
1183 /* Poll for TV detection */
1184 tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
1185 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1186 if (intel_crtc->pipe == 1)
1187 tv_ctl |= TV_ENC_PIPEB_SELECT;
1188 else
1189 tv_ctl &= ~TV_ENC_PIPEB_SELECT;
1190
1191 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1192 tv_dac |= (TVDAC_STATE_CHG_EN |
1193 TVDAC_A_SENSE_CTL |
1194 TVDAC_B_SENSE_CTL |
1195 TVDAC_C_SENSE_CTL |
1196 DAC_CTL_OVERRIDE |
1197 DAC_A_0_7_V |
1198 DAC_B_0_7_V |
1199 DAC_C_0_7_V);
1200
1201
1202 /*
1203 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1204 * the TV is misdetected. This is hardware requirement.
1205 */
1206 if (IS_GM45(dev))
1207 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1208 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1209
1210 I915_WRITE(TV_CTL, tv_ctl);
1211 I915_WRITE(TV_DAC, tv_dac);
1212 POSTING_READ(TV_DAC);
1213
1214 intel_wait_for_vblank(intel_tv->base.base.dev,
1215 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1216
1217 type = -1;
1218 tv_dac = I915_READ(TV_DAC);
1219 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1220 /*
1221 * A B C
1222 * 0 1 1 Composite
1223 * 1 0 X svideo
1224 * 0 0 0 Component
1225 */
1226 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1227 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1228 type = DRM_MODE_CONNECTOR_Composite;
1229 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1230 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1231 type = DRM_MODE_CONNECTOR_SVIDEO;
1232 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1233 DRM_DEBUG_KMS("Detected Component TV connection\n");
1234 type = DRM_MODE_CONNECTOR_Component;
1235 } else {
1236 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1237 type = -1;
1238 }
1239
1240 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1241 I915_WRITE(TV_CTL, save_tv_ctl);
1242 POSTING_READ(TV_CTL);
1243
1244 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1245 intel_wait_for_vblank(intel_tv->base.base.dev,
1246 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1247
1248 /* Restore interrupt config */
1249 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1250 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1251 i915_enable_pipestat(dev_priv, 0,
1252 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1253 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1254 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1255 }
1256
1257 return type;
1258 }
1259
1260 /*
1261 * Here we set accurate tv format according to connector type
1262 * i.e Component TV should not be assigned by NTSC or PAL
1263 */
1264 static void intel_tv_find_better_format(struct drm_connector *connector)
1265 {
1266 struct intel_tv *intel_tv = intel_attached_tv(connector);
1267 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1268 int i;
1269
1270 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1271 tv_mode->component_only)
1272 return;
1273
1274
1275 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1276 tv_mode = tv_modes + i;
1277
1278 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1279 tv_mode->component_only)
1280 break;
1281 }
1282
1283 intel_tv->tv_format = tv_mode->name;
1284 drm_connector_property_set_value(connector,
1285 connector->dev->mode_config.tv_mode_property, i);
1286 }
1287
1288 /**
1289 * Detect the TV connection.
1290 *
1291 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1292 * we have a pipe programmed in order to probe the TV.
1293 */
1294 static enum drm_connector_status
1295 intel_tv_detect(struct drm_connector *connector, bool force)
1296 {
1297 struct drm_display_mode mode;
1298 struct intel_tv *intel_tv = intel_attached_tv(connector);
1299 int type;
1300
1301 mode = reported_modes[0];
1302
1303 if (force) {
1304 struct intel_load_detect_pipe tmp;
1305
1306 if (intel_get_load_detect_pipe(&intel_tv->base, connector,
1307 &mode, &tmp)) {
1308 type = intel_tv_detect_type(intel_tv, connector);
1309 intel_release_load_detect_pipe(&intel_tv->base,
1310 connector,
1311 &tmp);
1312 } else
1313 return connector_status_unknown;
1314 } else
1315 return connector->status;
1316
1317 if (type < 0)
1318 return connector_status_disconnected;
1319
1320 intel_tv->type = type;
1321 intel_tv_find_better_format(connector);
1322
1323 return connector_status_connected;
1324 }
1325
1326 static const struct input_res {
1327 const char *name;
1328 int w, h;
1329 } input_res_table[] = {
1330 {"640x480", 640, 480},
1331 {"800x600", 800, 600},
1332 {"1024x768", 1024, 768},
1333 {"1280x1024", 1280, 1024},
1334 {"848x480", 848, 480},
1335 {"1280x720", 1280, 720},
1336 {"1920x1080", 1920, 1080},
1337 };
1338
1339 /*
1340 * Chose preferred mode according to line number of TV format
1341 */
1342 static void
1343 intel_tv_chose_preferred_modes(struct drm_connector *connector,
1344 struct drm_display_mode *mode_ptr)
1345 {
1346 struct intel_tv *intel_tv = intel_attached_tv(connector);
1347 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1348
1349 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1350 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1351 else if (tv_mode->nbr_end > 480) {
1352 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1353 if (mode_ptr->vdisplay == 720)
1354 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1355 } else if (mode_ptr->vdisplay == 1080)
1356 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1357 }
1358 }
1359
1360 /**
1361 * Stub get_modes function.
1362 *
1363 * This should probably return a set of fixed modes, unless we can figure out
1364 * how to probe modes off of TV connections.
1365 */
1366
1367 static int
1368 intel_tv_get_modes(struct drm_connector *connector)
1369 {
1370 struct drm_display_mode *mode_ptr;
1371 struct intel_tv *intel_tv = intel_attached_tv(connector);
1372 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1373 int j, count = 0;
1374 u64 tmp;
1375
1376 for (j = 0; j < ARRAY_SIZE(input_res_table);
1377 j++) {
1378 const struct input_res *input = &input_res_table[j];
1379 unsigned int hactive_s = input->w;
1380 unsigned int vactive_s = input->h;
1381
1382 if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1383 continue;
1384
1385 if (input->w > 1024 && (!tv_mode->progressive
1386 && !tv_mode->component_only))
1387 continue;
1388
1389 mode_ptr = drm_mode_create(connector->dev);
1390 if (!mode_ptr)
1391 continue;
1392 strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1393
1394 mode_ptr->hdisplay = hactive_s;
1395 mode_ptr->hsync_start = hactive_s + 1;
1396 mode_ptr->hsync_end = hactive_s + 64;
1397 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1398 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1399 mode_ptr->htotal = hactive_s + 96;
1400
1401 mode_ptr->vdisplay = vactive_s;
1402 mode_ptr->vsync_start = vactive_s + 1;
1403 mode_ptr->vsync_end = vactive_s + 32;
1404 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1405 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1406 mode_ptr->vtotal = vactive_s + 33;
1407
1408 tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
1409 tmp *= mode_ptr->htotal;
1410 tmp = div_u64(tmp, 1000000);
1411 mode_ptr->clock = (int) tmp;
1412
1413 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1414 intel_tv_chose_preferred_modes(connector, mode_ptr);
1415 drm_mode_probed_add(connector, mode_ptr);
1416 count++;
1417 }
1418
1419 return count;
1420 }
1421
1422 static void
1423 intel_tv_destroy(struct drm_connector *connector)
1424 {
1425 drm_sysfs_connector_remove(connector);
1426 drm_connector_cleanup(connector);
1427 kfree(connector);
1428 }
1429
1430
1431 static int
1432 intel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
1433 uint64_t val)
1434 {
1435 struct drm_device *dev = connector->dev;
1436 struct intel_tv *intel_tv = intel_attached_tv(connector);
1437 struct drm_crtc *crtc = intel_tv->base.base.crtc;
1438 int ret = 0;
1439 bool changed = false;
1440
1441 ret = drm_connector_property_set_value(connector, property, val);
1442 if (ret < 0)
1443 goto out;
1444
1445 if (property == dev->mode_config.tv_left_margin_property &&
1446 intel_tv->margin[TV_MARGIN_LEFT] != val) {
1447 intel_tv->margin[TV_MARGIN_LEFT] = val;
1448 changed = true;
1449 } else if (property == dev->mode_config.tv_right_margin_property &&
1450 intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1451 intel_tv->margin[TV_MARGIN_RIGHT] = val;
1452 changed = true;
1453 } else if (property == dev->mode_config.tv_top_margin_property &&
1454 intel_tv->margin[TV_MARGIN_TOP] != val) {
1455 intel_tv->margin[TV_MARGIN_TOP] = val;
1456 changed = true;
1457 } else if (property == dev->mode_config.tv_bottom_margin_property &&
1458 intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1459 intel_tv->margin[TV_MARGIN_BOTTOM] = val;
1460 changed = true;
1461 } else if (property == dev->mode_config.tv_mode_property) {
1462 if (val >= ARRAY_SIZE(tv_modes)) {
1463 ret = -EINVAL;
1464 goto out;
1465 }
1466 if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
1467 goto out;
1468
1469 intel_tv->tv_format = tv_modes[val].name;
1470 changed = true;
1471 } else {
1472 ret = -EINVAL;
1473 goto out;
1474 }
1475
1476 if (changed && crtc)
1477 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1478 crtc->y, crtc->fb);
1479 out:
1480 return ret;
1481 }
1482
1483 static const struct drm_encoder_helper_funcs intel_tv_helper_funcs = {
1484 .dpms = intel_tv_dpms,
1485 .mode_fixup = intel_tv_mode_fixup,
1486 .prepare = intel_encoder_prepare,
1487 .mode_set = intel_tv_mode_set,
1488 .commit = intel_encoder_commit,
1489 };
1490
1491 static const struct drm_connector_funcs intel_tv_connector_funcs = {
1492 .dpms = drm_helper_connector_dpms,
1493 .detect = intel_tv_detect,
1494 .destroy = intel_tv_destroy,
1495 .set_property = intel_tv_set_property,
1496 .fill_modes = drm_helper_probe_single_connector_modes,
1497 };
1498
1499 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1500 .mode_valid = intel_tv_mode_valid,
1501 .get_modes = intel_tv_get_modes,
1502 .best_encoder = intel_best_encoder,
1503 };
1504
1505 static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1506 .destroy = intel_encoder_destroy,
1507 };
1508
1509 /*
1510 * Enumerate the child dev array parsed from VBT to check whether
1511 * the integrated TV is present.
1512 * If it is present, return 1.
1513 * If it is not present, return false.
1514 * If no child dev is parsed from VBT, it assumes that the TV is present.
1515 */
1516 static int tv_is_present_in_vbt(struct drm_device *dev)
1517 {
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 struct child_device_config *p_child;
1520 int i, ret;
1521
1522 if (!dev_priv->child_dev_num)
1523 return 1;
1524
1525 ret = 0;
1526 for (i = 0; i < dev_priv->child_dev_num; i++) {
1527 p_child = dev_priv->child_dev + i;
1528 /*
1529 * If the device type is not TV, continue.
1530 */
1531 if (p_child->device_type != DEVICE_TYPE_INT_TV &&
1532 p_child->device_type != DEVICE_TYPE_TV)
1533 continue;
1534 /* Only when the addin_offset is non-zero, it is regarded
1535 * as present.
1536 */
1537 if (p_child->addin_offset) {
1538 ret = 1;
1539 break;
1540 }
1541 }
1542 return ret;
1543 }
1544
1545 void
1546 intel_tv_init(struct drm_device *dev)
1547 {
1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 struct drm_connector *connector;
1550 struct intel_tv *intel_tv;
1551 struct intel_encoder *intel_encoder;
1552 struct intel_connector *intel_connector;
1553 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1554 char *tv_format_names[ARRAY_SIZE(tv_modes)];
1555 int i, initial_mode = 0;
1556
1557 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1558 return;
1559
1560 if (!tv_is_present_in_vbt(dev)) {
1561 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1562 return;
1563 }
1564 /* Even if we have an encoder we may not have a connector */
1565 if (!dev_priv->int_tv_support)
1566 return;
1567
1568 /*
1569 * Sanity check the TV output by checking to see if the
1570 * DAC register holds a value
1571 */
1572 save_tv_dac = I915_READ(TV_DAC);
1573
1574 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1575 tv_dac_on = I915_READ(TV_DAC);
1576
1577 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1578 tv_dac_off = I915_READ(TV_DAC);
1579
1580 I915_WRITE(TV_DAC, save_tv_dac);
1581
1582 /*
1583 * If the register does not hold the state change enable
1584 * bit, (either as a 0 or a 1), assume it doesn't really
1585 * exist
1586 */
1587 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1588 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1589 return;
1590
1591 intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
1592 if (!intel_tv) {
1593 return;
1594 }
1595
1596 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1597 if (!intel_connector) {
1598 kfree(intel_tv);
1599 return;
1600 }
1601
1602 intel_encoder = &intel_tv->base;
1603 connector = &intel_connector->base;
1604
1605 /* The documentation, for the older chipsets at least, recommend
1606 * using a polling method rather than hotplug detection for TVs.
1607 * This is because in order to perform the hotplug detection, the PLLs
1608 * for the TV must be kept alive increasing power drain and starving
1609 * bandwidth from other encoders. Notably for instance, it causes
1610 * pipe underruns on Crestline when this encoder is supposedly idle.
1611 *
1612 * More recent chipsets favour HDMI rather than integrated S-Video.
1613 */
1614 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1615
1616 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1617 DRM_MODE_CONNECTOR_SVIDEO);
1618
1619 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1620 DRM_MODE_ENCODER_TVDAC);
1621
1622 intel_connector_attach_encoder(intel_connector, intel_encoder);
1623 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1624 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1625 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT);
1626 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1627 intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1628 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1629
1630 /* BIOS margin values */
1631 intel_tv->margin[TV_MARGIN_LEFT] = 54;
1632 intel_tv->margin[TV_MARGIN_TOP] = 36;
1633 intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1634 intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
1635
1636 intel_tv->tv_format = tv_modes[initial_mode].name;
1637
1638 drm_encoder_helper_add(&intel_encoder->base, &intel_tv_helper_funcs);
1639 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1640 connector->interlace_allowed = false;
1641 connector->doublescan_allowed = false;
1642
1643 /* Create TV properties then attach current values */
1644 for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
1645 tv_format_names[i] = (char *)tv_modes[i].name;
1646 drm_mode_create_tv_properties(dev,
1647 ARRAY_SIZE(tv_modes),
1648 tv_format_names);
1649
1650 drm_connector_attach_property(connector, dev->mode_config.tv_mode_property,
1651 initial_mode);
1652 drm_connector_attach_property(connector,
1653 dev->mode_config.tv_left_margin_property,
1654 intel_tv->margin[TV_MARGIN_LEFT]);
1655 drm_connector_attach_property(connector,
1656 dev->mode_config.tv_top_margin_property,
1657 intel_tv->margin[TV_MARGIN_TOP]);
1658 drm_connector_attach_property(connector,
1659 dev->mode_config.tv_right_margin_property,
1660 intel_tv->margin[TV_MARGIN_RIGHT]);
1661 drm_connector_attach_property(connector,
1662 dev->mode_config.tv_bottom_margin_property,
1663 intel_tv->margin[TV_MARGIN_BOTTOM]);
1664 drm_sysfs_connector_add(connector);
1665 }
Linux ARM platform port for MOXA ART SoC