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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
bloba0a3fe3c016be86665db1369c44bef832f829a1a
1 /*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "drmP.h"
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_gpio.h"
31
32 #include <linux/io-mapping.h>
33 #include <linux/firmware.h>
34
35 /* these defines are made up */
36 #define NV_CIO_CRE_44_HEADA 0x0
37 #define NV_CIO_CRE_44_HEADB 0x3
38 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
39
40 #define EDID1_LEN 128
41
42 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
43 #define LOG_OLD_VALUE(x)
44
45 struct init_exec {
46 bool execute;
47 bool repeat;
48 };
49
50 static bool nv_cksum(const uint8_t *data, unsigned int length)
51 {
52 /*
53 * There's a few checksums in the BIOS, so here's a generic checking
54 * function.
55 */
56 int i;
57 uint8_t sum = 0;
58
59 for (i = 0; i < length; i++)
60 sum += data[i];
61
62 if (sum)
63 return true;
64
65 return false;
66 }
67
68 static int
69 score_vbios(struct nvbios *bios, const bool writeable)
70 {
71 if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) {
72 NV_TRACEWARN(bios->dev, "... BIOS signature not found\n");
73 return 0;
74 }
75
76 if (nv_cksum(bios->data, bios->data[2] * 512)) {
77 NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n");
78 /* if a ro image is somewhat bad, it's probably all rubbish */
79 return writeable ? 2 : 1;
80 }
81
82 NV_TRACE(bios->dev, "... appears to be valid\n");
83 return 3;
84 }
85
86 static void
87 bios_shadow_prom(struct nvbios *bios)
88 {
89 struct drm_device *dev = bios->dev;
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 u32 pcireg, access;
92 u16 pcir;
93 int i;
94
95 /* enable access to rom */
96 if (dev_priv->card_type >= NV_50)
97 pcireg = 0x088050;
98 else
99 pcireg = NV_PBUS_PCI_NV_20;
100 access = nv_mask(dev, pcireg, 0x00000001, 0x00000000);
101
102 /* bail if no rom signature, with a workaround for a PROM reading
103 * issue on some chipsets. the first read after a period of
104 * inactivity returns the wrong result, so retry the first header
105 * byte a few times before giving up as a workaround
106 */
107 i = 16;
108 do {
109 if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55)
110 break;
111 } while (i--);
112
113 if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
114 goto out;
115
116 /* additional check (see note below) - read PCI record header */
117 pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
118 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
119 if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' ||
120 nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' ||
121 nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' ||
122 nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R')
123 goto out;
124
125 /* read entire bios image to system memory */
126 bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512;
127 bios->data = kmalloc(bios->length, GFP_KERNEL);
128 if (bios->data) {
129 for (i = 0; i < bios->length; i++)
130 bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
131 }
132
133 out:
134 /* disable access to rom */
135 nv_wr32(dev, pcireg, access);
136 }
137
138 static void
139 bios_shadow_pramin(struct nvbios *bios)
140 {
141 struct drm_device *dev = bios->dev;
142 struct drm_nouveau_private *dev_priv = dev->dev_private;
143 u32 bar0 = 0;
144 int i;
145
146 if (dev_priv->card_type >= NV_50) {
147 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
148 if (!addr) {
149 addr = (u64)nv_rd32(dev, 0x001700) << 16;
150 addr += 0xf0000;
151 }
152
153 bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16);
154 }
155
156 /* bail if no rom signature */
157 if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 ||
158 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
159 goto out;
160
161 bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512;
162 bios->data = kmalloc(bios->length, GFP_KERNEL);
163 if (bios->data) {
164 for (i = 0; i < bios->length; i++)
165 bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
166 }
167
168 out:
169 if (dev_priv->card_type >= NV_50)
170 nv_wr32(dev, 0x001700, bar0);
171 }
172
173 static void
174 bios_shadow_pci(struct nvbios *bios)
175 {
176 struct pci_dev *pdev = bios->dev->pdev;
177 size_t length;
178
179 if (!pci_enable_rom(pdev)) {
180 void __iomem *rom = pci_map_rom(pdev, &length);
181 if (rom && length) {
182 bios->data = kmalloc(length, GFP_KERNEL);
183 if (bios->data) {
184 memcpy_fromio(bios->data, rom, length);
185 bios->length = length;
186 }
187 }
188 if (rom)
189 pci_unmap_rom(pdev, rom);
190
191 pci_disable_rom(pdev);
192 }
193 }
194
195 static void
196 bios_shadow_acpi(struct nvbios *bios)
197 {
198 struct pci_dev *pdev = bios->dev->pdev;
199 int cnt = 65536 / ROM_BIOS_PAGE;
200 int ret;
201
202 if (!nouveau_acpi_rom_supported(pdev))
203 return;
204
205 bios->data = kmalloc(cnt * ROM_BIOS_PAGE, GFP_KERNEL);
206 if (!bios->data)
207 return;
208
209 bios->length = 0;
210 while (cnt--) {
211 ret = nouveau_acpi_get_bios_chunk(bios->data, bios->length,
212 ROM_BIOS_PAGE);
213 if (ret != ROM_BIOS_PAGE)
214 return;
215
216 bios->length += ROM_BIOS_PAGE;
217 }
218 }
219
220 struct methods {
221 const char desc[8];
222 void (*shadow)(struct nvbios *);
223 const bool rw;
224 int score;
225 u32 size;
226 u8 *data;
227 };
228
229 static bool
230 bios_shadow(struct drm_device *dev)
231 {
232 struct methods shadow_methods[] = {
233 { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL },
234 { "PROM", bios_shadow_prom, false, 0, 0, NULL },
235 { "ACPI", bios_shadow_acpi, true, 0, 0, NULL },
236 { "PCIROM", bios_shadow_pci, true, 0, 0, NULL },
237 {}
238 };
239 struct drm_nouveau_private *dev_priv = dev->dev_private;
240 struct nvbios *bios = &dev_priv->vbios;
241 struct methods *mthd, *best;
242 const struct firmware *fw;
243 char fname[32];
244 int ret;
245
246 if (nouveau_vbios) {
247 /* try to match one of the built-in methods */
248 mthd = shadow_methods;
249 do {
250 if (strcasecmp(nouveau_vbios, mthd->desc))
251 continue;
252 NV_INFO(dev, "VBIOS source: %s\n", mthd->desc);
253
254 mthd->shadow(bios);
255 mthd->score = score_vbios(bios, mthd->rw);
256 if (mthd->score)
257 return true;
258 } while ((++mthd)->shadow);
259
260 /* attempt to load firmware image */
261 snprintf(fname, sizeof(fname), "nouveau/%s", nouveau_vbios);
262 ret = request_firmware(&fw, fname, &dev->pdev->dev);
263 if (ret == 0) {
264 bios->length = fw->size;
265 bios->data = kmemdup(fw->data, fw->size, GFP_KERNEL);
266 release_firmware(fw);
267
268 NV_INFO(dev, "VBIOS image: %s\n", nouveau_vbios);
269 if (score_vbios(bios, 1))
270 return true;
271
272 kfree(bios->data);
273 bios->data = NULL;
274 }
275
276 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
277 }
278
279 mthd = shadow_methods;
280 do {
281 NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc);
282 mthd->shadow(bios);
283 mthd->score = score_vbios(bios, mthd->rw);
284 mthd->size = bios->length;
285 mthd->data = bios->data;
286 bios->data = NULL;
287 } while (mthd->score != 3 && (++mthd)->shadow);
288
289 mthd = shadow_methods;
290 best = mthd;
291 do {
292 if (mthd->score > best->score) {
293 kfree(best->data);
294 best = mthd;
295 }
296 } while ((++mthd)->shadow);
297
298 if (best->score) {
299 NV_TRACE(dev, "Using VBIOS from %s\n", best->desc);
300 bios->length = best->size;
301 bios->data = best->data;
302 return true;
303 }
304
305 NV_ERROR(dev, "No valid VBIOS image found\n");
306 return false;
307 }
308
309 struct init_tbl_entry {
310 char *name;
311 uint8_t id;
312 /* Return:
313 * > 0: success, length of opcode
314 * 0: success, but abort further parsing of table (INIT_DONE etc)
315 * < 0: failure, table parsing will be aborted
316 */
317 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
318 };
319
320 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
321
322 #define MACRO_INDEX_SIZE 2
323 #define MACRO_SIZE 8
324 #define CONDITION_SIZE 12
325 #define IO_FLAG_CONDITION_SIZE 9
326 #define IO_CONDITION_SIZE 5
327 #define MEM_INIT_SIZE 66
328
329 static void still_alive(void)
330 {
331 #if 0
332 sync();
333 mdelay(2);
334 #endif
335 }
336
337 static uint32_t
338 munge_reg(struct nvbios *bios, uint32_t reg)
339 {
340 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
341 struct dcb_entry *dcbent = bios->display.output;
342
343 if (dev_priv->card_type < NV_50)
344 return reg;
345
346 if (reg & 0x80000000) {
347 BUG_ON(bios->display.crtc < 0);
348 reg += bios->display.crtc * 0x800;
349 }
350
351 if (reg & 0x40000000) {
352 BUG_ON(!dcbent);
353
354 reg += (ffs(dcbent->or) - 1) * 0x800;
355 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
356 reg += 0x00000080;
357 }
358
359 reg &= ~0xe0000000;
360 return reg;
361 }
362
363 static int
364 valid_reg(struct nvbios *bios, uint32_t reg)
365 {
366 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
367 struct drm_device *dev = bios->dev;
368
369 /* C51 has misaligned regs on purpose. Marvellous */
370 if (reg & 0x2 ||
371 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
372 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
373
374 /* warn on C51 regs that haven't been verified accessible in tracing */
375 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
376 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
377 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
378 reg);
379
380 if (reg >= (8*1024*1024)) {
381 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
382 return 0;
383 }
384
385 return 1;
386 }
387
388 static bool
389 valid_idx_port(struct nvbios *bios, uint16_t port)
390 {
391 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
392 struct drm_device *dev = bios->dev;
393
394 /*
395 * If adding more ports here, the read/write functions below will need
396 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
397 * used for the port in question
398 */
399 if (dev_priv->card_type < NV_50) {
400 if (port == NV_CIO_CRX__COLOR)
401 return true;
402 if (port == NV_VIO_SRX)
403 return true;
404 } else {
405 if (port == NV_CIO_CRX__COLOR)
406 return true;
407 }
408
409 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
410 port);
411
412 return false;
413 }
414
415 static bool
416 valid_port(struct nvbios *bios, uint16_t port)
417 {
418 struct drm_device *dev = bios->dev;
419
420 /*
421 * If adding more ports here, the read/write functions below will need
422 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
423 * used for the port in question
424 */
425 if (port == NV_VIO_VSE2)
426 return true;
427
428 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
429
430 return false;
431 }
432
433 static uint32_t
434 bios_rd32(struct nvbios *bios, uint32_t reg)
435 {
436 uint32_t data;
437
438 reg = munge_reg(bios, reg);
439 if (!valid_reg(bios, reg))
440 return 0;
441
442 /*
443 * C51 sometimes uses regs with bit0 set in the address. For these
444 * cases there should exist a translation in a BIOS table to an IO
445 * port address which the BIOS uses for accessing the reg
446 *
447 * These only seem to appear for the power control regs to a flat panel,
448 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
449 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
450 * suspend-resume mmio trace from a C51 will be required to see if this
451 * is true for the power microcode in 0x14.., or whether the direct IO
452 * port access method is needed
453 */
454 if (reg & 0x1)
455 reg &= ~0x1;
456
457 data = nv_rd32(bios->dev, reg);
458
459 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
460
461 return data;
462 }
463
464 static void
465 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
466 {
467 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
468
469 reg = munge_reg(bios, reg);
470 if (!valid_reg(bios, reg))
471 return;
472
473 /* see note in bios_rd32 */
474 if (reg & 0x1)
475 reg &= 0xfffffffe;
476
477 LOG_OLD_VALUE(bios_rd32(bios, reg));
478 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
479
480 if (dev_priv->vbios.execute) {
481 still_alive();
482 nv_wr32(bios->dev, reg, data);
483 }
484 }
485
486 static uint8_t
487 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
488 {
489 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
490 struct drm_device *dev = bios->dev;
491 uint8_t data;
492
493 if (!valid_idx_port(bios, port))
494 return 0;
495
496 if (dev_priv->card_type < NV_50) {
497 if (port == NV_VIO_SRX)
498 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
499 else /* assume NV_CIO_CRX__COLOR */
500 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
501 } else {
502 uint32_t data32;
503
504 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
505 data = (data32 >> ((index & 3) << 3)) & 0xff;
506 }
507
508 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
509 "Head: 0x%02X, Data: 0x%02X\n",
510 port, index, bios->state.crtchead, data);
511 return data;
512 }
513
514 static void
515 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
516 {
517 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
518 struct drm_device *dev = bios->dev;
519
520 if (!valid_idx_port(bios, port))
521 return;
522
523 /*
524 * The current head is maintained in the nvbios member state.crtchead.
525 * We trap changes to CR44 and update the head variable and hence the
526 * register set written.
527 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
528 * of the write, and to head1 after the write
529 */
530 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
531 data != NV_CIO_CRE_44_HEADB)
532 bios->state.crtchead = 0;
533
534 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
535 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
536 "Head: 0x%02X, Data: 0x%02X\n",
537 port, index, bios->state.crtchead, data);
538
539 if (bios->execute && dev_priv->card_type < NV_50) {
540 still_alive();
541 if (port == NV_VIO_SRX)
542 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
543 else /* assume NV_CIO_CRX__COLOR */
544 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
545 } else
546 if (bios->execute) {
547 uint32_t data32, shift = (index & 3) << 3;
548
549 still_alive();
550
551 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
552 data32 &= ~(0xff << shift);
553 data32 |= (data << shift);
554 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
555 }
556
557 if (port == NV_CIO_CRX__COLOR &&
558 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
559 bios->state.crtchead = 1;
560 }
561
562 static uint8_t
563 bios_port_rd(struct nvbios *bios, uint16_t port)
564 {
565 uint8_t data, head = bios->state.crtchead;
566
567 if (!valid_port(bios, port))
568 return 0;
569
570 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
571
572 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
573 port, head, data);
574
575 return data;
576 }
577
578 static void
579 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
580 {
581 int head = bios->state.crtchead;
582
583 if (!valid_port(bios, port))
584 return;
585
586 LOG_OLD_VALUE(bios_port_rd(bios, port));
587 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
588 port, head, data);
589
590 if (!bios->execute)
591 return;
592
593 still_alive();
594 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
595 }
596
597 static bool
598 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
599 {
600 /*
601 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
602 * for the CRTC index; 1 byte for the mask to apply to the value
603 * retrieved from the CRTC; 1 byte for the shift right to apply to the
604 * masked CRTC value; 2 bytes for the offset to the flag array, to
605 * which the shifted value is added; 1 byte for the mask applied to the
606 * value read from the flag array; and 1 byte for the value to compare
607 * against the masked byte from the flag table.
608 */
609
610 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
611 uint16_t crtcport = ROM16(bios->data[condptr]);
612 uint8_t crtcindex = bios->data[condptr + 2];
613 uint8_t mask = bios->data[condptr + 3];
614 uint8_t shift = bios->data[condptr + 4];
615 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
616 uint8_t flagarraymask = bios->data[condptr + 7];
617 uint8_t cmpval = bios->data[condptr + 8];
618 uint8_t data;
619
620 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
621 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
622 "Cmpval: 0x%02X\n",
623 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
624
625 data = bios_idxprt_rd(bios, crtcport, crtcindex);
626
627 data = bios->data[flagarray + ((data & mask) >> shift)];
628 data &= flagarraymask;
629
630 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
631 offset, data, cmpval);
632
633 return (data == cmpval);
634 }
635
636 static bool
637 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
638 {
639 /*
640 * The condition table entry has 4 bytes for the address of the
641 * register to check, 4 bytes for a mask to apply to the register and
642 * 4 for a test comparison value
643 */
644
645 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
646 uint32_t reg = ROM32(bios->data[condptr]);
647 uint32_t mask = ROM32(bios->data[condptr + 4]);
648 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
649 uint32_t data;
650
651 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
652 offset, cond, reg, mask);
653
654 data = bios_rd32(bios, reg) & mask;
655
656 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
657 offset, data, cmpval);
658
659 return (data == cmpval);
660 }
661
662 static bool
663 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
664 {
665 /*
666 * The IO condition entry has 2 bytes for the IO port address; 1 byte
667 * for the index to write to io_port; 1 byte for the mask to apply to
668 * the byte read from io_port+1; and 1 byte for the value to compare
669 * against the masked byte.
670 */
671
672 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
673 uint16_t io_port = ROM16(bios->data[condptr]);
674 uint8_t port_index = bios->data[condptr + 2];
675 uint8_t mask = bios->data[condptr + 3];
676 uint8_t cmpval = bios->data[condptr + 4];
677
678 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
679
680 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
681 offset, data, cmpval);
682
683 return (data == cmpval);
684 }
685
686 static int
687 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
688 {
689 struct drm_nouveau_private *dev_priv = dev->dev_private;
690 struct nouveau_pll_vals pll;
691 struct pll_lims pll_limits;
692 u32 ctrl, mask, coef;
693 int ret;
694
695 ret = get_pll_limits(dev, reg, &pll_limits);
696 if (ret)
697 return ret;
698
699 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
700 if (!clk)
701 return -ERANGE;
702
703 coef = pll.N1 << 8 | pll.M1;
704 ctrl = pll.log2P << 16;
705 mask = 0x00070000;
706 if (reg == 0x004008) {
707 mask |= 0x01f80000;
708 ctrl |= (pll_limits.log2p_bias << 19);
709 ctrl |= (pll.log2P << 22);
710 }
711
712 if (!dev_priv->vbios.execute)
713 return 0;
714
715 nv_mask(dev, reg + 0, mask, ctrl);
716 nv_wr32(dev, reg + 4, coef);
717 return 0;
718 }
719
720 static int
721 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
722 {
723 struct drm_device *dev = bios->dev;
724 struct drm_nouveau_private *dev_priv = dev->dev_private;
725 /* clk in kHz */
726 struct pll_lims pll_lim;
727 struct nouveau_pll_vals pllvals;
728 int ret;
729
730 if (dev_priv->card_type >= NV_50)
731 return nv50_pll_set(dev, reg, clk);
732
733 /* high regs (such as in the mac g5 table) are not -= 4 */
734 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
735 if (ret)
736 return ret;
737
738 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
739 if (!clk)
740 return -ERANGE;
741
742 if (bios->execute) {
743 still_alive();
744 nouveau_hw_setpll(dev, reg, &pllvals);
745 }
746
747 return 0;
748 }
749
750 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
751 {
752 struct drm_nouveau_private *dev_priv = dev->dev_private;
753 struct nvbios *bios = &dev_priv->vbios;
754
755 /*
756 * For the results of this function to be correct, CR44 must have been
757 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
758 * and the DCB table parsed, before the script calling the function is
759 * run. run_digital_op_script is example of how to do such setup
760 */
761
762 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
763
764 if (dcb_entry > bios->dcb.entries) {
765 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
766 "(%02X)\n", dcb_entry);
767 dcb_entry = 0x7f; /* unused / invalid marker */
768 }
769
770 return dcb_entry;
771 }
772
773 static struct nouveau_i2c_chan *
774 init_i2c_device_find(struct drm_device *dev, int i2c_index)
775 {
776 if (i2c_index == 0xff) {
777 struct drm_nouveau_private *dev_priv = dev->dev_private;
778 struct dcb_table *dcb = &dev_priv->vbios.dcb;
779 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
780 int idx = dcb_entry_idx_from_crtchead(dev);
781
782 i2c_index = NV_I2C_DEFAULT(0);
783 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
784 i2c_index = NV_I2C_DEFAULT(1);
785 }
786
787 return nouveau_i2c_find(dev, i2c_index);
788 }
789
790 static uint32_t
791 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
792 {
793 /*
794 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
795 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
796 * CR58 for CR57 = 0 to index a table of offsets to the basic
797 * 0x6808b0 address.
798 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
799 * CR58 for CR57 = 0 to index a table of offsets to the basic
800 * 0x6808b0 address, and then flip the offset by 8.
801 */
802
803 struct drm_nouveau_private *dev_priv = dev->dev_private;
804 struct nvbios *bios = &dev_priv->vbios;
805 const int pramdac_offset[13] = {
806 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
807 const uint32_t pramdac_table[4] = {
808 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
809
810 if (mlv >= 0x80) {
811 int dcb_entry, dacoffset;
812
813 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
814 dcb_entry = dcb_entry_idx_from_crtchead(dev);
815 if (dcb_entry == 0x7f)
816 return 0;
817 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
818 if (mlv == 0x81)
819 dacoffset ^= 8;
820 return 0x6808b0 + dacoffset;
821 } else {
822 if (mlv >= ARRAY_SIZE(pramdac_table)) {
823 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
824 mlv);
825 return 0;
826 }
827 return pramdac_table[mlv];
828 }
829 }
830
831 static int
832 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
833 struct init_exec *iexec)
834 {
835 /*
836 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
837 *
838 * offset (8 bit): opcode
839 * offset + 1 (16 bit): CRTC port
840 * offset + 3 (8 bit): CRTC index
841 * offset + 4 (8 bit): mask
842 * offset + 5 (8 bit): shift
843 * offset + 6 (8 bit): count
844 * offset + 7 (32 bit): register
845 * offset + 11 (32 bit): configuration 1
846 * ...
847 *
848 * Starting at offset + 11 there are "count" 32 bit values.
849 * To find out which value to use read index "CRTC index" on "CRTC
850 * port", AND this value with "mask" and then bit shift right "shift"
851 * bits. Read the appropriate value using this index and write to
852 * "register"
853 */
854
855 uint16_t crtcport = ROM16(bios->data[offset + 1]);
856 uint8_t crtcindex = bios->data[offset + 3];
857 uint8_t mask = bios->data[offset + 4];
858 uint8_t shift = bios->data[offset + 5];
859 uint8_t count = bios->data[offset + 6];
860 uint32_t reg = ROM32(bios->data[offset + 7]);
861 uint8_t config;
862 uint32_t configval;
863 int len = 11 + count * 4;
864
865 if (!iexec->execute)
866 return len;
867
868 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
869 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
870 offset, crtcport, crtcindex, mask, shift, count, reg);
871
872 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
873 if (config > count) {
874 NV_ERROR(bios->dev,
875 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
876 offset, config, count);
877 return len;
878 }
879
880 configval = ROM32(bios->data[offset + 11 + config * 4]);
881
882 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
883
884 bios_wr32(bios, reg, configval);
885
886 return len;
887 }
888
889 static int
890 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
891 {
892 /*
893 * INIT_REPEAT opcode: 0x33 ('3')
894 *
895 * offset (8 bit): opcode
896 * offset + 1 (8 bit): count
897 *
898 * Execute script following this opcode up to INIT_REPEAT_END
899 * "count" times
900 */
901
902 uint8_t count = bios->data[offset + 1];
903 uint8_t i;
904
905 /* no iexec->execute check by design */
906
907 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
908 offset, count);
909
910 iexec->repeat = true;
911
912 /*
913 * count - 1, as the script block will execute once when we leave this
914 * opcode -- this is compatible with bios behaviour as:
915 * a) the block is always executed at least once, even if count == 0
916 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
917 * while we don't
918 */
919 for (i = 0; i < count - 1; i++)
920 parse_init_table(bios, offset + 2, iexec);
921
922 iexec->repeat = false;
923
924 return 2;
925 }
926
927 static int
928 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
929 struct init_exec *iexec)
930 {
931 /*
932 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
933 *
934 * offset (8 bit): opcode
935 * offset + 1 (16 bit): CRTC port
936 * offset + 3 (8 bit): CRTC index
937 * offset + 4 (8 bit): mask
938 * offset + 5 (8 bit): shift
939 * offset + 6 (8 bit): IO flag condition index
940 * offset + 7 (8 bit): count
941 * offset + 8 (32 bit): register
942 * offset + 12 (16 bit): frequency 1
943 * ...
944 *
945 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
946 * Set PLL register "register" to coefficients for frequency n,
947 * selected by reading index "CRTC index" of "CRTC port" ANDed with
948 * "mask" and shifted right by "shift".
949 *
950 * If "IO flag condition index" > 0, and condition met, double
951 * frequency before setting it.
952 */
953
954 uint16_t crtcport = ROM16(bios->data[offset + 1]);
955 uint8_t crtcindex = bios->data[offset + 3];
956 uint8_t mask = bios->data[offset + 4];
957 uint8_t shift = bios->data[offset + 5];
958 int8_t io_flag_condition_idx = bios->data[offset + 6];
959 uint8_t count = bios->data[offset + 7];
960 uint32_t reg = ROM32(bios->data[offset + 8]);
961 uint8_t config;
962 uint16_t freq;
963 int len = 12 + count * 2;
964
965 if (!iexec->execute)
966 return len;
967
968 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
969 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
970 "Count: 0x%02X, Reg: 0x%08X\n",
971 offset, crtcport, crtcindex, mask, shift,
972 io_flag_condition_idx, count, reg);
973
974 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
975 if (config > count) {
976 NV_ERROR(bios->dev,
977 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
978 offset, config, count);
979 return len;
980 }
981
982 freq = ROM16(bios->data[offset + 12 + config * 2]);
983
984 if (io_flag_condition_idx > 0) {
985 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
986 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
987 "frequency doubled\n", offset);
988 freq *= 2;
989 } else
990 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
991 "frequency unchanged\n", offset);
992 }
993
994 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
995 offset, reg, config, freq);
996
997 setPLL(bios, reg, freq * 10);
998
999 return len;
1000 }
1001
1002 static int
1003 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1004 {
1005 /*
1006 * INIT_END_REPEAT opcode: 0x36 ('6')
1007 *
1008 * offset (8 bit): opcode
1009 *
1010 * Marks the end of the block for INIT_REPEAT to repeat
1011 */
1012
1013 /* no iexec->execute check by design */
1014
1015 /*
1016 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1017 * we're not in repeat mode
1018 */
1019 if (iexec->repeat)
1020 return 0;
1021
1022 return 1;
1023 }
1024
1025 static int
1026 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1027 {
1028 /*
1029 * INIT_COPY opcode: 0x37 ('7')
1030 *
1031 * offset (8 bit): opcode
1032 * offset + 1 (32 bit): register
1033 * offset + 5 (8 bit): shift
1034 * offset + 6 (8 bit): srcmask
1035 * offset + 7 (16 bit): CRTC port
1036 * offset + 9 (8 bit): CRTC index
1037 * offset + 10 (8 bit): mask
1038 *
1039 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1040 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1041 * port
1042 */
1043
1044 uint32_t reg = ROM32(bios->data[offset + 1]);
1045 uint8_t shift = bios->data[offset + 5];
1046 uint8_t srcmask = bios->data[offset + 6];
1047 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1048 uint8_t crtcindex = bios->data[offset + 9];
1049 uint8_t mask = bios->data[offset + 10];
1050 uint32_t data;
1051 uint8_t crtcdata;
1052
1053 if (!iexec->execute)
1054 return 11;
1055
1056 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1057 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1058 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1059
1060 data = bios_rd32(bios, reg);
1061
1062 if (shift < 0x80)
1063 data >>= shift;
1064 else
1065 data <<= (0x100 - shift);
1066
1067 data &= srcmask;
1068
1069 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1070 crtcdata |= (uint8_t)data;
1071 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1072
1073 return 11;
1074 }
1075
1076 static int
1077 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1078 {
1079 /*
1080 * INIT_NOT opcode: 0x38 ('8')
1081 *
1082 * offset (8 bit): opcode
1083 *
1084 * Invert the current execute / no-execute condition (i.e. "else")
1085 */
1086 if (iexec->execute)
1087 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1088 else
1089 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1090
1091 iexec->execute = !iexec->execute;
1092 return 1;
1093 }
1094
1095 static int
1096 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1097 struct init_exec *iexec)
1098 {
1099 /*
1100 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1101 *
1102 * offset (8 bit): opcode
1103 * offset + 1 (8 bit): condition number
1104 *
1105 * Check condition "condition number" in the IO flag condition table.
1106 * If condition not met skip subsequent opcodes until condition is
1107 * inverted (INIT_NOT), or we hit INIT_RESUME
1108 */
1109
1110 uint8_t cond = bios->data[offset + 1];
1111
1112 if (!iexec->execute)
1113 return 2;
1114
1115 if (io_flag_condition_met(bios, offset, cond))
1116 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1117 else {
1118 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1119 iexec->execute = false;
1120 }
1121
1122 return 2;
1123 }
1124
1125 static int
1126 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1127 {
1128 /*
1129 * INIT_DP_CONDITION opcode: 0x3A ('')
1130 *
1131 * offset (8 bit): opcode
1132 * offset + 1 (8 bit): "sub" opcode
1133 * offset + 2 (8 bit): unknown
1134 *
1135 */
1136
1137 struct dcb_entry *dcb = bios->display.output;
1138 struct drm_device *dev = bios->dev;
1139 uint8_t cond = bios->data[offset + 1];
1140 uint8_t *table, *entry;
1141
1142 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1143
1144 if (!iexec->execute)
1145 return 3;
1146
1147 table = nouveau_dp_bios_data(dev, dcb, &entry);
1148 if (!table)
1149 return 3;
1150
1151 switch (cond) {
1152 case 0:
1153 entry = dcb_conn(dev, dcb->connector);
1154 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
1155 iexec->execute = false;
1156 break;
1157 case 1:
1158 case 2:
1159 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
1160 (table[0] == 0x40 && !(entry[4] & cond)))
1161 iexec->execute = false;
1162 break;
1163 case 5:
1164 {
1165 struct nouveau_i2c_chan *auxch;
1166 int ret;
1167
1168 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1169 if (!auxch) {
1170 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1171 return 3;
1172 }
1173
1174 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1175 if (ret) {
1176 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1177 return 3;
1178 }
1179
1180 if (!(cond & 1))
1181 iexec->execute = false;
1182 }
1183 break;
1184 default:
1185 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1186 break;
1187 }
1188
1189 if (iexec->execute)
1190 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1191 else
1192 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1193
1194 return 3;
1195 }
1196
1197 static int
1198 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1199 {
1200 /*
1201 * INIT_3B opcode: 0x3B ('')
1202 *
1203 * offset (8 bit): opcode
1204 * offset + 1 (8 bit): crtc index
1205 *
1206 */
1207
1208 uint8_t or = ffs(bios->display.output->or) - 1;
1209 uint8_t index = bios->data[offset + 1];
1210 uint8_t data;
1211
1212 if (!iexec->execute)
1213 return 2;
1214
1215 data = bios_idxprt_rd(bios, 0x3d4, index);
1216 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1217 return 2;
1218 }
1219
1220 static int
1221 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1222 {
1223 /*
1224 * INIT_3C opcode: 0x3C ('')
1225 *
1226 * offset (8 bit): opcode
1227 * offset + 1 (8 bit): crtc index
1228 *
1229 */
1230
1231 uint8_t or = ffs(bios->display.output->or) - 1;
1232 uint8_t index = bios->data[offset + 1];
1233 uint8_t data;
1234
1235 if (!iexec->execute)
1236 return 2;
1237
1238 data = bios_idxprt_rd(bios, 0x3d4, index);
1239 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1240 return 2;
1241 }
1242
1243 static int
1244 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1245 struct init_exec *iexec)
1246 {
1247 /*
1248 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1249 *
1250 * offset (8 bit): opcode
1251 * offset + 1 (32 bit): control register
1252 * offset + 5 (32 bit): data register
1253 * offset + 9 (32 bit): mask
1254 * offset + 13 (32 bit): data
1255 * offset + 17 (8 bit): count
1256 * offset + 18 (8 bit): address 1
1257 * offset + 19 (8 bit): data 1
1258 * ...
1259 *
1260 * For each of "count" address and data pairs, write "data n" to
1261 * "data register", read the current value of "control register",
1262 * and write it back once ANDed with "mask", ORed with "data",
1263 * and ORed with "address n"
1264 */
1265
1266 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1267 uint32_t datareg = ROM32(bios->data[offset + 5]);
1268 uint32_t mask = ROM32(bios->data[offset + 9]);
1269 uint32_t data = ROM32(bios->data[offset + 13]);
1270 uint8_t count = bios->data[offset + 17];
1271 int len = 18 + count * 2;
1272 uint32_t value;
1273 int i;
1274
1275 if (!iexec->execute)
1276 return len;
1277
1278 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1279 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1280 offset, controlreg, datareg, mask, data, count);
1281
1282 for (i = 0; i < count; i++) {
1283 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1284 uint8_t instdata = bios->data[offset + 19 + i * 2];
1285
1286 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1287 offset, instaddress, instdata);
1288
1289 bios_wr32(bios, datareg, instdata);
1290 value = bios_rd32(bios, controlreg) & mask;
1291 value |= data;
1292 value |= instaddress;
1293 bios_wr32(bios, controlreg, value);
1294 }
1295
1296 return len;
1297 }
1298
1299 static int
1300 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1301 struct init_exec *iexec)
1302 {
1303 /*
1304 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1305 *
1306 * offset (8 bit): opcode
1307 * offset + 1 (16 bit): CRTC port
1308 * offset + 3 (8 bit): CRTC index
1309 * offset + 4 (8 bit): mask
1310 * offset + 5 (8 bit): shift
1311 * offset + 6 (8 bit): count
1312 * offset + 7 (32 bit): register
1313 * offset + 11 (32 bit): frequency 1
1314 * ...
1315 *
1316 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1317 * Set PLL register "register" to coefficients for frequency n,
1318 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1319 * "mask" and shifted right by "shift".
1320 */
1321
1322 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1323 uint8_t crtcindex = bios->data[offset + 3];
1324 uint8_t mask = bios->data[offset + 4];
1325 uint8_t shift = bios->data[offset + 5];
1326 uint8_t count = bios->data[offset + 6];
1327 uint32_t reg = ROM32(bios->data[offset + 7]);
1328 int len = 11 + count * 4;
1329 uint8_t config;
1330 uint32_t freq;
1331
1332 if (!iexec->execute)
1333 return len;
1334
1335 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1336 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1337 offset, crtcport, crtcindex, mask, shift, count, reg);
1338
1339 if (!reg)
1340 return len;
1341
1342 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1343 if (config > count) {
1344 NV_ERROR(bios->dev,
1345 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1346 offset, config, count);
1347 return len;
1348 }
1349
1350 freq = ROM32(bios->data[offset + 11 + config * 4]);
1351
1352 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1353 offset, reg, config, freq);
1354
1355 setPLL(bios, reg, freq);
1356
1357 return len;
1358 }
1359
1360 static int
1361 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1362 {
1363 /*
1364 * INIT_PLL2 opcode: 0x4B ('K')
1365 *
1366 * offset (8 bit): opcode
1367 * offset + 1 (32 bit): register
1368 * offset + 5 (32 bit): freq
1369 *
1370 * Set PLL register "register" to coefficients for frequency "freq"
1371 */
1372
1373 uint32_t reg = ROM32(bios->data[offset + 1]);
1374 uint32_t freq = ROM32(bios->data[offset + 5]);
1375
1376 if (!iexec->execute)
1377 return 9;
1378
1379 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1380 offset, reg, freq);
1381
1382 setPLL(bios, reg, freq);
1383 return 9;
1384 }
1385
1386 static int
1387 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1388 {
1389 /*
1390 * INIT_I2C_BYTE opcode: 0x4C ('L')
1391 *
1392 * offset (8 bit): opcode
1393 * offset + 1 (8 bit): DCB I2C table entry index
1394 * offset + 2 (8 bit): I2C slave address
1395 * offset + 3 (8 bit): count
1396 * offset + 4 (8 bit): I2C register 1
1397 * offset + 5 (8 bit): mask 1
1398 * offset + 6 (8 bit): data 1
1399 * ...
1400 *
1401 * For each of "count" registers given by "I2C register n" on the device
1402 * addressed by "I2C slave address" on the I2C bus given by
1403 * "DCB I2C table entry index", read the register, AND the result with
1404 * "mask n" and OR it with "data n" before writing it back to the device
1405 */
1406
1407 struct drm_device *dev = bios->dev;
1408 uint8_t i2c_index = bios->data[offset + 1];
1409 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1410 uint8_t count = bios->data[offset + 3];
1411 struct nouveau_i2c_chan *chan;
1412 int len = 4 + count * 3;
1413 int ret, i;
1414
1415 if (!iexec->execute)
1416 return len;
1417
1418 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1419 "Count: 0x%02X\n",
1420 offset, i2c_index, i2c_address, count);
1421
1422 chan = init_i2c_device_find(dev, i2c_index);
1423 if (!chan) {
1424 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1425 return len;
1426 }
1427
1428 for (i = 0; i < count; i++) {
1429 uint8_t reg = bios->data[offset + 4 + i * 3];
1430 uint8_t mask = bios->data[offset + 5 + i * 3];
1431 uint8_t data = bios->data[offset + 6 + i * 3];
1432 union i2c_smbus_data val;
1433
1434 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1435 I2C_SMBUS_READ, reg,
1436 I2C_SMBUS_BYTE_DATA, &val);
1437 if (ret < 0) {
1438 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1439 return len;
1440 }
1441
1442 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1443 "Mask: 0x%02X, Data: 0x%02X\n",
1444 offset, reg, val.byte, mask, data);
1445
1446 if (!bios->execute)
1447 continue;
1448
1449 val.byte &= mask;
1450 val.byte |= data;
1451 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1452 I2C_SMBUS_WRITE, reg,
1453 I2C_SMBUS_BYTE_DATA, &val);
1454 if (ret < 0) {
1455 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1456 return len;
1457 }
1458 }
1459
1460 return len;
1461 }
1462
1463 static int
1464 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1465 {
1466 /*
1467 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1468 *
1469 * offset (8 bit): opcode
1470 * offset + 1 (8 bit): DCB I2C table entry index
1471 * offset + 2 (8 bit): I2C slave address
1472 * offset + 3 (8 bit): count
1473 * offset + 4 (8 bit): I2C register 1
1474 * offset + 5 (8 bit): data 1
1475 * ...
1476 *
1477 * For each of "count" registers given by "I2C register n" on the device
1478 * addressed by "I2C slave address" on the I2C bus given by
1479 * "DCB I2C table entry index", set the register to "data n"
1480 */
1481
1482 struct drm_device *dev = bios->dev;
1483 uint8_t i2c_index = bios->data[offset + 1];
1484 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1485 uint8_t count = bios->data[offset + 3];
1486 struct nouveau_i2c_chan *chan;
1487 int len = 4 + count * 2;
1488 int ret, i;
1489
1490 if (!iexec->execute)
1491 return len;
1492
1493 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1494 "Count: 0x%02X\n",
1495 offset, i2c_index, i2c_address, count);
1496
1497 chan = init_i2c_device_find(dev, i2c_index);
1498 if (!chan) {
1499 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1500 return len;
1501 }
1502
1503 for (i = 0; i < count; i++) {
1504 uint8_t reg = bios->data[offset + 4 + i * 2];
1505 union i2c_smbus_data val;
1506
1507 val.byte = bios->data[offset + 5 + i * 2];
1508
1509 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1510 offset, reg, val.byte);
1511
1512 if (!bios->execute)
1513 continue;
1514
1515 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1516 I2C_SMBUS_WRITE, reg,
1517 I2C_SMBUS_BYTE_DATA, &val);
1518 if (ret < 0) {
1519 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1520 return len;
1521 }
1522 }
1523
1524 return len;
1525 }
1526
1527 static int
1528 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1529 {
1530 /*
1531 * INIT_ZM_I2C opcode: 0x4E ('N')
1532 *
1533 * offset (8 bit): opcode
1534 * offset + 1 (8 bit): DCB I2C table entry index
1535 * offset + 2 (8 bit): I2C slave address
1536 * offset + 3 (8 bit): count
1537 * offset + 4 (8 bit): data 1
1538 * ...
1539 *
1540 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1541 * address" on the I2C bus given by "DCB I2C table entry index"
1542 */
1543
1544 struct drm_device *dev = bios->dev;
1545 uint8_t i2c_index = bios->data[offset + 1];
1546 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1547 uint8_t count = bios->data[offset + 3];
1548 int len = 4 + count;
1549 struct nouveau_i2c_chan *chan;
1550 struct i2c_msg msg;
1551 uint8_t data[256];
1552 int ret, i;
1553
1554 if (!iexec->execute)
1555 return len;
1556
1557 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1558 "Count: 0x%02X\n",
1559 offset, i2c_index, i2c_address, count);
1560
1561 chan = init_i2c_device_find(dev, i2c_index);
1562 if (!chan) {
1563 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1564 return len;
1565 }
1566
1567 for (i = 0; i < count; i++) {
1568 data[i] = bios->data[offset + 4 + i];
1569
1570 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1571 }
1572
1573 if (bios->execute) {
1574 msg.addr = i2c_address;
1575 msg.flags = 0;
1576 msg.len = count;
1577 msg.buf = data;
1578 ret = i2c_transfer(&chan->adapter, &msg, 1);
1579 if (ret != 1) {
1580 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1581 return len;
1582 }
1583 }
1584
1585 return len;
1586 }
1587
1588 static int
1589 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1590 {
1591 /*
1592 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1593 *
1594 * offset (8 bit): opcode
1595 * offset + 1 (8 bit): magic lookup value
1596 * offset + 2 (8 bit): TMDS address
1597 * offset + 3 (8 bit): mask
1598 * offset + 4 (8 bit): data
1599 *
1600 * Read the data reg for TMDS address "TMDS address", AND it with mask
1601 * and OR it with data, then write it back
1602 * "magic lookup value" determines which TMDS base address register is
1603 * used -- see get_tmds_index_reg()
1604 */
1605
1606 struct drm_device *dev = bios->dev;
1607 uint8_t mlv = bios->data[offset + 1];
1608 uint32_t tmdsaddr = bios->data[offset + 2];
1609 uint8_t mask = bios->data[offset + 3];
1610 uint8_t data = bios->data[offset + 4];
1611 uint32_t reg, value;
1612
1613 if (!iexec->execute)
1614 return 5;
1615
1616 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1617 "Mask: 0x%02X, Data: 0x%02X\n",
1618 offset, mlv, tmdsaddr, mask, data);
1619
1620 reg = get_tmds_index_reg(bios->dev, mlv);
1621 if (!reg) {
1622 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1623 return 5;
1624 }
1625
1626 bios_wr32(bios, reg,
1627 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1628 value = (bios_rd32(bios, reg + 4) & mask) | data;
1629 bios_wr32(bios, reg + 4, value);
1630 bios_wr32(bios, reg, tmdsaddr);
1631
1632 return 5;
1633 }
1634
1635 static int
1636 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1637 struct init_exec *iexec)
1638 {
1639 /*
1640 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1641 *
1642 * offset (8 bit): opcode
1643 * offset + 1 (8 bit): magic lookup value
1644 * offset + 2 (8 bit): count
1645 * offset + 3 (8 bit): addr 1
1646 * offset + 4 (8 bit): data 1
1647 * ...
1648 *
1649 * For each of "count" TMDS address and data pairs write "data n" to
1650 * "addr n". "magic lookup value" determines which TMDS base address
1651 * register is used -- see get_tmds_index_reg()
1652 */
1653
1654 struct drm_device *dev = bios->dev;
1655 uint8_t mlv = bios->data[offset + 1];
1656 uint8_t count = bios->data[offset + 2];
1657 int len = 3 + count * 2;
1658 uint32_t reg;
1659 int i;
1660
1661 if (!iexec->execute)
1662 return len;
1663
1664 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1665 offset, mlv, count);
1666
1667 reg = get_tmds_index_reg(bios->dev, mlv);
1668 if (!reg) {
1669 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1670 return len;
1671 }
1672
1673 for (i = 0; i < count; i++) {
1674 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1675 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1676
1677 bios_wr32(bios, reg + 4, tmdsdata);
1678 bios_wr32(bios, reg, tmdsaddr);
1679 }
1680
1681 return len;
1682 }
1683
1684 static int
1685 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1686 struct init_exec *iexec)
1687 {
1688 /*
1689 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1690 *
1691 * offset (8 bit): opcode
1692 * offset + 1 (8 bit): CRTC index1
1693 * offset + 2 (8 bit): CRTC index2
1694 * offset + 3 (8 bit): baseaddr
1695 * offset + 4 (8 bit): count
1696 * offset + 5 (8 bit): data 1
1697 * ...
1698 *
1699 * For each of "count" address and data pairs, write "baseaddr + n" to
1700 * "CRTC index1" and "data n" to "CRTC index2"
1701 * Once complete, restore initial value read from "CRTC index1"
1702 */
1703 uint8_t crtcindex1 = bios->data[offset + 1];
1704 uint8_t crtcindex2 = bios->data[offset + 2];
1705 uint8_t baseaddr = bios->data[offset + 3];
1706 uint8_t count = bios->data[offset + 4];
1707 int len = 5 + count;
1708 uint8_t oldaddr, data;
1709 int i;
1710
1711 if (!iexec->execute)
1712 return len;
1713
1714 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1715 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1716 offset, crtcindex1, crtcindex2, baseaddr, count);
1717
1718 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1719
1720 for (i = 0; i < count; i++) {
1721 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1722 baseaddr + i);
1723 data = bios->data[offset + 5 + i];
1724 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1725 }
1726
1727 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1728
1729 return len;
1730 }
1731
1732 static int
1733 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1734 {
1735 /*
1736 * INIT_CR opcode: 0x52 ('R')
1737 *
1738 * offset (8 bit): opcode
1739 * offset + 1 (8 bit): CRTC index
1740 * offset + 2 (8 bit): mask
1741 * offset + 3 (8 bit): data
1742 *
1743 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1744 * data back to "CRTC index"
1745 */
1746
1747 uint8_t crtcindex = bios->data[offset + 1];
1748 uint8_t mask = bios->data[offset + 2];
1749 uint8_t data = bios->data[offset + 3];
1750 uint8_t value;
1751
1752 if (!iexec->execute)
1753 return 4;
1754
1755 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1756 offset, crtcindex, mask, data);
1757
1758 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1759 value |= data;
1760 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1761
1762 return 4;
1763 }
1764
1765 static int
1766 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1767 {
1768 /*
1769 * INIT_ZM_CR opcode: 0x53 ('S')
1770 *
1771 * offset (8 bit): opcode
1772 * offset + 1 (8 bit): CRTC index
1773 * offset + 2 (8 bit): value
1774 *
1775 * Assign "value" to CRTC register with index "CRTC index".
1776 */
1777
1778 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1779 uint8_t data = bios->data[offset + 2];
1780
1781 if (!iexec->execute)
1782 return 3;
1783
1784 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1785
1786 return 3;
1787 }
1788
1789 static int
1790 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1791 {
1792 /*
1793 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1794 *
1795 * offset (8 bit): opcode
1796 * offset + 1 (8 bit): count
1797 * offset + 2 (8 bit): CRTC index 1
1798 * offset + 3 (8 bit): value 1
1799 * ...
1800 *
1801 * For "count", assign "value n" to CRTC register with index
1802 * "CRTC index n".
1803 */
1804
1805 uint8_t count = bios->data[offset + 1];
1806 int len = 2 + count * 2;
1807 int i;
1808
1809 if (!iexec->execute)
1810 return len;
1811
1812 for (i = 0; i < count; i++)
1813 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1814
1815 return len;
1816 }
1817
1818 static int
1819 init_condition_time(struct nvbios *bios, uint16_t offset,
1820 struct init_exec *iexec)
1821 {
1822 /*
1823 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1824 *
1825 * offset (8 bit): opcode
1826 * offset + 1 (8 bit): condition number
1827 * offset + 2 (8 bit): retries / 50
1828 *
1829 * Check condition "condition number" in the condition table.
1830 * Bios code then sleeps for 2ms if the condition is not met, and
1831 * repeats up to "retries" times, but on one C51 this has proved
1832 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1833 * this, and bail after "retries" times, or 2s, whichever is less.
1834 * If still not met after retries, clear execution flag for this table.
1835 */
1836
1837 uint8_t cond = bios->data[offset + 1];
1838 uint16_t retries = bios->data[offset + 2] * 50;
1839 unsigned cnt;
1840
1841 if (!iexec->execute)
1842 return 3;
1843
1844 if (retries > 100)
1845 retries = 100;
1846
1847 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1848 offset, cond, retries);
1849
1850 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1851 retries = 1;
1852
1853 for (cnt = 0; cnt < retries; cnt++) {
1854 if (bios_condition_met(bios, offset, cond)) {
1855 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1856 offset);
1857 break;
1858 } else {
1859 BIOSLOG(bios, "0x%04X: "
1860 "Condition not met, sleeping for 20ms\n",
1861 offset);
1862 mdelay(20);
1863 }
1864 }
1865
1866 if (!bios_condition_met(bios, offset, cond)) {
1867 NV_WARN(bios->dev,
1868 "0x%04X: Condition still not met after %dms, "
1869 "skipping following opcodes\n", offset, 20 * retries);
1870 iexec->execute = false;
1871 }
1872
1873 return 3;
1874 }
1875
1876 static int
1877 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1878 {
1879 /*
1880 * INIT_LTIME opcode: 0x57 ('V')
1881 *
1882 * offset (8 bit): opcode
1883 * offset + 1 (16 bit): time
1884 *
1885 * Sleep for "time" milliseconds.
1886 */
1887
1888 unsigned time = ROM16(bios->data[offset + 1]);
1889
1890 if (!iexec->execute)
1891 return 3;
1892
1893 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1894 offset, time);
1895
1896 mdelay(time);
1897
1898 return 3;
1899 }
1900
1901 static int
1902 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1903 struct init_exec *iexec)
1904 {
1905 /*
1906 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1907 *
1908 * offset (8 bit): opcode
1909 * offset + 1 (32 bit): base register
1910 * offset + 5 (8 bit): count
1911 * offset + 6 (32 bit): value 1
1912 * ...
1913 *
1914 * Starting at offset + 6 there are "count" 32 bit values.
1915 * For "count" iterations set "base register" + 4 * current_iteration
1916 * to "value current_iteration"
1917 */
1918
1919 uint32_t basereg = ROM32(bios->data[offset + 1]);
1920 uint32_t count = bios->data[offset + 5];
1921 int len = 6 + count * 4;
1922 int i;
1923
1924 if (!iexec->execute)
1925 return len;
1926
1927 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1928 offset, basereg, count);
1929
1930 for (i = 0; i < count; i++) {
1931 uint32_t reg = basereg + i * 4;
1932 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1933
1934 bios_wr32(bios, reg, data);
1935 }
1936
1937 return len;
1938 }
1939
1940 static int
1941 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1942 {
1943 /*
1944 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1945 *
1946 * offset (8 bit): opcode
1947 * offset + 1 (16 bit): subroutine offset (in bios)
1948 *
1949 * Calls a subroutine that will execute commands until INIT_DONE
1950 * is found.
1951 */
1952
1953 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1954
1955 if (!iexec->execute)
1956 return 3;
1957
1958 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1959 offset, sub_offset);
1960
1961 parse_init_table(bios, sub_offset, iexec);
1962
1963 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1964
1965 return 3;
1966 }
1967
1968 static int
1969 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1970 {
1971 /*
1972 * INIT_JUMP opcode: 0x5C ('\')
1973 *
1974 * offset (8 bit): opcode
1975 * offset + 1 (16 bit): offset (in bios)
1976 *
1977 * Continue execution of init table from 'offset'
1978 */
1979
1980 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1981
1982 if (!iexec->execute)
1983 return 3;
1984
1985 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1986 return jmp_offset - offset;
1987 }
1988
1989 static int
1990 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1991 {
1992 /*
1993 * INIT_I2C_IF opcode: 0x5E ('^')
1994 *
1995 * offset (8 bit): opcode
1996 * offset + 1 (8 bit): DCB I2C table entry index
1997 * offset + 2 (8 bit): I2C slave address
1998 * offset + 3 (8 bit): I2C register
1999 * offset + 4 (8 bit): mask
2000 * offset + 5 (8 bit): data
2001 *
2002 * Read the register given by "I2C register" on the device addressed
2003 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2004 * entry index". Compare the result AND "mask" to "data".
2005 * If they're not equal, skip subsequent opcodes until condition is
2006 * inverted (INIT_NOT), or we hit INIT_RESUME
2007 */
2008
2009 uint8_t i2c_index = bios->data[offset + 1];
2010 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2011 uint8_t reg = bios->data[offset + 3];
2012 uint8_t mask = bios->data[offset + 4];
2013 uint8_t data = bios->data[offset + 5];
2014 struct nouveau_i2c_chan *chan;
2015 union i2c_smbus_data val;
2016 int ret;
2017
2018 /* no execute check by design */
2019
2020 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2021 offset, i2c_index, i2c_address);
2022
2023 chan = init_i2c_device_find(bios->dev, i2c_index);
2024 if (!chan)
2025 return -ENODEV;
2026
2027 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2028 I2C_SMBUS_READ, reg,
2029 I2C_SMBUS_BYTE_DATA, &val);
2030 if (ret < 0) {
2031 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2032 "Mask: 0x%02X, Data: 0x%02X\n",
2033 offset, reg, mask, data);
2034 iexec->execute = 0;
2035 return 6;
2036 }
2037
2038 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2039 "Mask: 0x%02X, Data: 0x%02X\n",
2040 offset, reg, val.byte, mask, data);
2041
2042 iexec->execute = ((val.byte & mask) == data);
2043
2044 return 6;
2045 }
2046
2047 static int
2048 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2049 {
2050 /*
2051 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2052 *
2053 * offset (8 bit): opcode
2054 * offset + 1 (32 bit): src reg
2055 * offset + 5 (8 bit): shift
2056 * offset + 6 (32 bit): src mask
2057 * offset + 10 (32 bit): xor
2058 * offset + 14 (32 bit): dst reg
2059 * offset + 18 (32 bit): dst mask
2060 *
2061 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2062 * "src mask", then XOR with "xor". Write this OR'd with
2063 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2064 */
2065
2066 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2067 uint8_t shift = bios->data[offset + 5];
2068 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2069 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2070 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2071 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2072 uint32_t srcvalue, dstvalue;
2073
2074 if (!iexec->execute)
2075 return 22;
2076
2077 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2078 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2079 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2080
2081 srcvalue = bios_rd32(bios, srcreg);
2082
2083 if (shift < 0x80)
2084 srcvalue >>= shift;
2085 else
2086 srcvalue <<= (0x100 - shift);
2087
2088 srcvalue = (srcvalue & srcmask) ^ xor;
2089
2090 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2091
2092 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2093
2094 return 22;
2095 }
2096
2097 static int
2098 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2099 {
2100 /*
2101 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2102 *
2103 * offset (8 bit): opcode
2104 * offset + 1 (16 bit): CRTC port
2105 * offset + 3 (8 bit): CRTC index
2106 * offset + 4 (8 bit): data
2107 *
2108 * Write "data" to index "CRTC index" of "CRTC port"
2109 */
2110 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2111 uint8_t crtcindex = bios->data[offset + 3];
2112 uint8_t data = bios->data[offset + 4];
2113
2114 if (!iexec->execute)
2115 return 5;
2116
2117 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2118
2119 return 5;
2120 }
2121
2122 static inline void
2123 bios_md32(struct nvbios *bios, uint32_t reg,
2124 uint32_t mask, uint32_t val)
2125 {
2126 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2127 }
2128
2129 static uint32_t
2130 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2131 uint32_t off)
2132 {
2133 uint32_t val = 0;
2134
2135 if (off < pci_resource_len(dev->pdev, 1)) {
2136 uint8_t __iomem *p =
2137 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2138
2139 val = ioread32(p + (off & ~PAGE_MASK));
2140
2141 io_mapping_unmap_atomic(p);
2142 }
2143
2144 return val;
2145 }
2146
2147 static void
2148 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2149 uint32_t off, uint32_t val)
2150 {
2151 if (off < pci_resource_len(dev->pdev, 1)) {
2152 uint8_t __iomem *p =
2153 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2154
2155 iowrite32(val, p + (off & ~PAGE_MASK));
2156 wmb();
2157
2158 io_mapping_unmap_atomic(p);
2159 }
2160 }
2161
2162 static inline bool
2163 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2164 uint32_t off, uint32_t val)
2165 {
2166 poke_fb(dev, fb, off, val);
2167 return val == peek_fb(dev, fb, off);
2168 }
2169
2170 static int
2171 nv04_init_compute_mem(struct nvbios *bios)
2172 {
2173 struct drm_device *dev = bios->dev;
2174 uint32_t patt = 0xdeadbeef;
2175 struct io_mapping *fb;
2176 int i;
2177
2178 /* Map the framebuffer aperture */
2179 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2180 pci_resource_len(dev->pdev, 1));
2181 if (!fb)
2182 return -ENOMEM;
2183
2184 /* Sequencer and refresh off */
2185 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2186 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2187
2188 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2189 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2190 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2191 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2192
2193 for (i = 0; i < 4; i++)
2194 poke_fb(dev, fb, 4 * i, patt);
2195
2196 poke_fb(dev, fb, 0x400000, patt + 1);
2197
2198 if (peek_fb(dev, fb, 0) == patt + 1) {
2199 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2200 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2201 bios_md32(bios, NV04_PFB_DEBUG_0,
2202 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2203
2204 for (i = 0; i < 4; i++)
2205 poke_fb(dev, fb, 4 * i, patt);
2206
2207 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2208 bios_md32(bios, NV04_PFB_BOOT_0,
2209 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2210 NV04_PFB_BOOT_0_RAM_AMOUNT,
2211 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2212
2213 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2214 (patt & 0xffff0000)) {
2215 bios_md32(bios, NV04_PFB_BOOT_0,
2216 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2217 NV04_PFB_BOOT_0_RAM_AMOUNT,
2218 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2219
2220 } else if (peek_fb(dev, fb, 0) != patt) {
2221 if (read_back_fb(dev, fb, 0x800000, patt))
2222 bios_md32(bios, NV04_PFB_BOOT_0,
2223 NV04_PFB_BOOT_0_RAM_AMOUNT,
2224 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2225 else
2226 bios_md32(bios, NV04_PFB_BOOT_0,
2227 NV04_PFB_BOOT_0_RAM_AMOUNT,
2228 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2229
2230 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2231 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2232
2233 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2234 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2235 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2236
2237 }
2238
2239 /* Refresh on, sequencer on */
2240 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2241 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2242
2243 io_mapping_free(fb);
2244 return 0;
2245 }
2246
2247 static const uint8_t *
2248 nv05_memory_config(struct nvbios *bios)
2249 {
2250 /* Defaults for BIOSes lacking a memory config table */
2251 static const uint8_t default_config_tab[][2] = {
2252 { 0x24, 0x00 },
2253 { 0x28, 0x00 },
2254 { 0x24, 0x01 },
2255 { 0x1f, 0x00 },
2256 { 0x0f, 0x00 },
2257 { 0x17, 0x00 },
2258 { 0x06, 0x00 },
2259 { 0x00, 0x00 }
2260 };
2261 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2262 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2263
2264 if (bios->legacy.mem_init_tbl_ptr)
2265 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2266 else
2267 return default_config_tab[i];
2268 }
2269
2270 static int
2271 nv05_init_compute_mem(struct nvbios *bios)
2272 {
2273 struct drm_device *dev = bios->dev;
2274 const uint8_t *ramcfg = nv05_memory_config(bios);
2275 uint32_t patt = 0xdeadbeef;
2276 struct io_mapping *fb;
2277 int i, v;
2278
2279 /* Map the framebuffer aperture */
2280 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2281 pci_resource_len(dev->pdev, 1));
2282 if (!fb)
2283 return -ENOMEM;
2284
2285 /* Sequencer off */
2286 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2287
2288 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2289 goto out;
2290
2291 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2292
2293 /* If present load the hardcoded scrambling table */
2294 if (bios->legacy.mem_init_tbl_ptr) {
2295 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2296 bios->legacy.mem_init_tbl_ptr + 0x10];
2297
2298 for (i = 0; i < 8; i++)
2299 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2300 ROM32(scramble_tab[i]));
2301 }
2302
2303 /* Set memory type/width/length defaults depending on the straps */
2304 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2305
2306 if (ramcfg[1] & 0x80)
2307 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2308
2309 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2310 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2311
2312 /* Probe memory bus width */
2313 for (i = 0; i < 4; i++)
2314 poke_fb(dev, fb, 4 * i, patt);
2315
2316 if (peek_fb(dev, fb, 0xc) != patt)
2317 bios_md32(bios, NV04_PFB_BOOT_0,
2318 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2319
2320 /* Probe memory length */
2321 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2322
2323 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2324 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2325 !read_back_fb(dev, fb, 0, ++patt)))
2326 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2327 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2328
2329 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2330 !read_back_fb(dev, fb, 0x800000, ++patt))
2331 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2332 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2333
2334 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2335 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2336 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2337
2338 out:
2339 /* Sequencer on */
2340 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2341
2342 io_mapping_free(fb);
2343 return 0;
2344 }
2345
2346 static int
2347 nv10_init_compute_mem(struct nvbios *bios)
2348 {
2349 struct drm_device *dev = bios->dev;
2350 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2351 const int mem_width[] = { 0x10, 0x00, 0x20 };
2352 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2353 uint32_t patt = 0xdeadbeef;
2354 struct io_mapping *fb;
2355 int i, j, k;
2356
2357 /* Map the framebuffer aperture */
2358 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2359 pci_resource_len(dev->pdev, 1));
2360 if (!fb)
2361 return -ENOMEM;
2362
2363 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2364
2365 /* Probe memory bus width */
2366 for (i = 0; i < mem_width_count; i++) {
2367 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2368
2369 for (j = 0; j < 4; j++) {
2370 for (k = 0; k < 4; k++)
2371 poke_fb(dev, fb, 0x1c, 0);
2372
2373 poke_fb(dev, fb, 0x1c, patt);
2374 poke_fb(dev, fb, 0x3c, 0);
2375
2376 if (peek_fb(dev, fb, 0x1c) == patt)
2377 goto mem_width_found;
2378 }
2379 }
2380
2381 mem_width_found:
2382 patt <<= 1;
2383
2384 /* Probe amount of installed memory */
2385 for (i = 0; i < 4; i++) {
2386 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2387
2388 poke_fb(dev, fb, off, patt);
2389 poke_fb(dev, fb, 0, 0);
2390
2391 peek_fb(dev, fb, 0);
2392 peek_fb(dev, fb, 0);
2393 peek_fb(dev, fb, 0);
2394 peek_fb(dev, fb, 0);
2395
2396 if (peek_fb(dev, fb, off) == patt)
2397 goto amount_found;
2398 }
2399
2400 /* IC missing - disable the upper half memory space. */
2401 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2402
2403 amount_found:
2404 io_mapping_free(fb);
2405 return 0;
2406 }
2407
2408 static int
2409 nv20_init_compute_mem(struct nvbios *bios)
2410 {
2411 struct drm_device *dev = bios->dev;
2412 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2413 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2414 uint32_t amount, off;
2415 struct io_mapping *fb;
2416
2417 /* Map the framebuffer aperture */
2418 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2419 pci_resource_len(dev->pdev, 1));
2420 if (!fb)
2421 return -ENOMEM;
2422
2423 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2424
2425 /* Allow full addressing */
2426 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2427
2428 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2429 for (off = amount; off > 0x2000000; off -= 0x2000000)
2430 poke_fb(dev, fb, off - 4, off);
2431
2432 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2433 if (amount != peek_fb(dev, fb, amount - 4))
2434 /* IC missing - disable the upper half memory space. */
2435 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2436
2437 io_mapping_free(fb);
2438 return 0;
2439 }
2440
2441 static int
2442 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2443 {
2444 /*
2445 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2446 *
2447 * offset (8 bit): opcode
2448 *
2449 * This opcode is meant to set the PFB memory config registers
2450 * appropriately so that we can correctly calculate how much VRAM it
2451 * has (on nv10 and better chipsets the amount of installed VRAM is
2452 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2453 *
2454 * The implementation of this opcode in general consists of several
2455 * parts:
2456 *
2457 * 1) Determination of memory type and density. Only necessary for
2458 * really old chipsets, the memory type reported by the strap bits
2459 * (0x101000) is assumed to be accurate on nv05 and newer.
2460 *
2461 * 2) Determination of the memory bus width. Usually done by a cunning
2462 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2463 * seeing whether the written values are read back correctly.
2464 *
2465 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2466 * trust the straps.
2467 *
2468 * 3) Determination of how many of the card's RAM pads have ICs
2469 * attached, usually done by a cunning combination of writes to an
2470 * offset slightly less than the maximum memory reported by
2471 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2472 *
2473 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2474 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2475 * card show nothing being done for this opcode. Why is it still listed
2476 * in the table?!
2477 */
2478
2479 /* no iexec->execute check by design */
2480
2481 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2482 int ret;
2483
2484 if (dev_priv->chipset >= 0x40 ||
2485 dev_priv->chipset == 0x1a ||
2486 dev_priv->chipset == 0x1f)
2487 ret = 0;
2488 else if (dev_priv->chipset >= 0x20 &&
2489 dev_priv->chipset != 0x34)
2490 ret = nv20_init_compute_mem(bios);
2491 else if (dev_priv->chipset >= 0x10)
2492 ret = nv10_init_compute_mem(bios);
2493 else if (dev_priv->chipset >= 0x5)
2494 ret = nv05_init_compute_mem(bios);
2495 else
2496 ret = nv04_init_compute_mem(bios);
2497
2498 if (ret)
2499 return ret;
2500
2501 return 1;
2502 }
2503
2504 static int
2505 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2506 {
2507 /*
2508 * INIT_RESET opcode: 0x65 ('e')
2509 *
2510 * offset (8 bit): opcode
2511 * offset + 1 (32 bit): register
2512 * offset + 5 (32 bit): value1
2513 * offset + 9 (32 bit): value2
2514 *
2515 * Assign "value1" to "register", then assign "value2" to "register"
2516 */
2517
2518 uint32_t reg = ROM32(bios->data[offset + 1]);
2519 uint32_t value1 = ROM32(bios->data[offset + 5]);
2520 uint32_t value2 = ROM32(bios->data[offset + 9]);
2521 uint32_t pci_nv_19, pci_nv_20;
2522
2523 /* no iexec->execute check by design */
2524
2525 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2526 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2527
2528 bios_wr32(bios, reg, value1);
2529
2530 udelay(10);
2531
2532 bios_wr32(bios, reg, value2);
2533 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2534
2535 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2536 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2537 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2538
2539 return 13;
2540 }
2541
2542 static int
2543 init_configure_mem(struct nvbios *bios, uint16_t offset,
2544 struct init_exec *iexec)
2545 {
2546 /*
2547 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2548 *
2549 * offset (8 bit): opcode
2550 *
2551 * Equivalent to INIT_DONE on bios version 3 or greater.
2552 * For early bios versions, sets up the memory registers, using values
2553 * taken from the memory init table
2554 */
2555
2556 /* no iexec->execute check by design */
2557
2558 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2559 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2560 uint32_t reg, data;
2561
2562 if (bios->major_version > 2)
2563 return 0;
2564
2565 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2566 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2567
2568 if (bios->data[meminitoffs] & 1)
2569 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2570
2571 for (reg = ROM32(bios->data[seqtbloffs]);
2572 reg != 0xffffffff;
2573 reg = ROM32(bios->data[seqtbloffs += 4])) {
2574
2575 switch (reg) {
2576 case NV04_PFB_PRE:
2577 data = NV04_PFB_PRE_CMD_PRECHARGE;
2578 break;
2579 case NV04_PFB_PAD:
2580 data = NV04_PFB_PAD_CKE_NORMAL;
2581 break;
2582 case NV04_PFB_REF:
2583 data = NV04_PFB_REF_CMD_REFRESH;
2584 break;
2585 default:
2586 data = ROM32(bios->data[meminitdata]);
2587 meminitdata += 4;
2588 if (data == 0xffffffff)
2589 continue;
2590 }
2591
2592 bios_wr32(bios, reg, data);
2593 }
2594
2595 return 1;
2596 }
2597
2598 static int
2599 init_configure_clk(struct nvbios *bios, uint16_t offset,
2600 struct init_exec *iexec)
2601 {
2602 /*
2603 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2604 *
2605 * offset (8 bit): opcode
2606 *
2607 * Equivalent to INIT_DONE on bios version 3 or greater.
2608 * For early bios versions, sets up the NVClk and MClk PLLs, using
2609 * values taken from the memory init table
2610 */
2611
2612 /* no iexec->execute check by design */
2613
2614 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2615 int clock;
2616
2617 if (bios->major_version > 2)
2618 return 0;
2619
2620 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2621 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2622
2623 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2624 if (bios->data[meminitoffs] & 1) /* DDR */
2625 clock *= 2;
2626 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2627
2628 return 1;
2629 }
2630
2631 static int
2632 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2633 struct init_exec *iexec)
2634 {
2635 /*
2636 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2637 *
2638 * offset (8 bit): opcode
2639 *
2640 * Equivalent to INIT_DONE on bios version 3 or greater.
2641 * For early bios versions, does early init, loading ram and crystal
2642 * configuration from straps into CR3C
2643 */
2644
2645 /* no iexec->execute check by design */
2646
2647 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2648 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2649
2650 if (bios->major_version > 2)
2651 return 0;
2652
2653 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2654 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2655
2656 return 1;
2657 }
2658
2659 static int
2660 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2661 {
2662 /*
2663 * INIT_IO opcode: 0x69 ('i')
2664 *
2665 * offset (8 bit): opcode
2666 * offset + 1 (16 bit): CRTC port
2667 * offset + 3 (8 bit): mask
2668 * offset + 4 (8 bit): data
2669 *
2670 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2671 */
2672
2673 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2674 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2675 uint8_t mask = bios->data[offset + 3];
2676 uint8_t data = bios->data[offset + 4];
2677
2678 if (!iexec->execute)
2679 return 5;
2680
2681 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2682 offset, crtcport, mask, data);
2683
2684 /*
2685 * I have no idea what this does, but NVIDIA do this magic sequence
2686 * in the places where this INIT_IO happens..
2687 */
2688 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2689 int i;
2690
2691 bios_wr32(bios, 0x614100, (bios_rd32(
2692 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2693
2694 bios_wr32(bios, 0x00e18c, bios_rd32(
2695 bios, 0x00e18c) | 0x00020000);
2696
2697 bios_wr32(bios, 0x614900, (bios_rd32(
2698 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2699
2700 bios_wr32(bios, 0x000200, bios_rd32(
2701 bios, 0x000200) & ~0x40000000);
2702
2703 mdelay(10);
2704
2705 bios_wr32(bios, 0x00e18c, bios_rd32(
2706 bios, 0x00e18c) & ~0x00020000);
2707
2708 bios_wr32(bios, 0x000200, bios_rd32(
2709 bios, 0x000200) | 0x40000000);
2710
2711 bios_wr32(bios, 0x614100, 0x00800018);
2712 bios_wr32(bios, 0x614900, 0x00800018);
2713
2714 mdelay(10);
2715
2716 bios_wr32(bios, 0x614100, 0x10000018);
2717 bios_wr32(bios, 0x614900, 0x10000018);
2718
2719 for (i = 0; i < 3; i++)
2720 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2721 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2722
2723 for (i = 0; i < 2; i++)
2724 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2725 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2726
2727 for (i = 0; i < 3; i++)
2728 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2729 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2730
2731 for (i = 0; i < 2; i++)
2732 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2733 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2734
2735 for (i = 0; i < 2; i++)
2736 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2737 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2738 return 5;
2739 }
2740
2741 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2742 data);
2743 return 5;
2744 }
2745
2746 static int
2747 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2748 {
2749 /*
2750 * INIT_SUB opcode: 0x6B ('k')
2751 *
2752 * offset (8 bit): opcode
2753 * offset + 1 (8 bit): script number
2754 *
2755 * Execute script number "script number", as a subroutine
2756 */
2757
2758 uint8_t sub = bios->data[offset + 1];
2759
2760 if (!iexec->execute)
2761 return 2;
2762
2763 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2764
2765 parse_init_table(bios,
2766 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2767 iexec);
2768
2769 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2770
2771 return 2;
2772 }
2773
2774 static int
2775 init_ram_condition(struct nvbios *bios, uint16_t offset,
2776 struct init_exec *iexec)
2777 {
2778 /*
2779 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2780 *
2781 * offset (8 bit): opcode
2782 * offset + 1 (8 bit): mask
2783 * offset + 2 (8 bit): cmpval
2784 *
2785 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2786 * If condition not met skip subsequent opcodes until condition is
2787 * inverted (INIT_NOT), or we hit INIT_RESUME
2788 */
2789
2790 uint8_t mask = bios->data[offset + 1];
2791 uint8_t cmpval = bios->data[offset + 2];
2792 uint8_t data;
2793
2794 if (!iexec->execute)
2795 return 3;
2796
2797 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2798
2799 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2800 offset, data, cmpval);
2801
2802 if (data == cmpval)
2803 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2804 else {
2805 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2806 iexec->execute = false;
2807 }
2808
2809 return 3;
2810 }
2811
2812 static int
2813 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2814 {
2815 /*
2816 * INIT_NV_REG opcode: 0x6E ('n')
2817 *
2818 * offset (8 bit): opcode
2819 * offset + 1 (32 bit): register
2820 * offset + 5 (32 bit): mask
2821 * offset + 9 (32 bit): data
2822 *
2823 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2824 */
2825
2826 uint32_t reg = ROM32(bios->data[offset + 1]);
2827 uint32_t mask = ROM32(bios->data[offset + 5]);
2828 uint32_t data = ROM32(bios->data[offset + 9]);
2829
2830 if (!iexec->execute)
2831 return 13;
2832
2833 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2834 offset, reg, mask, data);
2835
2836 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2837
2838 return 13;
2839 }
2840
2841 static int
2842 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2843 {
2844 /*
2845 * INIT_MACRO opcode: 0x6F ('o')
2846 *
2847 * offset (8 bit): opcode
2848 * offset + 1 (8 bit): macro number
2849 *
2850 * Look up macro index "macro number" in the macro index table.
2851 * The macro index table entry has 1 byte for the index in the macro
2852 * table, and 1 byte for the number of times to repeat the macro.
2853 * The macro table entry has 4 bytes for the register address and
2854 * 4 bytes for the value to write to that register
2855 */
2856
2857 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2858 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2859 uint8_t macro_tbl_idx = bios->data[tmp];
2860 uint8_t count = bios->data[tmp + 1];
2861 uint32_t reg, data;
2862 int i;
2863
2864 if (!iexec->execute)
2865 return 2;
2866
2867 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2868 "Count: 0x%02X\n",
2869 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2870
2871 for (i = 0; i < count; i++) {
2872 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2873
2874 reg = ROM32(bios->data[macroentryptr]);
2875 data = ROM32(bios->data[macroentryptr + 4]);
2876
2877 bios_wr32(bios, reg, data);
2878 }
2879
2880 return 2;
2881 }
2882
2883 static int
2884 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2885 {
2886 /*
2887 * INIT_DONE opcode: 0x71 ('q')
2888 *
2889 * offset (8 bit): opcode
2890 *
2891 * End the current script
2892 */
2893
2894 /* mild retval abuse to stop parsing this table */
2895 return 0;
2896 }
2897
2898 static int
2899 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2900 {
2901 /*
2902 * INIT_RESUME opcode: 0x72 ('r')
2903 *
2904 * offset (8 bit): opcode
2905 *
2906 * End the current execute / no-execute condition
2907 */
2908
2909 if (iexec->execute)
2910 return 1;
2911
2912 iexec->execute = true;
2913 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2914
2915 return 1;
2916 }
2917
2918 static int
2919 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2920 {
2921 /*
2922 * INIT_TIME opcode: 0x74 ('t')
2923 *
2924 * offset (8 bit): opcode
2925 * offset + 1 (16 bit): time
2926 *
2927 * Sleep for "time" microseconds.
2928 */
2929
2930 unsigned time = ROM16(bios->data[offset + 1]);
2931
2932 if (!iexec->execute)
2933 return 3;
2934
2935 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2936 offset, time);
2937
2938 if (time < 1000)
2939 udelay(time);
2940 else
2941 mdelay((time + 900) / 1000);
2942
2943 return 3;
2944 }
2945
2946 static int
2947 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2948 {
2949 /*
2950 * INIT_CONDITION opcode: 0x75 ('u')
2951 *
2952 * offset (8 bit): opcode
2953 * offset + 1 (8 bit): condition number
2954 *
2955 * Check condition "condition number" in the condition table.
2956 * If condition not met skip subsequent opcodes until condition is
2957 * inverted (INIT_NOT), or we hit INIT_RESUME
2958 */
2959
2960 uint8_t cond = bios->data[offset + 1];
2961
2962 if (!iexec->execute)
2963 return 2;
2964
2965 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2966
2967 if (bios_condition_met(bios, offset, cond))
2968 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2969 else {
2970 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2971 iexec->execute = false;
2972 }
2973
2974 return 2;
2975 }
2976
2977 static int
2978 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2979 {
2980 /*
2981 * INIT_IO_CONDITION opcode: 0x76
2982 *
2983 * offset (8 bit): opcode
2984 * offset + 1 (8 bit): condition number
2985 *
2986 * Check condition "condition number" in the io condition table.
2987 * If condition not met skip subsequent opcodes until condition is
2988 * inverted (INIT_NOT), or we hit INIT_RESUME
2989 */
2990
2991 uint8_t cond = bios->data[offset + 1];
2992
2993 if (!iexec->execute)
2994 return 2;
2995
2996 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2997
2998 if (io_condition_met(bios, offset, cond))
2999 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3000 else {
3001 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3002 iexec->execute = false;
3003 }
3004
3005 return 2;
3006 }
3007
3008 static int
3009 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3010 {
3011 /*
3012 * INIT_INDEX_IO opcode: 0x78 ('x')
3013 *
3014 * offset (8 bit): opcode
3015 * offset + 1 (16 bit): CRTC port
3016 * offset + 3 (8 bit): CRTC index
3017 * offset + 4 (8 bit): mask
3018 * offset + 5 (8 bit): data
3019 *
3020 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3021 * OR with "data", write-back
3022 */
3023
3024 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3025 uint8_t crtcindex = bios->data[offset + 3];
3026 uint8_t mask = bios->data[offset + 4];
3027 uint8_t data = bios->data[offset + 5];
3028 uint8_t value;
3029
3030 if (!iexec->execute)
3031 return 6;
3032
3033 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3034 "Data: 0x%02X\n",
3035 offset, crtcport, crtcindex, mask, data);
3036
3037 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3038 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3039
3040 return 6;
3041 }
3042
3043 static int
3044 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3045 {
3046 /*
3047 * INIT_PLL opcode: 0x79 ('y')
3048 *
3049 * offset (8 bit): opcode
3050 * offset + 1 (32 bit): register
3051 * offset + 5 (16 bit): freq
3052 *
3053 * Set PLL register "register" to coefficients for frequency (10kHz)
3054 * "freq"
3055 */
3056
3057 uint32_t reg = ROM32(bios->data[offset + 1]);
3058 uint16_t freq = ROM16(bios->data[offset + 5]);
3059
3060 if (!iexec->execute)
3061 return 7;
3062
3063 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3064
3065 setPLL(bios, reg, freq * 10);
3066
3067 return 7;
3068 }
3069
3070 static int
3071 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3072 {
3073 /*
3074 * INIT_ZM_REG opcode: 0x7A ('z')
3075 *
3076 * offset (8 bit): opcode
3077 * offset + 1 (32 bit): register
3078 * offset + 5 (32 bit): value
3079 *
3080 * Assign "value" to "register"
3081 */
3082
3083 uint32_t reg = ROM32(bios->data[offset + 1]);
3084 uint32_t value = ROM32(bios->data[offset + 5]);
3085
3086 if (!iexec->execute)
3087 return 9;
3088
3089 if (reg == 0x000200)
3090 value |= 1;
3091
3092 bios_wr32(bios, reg, value);
3093
3094 return 9;
3095 }
3096
3097 static int
3098 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3099 struct init_exec *iexec)
3100 {
3101 /*
3102 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3103 *
3104 * offset (8 bit): opcode
3105 * offset + 1 (8 bit): PLL type
3106 * offset + 2 (32 bit): frequency 0
3107 *
3108 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3109 * ram_restrict_table_ptr. The value read from there is used to select
3110 * a frequency from the table starting at 'frequency 0' to be
3111 * programmed into the PLL corresponding to 'type'.
3112 *
3113 * The PLL limits table on cards using this opcode has a mapping of
3114 * 'type' to the relevant registers.
3115 */
3116
3117 struct drm_device *dev = bios->dev;
3118 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3119 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3120 uint8_t type = bios->data[offset + 1];
3121 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3122 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3123 int len = 2 + bios->ram_restrict_group_count * 4;
3124 int i;
3125
3126 if (!iexec->execute)
3127 return len;
3128
3129 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3130 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3131 return len; /* deliberate, allow default clocks to remain */
3132 }
3133
3134 entry = pll_limits + pll_limits[1];
3135 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3136 if (entry[0] == type) {
3137 uint32_t reg = ROM32(entry[3]);
3138
3139 BIOSLOG(bios, "0x%04X: "
3140 "Type %02x Reg 0x%08x Freq %dKHz\n",
3141 offset, type, reg, freq);
3142
3143 setPLL(bios, reg, freq);
3144 return len;
3145 }
3146 }
3147
3148 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3149 return len;
3150 }
3151
3152 static int
3153 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3154 {
3155 /*
3156 * INIT_8C opcode: 0x8C ('')
3157 *
3158 * NOP so far....
3159 *
3160 */
3161
3162 return 1;
3163 }
3164
3165 static int
3166 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3167 {
3168 /*
3169 * INIT_8D opcode: 0x8D ('')
3170 *
3171 * NOP so far....
3172 *
3173 */
3174
3175 return 1;
3176 }
3177
3178 static int
3179 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3180 {
3181 /*
3182 * INIT_GPIO opcode: 0x8E ('')
3183 *
3184 * offset (8 bit): opcode
3185 *
3186 * Loop over all entries in the DCB GPIO table, and initialise
3187 * each GPIO according to various values listed in each entry
3188 */
3189
3190 if (iexec->execute && bios->execute)
3191 nouveau_gpio_reset(bios->dev);
3192
3193 return 1;
3194 }
3195
3196 static int
3197 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3198 struct init_exec *iexec)
3199 {
3200 /*
3201 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3202 *
3203 * offset (8 bit): opcode
3204 * offset + 1 (32 bit): reg
3205 * offset + 5 (8 bit): regincrement
3206 * offset + 6 (8 bit): count
3207 * offset + 7 (32 bit): value 1,1
3208 * ...
3209 *
3210 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3211 * ram_restrict_table_ptr. The value read from here is 'n', and
3212 * "value 1,n" gets written to "reg". This repeats "count" times and on
3213 * each iteration 'm', "reg" increases by "regincrement" and
3214 * "value m,n" is used. The extent of n is limited by a number read
3215 * from the 'M' BIT table, herein called "blocklen"
3216 */
3217
3218 uint32_t reg = ROM32(bios->data[offset + 1]);
3219 uint8_t regincrement = bios->data[offset + 5];
3220 uint8_t count = bios->data[offset + 6];
3221 uint32_t strap_ramcfg, data;
3222 /* previously set by 'M' BIT table */
3223 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3224 int len = 7 + count * blocklen;
3225 uint8_t index;
3226 int i;
3227
3228 /* critical! to know the length of the opcode */;
3229 if (!blocklen) {
3230 NV_ERROR(bios->dev,
3231 "0x%04X: Zero block length - has the M table "
3232 "been parsed?\n", offset);
3233 return -EINVAL;
3234 }
3235
3236 if (!iexec->execute)
3237 return len;
3238
3239 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3240 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3241
3242 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3243 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3244 offset, reg, regincrement, count, strap_ramcfg, index);
3245
3246 for (i = 0; i < count; i++) {
3247 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3248
3249 bios_wr32(bios, reg, data);
3250
3251 reg += regincrement;
3252 }
3253
3254 return len;
3255 }
3256
3257 static int
3258 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3259 {
3260 /*
3261 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3262 *
3263 * offset (8 bit): opcode
3264 * offset + 1 (32 bit): src reg
3265 * offset + 5 (32 bit): dst reg
3266 *
3267 * Put contents of "src reg" into "dst reg"
3268 */
3269
3270 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3271 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3272
3273 if (!iexec->execute)
3274 return 9;
3275
3276 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3277
3278 return 9;
3279 }
3280
3281 static int
3282 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3283 struct init_exec *iexec)
3284 {
3285 /*
3286 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3287 *
3288 * offset (8 bit): opcode
3289 * offset + 1 (32 bit): dst reg
3290 * offset + 5 (8 bit): count
3291 * offset + 6 (32 bit): data 1
3292 * ...
3293 *
3294 * For each of "count" values write "data n" to "dst reg"
3295 */
3296
3297 uint32_t reg = ROM32(bios->data[offset + 1]);
3298 uint8_t count = bios->data[offset + 5];
3299 int len = 6 + count * 4;
3300 int i;
3301
3302 if (!iexec->execute)
3303 return len;
3304
3305 for (i = 0; i < count; i++) {
3306 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3307 bios_wr32(bios, reg, data);
3308 }
3309
3310 return len;
3311 }
3312
3313 static int
3314 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3315 {
3316 /*
3317 * INIT_RESERVED opcode: 0x92 ('')
3318 *
3319 * offset (8 bit): opcode
3320 *
3321 * Seemingly does nothing
3322 */
3323
3324 return 1;
3325 }
3326
3327 static int
3328 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3329 {
3330 /*
3331 * INIT_96 opcode: 0x96 ('')
3332 *
3333 * offset (8 bit): opcode
3334 * offset + 1 (32 bit): sreg
3335 * offset + 5 (8 bit): sshift
3336 * offset + 6 (8 bit): smask
3337 * offset + 7 (8 bit): index
3338 * offset + 8 (32 bit): reg
3339 * offset + 12 (32 bit): mask
3340 * offset + 16 (8 bit): shift
3341 *
3342 */
3343
3344 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3345 uint32_t reg = ROM32(bios->data[offset + 8]);
3346 uint32_t mask = ROM32(bios->data[offset + 12]);
3347 uint32_t val;
3348
3349 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3350 if (bios->data[offset + 5] < 0x80)
3351 val >>= bios->data[offset + 5];
3352 else
3353 val <<= (0x100 - bios->data[offset + 5]);
3354 val &= bios->data[offset + 6];
3355
3356 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3357 val <<= bios->data[offset + 16];
3358
3359 if (!iexec->execute)
3360 return 17;
3361
3362 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3363 return 17;
3364 }
3365
3366 static int
3367 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3368 {
3369 /*
3370 * INIT_97 opcode: 0x97 ('')
3371 *
3372 * offset (8 bit): opcode
3373 * offset + 1 (32 bit): register
3374 * offset + 5 (32 bit): mask
3375 * offset + 9 (32 bit): value
3376 *
3377 * Adds "value" to "register" preserving the fields specified
3378 * by "mask"
3379 */
3380
3381 uint32_t reg = ROM32(bios->data[offset + 1]);
3382 uint32_t mask = ROM32(bios->data[offset + 5]);
3383 uint32_t add = ROM32(bios->data[offset + 9]);
3384 uint32_t val;
3385
3386 val = bios_rd32(bios, reg);
3387 val = (val & mask) | ((val + add) & ~mask);
3388
3389 if (!iexec->execute)
3390 return 13;
3391
3392 bios_wr32(bios, reg, val);
3393 return 13;
3394 }
3395
3396 static int
3397 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3398 {
3399 /*
3400 * INIT_AUXCH opcode: 0x98 ('')
3401 *
3402 * offset (8 bit): opcode
3403 * offset + 1 (32 bit): address
3404 * offset + 5 (8 bit): count
3405 * offset + 6 (8 bit): mask 0
3406 * offset + 7 (8 bit): data 0
3407 * ...
3408 *
3409 */
3410
3411 struct drm_device *dev = bios->dev;
3412 struct nouveau_i2c_chan *auxch;
3413 uint32_t addr = ROM32(bios->data[offset + 1]);
3414 uint8_t count = bios->data[offset + 5];
3415 int len = 6 + count * 2;
3416 int ret, i;
3417
3418 if (!bios->display.output) {
3419 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3420 return len;
3421 }
3422
3423 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3424 if (!auxch) {
3425 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3426 bios->display.output->i2c_index);
3427 return len;
3428 }
3429
3430 if (!iexec->execute)
3431 return len;
3432
3433 offset += 6;
3434 for (i = 0; i < count; i++, offset += 2) {
3435 uint8_t data;
3436
3437 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3438 if (ret) {
3439 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3440 return len;
3441 }
3442
3443 data &= bios->data[offset + 0];
3444 data |= bios->data[offset + 1];
3445
3446 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3447 if (ret) {
3448 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3449 return len;
3450 }
3451 }
3452
3453 return len;
3454 }
3455
3456 static int
3457 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3458 {
3459 /*
3460 * INIT_ZM_AUXCH opcode: 0x99 ('')
3461 *
3462 * offset (8 bit): opcode
3463 * offset + 1 (32 bit): address
3464 * offset + 5 (8 bit): count
3465 * offset + 6 (8 bit): data 0
3466 * ...
3467 *
3468 */
3469
3470 struct drm_device *dev = bios->dev;
3471 struct nouveau_i2c_chan *auxch;
3472 uint32_t addr = ROM32(bios->data[offset + 1]);
3473 uint8_t count = bios->data[offset + 5];
3474 int len = 6 + count;
3475 int ret, i;
3476
3477 if (!bios->display.output) {
3478 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3479 return len;
3480 }
3481
3482 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3483 if (!auxch) {
3484 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3485 bios->display.output->i2c_index);
3486 return len;
3487 }
3488
3489 if (!iexec->execute)
3490 return len;
3491
3492 offset += 6;
3493 for (i = 0; i < count; i++, offset++) {
3494 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3495 if (ret) {
3496 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3497 return len;
3498 }
3499 }
3500
3501 return len;
3502 }
3503
3504 static int
3505 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3506 {
3507 /*
3508 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3509 *
3510 * offset (8 bit): opcode
3511 * offset + 1 (8 bit): DCB I2C table entry index
3512 * offset + 2 (8 bit): I2C slave address
3513 * offset + 3 (16 bit): I2C register
3514 * offset + 5 (8 bit): mask
3515 * offset + 6 (8 bit): data
3516 *
3517 * Read the register given by "I2C register" on the device addressed
3518 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3519 * entry index". Compare the result AND "mask" to "data".
3520 * If they're not equal, skip subsequent opcodes until condition is
3521 * inverted (INIT_NOT), or we hit INIT_RESUME
3522 */
3523
3524 uint8_t i2c_index = bios->data[offset + 1];
3525 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3526 uint8_t reglo = bios->data[offset + 3];
3527 uint8_t reghi = bios->data[offset + 4];
3528 uint8_t mask = bios->data[offset + 5];
3529 uint8_t data = bios->data[offset + 6];
3530 struct nouveau_i2c_chan *chan;
3531 uint8_t buf0[2] = { reghi, reglo };
3532 uint8_t buf1[1];
3533 struct i2c_msg msg[2] = {
3534 { i2c_address, 0, 1, buf0 },
3535 { i2c_address, I2C_M_RD, 1, buf1 },
3536 };
3537 int ret;
3538
3539 /* no execute check by design */
3540
3541 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3542 offset, i2c_index, i2c_address);
3543
3544 chan = init_i2c_device_find(bios->dev, i2c_index);
3545 if (!chan)
3546 return -ENODEV;
3547
3548
3549 ret = i2c_transfer(&chan->adapter, msg, 2);
3550 if (ret < 0) {
3551 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3552 "Mask: 0x%02X, Data: 0x%02X\n",
3553 offset, reghi, reglo, mask, data);
3554 iexec->execute = 0;
3555 return 7;
3556 }
3557
3558 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3559 "Mask: 0x%02X, Data: 0x%02X\n",
3560 offset, reghi, reglo, buf1[0], mask, data);
3561
3562 iexec->execute = ((buf1[0] & mask) == data);
3563
3564 return 7;
3565 }
3566
3567 static struct init_tbl_entry itbl_entry[] = {
3568 /* command name , id , length , offset , mult , command handler */
3569 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3570 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3571 { "INIT_REPEAT" , 0x33, init_repeat },
3572 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3573 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3574 { "INIT_COPY" , 0x37, init_copy },
3575 { "INIT_NOT" , 0x38, init_not },
3576 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3577 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3578 { "INIT_OP_3B" , 0x3B, init_op_3b },
3579 { "INIT_OP_3C" , 0x3C, init_op_3c },
3580 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3581 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3582 { "INIT_PLL2" , 0x4B, init_pll2 },
3583 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3584 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3585 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3586 { "INIT_TMDS" , 0x4F, init_tmds },
3587 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3588 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3589 { "INIT_CR" , 0x52, init_cr },
3590 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3591 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3592 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3593 { "INIT_LTIME" , 0x57, init_ltime },
3594 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3595 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3596 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3597 { "INIT_JUMP" , 0x5C, init_jump },
3598 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3599 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3600 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3601 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3602 { "INIT_RESET" , 0x65, init_reset },
3603 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3604 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3605 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3606 { "INIT_IO" , 0x69, init_io },
3607 { "INIT_SUB" , 0x6B, init_sub },
3608 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3609 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3610 { "INIT_MACRO" , 0x6F, init_macro },
3611 { "INIT_DONE" , 0x71, init_done },
3612 { "INIT_RESUME" , 0x72, init_resume },
3613 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3614 { "INIT_TIME" , 0x74, init_time },
3615 { "INIT_CONDITION" , 0x75, init_condition },
3616 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3617 { "INIT_INDEX_IO" , 0x78, init_index_io },
3618 { "INIT_PLL" , 0x79, init_pll },
3619 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3620 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3621 { "INIT_8C" , 0x8C, init_8c },
3622 { "INIT_8D" , 0x8D, init_8d },
3623 { "INIT_GPIO" , 0x8E, init_gpio },
3624 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3625 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3626 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3627 { "INIT_RESERVED" , 0x92, init_reserved },
3628 { "INIT_96" , 0x96, init_96 },
3629 { "INIT_97" , 0x97, init_97 },
3630 { "INIT_AUXCH" , 0x98, init_auxch },
3631 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3632 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3633 { NULL , 0 , NULL }
3634 };
3635
3636 #define MAX_TABLE_OPS 1000
3637
3638 static int
3639 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3640 {
3641 /*
3642 * Parses all commands in an init table.
3643 *
3644 * We start out executing all commands found in the init table. Some
3645 * opcodes may change the status of iexec->execute to SKIP, which will
3646 * cause the following opcodes to perform no operation until the value
3647 * is changed back to EXECUTE.
3648 */
3649
3650 int count = 0, i, ret;
3651 uint8_t id;
3652
3653 /* catch NULL script pointers */
3654 if (offset == 0)
3655 return 0;
3656
3657 /*
3658 * Loop until INIT_DONE causes us to break out of the loop
3659 * (or until offset > bios length just in case... )
3660 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3661 */
3662 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3663 id = bios->data[offset];
3664
3665 /* Find matching id in itbl_entry */
3666 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3667 ;
3668
3669 if (!itbl_entry[i].name) {
3670 NV_ERROR(bios->dev,
3671 "0x%04X: Init table command not found: "
3672 "0x%02X\n", offset, id);
3673 return -ENOENT;
3674 }
3675
3676 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3677 itbl_entry[i].id, itbl_entry[i].name);
3678
3679 /* execute eventual command handler */
3680 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3681 if (ret < 0) {
3682 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3683 "table opcode: %s %d\n", offset,
3684 itbl_entry[i].name, ret);
3685 }
3686
3687 if (ret <= 0)
3688 break;
3689
3690 /*
3691 * Add the offset of the current command including all data
3692 * of that command. The offset will then be pointing on the
3693 * next op code.
3694 */
3695 offset += ret;
3696 }
3697
3698 if (offset >= bios->length)
3699 NV_WARN(bios->dev,
3700 "Offset 0x%04X greater than known bios image length. "
3701 "Corrupt image?\n", offset);
3702 if (count >= MAX_TABLE_OPS)
3703 NV_WARN(bios->dev,
3704 "More than %d opcodes to a table is unlikely, "
3705 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3706
3707 return 0;
3708 }
3709
3710 static void
3711 parse_init_tables(struct nvbios *bios)
3712 {
3713 /* Loops and calls parse_init_table() for each present table. */
3714
3715 int i = 0;
3716 uint16_t table;
3717 struct init_exec iexec = {true, false};
3718
3719 if (bios->old_style_init) {
3720 if (bios->init_script_tbls_ptr)
3721 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3722 if (bios->extra_init_script_tbl_ptr)
3723 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3724
3725 return;
3726 }
3727
3728 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3729 NV_INFO(bios->dev,
3730 "Parsing VBIOS init table %d at offset 0x%04X\n",
3731 i / 2, table);
3732 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3733
3734 parse_init_table(bios, table, &iexec);
3735 i += 2;
3736 }
3737 }
3738
3739 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3740 {
3741 int compare_record_len, i = 0;
3742 uint16_t compareclk, scriptptr = 0;
3743
3744 if (bios->major_version < 5) /* pre BIT */
3745 compare_record_len = 3;
3746 else
3747 compare_record_len = 4;
3748
3749 do {
3750 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3751 if (pxclk >= compareclk * 10) {
3752 if (bios->major_version < 5) {
3753 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3754 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3755 } else
3756 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3757 break;
3758 }
3759 i++;
3760 } while (compareclk);
3761
3762 return scriptptr;
3763 }
3764
3765 static void
3766 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3767 struct dcb_entry *dcbent, int head, bool dl)
3768 {
3769 struct drm_nouveau_private *dev_priv = dev->dev_private;
3770 struct nvbios *bios = &dev_priv->vbios;
3771 struct init_exec iexec = {true, false};
3772
3773 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3774 scriptptr);
3775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3776 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3777 /* note: if dcb entries have been merged, index may be misleading */
3778 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3779 parse_init_table(bios, scriptptr, &iexec);
3780
3781 nv04_dfp_bind_head(dev, dcbent, head, dl);
3782 }
3783
3784 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3785 {
3786 struct drm_nouveau_private *dev_priv = dev->dev_private;
3787 struct nvbios *bios = &dev_priv->vbios;
3788 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3789 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3790
3791 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3792 return -EINVAL;
3793
3794 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3795
3796 if (script == LVDS_PANEL_OFF) {
3797 /* off-on delay in ms */
3798 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3799 }
3800 #ifdef __powerpc__
3801 /* Powerbook specific quirks */
3802 if (script == LVDS_RESET &&
3803 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3804 dev->pci_device == 0x0329))
3805 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3806 #endif
3807
3808 return 0;
3809 }
3810
3811 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3812 {
3813 /*
3814 * The BIT LVDS table's header has the information to setup the
3815 * necessary registers. Following the standard 4 byte header are:
3816 * A bitmask byte and a dual-link transition pxclk value for use in
3817 * selecting the init script when not using straps; 4 script pointers
3818 * for panel power, selected by output and on/off; and 8 table pointers
3819 * for panel init, the needed one determined by output, and bits in the
3820 * conf byte. These tables are similar to the TMDS tables, consisting
3821 * of a list of pxclks and script pointers.
3822 */
3823 struct drm_nouveau_private *dev_priv = dev->dev_private;
3824 struct nvbios *bios = &dev_priv->vbios;
3825 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3826 uint16_t scriptptr = 0, clktable;
3827
3828 /*
3829 * For now we assume version 3.0 table - g80 support will need some
3830 * changes
3831 */
3832
3833 switch (script) {
3834 case LVDS_INIT:
3835 return -ENOSYS;
3836 case LVDS_BACKLIGHT_ON:
3837 case LVDS_PANEL_ON:
3838 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3839 break;
3840 case LVDS_BACKLIGHT_OFF:
3841 case LVDS_PANEL_OFF:
3842 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3843 break;
3844 case LVDS_RESET:
3845 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3846 if (dcbent->or == 4)
3847 clktable += 8;
3848
3849 if (dcbent->lvdsconf.use_straps_for_mode) {
3850 if (bios->fp.dual_link)
3851 clktable += 4;
3852 if (bios->fp.if_is_24bit)
3853 clktable += 2;
3854 } else {
3855 /* using EDID */
3856 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3857
3858 if (bios->fp.dual_link) {
3859 clktable += 4;
3860 cmpval_24bit <<= 1;
3861 }
3862
3863 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3864 clktable += 2;
3865 }
3866
3867 clktable = ROM16(bios->data[clktable]);
3868 if (!clktable) {
3869 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3870 return -ENOENT;
3871 }
3872 scriptptr = clkcmptable(bios, clktable, pxclk);
3873 }
3874
3875 if (!scriptptr) {
3876 NV_ERROR(dev, "LVDS output init script not found\n");
3877 return -ENOENT;
3878 }
3879 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3880
3881 return 0;
3882 }
3883
3884 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3885 {
3886 /*
3887 * LVDS operations are multiplexed in an effort to present a single API
3888 * which works with two vastly differing underlying structures.
3889 * This acts as the demux
3890 */
3891
3892 struct drm_nouveau_private *dev_priv = dev->dev_private;
3893 struct nvbios *bios = &dev_priv->vbios;
3894 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3895 uint32_t sel_clk_binding, sel_clk;
3896 int ret;
3897
3898 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3899 (lvds_ver >= 0x30 && script == LVDS_INIT))
3900 return 0;
3901
3902 if (!bios->fp.lvds_init_run) {
3903 bios->fp.lvds_init_run = true;
3904 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3905 }
3906
3907 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3908 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3909 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3910 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3911
3912 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3913
3914 /* don't let script change pll->head binding */
3915 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3916
3917 if (lvds_ver < 0x30)
3918 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3919 else
3920 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3921
3922 bios->fp.last_script_invoc = (script << 1 | head);
3923
3924 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3925 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3926 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3927 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3928
3929 return ret;
3930 }
3931
3932 struct lvdstableheader {
3933 uint8_t lvds_ver, headerlen, recordlen;
3934 };
3935
3936 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3937 {
3938 /*
3939 * BMP version (0xa) LVDS table has a simple header of version and
3940 * record length. The BIT LVDS table has the typical BIT table header:
3941 * version byte, header length byte, record length byte, and a byte for
3942 * the maximum number of records that can be held in the table.
3943 */
3944
3945 uint8_t lvds_ver, headerlen, recordlen;
3946
3947 memset(lth, 0, sizeof(struct lvdstableheader));
3948
3949 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3950 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3951 return -EINVAL;
3952 }
3953
3954 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3955
3956 switch (lvds_ver) {
3957 case 0x0a: /* pre NV40 */
3958 headerlen = 2;
3959 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3960 break;
3961 case 0x30: /* NV4x */
3962 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3963 if (headerlen < 0x1f) {
3964 NV_ERROR(dev, "LVDS table header not understood\n");
3965 return -EINVAL;
3966 }
3967 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3968 break;
3969 case 0x40: /* G80/G90 */
3970 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3971 if (headerlen < 0x7) {
3972 NV_ERROR(dev, "LVDS table header not understood\n");
3973 return -EINVAL;
3974 }
3975 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3976 break;
3977 default:
3978 NV_ERROR(dev,
3979 "LVDS table revision %d.%d not currently supported\n",
3980 lvds_ver >> 4, lvds_ver & 0xf);
3981 return -ENOSYS;
3982 }
3983
3984 lth->lvds_ver = lvds_ver;
3985 lth->headerlen = headerlen;
3986 lth->recordlen = recordlen;
3987
3988 return 0;
3989 }
3990
3991 static int
3992 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3993 {
3994 struct drm_nouveau_private *dev_priv = dev->dev_private;
3995
3996 /*
3997 * The fp strap is normally dictated by the "User Strap" in
3998 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3999 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4000 * by the PCI subsystem ID during POST, but not before the previous user
4001 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4002 * read and used instead
4003 */
4004
4005 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4006 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4007
4008 if (dev_priv->card_type >= NV_50)
4009 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4010 else
4011 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4012 }
4013
4014 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4015 {
4016 uint8_t *fptable;
4017 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4018 int ret, ofs, fpstrapping;
4019 struct lvdstableheader lth;
4020
4021 if (bios->fp.fptablepointer == 0x0) {
4022 /* Apple cards don't have the fp table; the laptops use DDC */
4023 /* The table is also missing on some x86 IGPs */
4024 #ifndef __powerpc__
4025 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4026 #endif
4027 bios->digital_min_front_porch = 0x4b;
4028 return 0;
4029 }
4030
4031 fptable = &bios->data[bios->fp.fptablepointer];
4032 fptable_ver = fptable[0];
4033
4034 switch (fptable_ver) {
4035 /*
4036 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4037 * version field, and miss one of the spread spectrum/PWM bytes.
4038 * This could affect early GF2Go parts (not seen any appropriate ROMs
4039 * though). Here we assume that a version of 0x05 matches this case
4040 * (combining with a BMP version check would be better), as the
4041 * common case for the panel type field is 0x0005, and that is in
4042 * fact what we are reading the first byte of.
4043 */
4044 case 0x05: /* some NV10, 11, 15, 16 */
4045 recordlen = 42;
4046 ofs = -1;
4047 break;
4048 case 0x10: /* some NV15/16, and NV11+ */
4049 recordlen = 44;
4050 ofs = 0;
4051 break;
4052 case 0x20: /* NV40+ */
4053 headerlen = fptable[1];
4054 recordlen = fptable[2];
4055 fpentries = fptable[3];
4056 /*
4057 * fptable[4] is the minimum
4058 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4059 */
4060 bios->digital_min_front_porch = fptable[4];
4061 ofs = -7;
4062 break;
4063 default:
4064 NV_ERROR(dev,
4065 "FP table revision %d.%d not currently supported\n",
4066 fptable_ver >> 4, fptable_ver & 0xf);
4067 return -ENOSYS;
4068 }
4069
4070 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4071 return 0;
4072
4073 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4074 if (ret)
4075 return ret;
4076
4077 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4078 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4079 lth.headerlen + 1;
4080 bios->fp.xlatwidth = lth.recordlen;
4081 }
4082 if (bios->fp.fpxlatetableptr == 0x0) {
4083 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4084 return -EINVAL;
4085 }
4086
4087 fpstrapping = get_fp_strap(dev, bios);
4088
4089 fpindex = bios->data[bios->fp.fpxlatetableptr +
4090 fpstrapping * bios->fp.xlatwidth];
4091
4092 if (fpindex > fpentries) {
4093 NV_ERROR(dev, "Bad flat panel table index\n");
4094 return -ENOENT;
4095 }
4096
4097 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4098 if (lth.lvds_ver > 0x10)
4099 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4100
4101 /*
4102 * If either the strap or xlated fpindex value are 0xf there is no
4103 * panel using a strap-derived bios mode present. this condition
4104 * includes, but is different from, the DDC panel indicator above
4105 */
4106 if (fpstrapping == 0xf || fpindex == 0xf)
4107 return 0;
4108
4109 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4110 recordlen * fpindex + ofs;
4111
4112 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4113 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4114 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4115 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4116
4117 return 0;
4118 }
4119
4120 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4121 {
4122 struct drm_nouveau_private *dev_priv = dev->dev_private;
4123 struct nvbios *bios = &dev_priv->vbios;
4124 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4125
4126 if (!mode) /* just checking whether we can produce a mode */
4127 return bios->fp.mode_ptr;
4128
4129 memset(mode, 0, sizeof(struct drm_display_mode));
4130 /*
4131 * For version 1.0 (version in byte 0):
4132 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4133 * single/dual link, and type (TFT etc.)
4134 * bytes 3-6 are bits per colour in RGBX
4135 */
4136 mode->clock = ROM16(mode_entry[7]) * 10;
4137 /* bytes 9-10 is HActive */
4138 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4139 /*
4140 * bytes 13-14 is HValid Start
4141 * bytes 15-16 is HValid End
4142 */
4143 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4144 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4145 mode->htotal = ROM16(mode_entry[21]) + 1;
4146 /* bytes 23-24, 27-30 similarly, but vertical */
4147 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4148 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4149 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4150 mode->vtotal = ROM16(mode_entry[35]) + 1;
4151 mode->flags |= (mode_entry[37] & 0x10) ?
4152 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4153 mode->flags |= (mode_entry[37] & 0x1) ?
4154 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4155 /*
4156 * bytes 38-39 relate to spread spectrum settings
4157 * bytes 40-43 are something to do with PWM
4158 */
4159
4160 mode->status = MODE_OK;
4161 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4162 drm_mode_set_name(mode);
4163 return bios->fp.mode_ptr;
4164 }
4165
4166 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4167 {
4168 /*
4169 * The LVDS table header is (mostly) described in
4170 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4171 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4172 * straps are not being used for the panel, this specifies the frequency
4173 * at which modes should be set up in the dual link style.
4174 *
4175 * Following the header, the BMP (ver 0xa) table has several records,
4176 * indexed by a separate xlat table, indexed in turn by the fp strap in
4177 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4178 * numbers for use by INIT_SUB which controlled panel init and power,
4179 * and finally a dword of ms to sleep between power off and on
4180 * operations.
4181 *
4182 * In the BIT versions, the table following the header serves as an
4183 * integrated config and xlat table: the records in the table are
4184 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4185 * two bytes - the first as a config byte, the second for indexing the
4186 * fp mode table pointed to by the BIT 'D' table
4187 *
4188 * DDC is not used until after card init, so selecting the correct table
4189 * entry and setting the dual link flag for EDID equipped panels,
4190 * requiring tests against the native-mode pixel clock, cannot be done
4191 * until later, when this function should be called with non-zero pxclk
4192 */
4193 struct drm_nouveau_private *dev_priv = dev->dev_private;
4194 struct nvbios *bios = &dev_priv->vbios;
4195 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4196 struct lvdstableheader lth;
4197 uint16_t lvdsofs;
4198 int ret, chip_version = bios->chip_version;
4199
4200 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4201 if (ret)
4202 return ret;
4203
4204 switch (lth.lvds_ver) {
4205 case 0x0a: /* pre NV40 */
4206 lvdsmanufacturerindex = bios->data[
4207 bios->fp.fpxlatemanufacturertableptr +
4208 fpstrapping];
4209
4210 /* we're done if this isn't the EDID panel case */
4211 if (!pxclk)
4212 break;
4213
4214 if (chip_version < 0x25) {
4215 /* nv17 behaviour
4216 *
4217 * It seems the old style lvds script pointer is reused
4218 * to select 18/24 bit colour depth for EDID panels.
4219 */
4220 lvdsmanufacturerindex =
4221 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4222 2 : 0;
4223 if (pxclk >= bios->fp.duallink_transition_clk)
4224 lvdsmanufacturerindex++;
4225 } else if (chip_version < 0x30) {
4226 /* nv28 behaviour (off-chip encoder)
4227 *
4228 * nv28 does a complex dance of first using byte 121 of
4229 * the EDID to choose the lvdsmanufacturerindex, then
4230 * later attempting to match the EDID manufacturer and
4231 * product IDs in a table (signature 'pidt' (panel id
4232 * table?)), setting an lvdsmanufacturerindex of 0 and
4233 * an fp strap of the match index (or 0xf if none)
4234 */
4235 lvdsmanufacturerindex = 0;
4236 } else {
4237 /* nv31, nv34 behaviour */
4238 lvdsmanufacturerindex = 0;
4239 if (pxclk >= bios->fp.duallink_transition_clk)
4240 lvdsmanufacturerindex = 2;
4241 if (pxclk >= 140000)
4242 lvdsmanufacturerindex = 3;
4243 }
4244
4245 /*
4246 * nvidia set the high nibble of (cr57=f, cr58) to
4247 * lvdsmanufacturerindex in this case; we don't
4248 */
4249 break;
4250 case 0x30: /* NV4x */
4251 case 0x40: /* G80/G90 */
4252 lvdsmanufacturerindex = fpstrapping;
4253 break;
4254 default:
4255 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4256 return -ENOSYS;
4257 }
4258
4259 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4260 switch (lth.lvds_ver) {
4261 case 0x0a:
4262 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4263 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4264 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4265 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4266 *if_is_24bit = bios->data[lvdsofs] & 16;
4267 break;
4268 case 0x30:
4269 case 0x40:
4270 /*
4271 * No sign of the "power off for reset" or "reset for panel
4272 * on" bits, but it's safer to assume we should
4273 */
4274 bios->fp.power_off_for_reset = true;
4275 bios->fp.reset_after_pclk_change = true;
4276
4277 /*
4278 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4279 * over-written, and if_is_24bit isn't used
4280 */
4281 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4282 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4283 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4284 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4285 break;
4286 }
4287
4288 /* set dual_link flag for EDID case */
4289 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4290 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4291
4292 *dl = bios->fp.dual_link;
4293
4294 return 0;
4295 }
4296
4297 /* BIT 'U'/'d' table encoder subtables have hashes matching them to
4298 * a particular set of encoders.
4299 *
4300 * This function returns true if a particular DCB entry matches.
4301 */
4302 bool
4303 bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4304 {
4305 if ((hash & 0x000000f0) != (dcb->location << 4))
4306 return false;
4307 if ((hash & 0x0000000f) != dcb->type)
4308 return false;
4309 if (!(hash & (dcb->or << 16)))
4310 return false;
4311
4312 switch (dcb->type) {
4313 case OUTPUT_TMDS:
4314 case OUTPUT_LVDS:
4315 case OUTPUT_DP:
4316 if (hash & 0x00c00000) {
4317 if (!(hash & (dcb->sorconf.link << 22)))
4318 return false;
4319 }
4320 default:
4321 return true;
4322 }
4323 }
4324
4325 int
4326 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4327 struct dcb_entry *dcbent, int crtc)
4328 {
4329 /*
4330 * The display script table is located by the BIT 'U' table.
4331 *
4332 * It contains an array of pointers to various tables describing
4333 * a particular output type. The first 32-bits of the output
4334 * tables contains similar information to a DCB entry, and is
4335 * used to decide whether that particular table is suitable for
4336 * the output you want to access.
4337 *
4338 * The "record header length" field here seems to indicate the
4339 * offset of the first configuration entry in the output tables.
4340 * This is 10 on most cards I've seen, but 12 has been witnessed
4341 * on DP cards, and there's another script pointer within the
4342 * header.
4343 *
4344 * offset + 0 ( 8 bits): version
4345 * offset + 1 ( 8 bits): header length
4346 * offset + 2 ( 8 bits): record length
4347 * offset + 3 ( 8 bits): number of records
4348 * offset + 4 ( 8 bits): record header length
4349 * offset + 5 (16 bits): pointer to first output script table
4350 */
4351
4352 struct drm_nouveau_private *dev_priv = dev->dev_private;
4353 struct nvbios *bios = &dev_priv->vbios;
4354 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4355 uint8_t *otable = NULL;
4356 uint16_t script;
4357 int i;
4358
4359 if (!bios->display.script_table_ptr) {
4360 NV_ERROR(dev, "No pointer to output script table\n");
4361 return 1;
4362 }
4363
4364 /*
4365 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4366 * so until they are, we really don't need to care.
4367 */
4368 if (table[0] < 0x20)
4369 return 1;
4370
4371 if (table[0] != 0x20 && table[0] != 0x21) {
4372 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4373 table[0]);
4374 return 1;
4375 }
4376
4377 /*
4378 * The output script tables describing a particular output type
4379 * look as follows:
4380 *
4381 * offset + 0 (32 bits): output this table matches (hash of DCB)
4382 * offset + 4 ( 8 bits): unknown
4383 * offset + 5 ( 8 bits): number of configurations
4384 * offset + 6 (16 bits): pointer to some script
4385 * offset + 8 (16 bits): pointer to some script
4386 *
4387 * headerlen == 10
4388 * offset + 10 : configuration 0
4389 *
4390 * headerlen == 12
4391 * offset + 10 : pointer to some script
4392 * offset + 12 : configuration 0
4393 *
4394 * Each config entry is as follows:
4395 *
4396 * offset + 0 (16 bits): unknown, assumed to be a match value
4397 * offset + 2 (16 bits): pointer to script table (clock set?)
4398 * offset + 4 (16 bits): pointer to script table (reset?)
4399 *
4400 * There doesn't appear to be a count value to say how many
4401 * entries exist in each script table, instead, a 0 value in
4402 * the first 16-bit word seems to indicate both the end of the
4403 * list and the default entry. The second 16-bit word in the
4404 * script tables is a pointer to the script to execute.
4405 */
4406
4407 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4408 dcbent->type, dcbent->location, dcbent->or);
4409 for (i = 0; i < table[3]; i++) {
4410 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
4411 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4412 break;
4413 }
4414
4415 if (!otable) {
4416 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4417 return 1;
4418 }
4419
4420 if (pclk < -2 || pclk > 0) {
4421 /* Try to find matching script table entry */
4422 for (i = 0; i < otable[5]; i++) {
4423 if (ROM16(otable[table[4] + i*6]) == type)
4424 break;
4425 }
4426
4427 if (i == otable[5]) {
4428 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4429 "using first\n",
4430 type, dcbent->type, dcbent->or);
4431 i = 0;
4432 }
4433 }
4434
4435 if (pclk == 0) {
4436 script = ROM16(otable[6]);
4437 if (!script) {
4438 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4439 return 1;
4440 }
4441
4442 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4443 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4444 } else
4445 if (pclk == -1) {
4446 script = ROM16(otable[8]);
4447 if (!script) {
4448 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4449 return 1;
4450 }
4451
4452 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4453 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4454 } else
4455 if (pclk == -2) {
4456 if (table[4] >= 12)
4457 script = ROM16(otable[10]);
4458 else
4459 script = 0;
4460 if (!script) {
4461 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4462 return 1;
4463 }
4464
4465 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4466 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4467 } else
4468 if (pclk > 0) {
4469 script = ROM16(otable[table[4] + i*6 + 2]);
4470 if (script)
4471 script = clkcmptable(bios, script, pclk);
4472 if (!script) {
4473 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4474 return 1;
4475 }
4476
4477 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4478 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4479 } else
4480 if (pclk < 0) {
4481 script = ROM16(otable[table[4] + i*6 + 4]);
4482 if (script)
4483 script = clkcmptable(bios, script, -pclk);
4484 if (!script) {
4485 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4486 return 1;
4487 }
4488
4489 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4490 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4491 }
4492
4493 return 0;
4494 }
4495
4496
4497 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4498 {
4499 /*
4500 * the pxclk parameter is in kHz
4501 *
4502 * This runs the TMDS regs setting code found on BIT bios cards
4503 *
4504 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4505 * ffs(or) == 3, use the second.
4506 */
4507
4508 struct drm_nouveau_private *dev_priv = dev->dev_private;
4509 struct nvbios *bios = &dev_priv->vbios;
4510 int cv = bios->chip_version;
4511 uint16_t clktable = 0, scriptptr;
4512 uint32_t sel_clk_binding, sel_clk;
4513
4514 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4515 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4516 dcbent->location != DCB_LOC_ON_CHIP)
4517 return 0;
4518
4519 switch (ffs(dcbent->or)) {
4520 case 1:
4521 clktable = bios->tmds.output0_script_ptr;
4522 break;
4523 case 2:
4524 case 3:
4525 clktable = bios->tmds.output1_script_ptr;
4526 break;
4527 }
4528
4529 if (!clktable) {
4530 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4531 return -EINVAL;
4532 }
4533
4534 scriptptr = clkcmptable(bios, clktable, pxclk);
4535
4536 if (!scriptptr) {
4537 NV_ERROR(dev, "TMDS output init script not found\n");
4538 return -ENOENT;
4539 }
4540
4541 /* don't let script change pll->head binding */
4542 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4543 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4544 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4545 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4546
4547 return 0;
4548 }
4549
4550 struct pll_mapping {
4551 u8 type;
4552 u32 reg;
4553 };
4554
4555 static struct pll_mapping nv04_pll_mapping[] = {
4556 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4557 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4558 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4559 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4560 {}
4561 };
4562
4563 static struct pll_mapping nv40_pll_mapping[] = {
4564 { PLL_CORE , 0x004000 },
4565 { PLL_MEMORY, 0x004020 },
4566 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4567 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4568 {}
4569 };
4570
4571 static struct pll_mapping nv50_pll_mapping[] = {
4572 { PLL_CORE , 0x004028 },
4573 { PLL_SHADER, 0x004020 },
4574 { PLL_UNK03 , 0x004000 },
4575 { PLL_MEMORY, 0x004008 },
4576 { PLL_UNK40 , 0x00e810 },
4577 { PLL_UNK41 , 0x00e818 },
4578 { PLL_UNK42 , 0x00e824 },
4579 { PLL_VPLL0 , 0x614100 },
4580 { PLL_VPLL1 , 0x614900 },
4581 {}
4582 };
4583
4584 static struct pll_mapping nv84_pll_mapping[] = {
4585 { PLL_CORE , 0x004028 },
4586 { PLL_SHADER, 0x004020 },
4587 { PLL_MEMORY, 0x004008 },
4588 { PLL_VDEC , 0x004030 },
4589 { PLL_UNK41 , 0x00e818 },
4590 { PLL_VPLL0 , 0x614100 },
4591 { PLL_VPLL1 , 0x614900 },
4592 {}
4593 };
4594
4595 u32
4596 get_pll_register(struct drm_device *dev, enum pll_types type)
4597 {
4598 struct drm_nouveau_private *dev_priv = dev->dev_private;
4599 struct nvbios *bios = &dev_priv->vbios;
4600 struct pll_mapping *map;
4601 int i;
4602
4603 if (dev_priv->card_type < NV_40)
4604 map = nv04_pll_mapping;
4605 else
4606 if (dev_priv->card_type < NV_50)
4607 map = nv40_pll_mapping;
4608 else {
4609 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4610
4611 if (plim[0] >= 0x30) {
4612 u8 *entry = plim + plim[1];
4613 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4614 if (entry[0] == type)
4615 return ROM32(entry[3]);
4616 }
4617
4618 return 0;
4619 }
4620
4621 if (dev_priv->chipset == 0x50)
4622 map = nv50_pll_mapping;
4623 else
4624 map = nv84_pll_mapping;
4625 }
4626
4627 while (map->reg) {
4628 if (map->type == type)
4629 return map->reg;
4630 map++;
4631 }
4632
4633 return 0;
4634 }
4635
4636 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4637 {
4638 /*
4639 * PLL limits table
4640 *
4641 * Version 0x10: NV30, NV31
4642 * One byte header (version), one record of 24 bytes
4643 * Version 0x11: NV36 - Not implemented
4644 * Seems to have same record style as 0x10, but 3 records rather than 1
4645 * Version 0x20: Found on Geforce 6 cards
4646 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4647 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4648 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4649 * length in general, some (integrated) have an extra configuration byte
4650 * Version 0x30: Found on Geforce 8, separates the register mapping
4651 * from the limits tables.
4652 */
4653
4654 struct drm_nouveau_private *dev_priv = dev->dev_private;
4655 struct nvbios *bios = &dev_priv->vbios;
4656 int cv = bios->chip_version, pllindex = 0;
4657 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4658 uint32_t crystal_strap_mask, crystal_straps;
4659
4660 if (!bios->pll_limit_tbl_ptr) {
4661 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4662 cv >= 0x40) {
4663 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4664 return -EINVAL;
4665 }
4666 } else
4667 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4668
4669 crystal_strap_mask = 1 << 6;
4670 /* open coded dev->twoHeads test */
4671 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4672 crystal_strap_mask |= 1 << 22;
4673 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4674 crystal_strap_mask;
4675
4676 switch (pll_lim_ver) {
4677 /*
4678 * We use version 0 to indicate a pre limit table bios (single stage
4679 * pll) and load the hard coded limits instead.
4680 */
4681 case 0:
4682 break;
4683 case 0x10:
4684 case 0x11:
4685 /*
4686 * Strictly v0x11 has 3 entries, but the last two don't seem
4687 * to get used.
4688 */
4689 headerlen = 1;
4690 recordlen = 0x18;
4691 entries = 1;
4692 pllindex = 0;
4693 break;
4694 case 0x20:
4695 case 0x21:
4696 case 0x30:
4697 case 0x40:
4698 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4699 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4700 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4701 break;
4702 default:
4703 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4704 "supported\n", pll_lim_ver);
4705 return -ENOSYS;
4706 }
4707
4708 /* initialize all members to zero */
4709 memset(pll_lim, 0, sizeof(struct pll_lims));
4710
4711 /* if we were passed a type rather than a register, figure
4712 * out the register and store it
4713 */
4714 if (limit_match > PLL_MAX)
4715 pll_lim->reg = limit_match;
4716 else {
4717 pll_lim->reg = get_pll_register(dev, limit_match);
4718 if (!pll_lim->reg)
4719 return -ENOENT;
4720 }
4721
4722 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4723 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4724
4725 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4726 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4727 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4728 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4729 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4730 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4731 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4732
4733 /* these values taken from nv30/31/36 */
4734 pll_lim->vco1.min_n = 0x1;
4735 if (cv == 0x36)
4736 pll_lim->vco1.min_n = 0x5;
4737 pll_lim->vco1.max_n = 0xff;
4738 pll_lim->vco1.min_m = 0x1;
4739 pll_lim->vco1.max_m = 0xd;
4740 pll_lim->vco2.min_n = 0x4;
4741 /*
4742 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4743 * table version (apart from nv35)), N2 is compared to
4744 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4745 * save a comparison
4746 */
4747 pll_lim->vco2.max_n = 0x28;
4748 if (cv == 0x30 || cv == 0x35)
4749 /* only 5 bits available for N2 on nv30/35 */
4750 pll_lim->vco2.max_n = 0x1f;
4751 pll_lim->vco2.min_m = 0x1;
4752 pll_lim->vco2.max_m = 0x4;
4753 pll_lim->max_log2p = 0x7;
4754 pll_lim->max_usable_log2p = 0x6;
4755 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4756 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4757 uint8_t *pll_rec;
4758 int i;
4759
4760 /*
4761 * First entry is default match, if nothing better. warn if
4762 * reg field nonzero
4763 */
4764 if (ROM32(bios->data[plloffs]))
4765 NV_WARN(dev, "Default PLL limit entry has non-zero "
4766 "register field\n");
4767
4768 for (i = 1; i < entries; i++)
4769 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4770 pllindex = i;
4771 break;
4772 }
4773
4774 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4775 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4776 "limits table", pll_lim->reg);
4777 return -ENOENT;
4778 }
4779
4780 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4781
4782 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4783 pllindex ? pll_lim->reg : 0);
4784
4785 /*
4786 * Frequencies are stored in tables in MHz, kHz are more
4787 * useful, so we convert.
4788 */
4789
4790 /* What output frequencies can each VCO generate? */
4791 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4792 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4793 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4794 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4795
4796 /* What input frequencies they accept (past the m-divider)? */
4797 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4798 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4799 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4800 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4801
4802 /* What values are accepted as multiplier and divider? */
4803 pll_lim->vco1.min_n = pll_rec[20];
4804 pll_lim->vco1.max_n = pll_rec[21];
4805 pll_lim->vco1.min_m = pll_rec[22];
4806 pll_lim->vco1.max_m = pll_rec[23];
4807 pll_lim->vco2.min_n = pll_rec[24];
4808 pll_lim->vco2.max_n = pll_rec[25];
4809 pll_lim->vco2.min_m = pll_rec[26];
4810 pll_lim->vco2.max_m = pll_rec[27];
4811
4812 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4813 if (pll_lim->max_log2p > 0x7)
4814 /* pll decoding in nv_hw.c assumes never > 7 */
4815 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4816 pll_lim->max_log2p);
4817 if (cv < 0x60)
4818 pll_lim->max_usable_log2p = 0x6;
4819 pll_lim->log2p_bias = pll_rec[30];
4820
4821 if (recordlen > 0x22)
4822 pll_lim->refclk = ROM32(pll_rec[31]);
4823
4824 if (recordlen > 0x23 && pll_rec[35])
4825 NV_WARN(dev,
4826 "Bits set in PLL configuration byte (%x)\n",
4827 pll_rec[35]);
4828
4829 /* C51 special not seen elsewhere */
4830 if (cv == 0x51 && !pll_lim->refclk) {
4831 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4832
4833 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4834 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4835 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4836 pll_lim->refclk = 200000;
4837 else
4838 pll_lim->refclk = 25000;
4839 }
4840 }
4841 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4842 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4843 uint8_t *record = NULL;
4844 int i;
4845
4846 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4847 pll_lim->reg);
4848
4849 for (i = 0; i < entries; i++, entry += recordlen) {
4850 if (ROM32(entry[3]) == pll_lim->reg) {
4851 record = &bios->data[ROM16(entry[1])];
4852 break;
4853 }
4854 }
4855
4856 if (!record) {
4857 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4858 "limits table", pll_lim->reg);
4859 return -ENOENT;
4860 }
4861
4862 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4863 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4864 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4865 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4866 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4867 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4868 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4869 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4870 pll_lim->vco1.min_n = record[16];
4871 pll_lim->vco1.max_n = record[17];
4872 pll_lim->vco1.min_m = record[18];
4873 pll_lim->vco1.max_m = record[19];
4874 pll_lim->vco2.min_n = record[20];
4875 pll_lim->vco2.max_n = record[21];
4876 pll_lim->vco2.min_m = record[22];
4877 pll_lim->vco2.max_m = record[23];
4878 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4879 pll_lim->log2p_bias = record[27];
4880 pll_lim->refclk = ROM32(record[28]);
4881 } else if (pll_lim_ver) { /* ver 0x40 */
4882 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4883 uint8_t *record = NULL;
4884 int i;
4885
4886 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4887 pll_lim->reg);
4888
4889 for (i = 0; i < entries; i++, entry += recordlen) {
4890 if (ROM32(entry[3]) == pll_lim->reg) {
4891 record = &bios->data[ROM16(entry[1])];
4892 break;
4893 }
4894 }
4895
4896 if (!record) {
4897 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4898 "limits table", pll_lim->reg);
4899 return -ENOENT;
4900 }
4901
4902 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4903 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4904 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4905 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4906 pll_lim->vco1.min_m = record[8];
4907 pll_lim->vco1.max_m = record[9];
4908 pll_lim->vco1.min_n = record[10];
4909 pll_lim->vco1.max_n = record[11];
4910 pll_lim->min_p = record[12];
4911 pll_lim->max_p = record[13];
4912 pll_lim->refclk = ROM16(entry[9]) * 1000;
4913 }
4914
4915 /*
4916 * By now any valid limit table ought to have set a max frequency for
4917 * vco1, so if it's zero it's either a pre limit table bios, or one
4918 * with an empty limit table (seen on nv18)
4919 */
4920 if (!pll_lim->vco1.maxfreq) {
4921 pll_lim->vco1.minfreq = bios->fminvco;
4922 pll_lim->vco1.maxfreq = bios->fmaxvco;
4923 pll_lim->vco1.min_inputfreq = 0;
4924 pll_lim->vco1.max_inputfreq = INT_MAX;
4925 pll_lim->vco1.min_n = 0x1;
4926 pll_lim->vco1.max_n = 0xff;
4927 pll_lim->vco1.min_m = 0x1;
4928 if (crystal_straps == 0) {
4929 /* nv05 does this, nv11 doesn't, nv10 unknown */
4930 if (cv < 0x11)
4931 pll_lim->vco1.min_m = 0x7;
4932 pll_lim->vco1.max_m = 0xd;
4933 } else {
4934 if (cv < 0x11)
4935 pll_lim->vco1.min_m = 0x8;
4936 pll_lim->vco1.max_m = 0xe;
4937 }
4938 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4939 pll_lim->max_log2p = 4;
4940 else
4941 pll_lim->max_log2p = 5;
4942 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4943 }
4944
4945 if (!pll_lim->refclk)
4946 switch (crystal_straps) {
4947 case 0:
4948 pll_lim->refclk = 13500;
4949 break;
4950 case (1 << 6):
4951 pll_lim->refclk = 14318;
4952 break;
4953 case (1 << 22):
4954 pll_lim->refclk = 27000;
4955 break;
4956 case (1 << 22 | 1 << 6):
4957 pll_lim->refclk = 25000;
4958 break;
4959 }
4960
4961 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4962 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4963 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4964 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4965 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4966 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4967 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4968 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4969 if (pll_lim->vco2.maxfreq) {
4970 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4971 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4972 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4973 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4974 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4975 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4976 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4977 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4978 }
4979 if (!pll_lim->max_p) {
4980 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4981 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4982 } else {
4983 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4984 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4985 }
4986 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
4987
4988 return 0;
4989 }
4990
4991 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4992 {
4993 /*
4994 * offset + 0 (8 bits): Micro version
4995 * offset + 1 (8 bits): Minor version
4996 * offset + 2 (8 bits): Chip version
4997 * offset + 3 (8 bits): Major version
4998 */
4999
5000 bios->major_version = bios->data[offset + 3];
5001 bios->chip_version = bios->data[offset + 2];
5002 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5003 bios->data[offset + 3], bios->data[offset + 2],
5004 bios->data[offset + 1], bios->data[offset]);
5005 }
5006
5007 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5008 {
5009 /*
5010 * Parses the init table segment for pointers used in script execution.
5011 *
5012 * offset + 0 (16 bits): init script tables pointer
5013 * offset + 2 (16 bits): macro index table pointer
5014 * offset + 4 (16 bits): macro table pointer
5015 * offset + 6 (16 bits): condition table pointer
5016 * offset + 8 (16 bits): io condition table pointer
5017 * offset + 10 (16 bits): io flag condition table pointer
5018 * offset + 12 (16 bits): init function table pointer
5019 */
5020
5021 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5022 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5023 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5024 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5025 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5026 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5027 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5028 }
5029
5030 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5031 {
5032 /*
5033 * Parses the load detect values for g80 cards.
5034 *
5035 * offset + 0 (16 bits): loadval table pointer
5036 */
5037
5038 uint16_t load_table_ptr;
5039 uint8_t version, headerlen, entrylen, num_entries;
5040
5041 if (bitentry->length != 3) {
5042 NV_ERROR(dev, "Do not understand BIT A table\n");
5043 return -EINVAL;
5044 }
5045
5046 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5047
5048 if (load_table_ptr == 0x0) {
5049 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
5050 return -EINVAL;
5051 }
5052
5053 version = bios->data[load_table_ptr];
5054
5055 if (version != 0x10) {
5056 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5057 version >> 4, version & 0xF);
5058 return -ENOSYS;
5059 }
5060
5061 headerlen = bios->data[load_table_ptr + 1];
5062 entrylen = bios->data[load_table_ptr + 2];
5063 num_entries = bios->data[load_table_ptr + 3];
5064
5065 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5066 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5067 return -EINVAL;
5068 }
5069
5070 /* First entry is normal dac, 2nd tv-out perhaps? */
5071 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5072
5073 return 0;
5074 }
5075
5076 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5077 {
5078 /*
5079 * offset + 8 (16 bits): PLL limits table pointer
5080 *
5081 * There's more in here, but that's unknown.
5082 */
5083
5084 if (bitentry->length < 10) {
5085 NV_ERROR(dev, "Do not understand BIT C table\n");
5086 return -EINVAL;
5087 }
5088
5089 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5090
5091 return 0;
5092 }
5093
5094 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5095 {
5096 /*
5097 * Parses the flat panel table segment that the bit entry points to.
5098 * Starting at bitentry->offset:
5099 *
5100 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5101 * records beginning with a freq.
5102 * offset + 2 (16 bits): mode table pointer
5103 */
5104
5105 if (bitentry->length != 4) {
5106 NV_ERROR(dev, "Do not understand BIT display table\n");
5107 return -EINVAL;
5108 }
5109
5110 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5111
5112 return 0;
5113 }
5114
5115 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5116 {
5117 /*
5118 * Parses the init table segment that the bit entry points to.
5119 *
5120 * See parse_script_table_pointers for layout
5121 */
5122
5123 if (bitentry->length < 14) {
5124 NV_ERROR(dev, "Do not understand init table\n");
5125 return -EINVAL;
5126 }
5127
5128 parse_script_table_pointers(bios, bitentry->offset);
5129
5130 if (bitentry->length >= 16)
5131 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5132 if (bitentry->length >= 18)
5133 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5134
5135 return 0;
5136 }
5137
5138 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5139 {
5140 /*
5141 * BIT 'i' (info?) table
5142 *
5143 * offset + 0 (32 bits): BIOS version dword (as in B table)
5144 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5145 * offset + 13 (16 bits): pointer to table containing DAC load
5146 * detection comparison values
5147 *
5148 * There's other things in the table, purpose unknown
5149 */
5150
5151 uint16_t daccmpoffset;
5152 uint8_t dacver, dacheaderlen;
5153
5154 if (bitentry->length < 6) {
5155 NV_ERROR(dev, "BIT i table too short for needed information\n");
5156 return -EINVAL;
5157 }
5158
5159 parse_bios_version(dev, bios, bitentry->offset);
5160
5161 /*
5162 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5163 * Quadro identity crisis), other bits possibly as for BMP feature byte
5164 */
5165 bios->feature_byte = bios->data[bitentry->offset + 5];
5166 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5167
5168 if (bitentry->length < 15) {
5169 NV_WARN(dev, "BIT i table not long enough for DAC load "
5170 "detection comparison table\n");
5171 return -EINVAL;
5172 }
5173
5174 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5175
5176 /* doesn't exist on g80 */
5177 if (!daccmpoffset)
5178 return 0;
5179
5180 /*
5181 * The first value in the table, following the header, is the
5182 * comparison value, the second entry is a comparison value for
5183 * TV load detection.
5184 */
5185
5186 dacver = bios->data[daccmpoffset];
5187 dacheaderlen = bios->data[daccmpoffset + 1];
5188
5189 if (dacver != 0x00 && dacver != 0x10) {
5190 NV_WARN(dev, "DAC load detection comparison table version "
5191 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5192 return -ENOSYS;
5193 }
5194
5195 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5196 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5197
5198 return 0;
5199 }
5200
5201 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5202 {
5203 /*
5204 * Parses the LVDS table segment that the bit entry points to.
5205 * Starting at bitentry->offset:
5206 *
5207 * offset + 0 (16 bits): LVDS strap xlate table pointer
5208 */
5209
5210 if (bitentry->length != 2) {
5211 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5212 return -EINVAL;
5213 }
5214
5215 /*
5216 * No idea if it's still called the LVDS manufacturer table, but
5217 * the concept's close enough.
5218 */
5219 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5220
5221 return 0;
5222 }
5223
5224 static int
5225 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5226 struct bit_entry *bitentry)
5227 {
5228 /*
5229 * offset + 2 (8 bits): number of options in an
5230 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5231 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5232 * restrict option selection
5233 *
5234 * There's a bunch of bits in this table other than the RAM restrict
5235 * stuff that we don't use - their use currently unknown
5236 */
5237
5238 /*
5239 * Older bios versions don't have a sufficiently long table for
5240 * what we want
5241 */
5242 if (bitentry->length < 0x5)
5243 return 0;
5244
5245 if (bitentry->version < 2) {
5246 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5247 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5248 } else {
5249 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5250 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5251 }
5252
5253 return 0;
5254 }
5255
5256 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5257 {
5258 /*
5259 * Parses the pointer to the TMDS table
5260 *
5261 * Starting at bitentry->offset:
5262 *
5263 * offset + 0 (16 bits): TMDS table pointer
5264 *
5265 * The TMDS table is typically found just before the DCB table, with a
5266 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5267 * length?)
5268 *
5269 * At offset +7 is a pointer to a script, which I don't know how to
5270 * run yet.
5271 * At offset +9 is a pointer to another script, likewise
5272 * Offset +11 has a pointer to a table where the first word is a pxclk
5273 * frequency and the second word a pointer to a script, which should be
5274 * run if the comparison pxclk frequency is less than the pxclk desired.
5275 * This repeats for decreasing comparison frequencies
5276 * Offset +13 has a pointer to a similar table
5277 * The selection of table (and possibly +7/+9 script) is dictated by
5278 * "or" from the DCB.
5279 */
5280
5281 uint16_t tmdstableptr, script1, script2;
5282
5283 if (bitentry->length != 2) {
5284 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5285 return -EINVAL;
5286 }
5287
5288 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5289 if (!tmdstableptr) {
5290 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5291 return -EINVAL;
5292 }
5293
5294 NV_INFO(dev, "TMDS table version %d.%d\n",
5295 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5296
5297 /* nv50+ has v2.0, but we don't parse it atm */
5298 if (bios->data[tmdstableptr] != 0x11)
5299 return -ENOSYS;
5300
5301 /*
5302 * These two scripts are odd: they don't seem to get run even when
5303 * they are not stubbed.
5304 */
5305 script1 = ROM16(bios->data[tmdstableptr + 7]);
5306 script2 = ROM16(bios->data[tmdstableptr + 9]);
5307 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5308 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5309
5310 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5311 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5312
5313 return 0;
5314 }
5315
5316 static int
5317 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5318 struct bit_entry *bitentry)
5319 {
5320 /*
5321 * Parses the pointer to the G80 output script tables
5322 *
5323 * Starting at bitentry->offset:
5324 *
5325 * offset + 0 (16 bits): output script table pointer
5326 */
5327
5328 uint16_t outputscripttableptr;
5329
5330 if (bitentry->length != 3) {
5331 NV_ERROR(dev, "Do not understand BIT U table\n");
5332 return -EINVAL;
5333 }
5334
5335 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5336 bios->display.script_table_ptr = outputscripttableptr;
5337 return 0;
5338 }
5339
5340 struct bit_table {
5341 const char id;
5342 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5343 };
5344
5345 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5346
5347 int
5348 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5349 {
5350 struct drm_nouveau_private *dev_priv = dev->dev_private;
5351 struct nvbios *bios = &dev_priv->vbios;
5352 u8 entries, *entry;
5353
5354 if (bios->type != NVBIOS_BIT)
5355 return -ENODEV;
5356
5357 entries = bios->data[bios->offset + 10];
5358 entry = &bios->data[bios->offset + 12];
5359 while (entries--) {
5360 if (entry[0] == id) {
5361 bit->id = entry[0];
5362 bit->version = entry[1];
5363 bit->length = ROM16(entry[2]);
5364 bit->offset = ROM16(entry[4]);
5365 bit->data = ROMPTR(dev, entry[4]);
5366 return 0;
5367 }
5368
5369 entry += bios->data[bios->offset + 9];
5370 }
5371
5372 return -ENOENT;
5373 }
5374
5375 static int
5376 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5377 struct bit_table *table)
5378 {
5379 struct drm_device *dev = bios->dev;
5380 struct bit_entry bitentry;
5381
5382 if (bit_table(dev, table->id, &bitentry) == 0)
5383 return table->parse_fn(dev, bios, &bitentry);
5384
5385 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5386 return -ENOSYS;
5387 }
5388
5389 static int
5390 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5391 {
5392 int ret;
5393
5394 /*
5395 * The only restriction on parsing order currently is having 'i' first
5396 * for use of bios->*_version or bios->feature_byte while parsing;
5397 * functions shouldn't be actually *doing* anything apart from pulling
5398 * data from the image into the bios struct, thus no interdependencies
5399 */
5400 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5401 if (ret) /* info? */
5402 return ret;
5403 if (bios->major_version >= 0x60) /* g80+ */
5404 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5405 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5406 if (ret)
5407 return ret;
5408 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5409 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5410 if (ret)
5411 return ret;
5412 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5413 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5414 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5415 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5416
5417 return 0;
5418 }
5419
5420 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5421 {
5422 /*
5423 * Parses the BMP structure for useful things, but does not act on them
5424 *
5425 * offset + 5: BMP major version
5426 * offset + 6: BMP minor version
5427 * offset + 9: BMP feature byte
5428 * offset + 10: BCD encoded BIOS version
5429 *
5430 * offset + 18: init script table pointer (for bios versions < 5.10h)
5431 * offset + 20: extra init script table pointer (for bios
5432 * versions < 5.10h)
5433 *
5434 * offset + 24: memory init table pointer (used on early bios versions)
5435 * offset + 26: SDR memory sequencing setup data table
5436 * offset + 28: DDR memory sequencing setup data table
5437 *
5438 * offset + 54: index of I2C CRTC pair to use for CRT output
5439 * offset + 55: index of I2C CRTC pair to use for TV output
5440 * offset + 56: index of I2C CRTC pair to use for flat panel output
5441 * offset + 58: write CRTC index for I2C pair 0
5442 * offset + 59: read CRTC index for I2C pair 0
5443 * offset + 60: write CRTC index for I2C pair 1
5444 * offset + 61: read CRTC index for I2C pair 1
5445 *
5446 * offset + 67: maximum internal PLL frequency (single stage PLL)
5447 * offset + 71: minimum internal PLL frequency (single stage PLL)
5448 *
5449 * offset + 75: script table pointers, as described in
5450 * parse_script_table_pointers
5451 *
5452 * offset + 89: TMDS single link output A table pointer
5453 * offset + 91: TMDS single link output B table pointer
5454 * offset + 95: LVDS single link output A table pointer
5455 * offset + 105: flat panel timings table pointer
5456 * offset + 107: flat panel strapping translation table pointer
5457 * offset + 117: LVDS manufacturer panel config table pointer
5458 * offset + 119: LVDS manufacturer strapping translation table pointer
5459 *
5460 * offset + 142: PLL limits table pointer
5461 *
5462 * offset + 156: minimum pixel clock for LVDS dual link
5463 */
5464
5465 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5466 uint16_t bmplength;
5467 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5468
5469 /* load needed defaults in case we can't parse this info */
5470 bios->digital_min_front_porch = 0x4b;
5471 bios->fmaxvco = 256000;
5472 bios->fminvco = 128000;
5473 bios->fp.duallink_transition_clk = 90000;
5474
5475 bmp_version_major = bmp[5];
5476 bmp_version_minor = bmp[6];
5477
5478 NV_TRACE(dev, "BMP version %d.%d\n",
5479 bmp_version_major, bmp_version_minor);
5480
5481 /*
5482 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5483 * pointer on early versions
5484 */
5485 if (bmp_version_major < 5)
5486 *(uint16_t *)&bios->data[0x36] = 0;
5487
5488 /*
5489 * Seems that the minor version was 1 for all major versions prior
5490 * to 5. Version 6 could theoretically exist, but I suspect BIT
5491 * happened instead.
5492 */
5493 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5494 NV_ERROR(dev, "You have an unsupported BMP version. "
5495 "Please send in your bios\n");
5496 return -ENOSYS;
5497 }
5498
5499 if (bmp_version_major == 0)
5500 /* nothing that's currently useful in this version */
5501 return 0;
5502 else if (bmp_version_major == 1)
5503 bmplength = 44; /* exact for 1.01 */
5504 else if (bmp_version_major == 2)
5505 bmplength = 48; /* exact for 2.01 */
5506 else if (bmp_version_major == 3)
5507 bmplength = 54;
5508 /* guessed - mem init tables added in this version */
5509 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5510 /* don't know if 5.0 exists... */
5511 bmplength = 62;
5512 /* guessed - BMP I2C indices added in version 4*/
5513 else if (bmp_version_minor < 0x6)
5514 bmplength = 67; /* exact for 5.01 */
5515 else if (bmp_version_minor < 0x10)
5516 bmplength = 75; /* exact for 5.06 */
5517 else if (bmp_version_minor == 0x10)
5518 bmplength = 89; /* exact for 5.10h */
5519 else if (bmp_version_minor < 0x14)
5520 bmplength = 118; /* exact for 5.11h */
5521 else if (bmp_version_minor < 0x24)
5522 /*
5523 * Not sure of version where pll limits came in;
5524 * certainly exist by 0x24 though.
5525 */
5526 /* length not exact: this is long enough to get lvds members */
5527 bmplength = 123;
5528 else if (bmp_version_minor < 0x27)
5529 /*
5530 * Length not exact: this is long enough to get pll limit
5531 * member
5532 */
5533 bmplength = 144;
5534 else
5535 /*
5536 * Length not exact: this is long enough to get dual link
5537 * transition clock.
5538 */
5539 bmplength = 158;
5540
5541 /* checksum */
5542 if (nv_cksum(bmp, 8)) {
5543 NV_ERROR(dev, "Bad BMP checksum\n");
5544 return -EINVAL;
5545 }
5546
5547 /*
5548 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5549 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5550 * (not nv10gl), bit 5 that the flat panel tables are present, and
5551 * bit 6 a tv bios.
5552 */
5553 bios->feature_byte = bmp[9];
5554
5555 parse_bios_version(dev, bios, offset + 10);
5556
5557 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5558 bios->old_style_init = true;
5559 legacy_scripts_offset = 18;
5560 if (bmp_version_major < 2)
5561 legacy_scripts_offset -= 4;
5562 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5563 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5564
5565 if (bmp_version_major > 2) { /* appears in BMP 3 */
5566 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5567 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5568 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5569 }
5570
5571 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5572 if (bmplength > 61)
5573 legacy_i2c_offset = offset + 54;
5574 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5575 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5576 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5577
5578 if (bmplength > 74) {
5579 bios->fmaxvco = ROM32(bmp[67]);
5580 bios->fminvco = ROM32(bmp[71]);
5581 }
5582 if (bmplength > 88)
5583 parse_script_table_pointers(bios, offset + 75);
5584 if (bmplength > 94) {
5585 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5586 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5587 /*
5588 * Never observed in use with lvds scripts, but is reused for
5589 * 18/24 bit panel interface default for EDID equipped panels
5590 * (if_is_24bit not set directly to avoid any oscillation).
5591 */
5592 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5593 }
5594 if (bmplength > 108) {
5595 bios->fp.fptablepointer = ROM16(bmp[105]);
5596 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5597 bios->fp.xlatwidth = 1;
5598 }
5599 if (bmplength > 120) {
5600 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5601 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5602 }
5603 if (bmplength > 143)
5604 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5605
5606 if (bmplength > 157)
5607 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5608
5609 return 0;
5610 }
5611
5612 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5613 {
5614 int i, j;
5615
5616 for (i = 0; i <= (n - len); i++) {
5617 for (j = 0; j < len; j++)
5618 if (data[i + j] != str[j])
5619 break;
5620 if (j == len)
5621 return i;
5622 }
5623
5624 return 0;
5625 }
5626
5627 void *
5628 dcb_table(struct drm_device *dev)
5629 {
5630 struct drm_nouveau_private *dev_priv = dev->dev_private;
5631 u8 *dcb = NULL;
5632
5633 if (dev_priv->card_type > NV_04)
5634 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5635 if (!dcb) {
5636 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5637 return NULL;
5638 }
5639
5640 if (dcb[0] >= 0x41) {
5641 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5642 return NULL;
5643 } else
5644 if (dcb[0] >= 0x30) {
5645 if (ROM32(dcb[6]) == 0x4edcbdcb)
5646 return dcb;
5647 } else
5648 if (dcb[0] >= 0x20) {
5649 if (ROM32(dcb[4]) == 0x4edcbdcb)
5650 return dcb;
5651 } else
5652 if (dcb[0] >= 0x15) {
5653 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5654 return dcb;
5655 } else {
5656 /*
5657 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5658 * always has the same single (crt) entry, even when tv-out
5659 * present, so the conclusion is this version cannot really
5660 * be used.
5661 *
5662 * v1.2 tables (some NV6/10, and NV15+) normally have the
5663 * same 5 entries, which are not specific to the card and so
5664 * no use.
5665 *
5666 * v1.2 does have an I2C table that read_dcb_i2c_table can
5667 * handle, but cards exist (nv11 in #14821) with a bad i2c
5668 * table pointer, so use the indices parsed in
5669 * parse_bmp_structure.
5670 *
5671 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5672 */
5673 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5674 return NULL;
5675 }
5676
5677 NV_WARNONCE(dev, "DCB header validation failed\n");
5678 return NULL;
5679 }
5680
5681 void *
5682 dcb_outp(struct drm_device *dev, u8 idx)
5683 {
5684 u8 *dcb = dcb_table(dev);
5685 if (dcb && dcb[0] >= 0x30) {
5686 if (idx < dcb[2])
5687 return dcb + dcb[1] + (idx * dcb[3]);
5688 } else
5689 if (dcb && dcb[0] >= 0x20) {
5690 u8 *i2c = ROMPTR(dev, dcb[2]);
5691 u8 *ent = dcb + 8 + (idx * 8);
5692 if (i2c && ent < i2c)
5693 return ent;
5694 } else
5695 if (dcb && dcb[0] >= 0x15) {
5696 u8 *i2c = ROMPTR(dev, dcb[2]);
5697 u8 *ent = dcb + 4 + (idx * 10);
5698 if (i2c && ent < i2c)
5699 return ent;
5700 }
5701
5702 return NULL;
5703 }
5704
5705 int
5706 dcb_outp_foreach(struct drm_device *dev, void *data,
5707 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
5708 {
5709 int ret, idx = -1;
5710 u8 *outp = NULL;
5711 while ((outp = dcb_outp(dev, ++idx))) {
5712 if (ROM32(outp[0]) == 0x00000000)
5713 break; /* seen on an NV11 with DCB v1.5 */
5714 if (ROM32(outp[0]) == 0xffffffff)
5715 break; /* seen on an NV17 with DCB v2.0 */
5716
5717 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
5718 continue;
5719 if ((outp[0] & 0x0f) == OUTPUT_EOL)
5720 break;
5721
5722 ret = exec(dev, data, idx, outp);
5723 if (ret)
5724 return ret;
5725 }
5726
5727 return 0;
5728 }
5729
5730 u8 *
5731 dcb_conntab(struct drm_device *dev)
5732 {
5733 u8 *dcb = dcb_table(dev);
5734 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
5735 u8 *conntab = ROMPTR(dev, dcb[0x14]);
5736 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
5737 return conntab;
5738 }
5739 return NULL;
5740 }
5741
5742 u8 *
5743 dcb_conn(struct drm_device *dev, u8 idx)
5744 {
5745 u8 *conntab = dcb_conntab(dev);
5746 if (conntab && idx < conntab[2])
5747 return conntab + conntab[1] + (idx * conntab[3]);
5748 return NULL;
5749 }
5750
5751 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
5752 {
5753 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5754
5755 memset(entry, 0, sizeof(struct dcb_entry));
5756 entry->index = dcb->entries++;
5757
5758 return entry;
5759 }
5760
5761 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5762 int heads, int or)
5763 {
5764 struct dcb_entry *entry = new_dcb_entry(dcb);
5765
5766 entry->type = type;
5767 entry->i2c_index = i2c;
5768 entry->heads = heads;
5769 if (type != OUTPUT_ANALOG)
5770 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5771 entry->or = or;
5772 }
5773
5774 static bool
5775 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5776 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5777 {
5778 entry->type = conn & 0xf;
5779 entry->i2c_index = (conn >> 4) & 0xf;
5780 entry->heads = (conn >> 8) & 0xf;
5781 entry->connector = (conn >> 12) & 0xf;
5782 entry->bus = (conn >> 16) & 0xf;
5783 entry->location = (conn >> 20) & 0x3;
5784 entry->or = (conn >> 24) & 0xf;
5785
5786 switch (entry->type) {
5787 case OUTPUT_ANALOG:
5788 /*
5789 * Although the rest of a CRT conf dword is usually
5790 * zeros, mac biosen have stuff there so we must mask
5791 */
5792 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
5793 (conf & 0xffff) * 10 :
5794 (conf & 0xff) * 10000;
5795 break;
5796 case OUTPUT_LVDS:
5797 {
5798 uint32_t mask;
5799 if (conf & 0x1)
5800 entry->lvdsconf.use_straps_for_mode = true;
5801 if (dcb->version < 0x22) {
5802 mask = ~0xd;
5803 /*
5804 * The laptop in bug 14567 lies and claims to not use
5805 * straps when it does, so assume all DCB 2.0 laptops
5806 * use straps, until a broken EDID using one is produced
5807 */
5808 entry->lvdsconf.use_straps_for_mode = true;
5809 /*
5810 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5811 * mean the same thing (probably wrong, but might work)
5812 */
5813 if (conf & 0x4 || conf & 0x8)
5814 entry->lvdsconf.use_power_scripts = true;
5815 } else {
5816 mask = ~0x7;
5817 if (conf & 0x2)
5818 entry->lvdsconf.use_acpi_for_edid = true;
5819 if (conf & 0x4)
5820 entry->lvdsconf.use_power_scripts = true;
5821 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
5822 }
5823 if (conf & mask) {
5824 /*
5825 * Until we even try to use these on G8x, it's
5826 * useless reporting unknown bits. They all are.
5827 */
5828 if (dcb->version >= 0x40)
5829 break;
5830
5831 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5832 "please report\n");
5833 }
5834 break;
5835 }
5836 case OUTPUT_TV:
5837 {
5838 if (dcb->version >= 0x30)
5839 entry->tvconf.has_component_output = conf & (0x8 << 4);
5840 else
5841 entry->tvconf.has_component_output = false;
5842
5843 break;
5844 }
5845 case OUTPUT_DP:
5846 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5847 switch ((conf & 0x00e00000) >> 21) {
5848 case 0:
5849 entry->dpconf.link_bw = 162000;
5850 break;
5851 default:
5852 entry->dpconf.link_bw = 270000;
5853 break;
5854 }
5855 switch ((conf & 0x0f000000) >> 24) {
5856 case 0xf:
5857 entry->dpconf.link_nr = 4;
5858 break;
5859 case 0x3:
5860 entry->dpconf.link_nr = 2;
5861 break;
5862 default:
5863 entry->dpconf.link_nr = 1;
5864 break;
5865 }
5866 break;
5867 case OUTPUT_TMDS:
5868 if (dcb->version >= 0x40)
5869 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5870 else if (dcb->version >= 0x30)
5871 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
5872 else if (dcb->version >= 0x22)
5873 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5874
5875 break;
5876 case OUTPUT_EOL:
5877 /* weird g80 mobile type that "nv" treats as a terminator */
5878 dcb->entries--;
5879 return false;
5880 default:
5881 break;
5882 }
5883
5884 if (dcb->version < 0x40) {
5885 /* Normal entries consist of a single bit, but dual link has
5886 * the next most significant bit set too
5887 */
5888 entry->duallink_possible =
5889 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5890 } else {
5891 entry->duallink_possible = (entry->sorconf.link == 3);
5892 }
5893
5894 /* unsure what DCB version introduces this, 3.0? */
5895 if (conf & 0x100000)
5896 entry->i2c_upper_default = true;
5897
5898 return true;
5899 }
5900
5901 static bool
5902 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5903 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5904 {
5905 switch (conn & 0x0000000f) {
5906 case 0:
5907 entry->type = OUTPUT_ANALOG;
5908 break;
5909 case 1:
5910 entry->type = OUTPUT_TV;
5911 break;
5912 case 2:
5913 case 4:
5914 if (conn & 0x10)
5915 entry->type = OUTPUT_LVDS;
5916 else
5917 entry->type = OUTPUT_TMDS;
5918 break;
5919 case 3:
5920 entry->type = OUTPUT_LVDS;
5921 break;
5922 default:
5923 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5924 return false;
5925 }
5926
5927 entry->i2c_index = (conn & 0x0003c000) >> 14;
5928 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5929 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5930 entry->location = (conn & 0x01e00000) >> 21;
5931 entry->bus = (conn & 0x0e000000) >> 25;
5932 entry->duallink_possible = false;
5933
5934 switch (entry->type) {
5935 case OUTPUT_ANALOG:
5936 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5937 break;
5938 case OUTPUT_TV:
5939 entry->tvconf.has_component_output = false;
5940 break;
5941 case OUTPUT_LVDS:
5942 if ((conn & 0x00003f00) >> 8 != 0x10)
5943 entry->lvdsconf.use_straps_for_mode = true;
5944 entry->lvdsconf.use_power_scripts = true;
5945 break;
5946 default:
5947 break;
5948 }
5949
5950 return true;
5951 }
5952
5953 static
5954 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
5955 {
5956 /*
5957 * DCB v2.0 lists each output combination separately.
5958 * Here we merge compatible entries to have fewer outputs, with
5959 * more options
5960 */
5961
5962 int i, newentries = 0;
5963
5964 for (i = 0; i < dcb->entries; i++) {
5965 struct dcb_entry *ient = &dcb->entry[i];
5966 int j;
5967
5968 for (j = i + 1; j < dcb->entries; j++) {
5969 struct dcb_entry *jent = &dcb->entry[j];
5970
5971 if (jent->type == 100) /* already merged entry */
5972 continue;
5973
5974 /* merge heads field when all other fields the same */
5975 if (jent->i2c_index == ient->i2c_index &&
5976 jent->type == ient->type &&
5977 jent->location == ient->location &&
5978 jent->or == ient->or) {
5979 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5980 i, j);
5981 ient->heads |= jent->heads;
5982 jent->type = 100; /* dummy value */
5983 }
5984 }
5985 }
5986
5987 /* Compact entries merged into others out of dcb */
5988 for (i = 0; i < dcb->entries; i++) {
5989 if (dcb->entry[i].type == 100)
5990 continue;
5991
5992 if (newentries != i) {
5993 dcb->entry[newentries] = dcb->entry[i];
5994 dcb->entry[newentries].index = newentries;
5995 }
5996 newentries++;
5997 }
5998
5999 dcb->entries = newentries;
6000 }
6001
6002 static bool
6003 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6004 {
6005 struct drm_nouveau_private *dev_priv = dev->dev_private;
6006 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6007
6008 /* Dell Precision M6300
6009 * DCB entry 2: 02025312 00000010
6010 * DCB entry 3: 02026312 00000020
6011 *
6012 * Identical, except apparently a different connector on a
6013 * different SOR link. Not a clue how we're supposed to know
6014 * which one is in use if it even shares an i2c line...
6015 *
6016 * Ignore the connector on the second SOR link to prevent
6017 * nasty problems until this is sorted (assuming it's not a
6018 * VBIOS bug).
6019 */
6020 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6021 if (*conn == 0x02026312 && *conf == 0x00000020)
6022 return false;
6023 }
6024
6025 /* GeForce3 Ti 200
6026 *
6027 * DCB reports an LVDS output that should be TMDS:
6028 * DCB entry 1: f2005014 ffffffff
6029 */
6030 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6031 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6032 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6033 return false;
6034 }
6035 }
6036
6037 /* XFX GT-240X-YA
6038 *
6039 * So many things wrong here, replace the entire encoder table..
6040 */
6041 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6042 if (idx == 0) {
6043 *conn = 0x02001300; /* VGA, connector 1 */
6044 *conf = 0x00000028;
6045 } else
6046 if (idx == 1) {
6047 *conn = 0x01010312; /* DVI, connector 0 */
6048 *conf = 0x00020030;
6049 } else
6050 if (idx == 2) {
6051 *conn = 0x01010310; /* VGA, connector 0 */
6052 *conf = 0x00000028;
6053 } else
6054 if (idx == 3) {
6055 *conn = 0x02022362; /* HDMI, connector 2 */
6056 *conf = 0x00020010;
6057 } else {
6058 *conn = 0x0000000e; /* EOL */
6059 *conf = 0x00000000;
6060 }
6061 }
6062
6063 /* Some other twisted XFX board (rhbz#694914)
6064 *
6065 * The DVI/VGA encoder combo that's supposed to represent the
6066 * DVI-I connector actually point at two different ones, and
6067 * the HDMI connector ends up paired with the VGA instead.
6068 *
6069 * Connector table is missing anything for VGA at all, pointing it
6070 * an invalid conntab entry 2 so we figure it out ourself.
6071 */
6072 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6073 if (idx == 0) {
6074 *conn = 0x02002300; /* VGA, connector 2 */
6075 *conf = 0x00000028;
6076 } else
6077 if (idx == 1) {
6078 *conn = 0x01010312; /* DVI, connector 0 */
6079 *conf = 0x00020030;
6080 } else
6081 if (idx == 2) {
6082 *conn = 0x04020310; /* VGA, connector 0 */
6083 *conf = 0x00000028;
6084 } else
6085 if (idx == 3) {
6086 *conn = 0x02021322; /* HDMI, connector 1 */
6087 *conf = 0x00020010;
6088 } else {
6089 *conn = 0x0000000e; /* EOL */
6090 *conf = 0x00000000;
6091 }
6092 }
6093
6094 /* fdo#50830: connector indices for VGA and DVI-I are backwards */
6095 if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) {
6096 if (idx == 0 && *conn == 0x02000300)
6097 *conn = 0x02011300;
6098 else
6099 if (idx == 1 && *conn == 0x04011310)
6100 *conn = 0x04000310;
6101 else
6102 if (idx == 2 && *conn == 0x02011312)
6103 *conn = 0x02000312;
6104 }
6105
6106 return true;
6107 }
6108
6109 static void
6110 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6111 {
6112 struct dcb_table *dcb = &bios->dcb;
6113 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6114
6115 #ifdef __powerpc__
6116 /* Apple iMac G4 NV17 */
6117 if (of_machine_is_compatible("PowerMac4,5")) {
6118 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6119 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6120 return;
6121 }
6122 #endif
6123
6124 /* Make up some sane defaults */
6125 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6126 bios->legacy.i2c_indices.crt, 1, 1);
6127
6128 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6129 fabricate_dcb_output(dcb, OUTPUT_TV,
6130 bios->legacy.i2c_indices.tv,
6131 all_heads, 0);
6132
6133 else if (bios->tmds.output0_script_ptr ||
6134 bios->tmds.output1_script_ptr)
6135 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6136 bios->legacy.i2c_indices.panel,
6137 all_heads, 1);
6138 }
6139
6140 static int
6141 parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6142 {
6143 struct drm_nouveau_private *dev_priv = dev->dev_private;
6144 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6145 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
6146 u32 conn = ROM32(outp[0]);
6147 bool ret;
6148
6149 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
6150 struct dcb_entry *entry = new_dcb_entry(dcb);
6151
6152 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
6153
6154 if (dcb->version >= 0x20)
6155 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6156 else
6157 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6158 if (!ret)
6159 return 1; /* stop parsing */
6160
6161 /* Ignore the I2C index for on-chip TV-out, as there
6162 * are cards with bogus values (nv31m in bug 23212),
6163 * and it's otherwise useless.
6164 */
6165 if (entry->type == OUTPUT_TV &&
6166 entry->location == DCB_LOC_ON_CHIP)
6167 entry->i2c_index = 0x0f;
6168 }
6169
6170 return 0;
6171 }
6172
6173 static void
6174 dcb_fake_connectors(struct nvbios *bios)
6175 {
6176 struct dcb_table *dcbt = &bios->dcb;
6177 u8 map[16] = { };
6178 int i, idx = 0;
6179
6180 /* heuristic: if we ever get a non-zero connector field, assume
6181 * that all the indices are valid and we don't need fake them.
6182 *
6183 * and, as usual, a blacklist of boards with bad bios data..
6184 */
6185 if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) {
6186 for (i = 0; i < dcbt->entries; i++) {
6187 if (dcbt->entry[i].connector)
6188 return;
6189 }
6190 }
6191
6192 /* no useful connector info available, we need to make it up
6193 * ourselves. the rule here is: anything on the same i2c bus
6194 * is considered to be on the same connector. any output
6195 * without an associated i2c bus is assigned its own unique
6196 * connector index.
6197 */
6198 for (i = 0; i < dcbt->entries; i++) {
6199 u8 i2c = dcbt->entry[i].i2c_index;
6200 if (i2c == 0x0f) {
6201 dcbt->entry[i].connector = idx++;
6202 } else {
6203 if (!map[i2c])
6204 map[i2c] = ++idx;
6205 dcbt->entry[i].connector = map[i2c] - 1;
6206 }
6207 }
6208
6209 /* if we created more than one connector, destroy the connector
6210 * table - just in case it has random, rather than stub, entries.
6211 */
6212 if (i > 1) {
6213 u8 *conntab = dcb_conntab(bios->dev);
6214 if (conntab)
6215 conntab[0] = 0x00;
6216 }
6217 }
6218
6219 static int
6220 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6221 {
6222 struct dcb_table *dcb = &bios->dcb;
6223 u8 *dcbt, *conn;
6224 int idx;
6225
6226 dcbt = dcb_table(dev);
6227 if (!dcbt) {
6228 /* handle pre-DCB boards */
6229 if (bios->type == NVBIOS_BMP) {
6230 fabricate_dcb_encoder_table(dev, bios);
6231 return 0;
6232 }
6233
6234 return -EINVAL;
6235 }
6236
6237 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6238
6239 dcb->version = dcbt[0];
6240 dcb_outp_foreach(dev, NULL, parse_dcb_entry);
6241
6242 /*
6243 * apart for v2.1+ not being known for requiring merging, this
6244 * guarantees dcbent->index is the index of the entry in the rom image
6245 */
6246 if (dcb->version < 0x21)
6247 merge_like_dcb_entries(dev, dcb);
6248
6249 if (!dcb->entries)
6250 return -ENXIO;
6251
6252 /* dump connector table entries to log, if any exist */
6253 idx = -1;
6254 while ((conn = dcb_conn(dev, ++idx))) {
6255 if (conn[0] != 0xff) {
6256 NV_TRACE(dev, "DCB conn %02d: ", idx);
6257 if (dcb_conntab(dev)[3] < 4)
6258 printk("%04x\n", ROM16(conn[0]));
6259 else
6260 printk("%08x\n", ROM32(conn[0]));
6261 }
6262 }
6263 dcb_fake_connectors(bios);
6264 return 0;
6265 }
6266
6267 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6268 {
6269 /*
6270 * The header following the "HWSQ" signature has the number of entries,
6271 * and the entry size
6272 *
6273 * An entry consists of a dword to write to the sequencer control reg
6274 * (0x00001304), followed by the ucode bytes, written sequentially,
6275 * starting at reg 0x00001400
6276 */
6277
6278 uint8_t bytes_to_write;
6279 uint16_t hwsq_entry_offset;
6280 int i;
6281
6282 if (bios->data[hwsq_offset] <= entry) {
6283 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6284 "requested entry\n");
6285 return -ENOENT;
6286 }
6287
6288 bytes_to_write = bios->data[hwsq_offset + 1];
6289
6290 if (bytes_to_write != 36) {
6291 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6292 return -EINVAL;
6293 }
6294
6295 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6296
6297 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6298
6299 /* set sequencer control */
6300 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6301 bytes_to_write -= 4;
6302
6303 /* write ucode */
6304 for (i = 0; i < bytes_to_write; i += 4)
6305 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6306
6307 /* twiddle NV_PBUS_DEBUG_4 */
6308 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6309
6310 return 0;
6311 }
6312
6313 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6314 struct nvbios *bios)
6315 {
6316 /*
6317 * BMP based cards, from NV17, need a microcode loading to correctly
6318 * control the GPIO etc for LVDS panels
6319 *
6320 * BIT based cards seem to do this directly in the init scripts
6321 *
6322 * The microcode entries are found by the "HWSQ" signature.
6323 */
6324
6325 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6326 const int sz = sizeof(hwsq_signature);
6327 int hwsq_offset;
6328
6329 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6330 if (!hwsq_offset)
6331 return 0;
6332
6333 /* always use entry 0? */
6334 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6335 }
6336
6337 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6338 {
6339 struct drm_nouveau_private *dev_priv = dev->dev_private;
6340 struct nvbios *bios = &dev_priv->vbios;
6341 const uint8_t edid_sig[] = {
6342 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6343 uint16_t offset = 0;
6344 uint16_t newoffset;
6345 int searchlen = NV_PROM_SIZE;
6346
6347 if (bios->fp.edid)
6348 return bios->fp.edid;
6349
6350 while (searchlen) {
6351 newoffset = findstr(&bios->data[offset], searchlen,
6352 edid_sig, 8);
6353 if (!newoffset)
6354 return NULL;
6355 offset += newoffset;
6356 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6357 break;
6358
6359 searchlen -= offset;
6360 offset++;
6361 }
6362
6363 NV_TRACE(dev, "Found EDID in BIOS\n");
6364
6365 return bios->fp.edid = &bios->data[offset];
6366 }
6367
6368 void
6369 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6370 struct dcb_entry *dcbent, int crtc)
6371 {
6372 struct drm_nouveau_private *dev_priv = dev->dev_private;
6373 struct nvbios *bios = &dev_priv->vbios;
6374 struct init_exec iexec = { true, false };
6375
6376 spin_lock_bh(&bios->lock);
6377 bios->display.output = dcbent;
6378 bios->display.crtc = crtc;
6379 parse_init_table(bios, table, &iexec);
6380 bios->display.output = NULL;
6381 spin_unlock_bh(&bios->lock);
6382 }
6383
6384 void
6385 nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6386 {
6387 struct drm_nouveau_private *dev_priv = dev->dev_private;
6388 struct nvbios *bios = &dev_priv->vbios;
6389 struct init_exec iexec = { true, false };
6390
6391 parse_init_table(bios, table, &iexec);
6392 }
6393
6394 static bool NVInitVBIOS(struct drm_device *dev)
6395 {
6396 struct drm_nouveau_private *dev_priv = dev->dev_private;
6397 struct nvbios *bios = &dev_priv->vbios;
6398
6399 memset(bios, 0, sizeof(struct nvbios));
6400 spin_lock_init(&bios->lock);
6401 bios->dev = dev;
6402
6403 return bios_shadow(dev);
6404 }
6405
6406 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6407 {
6408 struct drm_nouveau_private *dev_priv = dev->dev_private;
6409 struct nvbios *bios = &dev_priv->vbios;
6410 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6411 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6412 int offset;
6413
6414 offset = findstr(bios->data, bios->length,
6415 bit_signature, sizeof(bit_signature));
6416 if (offset) {
6417 NV_TRACE(dev, "BIT BIOS found\n");
6418 bios->type = NVBIOS_BIT;
6419 bios->offset = offset;
6420 return parse_bit_structure(bios, offset + 6);
6421 }
6422
6423 offset = findstr(bios->data, bios->length,
6424 bmp_signature, sizeof(bmp_signature));
6425 if (offset) {
6426 NV_TRACE(dev, "BMP BIOS found\n");
6427 bios->type = NVBIOS_BMP;
6428 bios->offset = offset;
6429 return parse_bmp_structure(dev, bios, offset);
6430 }
6431
6432 NV_ERROR(dev, "No known BIOS signature found\n");
6433 return -ENODEV;
6434 }
6435
6436 int
6437 nouveau_run_vbios_init(struct drm_device *dev)
6438 {
6439 struct drm_nouveau_private *dev_priv = dev->dev_private;
6440 struct nvbios *bios = &dev_priv->vbios;
6441 int i, ret = 0;
6442
6443 /* Reset the BIOS head to 0. */
6444 bios->state.crtchead = 0;
6445
6446 if (bios->major_version < 5) /* BMP only */
6447 load_nv17_hw_sequencer_ucode(dev, bios);
6448
6449 if (bios->execute) {
6450 bios->fp.last_script_invoc = 0;
6451 bios->fp.lvds_init_run = false;
6452 }
6453
6454 parse_init_tables(bios);
6455
6456 /*
6457 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6458 * parser will run this right after the init tables, the binary
6459 * driver appears to run it at some point later.
6460 */
6461 if (bios->some_script_ptr) {
6462 struct init_exec iexec = {true, false};
6463
6464 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6465 bios->some_script_ptr);
6466 parse_init_table(bios, bios->some_script_ptr, &iexec);
6467 }
6468
6469 if (dev_priv->card_type >= NV_50) {
6470 for (i = 0; i < bios->dcb.entries; i++) {
6471 nouveau_bios_run_display_table(dev, 0, 0,
6472 &bios->dcb.entry[i], -1);
6473 }
6474 }
6475
6476 return ret;
6477 }
6478
6479 static bool
6480 nouveau_bios_posted(struct drm_device *dev)
6481 {
6482 struct drm_nouveau_private *dev_priv = dev->dev_private;
6483 unsigned htotal;
6484
6485 if (dev_priv->card_type >= NV_50) {
6486 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6487 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6488 return false;
6489 return true;
6490 }
6491
6492 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6493 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6494 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6495 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6496 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6497
6498 return (htotal != 0);
6499 }
6500
6501 int
6502 nouveau_bios_init(struct drm_device *dev)
6503 {
6504 struct drm_nouveau_private *dev_priv = dev->dev_private;
6505 struct nvbios *bios = &dev_priv->vbios;
6506 int ret;
6507
6508 if (!NVInitVBIOS(dev))
6509 return -ENODEV;
6510
6511 ret = nouveau_parse_vbios_struct(dev);
6512 if (ret)
6513 return ret;
6514
6515 ret = nouveau_i2c_init(dev);
6516 if (ret)
6517 return ret;
6518
6519 ret = nouveau_mxm_init(dev);
6520 if (ret)
6521 return ret;
6522
6523 ret = parse_dcb_table(dev, bios);
6524 if (ret)
6525 return ret;
6526
6527 if (!bios->major_version) /* we don't run version 0 bios */
6528 return 0;
6529
6530 /* init script execution disabled */
6531 bios->execute = false;
6532
6533 /* ... unless card isn't POSTed already */
6534 if (!nouveau_bios_posted(dev)) {
6535 NV_INFO(dev, "Adaptor not initialised, "
6536 "running VBIOS init tables.\n");
6537 bios->execute = true;
6538 }
6539 if (nouveau_force_post)
6540 bios->execute = true;
6541
6542 ret = nouveau_run_vbios_init(dev);
6543 if (ret)
6544 return ret;
6545
6546 /* feature_byte on BMP is poor, but init always sets CR4B */
6547 if (bios->major_version < 5)
6548 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6549
6550 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6551 if (bios->is_mobile || bios->major_version >= 5)
6552 ret = parse_fp_mode_table(dev, bios);
6553
6554 /* allow subsequent scripts to execute */
6555 bios->execute = true;
6556
6557 return 0;
6558 }
6559
6560 void
6561 nouveau_bios_takedown(struct drm_device *dev)
6562 {
6563 struct drm_nouveau_private *dev_priv = dev->dev_private;
6564
6565 nouveau_mxm_fini(dev);
6566 nouveau_i2c_fini(dev);
6567
6568 kfree(dev_priv->vbios.data);
6569 }
Linux ARM platform port for MOXA ART SoC