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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blobf5e95846b4c8ef206e45fb6c38b7f32e6ea495cb
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_gpio.h"
40 #include "nouveau_pm.h"
41 #include "nv50_display.h"
42 #include "nouveau_fifo.h"
43 #include "nouveau_fence.h"
44 #include "nouveau_software.h"
45
46 static void nouveau_stub_takedown(struct drm_device *dev) {}
47 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
48
49 static int nouveau_init_engine_ptrs(struct drm_device *dev)
50 {
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_engine *engine = &dev_priv->engine;
53 u32 pclass = dev->pdev->class >> 8;
54
55 switch (dev_priv->chipset & 0xf0) {
56 case 0x00:
57 engine->instmem.init = nv04_instmem_init;
58 engine->instmem.takedown = nv04_instmem_takedown;
59 engine->instmem.suspend = nv04_instmem_suspend;
60 engine->instmem.resume = nv04_instmem_resume;
61 engine->instmem.get = nv04_instmem_get;
62 engine->instmem.put = nv04_instmem_put;
63 engine->instmem.map = nv04_instmem_map;
64 engine->instmem.unmap = nv04_instmem_unmap;
65 engine->instmem.flush = nv04_instmem_flush;
66 engine->mc.init = nv04_mc_init;
67 engine->mc.takedown = nv04_mc_takedown;
68 engine->timer.init = nv04_timer_init;
69 engine->timer.read = nv04_timer_read;
70 engine->timer.takedown = nv04_timer_takedown;
71 engine->fb.init = nv04_fb_init;
72 engine->fb.takedown = nv04_fb_takedown;
73 engine->display.early_init = nv04_display_early_init;
74 engine->display.late_takedown = nv04_display_late_takedown;
75 engine->display.create = nv04_display_create;
76 engine->display.destroy = nv04_display_destroy;
77 engine->display.init = nv04_display_init;
78 engine->display.fini = nv04_display_fini;
79 engine->pm.clocks_get = nv04_pm_clocks_get;
80 engine->pm.clocks_pre = nv04_pm_clocks_pre;
81 engine->pm.clocks_set = nv04_pm_clocks_set;
82 engine->vram.init = nv04_fb_vram_init;
83 engine->vram.takedown = nouveau_stub_takedown;
84 engine->vram.flags_valid = nouveau_mem_flags_valid;
85 break;
86 case 0x10:
87 engine->instmem.init = nv04_instmem_init;
88 engine->instmem.takedown = nv04_instmem_takedown;
89 engine->instmem.suspend = nv04_instmem_suspend;
90 engine->instmem.resume = nv04_instmem_resume;
91 engine->instmem.get = nv04_instmem_get;
92 engine->instmem.put = nv04_instmem_put;
93 engine->instmem.map = nv04_instmem_map;
94 engine->instmem.unmap = nv04_instmem_unmap;
95 engine->instmem.flush = nv04_instmem_flush;
96 engine->mc.init = nv04_mc_init;
97 engine->mc.takedown = nv04_mc_takedown;
98 engine->timer.init = nv04_timer_init;
99 engine->timer.read = nv04_timer_read;
100 engine->timer.takedown = nv04_timer_takedown;
101 engine->fb.init = nv10_fb_init;
102 engine->fb.takedown = nv10_fb_takedown;
103 engine->fb.init_tile_region = nv10_fb_init_tile_region;
104 engine->fb.set_tile_region = nv10_fb_set_tile_region;
105 engine->fb.free_tile_region = nv10_fb_free_tile_region;
106 engine->display.early_init = nv04_display_early_init;
107 engine->display.late_takedown = nv04_display_late_takedown;
108 engine->display.create = nv04_display_create;
109 engine->display.destroy = nv04_display_destroy;
110 engine->display.init = nv04_display_init;
111 engine->display.fini = nv04_display_fini;
112 engine->gpio.drive = nv10_gpio_drive;
113 engine->gpio.sense = nv10_gpio_sense;
114 engine->pm.clocks_get = nv04_pm_clocks_get;
115 engine->pm.clocks_pre = nv04_pm_clocks_pre;
116 engine->pm.clocks_set = nv04_pm_clocks_set;
117 if (dev_priv->chipset == 0x1a ||
118 dev_priv->chipset == 0x1f)
119 engine->vram.init = nv1a_fb_vram_init;
120 else
121 engine->vram.init = nv10_fb_vram_init;
122 engine->vram.takedown = nouveau_stub_takedown;
123 engine->vram.flags_valid = nouveau_mem_flags_valid;
124 break;
125 case 0x20:
126 engine->instmem.init = nv04_instmem_init;
127 engine->instmem.takedown = nv04_instmem_takedown;
128 engine->instmem.suspend = nv04_instmem_suspend;
129 engine->instmem.resume = nv04_instmem_resume;
130 engine->instmem.get = nv04_instmem_get;
131 engine->instmem.put = nv04_instmem_put;
132 engine->instmem.map = nv04_instmem_map;
133 engine->instmem.unmap = nv04_instmem_unmap;
134 engine->instmem.flush = nv04_instmem_flush;
135 engine->mc.init = nv04_mc_init;
136 engine->mc.takedown = nv04_mc_takedown;
137 engine->timer.init = nv04_timer_init;
138 engine->timer.read = nv04_timer_read;
139 engine->timer.takedown = nv04_timer_takedown;
140 engine->fb.init = nv20_fb_init;
141 engine->fb.takedown = nv20_fb_takedown;
142 engine->fb.init_tile_region = nv20_fb_init_tile_region;
143 engine->fb.set_tile_region = nv20_fb_set_tile_region;
144 engine->fb.free_tile_region = nv20_fb_free_tile_region;
145 engine->display.early_init = nv04_display_early_init;
146 engine->display.late_takedown = nv04_display_late_takedown;
147 engine->display.create = nv04_display_create;
148 engine->display.destroy = nv04_display_destroy;
149 engine->display.init = nv04_display_init;
150 engine->display.fini = nv04_display_fini;
151 engine->gpio.drive = nv10_gpio_drive;
152 engine->gpio.sense = nv10_gpio_sense;
153 engine->pm.clocks_get = nv04_pm_clocks_get;
154 engine->pm.clocks_pre = nv04_pm_clocks_pre;
155 engine->pm.clocks_set = nv04_pm_clocks_set;
156 engine->vram.init = nv20_fb_vram_init;
157 engine->vram.takedown = nouveau_stub_takedown;
158 engine->vram.flags_valid = nouveau_mem_flags_valid;
159 break;
160 case 0x30:
161 engine->instmem.init = nv04_instmem_init;
162 engine->instmem.takedown = nv04_instmem_takedown;
163 engine->instmem.suspend = nv04_instmem_suspend;
164 engine->instmem.resume = nv04_instmem_resume;
165 engine->instmem.get = nv04_instmem_get;
166 engine->instmem.put = nv04_instmem_put;
167 engine->instmem.map = nv04_instmem_map;
168 engine->instmem.unmap = nv04_instmem_unmap;
169 engine->instmem.flush = nv04_instmem_flush;
170 engine->mc.init = nv04_mc_init;
171 engine->mc.takedown = nv04_mc_takedown;
172 engine->timer.init = nv04_timer_init;
173 engine->timer.read = nv04_timer_read;
174 engine->timer.takedown = nv04_timer_takedown;
175 engine->fb.init = nv30_fb_init;
176 engine->fb.takedown = nv30_fb_takedown;
177 engine->fb.init_tile_region = nv30_fb_init_tile_region;
178 engine->fb.set_tile_region = nv10_fb_set_tile_region;
179 engine->fb.free_tile_region = nv30_fb_free_tile_region;
180 engine->display.early_init = nv04_display_early_init;
181 engine->display.late_takedown = nv04_display_late_takedown;
182 engine->display.create = nv04_display_create;
183 engine->display.destroy = nv04_display_destroy;
184 engine->display.init = nv04_display_init;
185 engine->display.fini = nv04_display_fini;
186 engine->gpio.drive = nv10_gpio_drive;
187 engine->gpio.sense = nv10_gpio_sense;
188 engine->pm.clocks_get = nv04_pm_clocks_get;
189 engine->pm.clocks_pre = nv04_pm_clocks_pre;
190 engine->pm.clocks_set = nv04_pm_clocks_set;
191 engine->pm.voltage_get = nouveau_voltage_gpio_get;
192 engine->pm.voltage_set = nouveau_voltage_gpio_set;
193 engine->vram.init = nv20_fb_vram_init;
194 engine->vram.takedown = nouveau_stub_takedown;
195 engine->vram.flags_valid = nouveau_mem_flags_valid;
196 break;
197 case 0x40:
198 case 0x60:
199 engine->instmem.init = nv04_instmem_init;
200 engine->instmem.takedown = nv04_instmem_takedown;
201 engine->instmem.suspend = nv04_instmem_suspend;
202 engine->instmem.resume = nv04_instmem_resume;
203 engine->instmem.get = nv04_instmem_get;
204 engine->instmem.put = nv04_instmem_put;
205 engine->instmem.map = nv04_instmem_map;
206 engine->instmem.unmap = nv04_instmem_unmap;
207 engine->instmem.flush = nv04_instmem_flush;
208 engine->mc.init = nv40_mc_init;
209 engine->mc.takedown = nv40_mc_takedown;
210 engine->timer.init = nv04_timer_init;
211 engine->timer.read = nv04_timer_read;
212 engine->timer.takedown = nv04_timer_takedown;
213 engine->fb.init = nv40_fb_init;
214 engine->fb.takedown = nv40_fb_takedown;
215 engine->fb.init_tile_region = nv30_fb_init_tile_region;
216 engine->fb.set_tile_region = nv40_fb_set_tile_region;
217 engine->fb.free_tile_region = nv30_fb_free_tile_region;
218 engine->display.early_init = nv04_display_early_init;
219 engine->display.late_takedown = nv04_display_late_takedown;
220 engine->display.create = nv04_display_create;
221 engine->display.destroy = nv04_display_destroy;
222 engine->display.init = nv04_display_init;
223 engine->display.fini = nv04_display_fini;
224 engine->gpio.init = nv10_gpio_init;
225 engine->gpio.fini = nv10_gpio_fini;
226 engine->gpio.drive = nv10_gpio_drive;
227 engine->gpio.sense = nv10_gpio_sense;
228 engine->gpio.irq_enable = nv10_gpio_irq_enable;
229 engine->pm.clocks_get = nv40_pm_clocks_get;
230 engine->pm.clocks_pre = nv40_pm_clocks_pre;
231 engine->pm.clocks_set = nv40_pm_clocks_set;
232 engine->pm.voltage_get = nouveau_voltage_gpio_get;
233 engine->pm.voltage_set = nouveau_voltage_gpio_set;
234 engine->pm.temp_get = nv40_temp_get;
235 engine->pm.pwm_get = nv40_pm_pwm_get;
236 engine->pm.pwm_set = nv40_pm_pwm_set;
237 engine->vram.init = nv40_fb_vram_init;
238 engine->vram.takedown = nouveau_stub_takedown;
239 engine->vram.flags_valid = nouveau_mem_flags_valid;
240 break;
241 case 0x50:
242 case 0x80: /* gotta love NVIDIA's consistency.. */
243 case 0x90:
244 case 0xa0:
245 engine->instmem.init = nv50_instmem_init;
246 engine->instmem.takedown = nv50_instmem_takedown;
247 engine->instmem.suspend = nv50_instmem_suspend;
248 engine->instmem.resume = nv50_instmem_resume;
249 engine->instmem.get = nv50_instmem_get;
250 engine->instmem.put = nv50_instmem_put;
251 engine->instmem.map = nv50_instmem_map;
252 engine->instmem.unmap = nv50_instmem_unmap;
253 if (dev_priv->chipset == 0x50)
254 engine->instmem.flush = nv50_instmem_flush;
255 else
256 engine->instmem.flush = nv84_instmem_flush;
257 engine->mc.init = nv50_mc_init;
258 engine->mc.takedown = nv50_mc_takedown;
259 engine->timer.init = nv04_timer_init;
260 engine->timer.read = nv04_timer_read;
261 engine->timer.takedown = nv04_timer_takedown;
262 engine->fb.init = nv50_fb_init;
263 engine->fb.takedown = nv50_fb_takedown;
264 engine->display.early_init = nv50_display_early_init;
265 engine->display.late_takedown = nv50_display_late_takedown;
266 engine->display.create = nv50_display_create;
267 engine->display.destroy = nv50_display_destroy;
268 engine->display.init = nv50_display_init;
269 engine->display.fini = nv50_display_fini;
270 engine->gpio.init = nv50_gpio_init;
271 engine->gpio.fini = nv50_gpio_fini;
272 engine->gpio.drive = nv50_gpio_drive;
273 engine->gpio.sense = nv50_gpio_sense;
274 engine->gpio.irq_enable = nv50_gpio_irq_enable;
275 switch (dev_priv->chipset) {
276 case 0x84:
277 case 0x86:
278 case 0x92:
279 case 0x94:
280 case 0x96:
281 case 0x98:
282 case 0xa0:
283 case 0xaa:
284 case 0xac:
285 case 0x50:
286 engine->pm.clocks_get = nv50_pm_clocks_get;
287 engine->pm.clocks_pre = nv50_pm_clocks_pre;
288 engine->pm.clocks_set = nv50_pm_clocks_set;
289 break;
290 default:
291 engine->pm.clocks_get = nva3_pm_clocks_get;
292 engine->pm.clocks_pre = nva3_pm_clocks_pre;
293 engine->pm.clocks_set = nva3_pm_clocks_set;
294 break;
295 }
296 engine->pm.voltage_get = nouveau_voltage_gpio_get;
297 engine->pm.voltage_set = nouveau_voltage_gpio_set;
298 if (dev_priv->chipset >= 0x84)
299 engine->pm.temp_get = nv84_temp_get;
300 else
301 engine->pm.temp_get = nv40_temp_get;
302 engine->pm.pwm_get = nv50_pm_pwm_get;
303 engine->pm.pwm_set = nv50_pm_pwm_set;
304 engine->vram.init = nv50_vram_init;
305 engine->vram.takedown = nv50_vram_fini;
306 engine->vram.get = nv50_vram_new;
307 engine->vram.put = nv50_vram_del;
308 engine->vram.flags_valid = nv50_vram_flags_valid;
309 break;
310 case 0xc0:
311 engine->instmem.init = nvc0_instmem_init;
312 engine->instmem.takedown = nvc0_instmem_takedown;
313 engine->instmem.suspend = nvc0_instmem_suspend;
314 engine->instmem.resume = nvc0_instmem_resume;
315 engine->instmem.get = nv50_instmem_get;
316 engine->instmem.put = nv50_instmem_put;
317 engine->instmem.map = nv50_instmem_map;
318 engine->instmem.unmap = nv50_instmem_unmap;
319 engine->instmem.flush = nv84_instmem_flush;
320 engine->mc.init = nv50_mc_init;
321 engine->mc.takedown = nv50_mc_takedown;
322 engine->timer.init = nv04_timer_init;
323 engine->timer.read = nv04_timer_read;
324 engine->timer.takedown = nv04_timer_takedown;
325 engine->fb.init = nvc0_fb_init;
326 engine->fb.takedown = nvc0_fb_takedown;
327 engine->display.early_init = nv50_display_early_init;
328 engine->display.late_takedown = nv50_display_late_takedown;
329 engine->display.create = nv50_display_create;
330 engine->display.destroy = nv50_display_destroy;
331 engine->display.init = nv50_display_init;
332 engine->display.fini = nv50_display_fini;
333 engine->gpio.init = nv50_gpio_init;
334 engine->gpio.fini = nv50_gpio_fini;
335 engine->gpio.drive = nv50_gpio_drive;
336 engine->gpio.sense = nv50_gpio_sense;
337 engine->gpio.irq_enable = nv50_gpio_irq_enable;
338 engine->vram.init = nvc0_vram_init;
339 engine->vram.takedown = nv50_vram_fini;
340 engine->vram.get = nvc0_vram_new;
341 engine->vram.put = nv50_vram_del;
342 engine->vram.flags_valid = nvc0_vram_flags_valid;
343 engine->pm.temp_get = nv84_temp_get;
344 engine->pm.clocks_get = nvc0_pm_clocks_get;
345 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
346 engine->pm.clocks_set = nvc0_pm_clocks_set;
347 engine->pm.voltage_get = nouveau_voltage_gpio_get;
348 engine->pm.voltage_set = nouveau_voltage_gpio_set;
349 engine->pm.pwm_get = nv50_pm_pwm_get;
350 engine->pm.pwm_set = nv50_pm_pwm_set;
351 break;
352 case 0xd0:
353 engine->instmem.init = nvc0_instmem_init;
354 engine->instmem.takedown = nvc0_instmem_takedown;
355 engine->instmem.suspend = nvc0_instmem_suspend;
356 engine->instmem.resume = nvc0_instmem_resume;
357 engine->instmem.get = nv50_instmem_get;
358 engine->instmem.put = nv50_instmem_put;
359 engine->instmem.map = nv50_instmem_map;
360 engine->instmem.unmap = nv50_instmem_unmap;
361 engine->instmem.flush = nv84_instmem_flush;
362 engine->mc.init = nv50_mc_init;
363 engine->mc.takedown = nv50_mc_takedown;
364 engine->timer.init = nv04_timer_init;
365 engine->timer.read = nv04_timer_read;
366 engine->timer.takedown = nv04_timer_takedown;
367 engine->fb.init = nvc0_fb_init;
368 engine->fb.takedown = nvc0_fb_takedown;
369 engine->display.early_init = nouveau_stub_init;
370 engine->display.late_takedown = nouveau_stub_takedown;
371 engine->display.create = nvd0_display_create;
372 engine->display.destroy = nvd0_display_destroy;
373 engine->display.init = nvd0_display_init;
374 engine->display.fini = nvd0_display_fini;
375 engine->gpio.init = nv50_gpio_init;
376 engine->gpio.fini = nv50_gpio_fini;
377 engine->gpio.drive = nvd0_gpio_drive;
378 engine->gpio.sense = nvd0_gpio_sense;
379 engine->gpio.irq_enable = nv50_gpio_irq_enable;
380 engine->vram.init = nvc0_vram_init;
381 engine->vram.takedown = nv50_vram_fini;
382 engine->vram.get = nvc0_vram_new;
383 engine->vram.put = nv50_vram_del;
384 engine->vram.flags_valid = nvc0_vram_flags_valid;
385 engine->pm.temp_get = nv84_temp_get;
386 engine->pm.clocks_get = nvc0_pm_clocks_get;
387 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
388 engine->pm.clocks_set = nvc0_pm_clocks_set;
389 engine->pm.voltage_get = nouveau_voltage_gpio_get;
390 engine->pm.voltage_set = nouveau_voltage_gpio_set;
391 break;
392 case 0xe0:
393 engine->instmem.init = nvc0_instmem_init;
394 engine->instmem.takedown = nvc0_instmem_takedown;
395 engine->instmem.suspend = nvc0_instmem_suspend;
396 engine->instmem.resume = nvc0_instmem_resume;
397 engine->instmem.get = nv50_instmem_get;
398 engine->instmem.put = nv50_instmem_put;
399 engine->instmem.map = nv50_instmem_map;
400 engine->instmem.unmap = nv50_instmem_unmap;
401 engine->instmem.flush = nv84_instmem_flush;
402 engine->mc.init = nv50_mc_init;
403 engine->mc.takedown = nv50_mc_takedown;
404 engine->timer.init = nv04_timer_init;
405 engine->timer.read = nv04_timer_read;
406 engine->timer.takedown = nv04_timer_takedown;
407 engine->fb.init = nvc0_fb_init;
408 engine->fb.takedown = nvc0_fb_takedown;
409 engine->display.early_init = nouveau_stub_init;
410 engine->display.late_takedown = nouveau_stub_takedown;
411 engine->display.create = nvd0_display_create;
412 engine->display.destroy = nvd0_display_destroy;
413 engine->display.init = nvd0_display_init;
414 engine->display.fini = nvd0_display_fini;
415 engine->gpio.init = nv50_gpio_init;
416 engine->gpio.fini = nv50_gpio_fini;
417 engine->gpio.drive = nvd0_gpio_drive;
418 engine->gpio.sense = nvd0_gpio_sense;
419 engine->gpio.irq_enable = nv50_gpio_irq_enable;
420 engine->vram.init = nvc0_vram_init;
421 engine->vram.takedown = nv50_vram_fini;
422 engine->vram.get = nvc0_vram_new;
423 engine->vram.put = nv50_vram_del;
424 engine->vram.flags_valid = nvc0_vram_flags_valid;
425 break;
426 default:
427 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
428 return 1;
429 }
430
431 /* headless mode */
432 if (nouveau_modeset == 2 ||
433 (nouveau_modeset < 0 && pclass != PCI_CLASS_DISPLAY_VGA)) {
434 engine->display.early_init = nouveau_stub_init;
435 engine->display.late_takedown = nouveau_stub_takedown;
436 engine->display.create = nouveau_stub_init;
437 engine->display.init = nouveau_stub_init;
438 engine->display.destroy = nouveau_stub_takedown;
439 }
440
441 return 0;
442 }
443
444 static unsigned int
445 nouveau_vga_set_decode(void *priv, bool state)
446 {
447 struct drm_device *dev = priv;
448 struct drm_nouveau_private *dev_priv = dev->dev_private;
449
450 if (dev_priv->chipset >= 0x40)
451 nv_wr32(dev, 0x88054, state);
452 else
453 nv_wr32(dev, 0x1854, state);
454
455 if (state)
456 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
457 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
458 else
459 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
460 }
461
462 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
463 enum vga_switcheroo_state state)
464 {
465 struct drm_device *dev = pci_get_drvdata(pdev);
466 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
467 if (state == VGA_SWITCHEROO_ON) {
468 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
469 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
470 nouveau_pci_resume(pdev);
471 drm_kms_helper_poll_enable(dev);
472 dev->switch_power_state = DRM_SWITCH_POWER_ON;
473 } else {
474 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
475 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
476 drm_kms_helper_poll_disable(dev);
477 nouveau_switcheroo_optimus_dsm();
478 nouveau_pci_suspend(pdev, pmm);
479 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
480 }
481 }
482
483 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
484 {
485 struct drm_device *dev = pci_get_drvdata(pdev);
486 nouveau_fbcon_output_poll_changed(dev);
487 }
488
489 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
490 {
491 struct drm_device *dev = pci_get_drvdata(pdev);
492 bool can_switch;
493
494 spin_lock(&dev->count_lock);
495 can_switch = (dev->open_count == 0);
496 spin_unlock(&dev->count_lock);
497 return can_switch;
498 }
499
500 static void
501 nouveau_card_channel_fini(struct drm_device *dev)
502 {
503 struct drm_nouveau_private *dev_priv = dev->dev_private;
504
505 if (dev_priv->channel)
506 nouveau_channel_put_unlocked(&dev_priv->channel);
507 }
508
509 static int
510 nouveau_card_channel_init(struct drm_device *dev)
511 {
512 struct drm_nouveau_private *dev_priv = dev->dev_private;
513 struct nouveau_channel *chan;
514 int ret;
515
516 ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
517 dev_priv->channel = chan;
518 if (ret)
519 return ret;
520 mutex_unlock(&dev_priv->channel->mutex);
521
522 nouveau_bo_move_init(chan);
523 return 0;
524 }
525
526 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
527 .set_gpu_state = nouveau_switcheroo_set_state,
528 .reprobe = nouveau_switcheroo_reprobe,
529 .can_switch = nouveau_switcheroo_can_switch,
530 };
531
532 int
533 nouveau_card_init(struct drm_device *dev)
534 {
535 struct drm_nouveau_private *dev_priv = dev->dev_private;
536 struct nouveau_engine *engine;
537 int ret, e = 0;
538
539 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
540 vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
541
542 /* Initialise internal driver API hooks */
543 ret = nouveau_init_engine_ptrs(dev);
544 if (ret)
545 goto out;
546 engine = &dev_priv->engine;
547 spin_lock_init(&dev_priv->channels.lock);
548 spin_lock_init(&dev_priv->tile.lock);
549 spin_lock_init(&dev_priv->context_switch_lock);
550 spin_lock_init(&dev_priv->vm_lock);
551
552 /* Make the CRTCs and I2C buses accessible */
553 ret = engine->display.early_init(dev);
554 if (ret)
555 goto out;
556
557 /* Parse BIOS tables / Run init tables if card not POSTed */
558 ret = nouveau_bios_init(dev);
559 if (ret)
560 goto out_display_early;
561
562 /* workaround an odd issue on nvc1 by disabling the device's
563 * nosnoop capability. hopefully won't cause issues until a
564 * better fix is found - assuming there is one...
565 */
566 if (dev_priv->chipset == 0xc1) {
567 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
568 }
569
570 /* PMC */
571 ret = engine->mc.init(dev);
572 if (ret)
573 goto out_bios;
574
575 /* PTIMER */
576 ret = engine->timer.init(dev);
577 if (ret)
578 goto out_mc;
579
580 /* PFB */
581 ret = engine->fb.init(dev);
582 if (ret)
583 goto out_timer;
584
585 ret = engine->vram.init(dev);
586 if (ret)
587 goto out_fb;
588
589 /* PGPIO */
590 ret = nouveau_gpio_create(dev);
591 if (ret)
592 goto out_vram;
593
594 ret = nouveau_gpuobj_init(dev);
595 if (ret)
596 goto out_gpio;
597
598 ret = engine->instmem.init(dev);
599 if (ret)
600 goto out_gpuobj;
601
602 ret = nouveau_mem_vram_init(dev);
603 if (ret)
604 goto out_instmem;
605
606 ret = nouveau_mem_gart_init(dev);
607 if (ret)
608 goto out_ttmvram;
609
610 if (!dev_priv->noaccel) {
611 switch (dev_priv->card_type) {
612 case NV_04:
613 nv04_fifo_create(dev);
614 break;
615 case NV_10:
616 case NV_20:
617 case NV_30:
618 if (dev_priv->chipset < 0x17)
619 nv10_fifo_create(dev);
620 else
621 nv17_fifo_create(dev);
622 break;
623 case NV_40:
624 nv40_fifo_create(dev);
625 break;
626 case NV_50:
627 if (dev_priv->chipset == 0x50)
628 nv50_fifo_create(dev);
629 else
630 nv84_fifo_create(dev);
631 break;
632 case NV_C0:
633 case NV_D0:
634 nvc0_fifo_create(dev);
635 break;
636 case NV_E0:
637 nve0_fifo_create(dev);
638 break;
639 default:
640 break;
641 }
642
643 switch (dev_priv->card_type) {
644 case NV_04:
645 nv04_fence_create(dev);
646 break;
647 case NV_10:
648 case NV_20:
649 case NV_30:
650 case NV_40:
651 case NV_50:
652 if (dev_priv->chipset < 0x84)
653 nv10_fence_create(dev);
654 else
655 nv84_fence_create(dev);
656 break;
657 case NV_C0:
658 case NV_D0:
659 case NV_E0:
660 nvc0_fence_create(dev);
661 break;
662 default:
663 break;
664 }
665
666 switch (dev_priv->card_type) {
667 case NV_04:
668 case NV_10:
669 case NV_20:
670 case NV_30:
671 case NV_40:
672 nv04_software_create(dev);
673 break;
674 case NV_50:
675 nv50_software_create(dev);
676 break;
677 case NV_C0:
678 case NV_D0:
679 case NV_E0:
680 nvc0_software_create(dev);
681 break;
682 default:
683 break;
684 }
685
686 switch (dev_priv->card_type) {
687 case NV_04:
688 nv04_graph_create(dev);
689 break;
690 case NV_10:
691 nv10_graph_create(dev);
692 break;
693 case NV_20:
694 case NV_30:
695 nv20_graph_create(dev);
696 break;
697 case NV_40:
698 nv40_graph_create(dev);
699 break;
700 case NV_50:
701 nv50_graph_create(dev);
702 break;
703 case NV_C0:
704 case NV_D0:
705 nvc0_graph_create(dev);
706 break;
707 case NV_E0:
708 nve0_graph_create(dev);
709 break;
710 default:
711 break;
712 }
713
714 switch (dev_priv->chipset) {
715 case 0x84:
716 case 0x86:
717 case 0x92:
718 case 0x94:
719 case 0x96:
720 case 0xa0:
721 nv84_crypt_create(dev);
722 break;
723 case 0x98:
724 case 0xaa:
725 case 0xac:
726 nv98_crypt_create(dev);
727 break;
728 }
729
730 switch (dev_priv->card_type) {
731 case NV_50:
732 switch (dev_priv->chipset) {
733 case 0xa3:
734 case 0xa5:
735 case 0xa8:
736 nva3_copy_create(dev);
737 break;
738 }
739 break;
740 case NV_C0:
741 if (!(nv_rd32(dev, 0x022500) & 0x00000200))
742 nvc0_copy_create(dev, 1);
743 case NV_D0:
744 if (!(nv_rd32(dev, 0x022500) & 0x00000100))
745 nvc0_copy_create(dev, 0);
746 break;
747 default:
748 break;
749 }
750
751 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
752 nv84_bsp_create(dev);
753 nv84_vp_create(dev);
754 nv98_ppp_create(dev);
755 } else
756 if (dev_priv->chipset >= 0x84) {
757 nv50_mpeg_create(dev);
758 nv84_bsp_create(dev);
759 nv84_vp_create(dev);
760 } else
761 if (dev_priv->chipset >= 0x50) {
762 nv50_mpeg_create(dev);
763 } else
764 if (dev_priv->card_type == NV_40 ||
765 dev_priv->chipset == 0x31 ||
766 dev_priv->chipset == 0x34 ||
767 dev_priv->chipset == 0x36) {
768 nv31_mpeg_create(dev);
769 }
770
771 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
772 if (dev_priv->eng[e]) {
773 ret = dev_priv->eng[e]->init(dev, e);
774 if (ret)
775 goto out_engine;
776 }
777 }
778 }
779
780 ret = nouveau_irq_init(dev);
781 if (ret)
782 goto out_engine;
783
784 ret = nouveau_display_create(dev);
785 if (ret)
786 goto out_irq;
787
788 nouveau_backlight_init(dev);
789 nouveau_pm_init(dev);
790
791 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
792 ret = nouveau_card_channel_init(dev);
793 if (ret)
794 goto out_pm;
795 }
796
797 if (dev->mode_config.num_crtc) {
798 ret = nouveau_display_init(dev);
799 if (ret)
800 goto out_chan;
801
802 nouveau_fbcon_init(dev);
803 }
804
805 return 0;
806
807 out_chan:
808 nouveau_card_channel_fini(dev);
809 out_pm:
810 nouveau_pm_fini(dev);
811 nouveau_backlight_exit(dev);
812 nouveau_display_destroy(dev);
813 out_irq:
814 nouveau_irq_fini(dev);
815 out_engine:
816 if (!dev_priv->noaccel) {
817 for (e = e - 1; e >= 0; e--) {
818 if (!dev_priv->eng[e])
819 continue;
820 dev_priv->eng[e]->fini(dev, e, false);
821 dev_priv->eng[e]->destroy(dev,e );
822 }
823 }
824 nouveau_mem_gart_fini(dev);
825 out_ttmvram:
826 nouveau_mem_vram_fini(dev);
827 out_instmem:
828 engine->instmem.takedown(dev);
829 out_gpuobj:
830 nouveau_gpuobj_takedown(dev);
831 out_gpio:
832 nouveau_gpio_destroy(dev);
833 out_vram:
834 engine->vram.takedown(dev);
835 out_fb:
836 engine->fb.takedown(dev);
837 out_timer:
838 engine->timer.takedown(dev);
839 out_mc:
840 engine->mc.takedown(dev);
841 out_bios:
842 nouveau_bios_takedown(dev);
843 out_display_early:
844 engine->display.late_takedown(dev);
845 out:
846 vga_switcheroo_unregister_client(dev->pdev);
847 vga_client_register(dev->pdev, NULL, NULL, NULL);
848 return ret;
849 }
850
851 static void nouveau_card_takedown(struct drm_device *dev)
852 {
853 struct drm_nouveau_private *dev_priv = dev->dev_private;
854 struct nouveau_engine *engine = &dev_priv->engine;
855 int e;
856
857 if (dev->mode_config.num_crtc) {
858 nouveau_fbcon_fini(dev);
859 nouveau_display_fini(dev);
860 }
861
862 nouveau_card_channel_fini(dev);
863 nouveau_pm_fini(dev);
864 nouveau_backlight_exit(dev);
865 nouveau_display_destroy(dev);
866
867 if (!dev_priv->noaccel) {
868 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
869 if (dev_priv->eng[e]) {
870 dev_priv->eng[e]->fini(dev, e, false);
871 dev_priv->eng[e]->destroy(dev,e );
872 }
873 }
874 }
875
876 if (dev_priv->vga_ram) {
877 nouveau_bo_unpin(dev_priv->vga_ram);
878 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
879 }
880
881 mutex_lock(&dev->struct_mutex);
882 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
883 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
884 mutex_unlock(&dev->struct_mutex);
885 nouveau_mem_gart_fini(dev);
886 nouveau_mem_vram_fini(dev);
887
888 engine->instmem.takedown(dev);
889 nouveau_gpuobj_takedown(dev);
890
891 nouveau_gpio_destroy(dev);
892 engine->vram.takedown(dev);
893 engine->fb.takedown(dev);
894 engine->timer.takedown(dev);
895 engine->mc.takedown(dev);
896
897 nouveau_bios_takedown(dev);
898 engine->display.late_takedown(dev);
899
900 nouveau_irq_fini(dev);
901
902 vga_switcheroo_unregister_client(dev->pdev);
903 vga_client_register(dev->pdev, NULL, NULL, NULL);
904 }
905
906 int
907 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
908 {
909 struct drm_nouveau_private *dev_priv = dev->dev_private;
910 struct nouveau_fpriv *fpriv;
911 int ret;
912
913 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
914 if (unlikely(!fpriv))
915 return -ENOMEM;
916
917 spin_lock_init(&fpriv->lock);
918 INIT_LIST_HEAD(&fpriv->channels);
919
920 if (dev_priv->card_type == NV_50) {
921 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
922 &fpriv->vm);
923 if (ret) {
924 kfree(fpriv);
925 return ret;
926 }
927 } else
928 if (dev_priv->card_type >= NV_C0) {
929 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
930 &fpriv->vm);
931 if (ret) {
932 kfree(fpriv);
933 return ret;
934 }
935 }
936
937 file_priv->driver_priv = fpriv;
938 return 0;
939 }
940
941 /* here a client dies, release the stuff that was allocated for its
942 * file_priv */
943 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
944 {
945 nouveau_channel_cleanup(dev, file_priv);
946 }
947
948 void
949 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
950 {
951 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
952 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
953 kfree(fpriv);
954 }
955
956 /* first module load, setup the mmio/fb mapping */
957 /* KMS: we need mmio at load time, not when the first drm client opens. */
958 int nouveau_firstopen(struct drm_device *dev)
959 {
960 return 0;
961 }
962
963 /* if we have an OF card, copy vbios to RAMIN */
964 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
965 {
966 #if defined(__powerpc__)
967 int size, i;
968 const uint32_t *bios;
969 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
970 if (!dn) {
971 NV_INFO(dev, "Unable to get the OF node\n");
972 return;
973 }
974
975 bios = of_get_property(dn, "NVDA,BMP", &size);
976 if (bios) {
977 for (i = 0; i < size; i += 4)
978 nv_wi32(dev, i, bios[i/4]);
979 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
980 } else {
981 NV_INFO(dev, "Unable to get the OF bios\n");
982 }
983 #endif
984 }
985
986 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
987 {
988 struct pci_dev *pdev = dev->pdev;
989 struct apertures_struct *aper = alloc_apertures(3);
990 if (!aper)
991 return NULL;
992
993 aper->ranges[0].base = pci_resource_start(pdev, 1);
994 aper->ranges[0].size = pci_resource_len(pdev, 1);
995 aper->count = 1;
996
997 if (pci_resource_len(pdev, 2)) {
998 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
999 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1000 aper->count++;
1001 }
1002
1003 if (pci_resource_len(pdev, 3)) {
1004 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1005 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1006 aper->count++;
1007 }
1008
1009 return aper;
1010 }
1011
1012 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1013 {
1014 struct drm_nouveau_private *dev_priv = dev->dev_private;
1015 bool primary = false;
1016 dev_priv->apertures = nouveau_get_apertures(dev);
1017 if (!dev_priv->apertures)
1018 return -ENOMEM;
1019
1020 #ifdef CONFIG_X86
1021 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1022 #endif
1023
1024 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1025 return 0;
1026 }
1027
1028 int nouveau_load(struct drm_device *dev, unsigned long flags)
1029 {
1030 struct drm_nouveau_private *dev_priv;
1031 unsigned long long offset, length;
1032 uint32_t reg0 = ~0, strap;
1033 int ret;
1034
1035 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1036 if (!dev_priv) {
1037 ret = -ENOMEM;
1038 goto err_out;
1039 }
1040 dev->dev_private = dev_priv;
1041 dev_priv->dev = dev;
1042
1043 pci_set_master(dev->pdev);
1044
1045 dev_priv->flags = flags & NOUVEAU_FLAGS;
1046
1047 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1048 dev->pci_vendor, dev->pci_device, dev->pdev->class);
1049
1050 /* first up, map the start of mmio and determine the chipset */
1051 dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1052 if (dev_priv->mmio) {
1053 #ifdef __BIG_ENDIAN
1054 /* put the card into big-endian mode if it's not */
1055 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1056 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1057 DRM_MEMORYBARRIER();
1058 #endif
1059
1060 /* determine chipset and derive architecture from it */
1061 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1062 if ((reg0 & 0x0f000000) > 0) {
1063 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1064 switch (dev_priv->chipset & 0xf0) {
1065 case 0x10:
1066 case 0x20:
1067 case 0x30:
1068 dev_priv->card_type = dev_priv->chipset & 0xf0;
1069 break;
1070 case 0x40:
1071 case 0x60:
1072 dev_priv->card_type = NV_40;
1073 break;
1074 case 0x50:
1075 case 0x80:
1076 case 0x90:
1077 case 0xa0:
1078 dev_priv->card_type = NV_50;
1079 break;
1080 case 0xc0:
1081 dev_priv->card_type = NV_C0;
1082 break;
1083 case 0xd0:
1084 dev_priv->card_type = NV_D0;
1085 break;
1086 case 0xe0:
1087 dev_priv->card_type = NV_E0;
1088 break;
1089 default:
1090 break;
1091 }
1092 } else
1093 if ((reg0 & 0xff00fff0) == 0x20004000) {
1094 if (reg0 & 0x00f00000)
1095 dev_priv->chipset = 0x05;
1096 else
1097 dev_priv->chipset = 0x04;
1098 dev_priv->card_type = NV_04;
1099 }
1100
1101 iounmap(dev_priv->mmio);
1102 }
1103
1104 if (!dev_priv->card_type) {
1105 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1106 ret = -EINVAL;
1107 goto err_priv;
1108 }
1109
1110 NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
1111 dev_priv->card_type, reg0);
1112
1113 /* map the mmio regs, limiting the amount to preserve vmap space */
1114 offset = pci_resource_start(dev->pdev, 0);
1115 length = pci_resource_len(dev->pdev, 0);
1116 if (dev_priv->card_type < NV_E0)
1117 length = min(length, (unsigned long long)0x00800000);
1118
1119 dev_priv->mmio = ioremap(offset, length);
1120 if (!dev_priv->mmio) {
1121 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1122 "Please report your setup to " DRIVER_EMAIL "\n");
1123 ret = -EINVAL;
1124 goto err_priv;
1125 }
1126 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1127
1128 /* determine frequency of timing crystal */
1129 strap = nv_rd32(dev, 0x101000);
1130 if ( dev_priv->chipset < 0x17 ||
1131 (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1132 strap &= 0x00000040;
1133 else
1134 strap &= 0x00400040;
1135
1136 switch (strap) {
1137 case 0x00000000: dev_priv->crystal = 13500; break;
1138 case 0x00000040: dev_priv->crystal = 14318; break;
1139 case 0x00400000: dev_priv->crystal = 27000; break;
1140 case 0x00400040: dev_priv->crystal = 25000; break;
1141 }
1142
1143 NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1144
1145 /* Determine whether we'll attempt acceleration or not, some
1146 * cards are disabled by default here due to them being known
1147 * non-functional, or never been tested due to lack of hw.
1148 */
1149 dev_priv->noaccel = !!nouveau_noaccel;
1150 if (nouveau_noaccel == -1) {
1151 switch (dev_priv->chipset) {
1152 case 0xd9: /* known broken */
1153 case 0xe4: /* needs binary driver firmware */
1154 case 0xe7: /* needs binary driver firmware */
1155 NV_INFO(dev, "acceleration disabled by default, pass "
1156 "noaccel=0 to force enable\n");
1157 dev_priv->noaccel = true;
1158 break;
1159 default:
1160 dev_priv->noaccel = false;
1161 break;
1162 }
1163 }
1164
1165 ret = nouveau_remove_conflicting_drivers(dev);
1166 if (ret)
1167 goto err_mmio;
1168
1169 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1170 if (dev_priv->card_type >= NV_40) {
1171 int ramin_bar = 2;
1172 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1173 ramin_bar = 3;
1174
1175 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1176 dev_priv->ramin =
1177 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1178 dev_priv->ramin_size);
1179 if (!dev_priv->ramin) {
1180 NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1181 ret = -ENOMEM;
1182 goto err_mmio;
1183 }
1184 } else {
1185 dev_priv->ramin_size = 1 * 1024 * 1024;
1186 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1187 dev_priv->ramin_size);
1188 if (!dev_priv->ramin) {
1189 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1190 ret = -ENOMEM;
1191 goto err_mmio;
1192 }
1193 }
1194
1195 nouveau_OF_copy_vbios_to_ramin(dev);
1196
1197 /* Special flags */
1198 if (dev->pci_device == 0x01a0)
1199 dev_priv->flags |= NV_NFORCE;
1200 else if (dev->pci_device == 0x01f0)
1201 dev_priv->flags |= NV_NFORCE2;
1202
1203 /* For kernel modesetting, init card now and bring up fbcon */
1204 ret = nouveau_card_init(dev);
1205 if (ret)
1206 goto err_ramin;
1207
1208 return 0;
1209
1210 err_ramin:
1211 iounmap(dev_priv->ramin);
1212 err_mmio:
1213 iounmap(dev_priv->mmio);
1214 err_priv:
1215 kfree(dev_priv);
1216 dev->dev_private = NULL;
1217 err_out:
1218 return ret;
1219 }
1220
1221 void nouveau_lastclose(struct drm_device *dev)
1222 {
1223 vga_switcheroo_process_delayed_switch();
1224 }
1225
1226 int nouveau_unload(struct drm_device *dev)
1227 {
1228 struct drm_nouveau_private *dev_priv = dev->dev_private;
1229
1230 nouveau_card_takedown(dev);
1231
1232 iounmap(dev_priv->mmio);
1233 iounmap(dev_priv->ramin);
1234
1235 kfree(dev_priv);
1236 dev->dev_private = NULL;
1237 return 0;
1238 }
1239
1240 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1241 bool
1242 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1243 uint32_t reg, uint32_t mask, uint32_t val)
1244 {
1245 struct drm_nouveau_private *dev_priv = dev->dev_private;
1246 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1247 uint64_t start = ptimer->read(dev);
1248
1249 do {
1250 if ((nv_rd32(dev, reg) & mask) == val)
1251 return true;
1252 } while (ptimer->read(dev) - start < timeout);
1253
1254 return false;
1255 }
1256
1257 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1258 bool
1259 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1260 uint32_t reg, uint32_t mask, uint32_t val)
1261 {
1262 struct drm_nouveau_private *dev_priv = dev->dev_private;
1263 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1264 uint64_t start = ptimer->read(dev);
1265
1266 do {
1267 if ((nv_rd32(dev, reg) & mask) != val)
1268 return true;
1269 } while (ptimer->read(dev) - start < timeout);
1270
1271 return false;
1272 }
1273
1274 /* Wait until cond(data) == true, up until timeout has hit */
1275 bool
1276 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1277 bool (*cond)(void *), void *data)
1278 {
1279 struct drm_nouveau_private *dev_priv = dev->dev_private;
1280 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1281 u64 start = ptimer->read(dev);
1282
1283 do {
1284 if (cond(data) == true)
1285 return true;
1286 } while (ptimer->read(dev) - start < timeout);
1287
1288 return false;
1289 }
1290
1291 /* Waits for PGRAPH to go completely idle */
1292 bool nouveau_wait_for_idle(struct drm_device *dev)
1293 {
1294 struct drm_nouveau_private *dev_priv = dev->dev_private;
1295 uint32_t mask = ~0;
1296
1297 if (dev_priv->card_type == NV_40)
1298 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1299
1300 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1301 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1302 nv_rd32(dev, NV04_PGRAPH_STATUS));
1303 return false;
1304 }
1305
1306 return true;
1307 }
1308
Linux ARM platform port for MOXA ART SoC