drivers/gpu/drm/nouveau/nv04_instmem.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3
   4 #include "nouveau_drv.h"
   5 #include "nouveau_fifo.h"
   6 #include "nouveau_ramht.h"
   7
   8 /* returns the size of fifo context */
   9 static int
  10 nouveau_fifo_ctx_size(struct drm_device *dev)
  11 {
  12         struct drm_nouveau_private *dev_priv = dev->dev_private;
  13
  14         if (dev_priv->chipset >= 0x40)
  15                 return 128 * 32;
  16         else
  17         if (dev_priv->chipset >= 0x17)
  18                 return 64 * 32;
  19         else
  20         if (dev_priv->chipset >= 0x10)
  21                 return 32 * 32;
  22
  23         return 32 * 16;
  24 }
  25
  26 int nv04_instmem_init(struct drm_device *dev)
  27 {
  28         struct drm_nouveau_private *dev_priv = dev->dev_private;
  29         struct nouveau_gpuobj *ramht = NULL;
  30         u32 offset, length;
  31         int ret;
  32
  33         /* RAMIN always available */
  34         dev_priv->ramin_available = true;
  35
  36         /* Reserve space at end of VRAM for PRAMIN */
  37         if (dev_priv->card_type >= NV_40) {
  38                 u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);
  39                 u32 rsvd;
  40
  41                 /* estimate grctx size, the magics come from nv40_grctx.c */
  42                 if      (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;
  43                 else if (dev_priv->chipset  < 0x43) rsvd = 0x4f00 * vs;
  44                 else if (nv44_graph_class(dev))     rsvd = 0x4980 * vs;
  45                 else                                rsvd = 0x4a40 * vs;
  46                 rsvd += 16 * 1024;
  47                 rsvd *= 32; /* per-channel */
  48
  49                 rsvd += 512 * 1024; /* pci(e)gart table */
  50                 rsvd += 512 * 1024; /* object storage */
  51
  52                 dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
  53         } else {
  54                 dev_priv->ramin_rsvd_vram = 512 * 1024;
  55         }
  56
  57         /* Setup shared RAMHT */
  58         ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,
  59                                       NVOBJ_FLAG_ZERO_ALLOC, &ramht);
  60         if (ret)
  61                 return ret;
  62
  63         ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht);
  64         nouveau_gpuobj_ref(NULL, &ramht);
  65         if (ret)
  66                 return ret;
  67
  68         /* And RAMRO */
  69         ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512,
  70                                       NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro);
  71         if (ret)
  72                 return ret;
  73
  74         /* And RAMFC */
  75         length = nouveau_fifo_ctx_size(dev);
  76         switch (dev_priv->card_type) {
  77         case NV_40:
  78                 offset = 0x20000;
  79                 break;
  80         default:
  81                 offset = 0x11400;
  82                 break;
  83         }
  84
  85         ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length,
  86                                       NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc);
  87         if (ret)
  88                 return ret;
  89
  90         /* Only allow space after RAMFC to be used for object allocation */
  91         offset += length;
  92
  93         /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230
  94          * on certain NV4x chipsets as well as RAMFC.  When 0x2230 == 0
  95          * ("new style" control) the upper 16-bits of 0x2220 points at this
  96          * other mysterious table that's clobbering important things.
  97          *
  98          * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting
  99          * smashed to pieces on us, so reserve 0x30000-0x40000 too..
 100          */
 101         if (dev_priv->card_type >= NV_40) {
 102                 if (offset < 0x40000)
 103                         offset = 0x40000;
 104         }
 105
 106         ret = drm_mm_init(&dev_priv->ramin_heap, offset,
 107                           dev_priv->ramin_rsvd_vram - offset);
 108         if (ret) {
 109                 NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret);
 110                 return ret;
 111         }
 112
 113         return 0;
 114 }
 115
 116 void
 117 nv04_instmem_takedown(struct drm_device *dev)
 118 {
 119         struct drm_nouveau_private *dev_priv = dev->dev_private;
 120
 121         nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
 122         nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
 123         nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
 124
 125         if (drm_mm_initialized(&dev_priv->ramin_heap))
 126                 drm_mm_takedown(&dev_priv->ramin_heap);
 127 }
 128
 129 int
 130 nv04_instmem_suspend(struct drm_device *dev)
 131 {
 132         return 0;
 133 }
 134
 135 void
 136 nv04_instmem_resume(struct drm_device *dev)
 137 {
 138 }
 139
 140 int
 141 nv04_instmem_get(struct nouveau_gpuobj *gpuobj, struct nouveau_channel *chan,
 142                  u32 size, u32 align)
 143 {
 144         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 145         struct drm_mm_node *ramin = NULL;
 146
 147         do {
 148                 if (drm_mm_pre_get(&dev_priv->ramin_heap))
 149                         return -ENOMEM;
 150
 151                 spin_lock(&dev_priv->ramin_lock);
 152                 ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0);
 153                 if (ramin == NULL) {
 154                         spin_unlock(&dev_priv->ramin_lock);
 155                         return -ENOMEM;
 156                 }
 157
 158                 ramin = drm_mm_get_block_atomic(ramin, size, align);
 159                 spin_unlock(&dev_priv->ramin_lock);
 160         } while (ramin == NULL);
 161
 162         gpuobj->node  = ramin;
 163         gpuobj->vinst = ramin->start;
 164         return 0;
 165 }
 166
 167 void
 168 nv04_instmem_put(struct nouveau_gpuobj *gpuobj)
 169 {
 170         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 171
 172         spin_lock(&dev_priv->ramin_lock);
 173         drm_mm_put_block(gpuobj->node);
 174         gpuobj->node = NULL;
 175         spin_unlock(&dev_priv->ramin_lock);
 176 }
 177
 178 int
 179 nv04_instmem_map(struct nouveau_gpuobj *gpuobj)
 180 {
 181         gpuobj->pinst = gpuobj->vinst;
 182         return 0;
 183 }
 184
 185 void
 186 nv04_instmem_unmap(struct nouveau_gpuobj *gpuobj)
 187 {
 188 }
 189
 190 void
 191 nv04_instmem_flush(struct drm_device *dev)
 192 {
 193 }