2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
27 #include "radeon_drm.h"
29 #include "radeon_asic.h"
36 enum r600_hdmi_color_format
{
43 * IEC60958 status bits
45 enum r600_hdmi_iec_status_bits
{
46 AUDIO_STATUS_DIG_ENABLE
= 0x01,
47 AUDIO_STATUS_V
= 0x02,
48 AUDIO_STATUS_VCFG
= 0x04,
49 AUDIO_STATUS_EMPHASIS
= 0x08,
50 AUDIO_STATUS_COPYRIGHT
= 0x10,
51 AUDIO_STATUS_NONAUDIO
= 0x20,
52 AUDIO_STATUS_PROFESSIONAL
= 0x40,
53 AUDIO_STATUS_LEVEL
= 0x80
56 struct radeon_hdmi_acr r600_hdmi_predefined_acr
[] = {
57 /* 32kHz 44.1kHz 48kHz */
58 /* Clock N CTS N CTS N CTS */
59 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
60 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
61 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
62 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
63 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
64 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
65 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
66 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
67 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
68 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
69 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
73 * calculate CTS value if it's not found in the table
75 static void r600_hdmi_calc_cts(uint32_t clock
, int *CTS
, int N
, int freq
)
78 *CTS
= clock
* N
/ (128 * freq
) * 1000;
79 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
83 struct radeon_hdmi_acr
r600_hdmi_acr(uint32_t clock
)
85 struct radeon_hdmi_acr res
;
88 for (i
= 0; r600_hdmi_predefined_acr
[i
].clock
!= clock
&&
89 r600_hdmi_predefined_acr
[i
].clock
!= 0; i
++)
91 res
= r600_hdmi_predefined_acr
[i
];
93 /* In case some CTS are missing */
94 r600_hdmi_calc_cts(clock
, &res
.cts_32khz
, res
.n_32khz
, 32000);
95 r600_hdmi_calc_cts(clock
, &res
.cts_44_1khz
, res
.n_44_1khz
, 44100);
96 r600_hdmi_calc_cts(clock
, &res
.cts_48khz
, res
.n_48khz
, 48000);
102 * update the N and CTS parameters for a given pixel clock rate
104 static void r600_hdmi_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
106 struct drm_device
*dev
= encoder
->dev
;
107 struct radeon_device
*rdev
= dev
->dev_private
;
108 struct radeon_hdmi_acr acr
= r600_hdmi_acr(clock
);
109 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
110 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
111 uint32_t offset
= dig
->afmt
->offset
;
113 WREG32(HDMI0_ACR_32_0
+ offset
, HDMI0_ACR_CTS_32(acr
.cts_32khz
));
114 WREG32(HDMI0_ACR_32_1
+ offset
, acr
.n_32khz
);
116 WREG32(HDMI0_ACR_44_0
+ offset
, HDMI0_ACR_CTS_44(acr
.cts_44_1khz
));
117 WREG32(HDMI0_ACR_44_1
+ offset
, acr
.n_44_1khz
);
119 WREG32(HDMI0_ACR_48_0
+ offset
, HDMI0_ACR_CTS_48(acr
.cts_48khz
));
120 WREG32(HDMI0_ACR_48_1
+ offset
, acr
.n_48khz
);
124 * calculate the crc for a given info frame
126 static void r600_hdmi_infoframe_checksum(uint8_t packetType
,
127 uint8_t versionNumber
,
132 frame
[0] = packetType
+ versionNumber
+ length
;
133 for (i
= 1; i
<= length
; i
++)
134 frame
[0] += frame
[i
];
135 frame
[0] = 0x100 - frame
[0];
139 * build a HDMI Video Info Frame
141 static void r600_hdmi_videoinfoframe(
142 struct drm_encoder
*encoder
,
143 enum r600_hdmi_color_format color_format
,
144 int active_information_present
,
145 uint8_t active_format_aspect_ratio
,
146 uint8_t scan_information
,
148 uint8_t ex_colorimetry
,
149 uint8_t quantization
,
151 uint8_t picture_aspect_ratio
,
152 uint8_t video_format_identification
,
153 uint8_t pixel_repetition
,
154 uint8_t non_uniform_picture_scaling
,
155 uint8_t bar_info_data_valid
,
162 struct drm_device
*dev
= encoder
->dev
;
163 struct radeon_device
*rdev
= dev
->dev_private
;
164 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
165 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
166 uint32_t offset
= dig
->afmt
->offset
;
172 (scan_information
& 0x3) |
173 ((bar_info_data_valid
& 0x3) << 2) |
174 ((active_information_present
& 0x1) << 4) |
175 ((color_format
& 0x3) << 5);
177 (active_format_aspect_ratio
& 0xF) |
178 ((picture_aspect_ratio
& 0x3) << 4) |
179 ((colorimetry
& 0x3) << 6);
181 (non_uniform_picture_scaling
& 0x3) |
182 ((quantization
& 0x3) << 2) |
183 ((ex_colorimetry
& 0x7) << 4) |
185 frame
[0x4] = (video_format_identification
& 0x7F);
186 frame
[0x5] = (pixel_repetition
& 0xF);
187 frame
[0x6] = (top_bar
& 0xFF);
188 frame
[0x7] = (top_bar
>> 8);
189 frame
[0x8] = (bottom_bar
& 0xFF);
190 frame
[0x9] = (bottom_bar
>> 8);
191 frame
[0xA] = (left_bar
& 0xFF);
192 frame
[0xB] = (left_bar
>> 8);
193 frame
[0xC] = (right_bar
& 0xFF);
194 frame
[0xD] = (right_bar
>> 8);
196 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame
);
197 /* Our header values (type, version, length) should be alright, Intel
198 * is using the same. Checksum function also seems to be OK, it works
199 * fine for audio infoframe. However calculated value is always lower
200 * by 2 in comparison to fglrx. It breaks displaying anything in case
201 * of TVs that strictly check the checksum. Hack it manually here to
202 * workaround this issue. */
205 WREG32(HDMI0_AVI_INFO0
+ offset
,
206 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
207 WREG32(HDMI0_AVI_INFO1
+ offset
,
208 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
209 WREG32(HDMI0_AVI_INFO2
+ offset
,
210 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
211 WREG32(HDMI0_AVI_INFO3
+ offset
,
212 frame
[0xC] | (frame
[0xD] << 8));
216 * build a Audio Info Frame
218 static void r600_hdmi_audioinfoframe(
219 struct drm_encoder
*encoder
,
220 uint8_t channel_count
,
223 uint8_t sample_frequency
,
225 uint8_t channel_allocation
,
230 struct drm_device
*dev
= encoder
->dev
;
231 struct radeon_device
*rdev
= dev
->dev_private
;
232 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
233 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
234 uint32_t offset
= dig
->afmt
->offset
;
239 frame
[0x1] = (channel_count
& 0x7) | ((coding_type
& 0xF) << 4);
240 frame
[0x2] = (sample_size
& 0x3) | ((sample_frequency
& 0x7) << 2);
242 frame
[0x4] = channel_allocation
;
243 frame
[0x5] = ((level_shift
& 0xF) << 3) | ((downmix_inhibit
& 0x1) << 7);
250 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame
);
252 WREG32(HDMI0_AUDIO_INFO0
+ offset
,
253 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
254 WREG32(HDMI0_AUDIO_INFO1
+ offset
,
255 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x8] << 24));
259 * test if audio buffer is filled enough to start playing
261 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder
*encoder
)
263 struct drm_device
*dev
= encoder
->dev
;
264 struct radeon_device
*rdev
= dev
->dev_private
;
265 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
266 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
267 uint32_t offset
= dig
->afmt
->offset
;
269 return (RREG32(HDMI0_STATUS
+ offset
) & 0x10) != 0;
273 * have buffer status changed since last call?
275 int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
)
277 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
278 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
281 if (!dig
->afmt
|| !dig
->afmt
->enabled
)
284 status
= r600_hdmi_is_audio_buffer_filled(encoder
);
285 result
= dig
->afmt
->last_buffer_filled_status
!= status
;
286 dig
->afmt
->last_buffer_filled_status
= status
;
292 * write the audio workaround status to the hardware
294 static void r600_hdmi_audio_workaround(struct drm_encoder
*encoder
)
296 struct drm_device
*dev
= encoder
->dev
;
297 struct radeon_device
*rdev
= dev
->dev_private
;
298 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
299 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
300 uint32_t offset
= dig
->afmt
->offset
;
301 bool hdmi_audio_workaround
= false; /* FIXME */
304 if (!hdmi_audio_workaround
||
305 r600_hdmi_is_audio_buffer_filled(encoder
))
306 value
= 0; /* disable workaround */
308 value
= HDMI0_AUDIO_TEST_EN
; /* enable workaround */
309 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
310 value
, ~HDMI0_AUDIO_TEST_EN
);
315 * update the info frames with the data from the current display mode
317 void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
319 struct drm_device
*dev
= encoder
->dev
;
320 struct radeon_device
*rdev
= dev
->dev_private
;
321 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
322 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
325 /* Silent, r600_hdmi_enable will raise WARN for us */
326 if (!dig
->afmt
->enabled
)
328 offset
= dig
->afmt
->offset
;
330 r600_audio_set_clock(encoder
, mode
->clock
);
332 WREG32(HDMI0_VBI_PACKET_CONTROL
+ offset
,
333 HDMI0_NULL_SEND
); /* send null packets when required */
335 WREG32(HDMI0_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
337 if (ASIC_IS_DCE32(rdev
)) {
338 WREG32(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
339 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
340 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
341 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ offset
,
342 AFMT_AUDIO_SAMPLE_SEND
| /* send audio packets */
343 AFMT_60958_CS_UPDATE
); /* allow 60958 channel status fields to be updated */
345 WREG32(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
346 HDMI0_AUDIO_SAMPLE_SEND
| /* send audio packets */
347 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
348 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
349 HDMI0_60958_CS_UPDATE
); /* allow 60958 channel status fields to be updated */
352 WREG32(HDMI0_ACR_PACKET_CONTROL
+ offset
,
353 HDMI0_ACR_AUTO_SEND
| /* allow hw to sent ACR packets when required */
354 HDMI0_ACR_SOURCE
); /* select SW CTS value */
356 WREG32(HDMI0_VBI_PACKET_CONTROL
+ offset
,
357 HDMI0_NULL_SEND
| /* send null packets when required */
358 HDMI0_GC_SEND
| /* send general control packets */
359 HDMI0_GC_CONT
); /* send general control packets every frame */
361 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
362 WREG32(HDMI0_INFOFRAME_CONTROL0
+ offset
,
363 HDMI0_AVI_INFO_SEND
| /* enable AVI info frames */
364 HDMI0_AVI_INFO_CONT
| /* send AVI info frames every frame/field */
365 HDMI0_AUDIO_INFO_SEND
| /* enable audio info frames (frames won't be set until audio is enabled) */
366 HDMI0_AUDIO_INFO_CONT
); /* send audio info frames every frame/field */
368 WREG32(HDMI0_INFOFRAME_CONTROL1
+ offset
,
369 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
370 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
372 WREG32(HDMI0_GC
+ offset
, 0); /* unset HDMI0_GC_AVMUTE */
374 r600_hdmi_videoinfoframe(encoder
, RGB
, 0, 0, 0, 0,
375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
377 r600_hdmi_update_ACR(encoder
, mode
->clock
);
379 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
380 WREG32(HDMI0_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
381 WREG32(HDMI0_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
382 WREG32(HDMI0_RAMP_CONTROL2
+ offset
, 0x00000001);
383 WREG32(HDMI0_RAMP_CONTROL3
+ offset
, 0x00000001);
385 r600_hdmi_audio_workaround(encoder
);
389 * update settings with current parameters from audio engine
391 void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
)
393 struct drm_device
*dev
= encoder
->dev
;
394 struct radeon_device
*rdev
= dev
->dev_private
;
395 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
396 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
397 struct r600_audio audio
= r600_audio_status(rdev
);
401 if (!dig
->afmt
|| !dig
->afmt
->enabled
)
403 offset
= dig
->afmt
->offset
;
405 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
406 r600_hdmi_is_audio_buffer_filled(encoder
) ? "playing" : "stopped",
407 audio
.channels
, audio
.rate
, audio
.bits_per_sample
);
408 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
409 (int)audio
.status_bits
, (int)audio
.category_code
);
412 if (audio
.status_bits
& AUDIO_STATUS_PROFESSIONAL
)
414 if (audio
.status_bits
& AUDIO_STATUS_NONAUDIO
)
416 if (audio
.status_bits
& AUDIO_STATUS_COPYRIGHT
)
418 if (audio
.status_bits
& AUDIO_STATUS_EMPHASIS
)
421 iec
|= HDMI0_60958_CS_CATEGORY_CODE(audio
.category_code
);
423 switch (audio
.rate
) {
425 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
428 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
431 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
434 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
437 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
440 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
443 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
447 WREG32(HDMI0_60958_0
+ offset
, iec
);
450 switch (audio
.bits_per_sample
) {
452 iec
|= HDMI0_60958_CS_WORD_LENGTH(0x2);
455 iec
|= HDMI0_60958_CS_WORD_LENGTH(0x3);
458 iec
|= HDMI0_60958_CS_WORD_LENGTH(0xb);
461 if (audio
.status_bits
& AUDIO_STATUS_V
)
463 WREG32_P(HDMI0_60958_1
+ offset
, iec
, ~0x5000f);
465 r600_hdmi_audioinfoframe(encoder
, audio
.channels
- 1, 0, 0, 0, 0, 0, 0,
468 r600_hdmi_audio_workaround(encoder
);
472 * enable the HDMI engine
474 void r600_hdmi_enable(struct drm_encoder
*encoder
)
476 struct drm_device
*dev
= encoder
->dev
;
477 struct radeon_device
*rdev
= dev
->dev_private
;
478 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
479 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
483 if (ASIC_IS_DCE6(rdev
))
486 /* Silent, r600_hdmi_enable will raise WARN for us */
487 if (dig
->afmt
->enabled
)
489 offset
= dig
->afmt
->offset
;
491 /* Older chipsets require setting HDMI and routing manually */
492 if (rdev
->family
>= CHIP_R600
&& !ASIC_IS_DCE3(rdev
)) {
493 hdmi
= HDMI0_ERROR_ACK
| HDMI0_ENABLE
;
494 switch (radeon_encoder
->encoder_id
) {
495 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
496 WREG32_P(AVIVO_TMDSA_CNTL
, AVIVO_TMDSA_CNTL_HDMI_EN
,
497 ~AVIVO_TMDSA_CNTL_HDMI_EN
);
498 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_TMDSA
);
500 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
501 WREG32_P(AVIVO_LVTMA_CNTL
, AVIVO_LVTMA_CNTL_HDMI_EN
,
502 ~AVIVO_LVTMA_CNTL_HDMI_EN
);
503 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_LVTMA
);
505 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
506 WREG32_P(DDIA_CNTL
, DDIA_HDMI_EN
, ~DDIA_HDMI_EN
);
507 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_DDIA
);
509 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
510 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_DVOA
);
513 dev_err(rdev
->dev
, "Invalid encoder for HDMI: 0x%X\n",
514 radeon_encoder
->encoder_id
);
517 WREG32(HDMI0_CONTROL
+ offset
, hdmi
);
520 if (rdev
->irq
.installed
) {
521 /* if irq is available use it */
522 radeon_irq_kms_enable_afmt(rdev
, dig
->afmt
->id
);
525 dig
->afmt
->enabled
= true;
527 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
528 offset
, radeon_encoder
->encoder_id
);
532 * disable the HDMI engine
534 void r600_hdmi_disable(struct drm_encoder
*encoder
)
536 struct drm_device
*dev
= encoder
->dev
;
537 struct radeon_device
*rdev
= dev
->dev_private
;
538 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
539 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
542 if (ASIC_IS_DCE6(rdev
))
545 /* Called for ATOM_ENCODER_MODE_HDMI only */
546 if (!dig
|| !dig
->afmt
) {
550 if (!dig
->afmt
->enabled
)
552 offset
= dig
->afmt
->offset
;
554 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
555 offset
, radeon_encoder
->encoder_id
);
558 radeon_irq_kms_disable_afmt(rdev
, dig
->afmt
->id
);
560 /* Older chipsets not handled by AtomBIOS */
561 if (rdev
->family
>= CHIP_R600
&& !ASIC_IS_DCE3(rdev
)) {
562 switch (radeon_encoder
->encoder_id
) {
563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
564 WREG32_P(AVIVO_TMDSA_CNTL
, 0,
565 ~AVIVO_TMDSA_CNTL_HDMI_EN
);
567 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
568 WREG32_P(AVIVO_LVTMA_CNTL
, 0,
569 ~AVIVO_LVTMA_CNTL_HDMI_EN
);
571 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
572 WREG32_P(DDIA_CNTL
, 0, ~DDIA_HDMI_EN
);
574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
577 dev_err(rdev
->dev
, "Invalid encoder for HDMI: 0x%X\n",
578 radeon_encoder
->encoder_id
);
581 WREG32(HDMI0_CONTROL
+ offset
, HDMI0_ERROR_ACK
);
584 dig
->afmt
->enabled
= false;