drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #ifdef CONFIG_ACPI
  28 #include <linux/acpi.h>
  29 #endif
  30 #include <linux/power_supply.h>
  31 #include <linux/hwmon.h>
  32 #include <linux/hwmon-sysfs.h>
  33
  34 #define RADEON_IDLE_LOOP_MS 100
  35 #define RADEON_RECLOCK_DELAY_MS 200
  36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  37
  38 static const char *radeon_pm_state_type_name[5] = {
  39         "Default",
  40         "Powersave",
  41         "Battery",
  42         "Balanced",
  43         "Performance",
  44 };
  45
  46 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  47 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  48 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  50 static void radeon_pm_update_profile(struct radeon_device *rdev);
  51 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  52
  53 #define ACPI_AC_CLASS           "ac_adapter"
  54
  55 int radeon_pm_get_type_index(struct radeon_device *rdev,
  56                              enum radeon_pm_state_type ps_type,
  57                              int instance)
  58 {
  59         int i;
  60         int found_instance = -1;
  61
  62         for (i = 0; i < rdev->pm.num_power_states; i++) {
  63                 if (rdev->pm.power_state[i].type == ps_type) {
  64                         found_instance++;
  65                         if (found_instance == instance)
  66                                 return i;
  67                 }
  68         }
  69         /* return default if no match */
  70         return rdev->pm.default_power_state_index;
  71 }
  72
  73 #ifdef CONFIG_ACPI
  74 static int radeon_acpi_event(struct notifier_block *nb,
  75                              unsigned long val,
  76                              void *data)
  77 {
  78         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  79         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  80
  81         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  82                 if (power_supply_is_system_supplied() > 0)
  83                         DRM_DEBUG_DRIVER("pm: AC\n");
  84                 else
  85                         DRM_DEBUG_DRIVER("pm: DC\n");
  86
  87                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  88                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  89                                 mutex_lock(&rdev->pm.mutex);
  90                                 radeon_pm_update_profile(rdev);
  91                                 radeon_pm_set_clocks(rdev);
  92                                 mutex_unlock(&rdev->pm.mutex);
  93                         }
  94                 }
  95         }
  96
  97         return NOTIFY_OK;
  98 }
  99 #endif
 100
 101 static void radeon_pm_update_profile(struct radeon_device *rdev)
 102 {
 103         switch (rdev->pm.profile) {
 104         case PM_PROFILE_DEFAULT:
 105                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
 106                 break;
 107         case PM_PROFILE_AUTO:
 108                 if (power_supply_is_system_supplied() > 0) {
 109                         if (rdev->pm.active_crtc_count > 1)
 110                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 111                         else
 112                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 113                 } else {
 114                         if (rdev->pm.active_crtc_count > 1)
 115                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 116                         else
 117                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 118                 }
 119                 break;
 120         case PM_PROFILE_LOW:
 121                 if (rdev->pm.active_crtc_count > 1)
 122                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 123                 else
 124                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 125                 break;
 126         case PM_PROFILE_MID:
 127                 if (rdev->pm.active_crtc_count > 1)
 128                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 129                 else
 130                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 131                 break;
 132         case PM_PROFILE_HIGH:
 133                 if (rdev->pm.active_crtc_count > 1)
 134                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 135                 else
 136                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 137                 break;
 138         }
 139
 140         if (rdev->pm.active_crtc_count == 0) {
 141                 rdev->pm.requested_power_state_index =
 142                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 143                 rdev->pm.requested_clock_mode_index =
 144                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 145         } else {
 146                 rdev->pm.requested_power_state_index =
 147                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 148                 rdev->pm.requested_clock_mode_index =
 149                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 150         }
 151 }
 152
 153 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 154 {
 155         struct radeon_bo *bo, *n;
 156
 157         if (list_empty(&rdev->gem.objects))
 158                 return;
 159
 160         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 161                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 162                         ttm_bo_unmap_virtual(&bo->tbo);
 163         }
 164 }
 165
 166 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 167 {
 168         if (rdev->pm.active_crtcs) {
 169                 rdev->pm.vblank_sync = false;
 170                 wait_event_timeout(
 171                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 172                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 173         }
 174 }
 175
 176 static void radeon_set_power_state(struct radeon_device *rdev)
 177 {
 178         u32 sclk, mclk;
 179         bool misc_after = false;
 180
 181         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 182             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 183                 return;
 184
 185         if (radeon_gui_idle(rdev)) {
 186                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 187                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 188                 if (sclk > rdev->pm.default_sclk)
 189                         sclk = rdev->pm.default_sclk;
 190
 191                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 192                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 193                 if (mclk > rdev->pm.default_mclk)
 194                         mclk = rdev->pm.default_mclk;
 195
 196                 /* upvolt before raising clocks, downvolt after lowering clocks */
 197                 if (sclk < rdev->pm.current_sclk)
 198                         misc_after = true;
 199
 200                 radeon_sync_with_vblank(rdev);
 201
 202                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 203                         if (!radeon_pm_in_vbl(rdev))
 204                                 return;
 205                 }
 206
 207                 radeon_pm_prepare(rdev);
 208
 209                 if (!misc_after)
 210                         /* voltage, pcie lanes, etc.*/
 211                         radeon_pm_misc(rdev);
 212
 213                 /* set engine clock */
 214                 if (sclk != rdev->pm.current_sclk) {
 215                         radeon_pm_debug_check_in_vbl(rdev, false);
 216                         radeon_set_engine_clock(rdev, sclk);
 217                         radeon_pm_debug_check_in_vbl(rdev, true);
 218                         rdev->pm.current_sclk = sclk;
 219                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 220                 }
 221
 222                 /* set memory clock */
 223                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 224                         radeon_pm_debug_check_in_vbl(rdev, false);
 225                         radeon_set_memory_clock(rdev, mclk);
 226                         radeon_pm_debug_check_in_vbl(rdev, true);
 227                         rdev->pm.current_mclk = mclk;
 228                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 229                 }
 230
 231                 if (misc_after)
 232                         /* voltage, pcie lanes, etc.*/
 233                         radeon_pm_misc(rdev);
 234
 235                 radeon_pm_finish(rdev);
 236
 237                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 238                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 239         } else
 240                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 241 }
 242
 243 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 244 {
 245         int i;
 246
 247         /* no need to take locks, etc. if nothing's going to change */
 248         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 249             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 250                 return;
 251
 252         mutex_lock(&rdev->ddev->struct_mutex);
 253         down_write(&rdev->pm.mclk_lock);
 254         mutex_lock(&rdev->ring_lock);
 255
 256         /* gui idle int has issues on older chips it seems */
 257         if (rdev->family >= CHIP_R600) {
 258                 if (rdev->irq.installed) {
 259                         /* wait for GPU to become idle */
 260                         radeon_irq_kms_wait_gui_idle(rdev);
 261                 }
 262         } else {
 263                 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 264                 if (ring->ready) {
 265                         radeon_fence_wait_empty_locked(rdev, RADEON_RING_TYPE_GFX_INDEX);
 266                 }
 267         }
 268         radeon_unmap_vram_bos(rdev);
 269
 270         if (rdev->irq.installed) {
 271                 for (i = 0; i < rdev->num_crtc; i++) {
 272                         if (rdev->pm.active_crtcs & (1 << i)) {
 273                                 rdev->pm.req_vblank |= (1 << i);
 274                                 drm_vblank_get(rdev->ddev, i);
 275                         }
 276                 }
 277         }
 278
 279         radeon_set_power_state(rdev);
 280
 281         if (rdev->irq.installed) {
 282                 for (i = 0; i < rdev->num_crtc; i++) {
 283                         if (rdev->pm.req_vblank & (1 << i)) {
 284                                 rdev->pm.req_vblank &= ~(1 << i);
 285                                 drm_vblank_put(rdev->ddev, i);
 286                         }
 287                 }
 288         }
 289
 290         /* update display watermarks based on new power state */
 291         radeon_update_bandwidth_info(rdev);
 292         if (rdev->pm.active_crtc_count)
 293                 radeon_bandwidth_update(rdev);
 294
 295         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 296
 297         mutex_unlock(&rdev->ring_lock);
 298         up_write(&rdev->pm.mclk_lock);
 299         mutex_unlock(&rdev->ddev->struct_mutex);
 300 }
 301
 302 static void radeon_pm_print_states(struct radeon_device *rdev)
 303 {
 304         int i, j;
 305         struct radeon_power_state *power_state;
 306         struct radeon_pm_clock_info *clock_info;
 307
 308         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 309         for (i = 0; i < rdev->pm.num_power_states; i++) {
 310                 power_state = &rdev->pm.power_state[i];
 311                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 312                         radeon_pm_state_type_name[power_state->type]);
 313                 if (i == rdev->pm.default_power_state_index)
 314                         DRM_DEBUG_DRIVER("\tDefault");
 315                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 316                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 317                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 318                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 319                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 320                 for (j = 0; j < power_state->num_clock_modes; j++) {
 321                         clock_info = &(power_state->clock_info[j]);
 322                         if (rdev->flags & RADEON_IS_IGP)
 323                                 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
 324                                         j,
 325                                         clock_info->sclk * 10,
 326                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 327                         else
 328                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 329                                         j,
 330                                         clock_info->sclk * 10,
 331                                         clock_info->mclk * 10,
 332                                         clock_info->voltage.voltage,
 333                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 334                 }
 335         }
 336 }
 337
 338 static ssize_t radeon_get_pm_profile(struct device *dev,
 339                                      struct device_attribute *attr,
 340                                      char *buf)
 341 {
 342         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 343         struct radeon_device *rdev = ddev->dev_private;
 344         int cp = rdev->pm.profile;
 345
 346         return snprintf(buf, PAGE_SIZE, "%s\n",
 347                         (cp == PM_PROFILE_AUTO) ? "auto" :
 348                         (cp == PM_PROFILE_LOW) ? "low" :
 349                         (cp == PM_PROFILE_MID) ? "mid" :
 350                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 351 }
 352
 353 static ssize_t radeon_set_pm_profile(struct device *dev,
 354                                      struct device_attribute *attr,
 355                                      const char *buf,
 356                                      size_t count)
 357 {
 358         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 359         struct radeon_device *rdev = ddev->dev_private;
 360
 361         mutex_lock(&rdev->pm.mutex);
 362         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 363                 if (strncmp("default", buf, strlen("default")) == 0)
 364                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 365                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 366                         rdev->pm.profile = PM_PROFILE_AUTO;
 367                 else if (strncmp("low", buf, strlen("low")) == 0)
 368                         rdev->pm.profile = PM_PROFILE_LOW;
 369                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 370                         rdev->pm.profile = PM_PROFILE_MID;
 371                 else if (strncmp("high", buf, strlen("high")) == 0)
 372                         rdev->pm.profile = PM_PROFILE_HIGH;
 373                 else {
 374                         count = -EINVAL;
 375                         goto fail;
 376                 }
 377                 radeon_pm_update_profile(rdev);
 378                 radeon_pm_set_clocks(rdev);
 379         } else
 380                 count = -EINVAL;
 381
 382 fail:
 383         mutex_unlock(&rdev->pm.mutex);
 384
 385         return count;
 386 }
 387
 388 static ssize_t radeon_get_pm_method(struct device *dev,
 389                                     struct device_attribute *attr,
 390                                     char *buf)
 391 {
 392         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 393         struct radeon_device *rdev = ddev->dev_private;
 394         int pm = rdev->pm.pm_method;
 395
 396         return snprintf(buf, PAGE_SIZE, "%s\n",
 397                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 398 }
 399
 400 static ssize_t radeon_set_pm_method(struct device *dev,
 401                                     struct device_attribute *attr,
 402                                     const char *buf,
 403                                     size_t count)
 404 {
 405         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 406         struct radeon_device *rdev = ddev->dev_private;
 407
 408
 409         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 410                 mutex_lock(&rdev->pm.mutex);
 411                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 412                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 413                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 414                 mutex_unlock(&rdev->pm.mutex);
 415         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 416                 mutex_lock(&rdev->pm.mutex);
 417                 /* disable dynpm */
 418                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 419                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 420                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 421                 mutex_unlock(&rdev->pm.mutex);
 422                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 423         } else {
 424                 count = -EINVAL;
 425                 goto fail;
 426         }
 427         radeon_pm_compute_clocks(rdev);
 428 fail:
 429         return count;
 430 }
 431
 432 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 433 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 434
 435 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 436                                       struct device_attribute *attr,
 437                                       char *buf)
 438 {
 439         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 440         struct radeon_device *rdev = ddev->dev_private;
 441         int temp;
 442
 443         switch (rdev->pm.int_thermal_type) {
 444         case THERMAL_TYPE_RV6XX:
 445                 temp = rv6xx_get_temp(rdev);
 446                 break;
 447         case THERMAL_TYPE_RV770:
 448                 temp = rv770_get_temp(rdev);
 449                 break;
 450         case THERMAL_TYPE_EVERGREEN:
 451         case THERMAL_TYPE_NI:
 452                 temp = evergreen_get_temp(rdev);
 453                 break;
 454         case THERMAL_TYPE_SUMO:
 455                 temp = sumo_get_temp(rdev);
 456                 break;
 457         case THERMAL_TYPE_SI:
 458                 temp = si_get_temp(rdev);
 459                 break;
 460         default:
 461                 temp = 0;
 462                 break;
 463         }
 464
 465         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 466 }
 467
 468 static ssize_t radeon_hwmon_show_name(struct device *dev,
 469                                       struct device_attribute *attr,
 470                                       char *buf)
 471 {
 472         return sprintf(buf, "radeon\n");
 473 }
 474
 475 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 476 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 477
 478 static struct attribute *hwmon_attributes[] = {
 479         &sensor_dev_attr_temp1_input.dev_attr.attr,
 480         &sensor_dev_attr_name.dev_attr.attr,
 481         NULL
 482 };
 483
 484 static const struct attribute_group hwmon_attrgroup = {
 485         .attrs = hwmon_attributes,
 486 };
 487
 488 static int radeon_hwmon_init(struct radeon_device *rdev)
 489 {
 490         int err = 0;
 491
 492         rdev->pm.int_hwmon_dev = NULL;
 493
 494         switch (rdev->pm.int_thermal_type) {
 495         case THERMAL_TYPE_RV6XX:
 496         case THERMAL_TYPE_RV770:
 497         case THERMAL_TYPE_EVERGREEN:
 498         case THERMAL_TYPE_NI:
 499         case THERMAL_TYPE_SUMO:
 500         case THERMAL_TYPE_SI:
 501                 /* No support for TN yet */
 502                 if (rdev->family == CHIP_ARUBA)
 503                         return err;
 504                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 505                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 506                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 507                         dev_err(rdev->dev,
 508                                 "Unable to register hwmon device: %d\n", err);
 509                         break;
 510                 }
 511                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 512                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 513                                          &hwmon_attrgroup);
 514                 if (err) {
 515                         dev_err(rdev->dev,
 516                                 "Unable to create hwmon sysfs file: %d\n", err);
 517                         hwmon_device_unregister(rdev->dev);
 518                 }
 519                 break;
 520         default:
 521                 break;
 522         }
 523
 524         return err;
 525 }
 526
 527 static void radeon_hwmon_fini(struct radeon_device *rdev)
 528 {
 529         if (rdev->pm.int_hwmon_dev) {
 530                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 531                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 532         }
 533 }
 534
 535 void radeon_pm_suspend(struct radeon_device *rdev)
 536 {
 537         mutex_lock(&rdev->pm.mutex);
 538         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 539                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 540                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 541         }
 542         mutex_unlock(&rdev->pm.mutex);
 543
 544         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 545 }
 546
 547 void radeon_pm_resume(struct radeon_device *rdev)
 548 {
 549         /* set up the default clocks if the MC ucode is loaded */
 550         if ((rdev->family >= CHIP_BARTS) &&
 551             (rdev->family <= CHIP_CAYMAN) &&
 552             rdev->mc_fw) {
 553                 if (rdev->pm.default_vddc)
 554                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 555                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 556                 if (rdev->pm.default_vddci)
 557                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 558                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 559                 if (rdev->pm.default_sclk)
 560                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 561                 if (rdev->pm.default_mclk)
 562                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 563         }
 564         /* asic init will reset the default power state */
 565         mutex_lock(&rdev->pm.mutex);
 566         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 567         rdev->pm.current_clock_mode_index = 0;
 568         rdev->pm.current_sclk = rdev->pm.default_sclk;
 569         rdev->pm.current_mclk = rdev->pm.default_mclk;
 570         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 571         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 572         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 573             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 574                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 575                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 576                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 577         }
 578         mutex_unlock(&rdev->pm.mutex);
 579         radeon_pm_compute_clocks(rdev);
 580 }
 581
 582 int radeon_pm_init(struct radeon_device *rdev)
 583 {
 584         int ret;
 585
 586         /* default to profile method */
 587         rdev->pm.pm_method = PM_METHOD_PROFILE;
 588         rdev->pm.profile = PM_PROFILE_DEFAULT;
 589         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 590         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 591         rdev->pm.dynpm_can_upclock = true;
 592         rdev->pm.dynpm_can_downclock = true;
 593         rdev->pm.default_sclk = rdev->clock.default_sclk;
 594         rdev->pm.default_mclk = rdev->clock.default_mclk;
 595         rdev->pm.current_sclk = rdev->clock.default_sclk;
 596         rdev->pm.current_mclk = rdev->clock.default_mclk;
 597         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 598
 599         if (rdev->bios) {
 600                 if (rdev->is_atom_bios)
 601                         radeon_atombios_get_power_modes(rdev);
 602                 else
 603                         radeon_combios_get_power_modes(rdev);
 604                 radeon_pm_print_states(rdev);
 605                 radeon_pm_init_profile(rdev);
 606                 /* set up the default clocks if the MC ucode is loaded */
 607                 if ((rdev->family >= CHIP_BARTS) &&
 608                     (rdev->family <= CHIP_CAYMAN) &&
 609                     rdev->mc_fw) {
 610                         if (rdev->pm.default_vddc)
 611                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 612                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 613                         if (rdev->pm.default_vddci)
 614                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 615                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 616                         if (rdev->pm.default_sclk)
 617                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 618                         if (rdev->pm.default_mclk)
 619                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 620                 }
 621         }
 622
 623         /* set up the internal thermal sensor if applicable */
 624         ret = radeon_hwmon_init(rdev);
 625         if (ret)
 626                 return ret;
 627
 628         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 629
 630         if (rdev->pm.num_power_states > 1) {
 631                 /* where's the best place to put these? */
 632                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 633                 if (ret)
 634                         DRM_ERROR("failed to create device file for power profile\n");
 635                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 636                 if (ret)
 637                         DRM_ERROR("failed to create device file for power method\n");
 638
 639 #ifdef CONFIG_ACPI
 640                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 641                 register_acpi_notifier(&rdev->acpi_nb);
 642 #endif
 643                 if (radeon_debugfs_pm_init(rdev)) {
 644                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 645                 }
 646
 647                 DRM_INFO("radeon: power management initialized\n");
 648         }
 649
 650         return 0;
 651 }
 652
 653 void radeon_pm_fini(struct radeon_device *rdev)
 654 {
 655         if (rdev->pm.num_power_states > 1) {
 656                 mutex_lock(&rdev->pm.mutex);
 657                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 658                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 659                         radeon_pm_update_profile(rdev);
 660                         radeon_pm_set_clocks(rdev);
 661                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 662                         /* reset default clocks */
 663                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 664                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 665                         radeon_pm_set_clocks(rdev);
 666                 }
 667                 mutex_unlock(&rdev->pm.mutex);
 668
 669                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 670
 671                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 672                 device_remove_file(rdev->dev, &dev_attr_power_method);
 673 #ifdef CONFIG_ACPI
 674                 unregister_acpi_notifier(&rdev->acpi_nb);
 675 #endif
 676         }
 677
 678         if (rdev->pm.power_state)
 679                 kfree(rdev->pm.power_state);
 680
 681         radeon_hwmon_fini(rdev);
 682 }
 683
 684 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 685 {
 686         struct drm_device *ddev = rdev->ddev;
 687         struct drm_crtc *crtc;
 688         struct radeon_crtc *radeon_crtc;
 689
 690         if (rdev->pm.num_power_states < 2)
 691                 return;
 692
 693         mutex_lock(&rdev->pm.mutex);
 694
 695         rdev->pm.active_crtcs = 0;
 696         rdev->pm.active_crtc_count = 0;
 697         list_for_each_entry(crtc,
 698                 &ddev->mode_config.crtc_list, head) {
 699                 radeon_crtc = to_radeon_crtc(crtc);
 700                 if (radeon_crtc->enabled) {
 701                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 702                         rdev->pm.active_crtc_count++;
 703                 }
 704         }
 705
 706         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 707                 radeon_pm_update_profile(rdev);
 708                 radeon_pm_set_clocks(rdev);
 709         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 710                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 711                         if (rdev->pm.active_crtc_count > 1) {
 712                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 713                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 714
 715                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 716                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 717                                         radeon_pm_get_dynpm_state(rdev);
 718                                         radeon_pm_set_clocks(rdev);
 719
 720                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 721                                 }
 722                         } else if (rdev->pm.active_crtc_count == 1) {
 723                                 /* TODO: Increase clocks if needed for current mode */
 724
 725                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 726                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 727                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 728                                         radeon_pm_get_dynpm_state(rdev);
 729                                         radeon_pm_set_clocks(rdev);
 730
 731                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 732                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 733                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 734                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 735                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 736                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 737                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 738                                 }
 739                         } else { /* count == 0 */
 740                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 741                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 742
 743                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 744                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 745                                         radeon_pm_get_dynpm_state(rdev);
 746                                         radeon_pm_set_clocks(rdev);
 747                                 }
 748                         }
 749                 }
 750         }
 751
 752         mutex_unlock(&rdev->pm.mutex);
 753 }
 754
 755 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 756 {
 757         int  crtc, vpos, hpos, vbl_status;
 758         bool in_vbl = true;
 759
 760         /* Iterate over all active crtc's. All crtc's must be in vblank,
 761          * otherwise return in_vbl == false.
 762          */
 763         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 764                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 765                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 766                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 767                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 768                                 in_vbl = false;
 769                 }
 770         }
 771
 772         return in_vbl;
 773 }
 774
 775 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 776 {
 777         u32 stat_crtc = 0;
 778         bool in_vbl = radeon_pm_in_vbl(rdev);
 779
 780         if (in_vbl == false)
 781                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 782                          finish ? "exit" : "entry");
 783         return in_vbl;
 784 }
 785
 786 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 787 {
 788         struct radeon_device *rdev;
 789         int resched;
 790         rdev = container_of(work, struct radeon_device,
 791                                 pm.dynpm_idle_work.work);
 792
 793         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 794         mutex_lock(&rdev->pm.mutex);
 795         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 796                 int not_processed = 0;
 797                 int i;
 798
 799                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 800                         struct radeon_ring *ring = &rdev->ring[i];
 801
 802                         if (ring->ready) {
 803                                 not_processed += radeon_fence_count_emitted(rdev, i);
 804                                 if (not_processed >= 3)
 805                                         break;
 806                         }
 807                 }
 808
 809                 if (not_processed >= 3) { /* should upclock */
 810                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 811                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 812                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 813                                    rdev->pm.dynpm_can_upclock) {
 814                                 rdev->pm.dynpm_planned_action =
 815                                         DYNPM_ACTION_UPCLOCK;
 816                                 rdev->pm.dynpm_action_timeout = jiffies +
 817                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 818                         }
 819                 } else if (not_processed == 0) { /* should downclock */
 820                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 821                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 822                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 823                                    rdev->pm.dynpm_can_downclock) {
 824                                 rdev->pm.dynpm_planned_action =
 825                                         DYNPM_ACTION_DOWNCLOCK;
 826                                 rdev->pm.dynpm_action_timeout = jiffies +
 827                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 828                         }
 829                 }
 830
 831                 /* Note, radeon_pm_set_clocks is called with static_switch set
 832                  * to false since we want to wait for vbl to avoid flicker.
 833                  */
 834                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 835                     jiffies > rdev->pm.dynpm_action_timeout) {
 836                         radeon_pm_get_dynpm_state(rdev);
 837                         radeon_pm_set_clocks(rdev);
 838                 }
 839
 840                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 841                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 842         }
 843         mutex_unlock(&rdev->pm.mutex);
 844         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 845 }
 846
 847 /*
 848  * Debugfs info
 849  */
 850 #if defined(CONFIG_DEBUG_FS)
 851
 852 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 853 {
 854         struct drm_info_node *node = (struct drm_info_node *) m->private;
 855         struct drm_device *dev = node->minor->dev;
 856         struct radeon_device *rdev = dev->dev_private;
 857
 858         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 859         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 860         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 861         if (rdev->asic->pm.get_memory_clock)
 862                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 863         if (rdev->pm.current_vddc)
 864                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 865         if (rdev->asic->pm.get_pcie_lanes)
 866                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 867
 868         return 0;
 869 }
 870
 871 static struct drm_info_list radeon_pm_info_list[] = {
 872         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 873 };
 874 #endif
 875
 876 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 877 {
 878 #if defined(CONFIG_DEBUG_FS)
 879         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 880 #else
 881         return 0;
 882 #endif
 883 }