drivers/media/video/davinci/vpbe_osd.c

   1 /*
   2  * Copyright (C) 2007-2010 Texas Instruments Inc
   3  * Copyright (C) 2007 MontaVista Software, Inc.
   4  *
   5  * Andy Lowe (alowe@mvista.com), MontaVista Software
   6  * - Initial version
   7  * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
   8  * - ported to sub device interface
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation version 2.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  */
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/slab.h>
  30
  31 #include <mach/cputype.h>
  32 #include <mach/hardware.h>
  33
  34 #include <media/davinci/vpss.h>
  35 #include <media/v4l2-device.h>
  36 #include <media/davinci/vpbe_types.h>
  37 #include <media/davinci/vpbe_osd.h>
  38
  39 #include <linux/io.h>
  40 #include "vpbe_osd_regs.h"
  41
  42 #define MODULE_NAME     VPBE_OSD_SUBDEV_NAME
  43
  44 /* register access routines */
  45 static inline u32 osd_read(struct osd_state *sd, u32 offset)
  46 {
  47         struct osd_state *osd = sd;
  48
  49         return readl(osd->osd_base + offset);
  50 }
  51
  52 static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset)
  53 {
  54         struct osd_state *osd = sd;
  55
  56         writel(val, osd->osd_base + offset);
  57
  58         return val;
  59 }
  60
  61 static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset)
  62 {
  63         struct osd_state *osd = sd;
  64
  65         u32 addr = osd->osd_base + offset;
  66         u32 val = readl(addr) | mask;
  67
  68         writel(val, addr);
  69
  70         return val;
  71 }
  72
  73 static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset)
  74 {
  75         struct osd_state *osd = sd;
  76
  77         u32 addr = osd->osd_base + offset;
  78         u32 val = readl(addr) & ~mask;
  79
  80         writel(val, addr);
  81
  82         return val;
  83 }
  84
  85 static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val,
  86                                  u32 offset)
  87 {
  88         struct osd_state *osd = sd;
  89
  90         u32 addr = osd->osd_base + offset;
  91         u32 new_val = (readl(addr) & ~mask) | (val & mask);
  92
  93         writel(new_val, addr);
  94
  95         return new_val;
  96 }
  97
  98 /* define some macros for layer and pixfmt classification */
  99 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
 100 #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1))
 101 #define is_rgb_pixfmt(pixfmt) \
 102         (((pixfmt) == PIXFMT_RGB565) || ((pixfmt) == PIXFMT_RGB888))
 103 #define is_yc_pixfmt(pixfmt) \
 104         (((pixfmt) == PIXFMT_YCbCrI) || ((pixfmt) == PIXFMT_YCrCbI) || \
 105         ((pixfmt) == PIXFMT_NV12))
 106 #define MAX_WIN_SIZE OSD_VIDWIN0XP_V0X
 107 #define MAX_LINE_LENGTH (OSD_VIDWIN0OFST_V0LO << 5)
 108
 109 /**
 110  * _osd_dm6446_vid0_pingpong() - field inversion fix for DM6446
 111  * @sd - ptr to struct osd_state
 112  * @field_inversion - inversion flag
 113  * @fb_base_phys - frame buffer address
 114  * @lconfig - ptr to layer config
 115  *
 116  * This routine implements a workaround for the field signal inversion silicon
 117  * erratum described in Advisory 1.3.8 for the DM6446.  The fb_base_phys and
 118  * lconfig parameters apply to the vid0 window.  This routine should be called
 119  * whenever the vid0 layer configuration or start address is modified, or when
 120  * the OSD field inversion setting is modified.
 121  * Returns: 1 if the ping-pong buffers need to be toggled in the vsync isr, or
 122  *          0 otherwise
 123  */
 124 static int _osd_dm6446_vid0_pingpong(struct osd_state *sd,
 125                                      int field_inversion,
 126                                      unsigned long fb_base_phys,
 127                                      const struct osd_layer_config *lconfig)
 128 {
 129         struct osd_platform_data *pdata;
 130
 131         pdata = (struct osd_platform_data *)sd->dev->platform_data;
 132         if (pdata->field_inv_wa_enable) {
 133
 134                 if (!field_inversion || !lconfig->interlaced) {
 135                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
 136                         osd_write(sd, fb_base_phys & ~0x1F, OSD_PPVWIN0ADR);
 137                         osd_modify(sd, OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, 0,
 138                                    OSD_MISCCTL);
 139                         return 0;
 140                 } else {
 141                         unsigned miscctl = OSD_MISCCTL_PPRV;
 142
 143                         osd_write(sd,
 144                                 (fb_base_phys & ~0x1F) - lconfig->line_length,
 145                                 OSD_VIDWIN0ADR);
 146                         osd_write(sd,
 147                                 (fb_base_phys & ~0x1F) + lconfig->line_length,
 148                                 OSD_PPVWIN0ADR);
 149                         osd_modify(sd,
 150                                 OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, miscctl,
 151                                 OSD_MISCCTL);
 152
 153                         return 1;
 154                 }
 155         }
 156
 157         return 0;
 158 }
 159
 160 static void _osd_set_field_inversion(struct osd_state *sd, int enable)
 161 {
 162         unsigned fsinv = 0;
 163
 164         if (enable)
 165                 fsinv = OSD_MODE_FSINV;
 166
 167         osd_modify(sd, OSD_MODE_FSINV, fsinv, OSD_MODE);
 168 }
 169
 170 static void _osd_set_blink_attribute(struct osd_state *sd, int enable,
 171                                      enum osd_blink_interval blink)
 172 {
 173         u32 osdatrmd = 0;
 174
 175         if (enable) {
 176                 osdatrmd |= OSD_OSDATRMD_BLNK;
 177                 osdatrmd |= blink << OSD_OSDATRMD_BLNKINT_SHIFT;
 178         }
 179         /* caller must ensure that OSD1 is configured in attribute mode */
 180         osd_modify(sd, OSD_OSDATRMD_BLNKINT | OSD_OSDATRMD_BLNK, osdatrmd,
 181                   OSD_OSDATRMD);
 182 }
 183
 184 static void _osd_set_rom_clut(struct osd_state *sd,
 185                               enum osd_rom_clut rom_clut)
 186 {
 187         if (rom_clut == ROM_CLUT0)
 188                 osd_clear(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
 189         else
 190                 osd_set(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
 191 }
 192
 193 static void _osd_set_palette_map(struct osd_state *sd,
 194                                  enum osd_win_layer osdwin,
 195                                  unsigned char pixel_value,
 196                                  unsigned char clut_index,
 197                                  enum osd_pix_format pixfmt)
 198 {
 199         static const int map_2bpp[] = { 0, 5, 10, 15 };
 200         static const int map_1bpp[] = { 0, 15 };
 201         int bmp_offset;
 202         int bmp_shift;
 203         int bmp_mask;
 204         int bmp_reg;
 205
 206         switch (pixfmt) {
 207         case PIXFMT_1BPP:
 208                 bmp_reg = map_1bpp[pixel_value & 0x1];
 209                 break;
 210         case PIXFMT_2BPP:
 211                 bmp_reg = map_2bpp[pixel_value & 0x3];
 212                 break;
 213         case PIXFMT_4BPP:
 214                 bmp_reg = pixel_value & 0xf;
 215                 break;
 216         default:
 217                 return;
 218         }
 219
 220         switch (osdwin) {
 221         case OSDWIN_OSD0:
 222                 bmp_offset = OSD_W0BMP01 + (bmp_reg >> 1) * sizeof(u32);
 223                 break;
 224         case OSDWIN_OSD1:
 225                 bmp_offset = OSD_W1BMP01 + (bmp_reg >> 1) * sizeof(u32);
 226                 break;
 227         default:
 228                 return;
 229         }
 230
 231         if (bmp_reg & 1) {
 232                 bmp_shift = 8;
 233                 bmp_mask = 0xff << 8;
 234         } else {
 235                 bmp_shift = 0;
 236                 bmp_mask = 0xff;
 237         }
 238
 239         osd_modify(sd, bmp_mask, clut_index << bmp_shift, bmp_offset);
 240 }
 241
 242 static void _osd_set_rec601_attenuation(struct osd_state *sd,
 243                                         enum osd_win_layer osdwin, int enable)
 244 {
 245         switch (osdwin) {
 246         case OSDWIN_OSD0:
 247                 osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
 248                           enable ? OSD_OSDWIN0MD_ATN0E : 0,
 249                           OSD_OSDWIN0MD);
 250                 if (sd->vpbe_type == VPBE_VERSION_1)
 251                         osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
 252                                   enable ? OSD_OSDWIN0MD_ATN0E : 0,
 253                                   OSD_OSDWIN0MD);
 254                 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 255                            (sd->vpbe_type == VPBE_VERSION_2))
 256                         osd_modify(sd, OSD_EXTMODE_ATNOSD0EN,
 257                                   enable ? OSD_EXTMODE_ATNOSD0EN : 0,
 258                                   OSD_EXTMODE);
 259                 break;
 260         case OSDWIN_OSD1:
 261                 osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
 262                           enable ? OSD_OSDWIN1MD_ATN1E : 0,
 263                           OSD_OSDWIN1MD);
 264                 if (sd->vpbe_type == VPBE_VERSION_1)
 265                         osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
 266                                   enable ? OSD_OSDWIN1MD_ATN1E : 0,
 267                                   OSD_OSDWIN1MD);
 268                 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 269                            (sd->vpbe_type == VPBE_VERSION_2))
 270                         osd_modify(sd, OSD_EXTMODE_ATNOSD1EN,
 271                                   enable ? OSD_EXTMODE_ATNOSD1EN : 0,
 272                                   OSD_EXTMODE);
 273                 break;
 274         }
 275 }
 276
 277 static void _osd_set_blending_factor(struct osd_state *sd,
 278                                      enum osd_win_layer osdwin,
 279                                      enum osd_blending_factor blend)
 280 {
 281         switch (osdwin) {
 282         case OSDWIN_OSD0:
 283                 osd_modify(sd, OSD_OSDWIN0MD_BLND0,
 284                           blend << OSD_OSDWIN0MD_BLND0_SHIFT, OSD_OSDWIN0MD);
 285                 break;
 286         case OSDWIN_OSD1:
 287                 osd_modify(sd, OSD_OSDWIN1MD_BLND1,
 288                           blend << OSD_OSDWIN1MD_BLND1_SHIFT, OSD_OSDWIN1MD);
 289                 break;
 290         }
 291 }
 292
 293 static void _osd_enable_rgb888_pixblend(struct osd_state *sd,
 294                                         enum osd_win_layer osdwin)
 295 {
 296
 297         osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL);
 298         switch (osdwin) {
 299         case OSDWIN_OSD0:
 300                 osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR,
 301                           OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE);
 302                 break;
 303         case OSDWIN_OSD1:
 304                 osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR,
 305                           OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE);
 306                 break;
 307         }
 308 }
 309
 310 static void _osd_enable_color_key(struct osd_state *sd,
 311                                   enum osd_win_layer osdwin,
 312                                   unsigned colorkey,
 313                                   enum osd_pix_format pixfmt)
 314 {
 315         switch (pixfmt) {
 316         case PIXFMT_1BPP:
 317         case PIXFMT_2BPP:
 318         case PIXFMT_4BPP:
 319         case PIXFMT_8BPP:
 320                 if (sd->vpbe_type == VPBE_VERSION_3) {
 321                         switch (osdwin) {
 322                         case OSDWIN_OSD0:
 323                                 osd_modify(sd, OSD_TRANSPBMPIDX_BMP0,
 324                                           colorkey <<
 325                                           OSD_TRANSPBMPIDX_BMP0_SHIFT,
 326                                           OSD_TRANSPBMPIDX);
 327                                 break;
 328                         case OSDWIN_OSD1:
 329                                 osd_modify(sd, OSD_TRANSPBMPIDX_BMP1,
 330                                           colorkey <<
 331                                           OSD_TRANSPBMPIDX_BMP1_SHIFT,
 332                                           OSD_TRANSPBMPIDX);
 333                                 break;
 334                         }
 335                 }
 336                 break;
 337         case PIXFMT_RGB565:
 338                 if (sd->vpbe_type == VPBE_VERSION_1)
 339                         osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS,
 340                                   OSD_TRANSPVAL);
 341                 else if (sd->vpbe_type == VPBE_VERSION_3)
 342                         osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
 343                                   OSD_TRANSPVALL);
 344                 break;
 345         case PIXFMT_YCbCrI:
 346         case PIXFMT_YCrCbI:
 347                 if (sd->vpbe_type == VPBE_VERSION_3)
 348                         osd_modify(sd, OSD_TRANSPVALU_Y, colorkey,
 349                                    OSD_TRANSPVALU);
 350                 break;
 351         case PIXFMT_RGB888:
 352                 if (sd->vpbe_type == VPBE_VERSION_3) {
 353                         osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
 354                                   OSD_TRANSPVALL);
 355                         osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16,
 356                                   OSD_TRANSPVALU);
 357                 }
 358                 break;
 359         default:
 360                 break;
 361         }
 362
 363         switch (osdwin) {
 364         case OSDWIN_OSD0:
 365                 osd_set(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
 366                 break;
 367         case OSDWIN_OSD1:
 368                 osd_set(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
 369                 break;
 370         }
 371 }
 372
 373 static void _osd_disable_color_key(struct osd_state *sd,
 374                                    enum osd_win_layer osdwin)
 375 {
 376         switch (osdwin) {
 377         case OSDWIN_OSD0:
 378                 osd_clear(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
 379                 break;
 380         case OSDWIN_OSD1:
 381                 osd_clear(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
 382                 break;
 383         }
 384 }
 385
 386 static void _osd_set_osd_clut(struct osd_state *sd,
 387                               enum osd_win_layer osdwin,
 388                               enum osd_clut clut)
 389 {
 390         u32 winmd = 0;
 391
 392         switch (osdwin) {
 393         case OSDWIN_OSD0:
 394                 if (clut == RAM_CLUT)
 395                         winmd |= OSD_OSDWIN0MD_CLUTS0;
 396                 osd_modify(sd, OSD_OSDWIN0MD_CLUTS0, winmd, OSD_OSDWIN0MD);
 397                 break;
 398         case OSDWIN_OSD1:
 399                 if (clut == RAM_CLUT)
 400                         winmd |= OSD_OSDWIN1MD_CLUTS1;
 401                 osd_modify(sd, OSD_OSDWIN1MD_CLUTS1, winmd, OSD_OSDWIN1MD);
 402                 break;
 403         }
 404 }
 405
 406 static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer,
 407                           enum osd_zoom_factor h_zoom,
 408                           enum osd_zoom_factor v_zoom)
 409 {
 410         u32 winmd = 0;
 411
 412         switch (layer) {
 413         case WIN_OSD0:
 414                 winmd |= (h_zoom << OSD_OSDWIN0MD_OHZ0_SHIFT);
 415                 winmd |= (v_zoom << OSD_OSDWIN0MD_OVZ0_SHIFT);
 416                 osd_modify(sd, OSD_OSDWIN0MD_OHZ0 | OSD_OSDWIN0MD_OVZ0, winmd,
 417                           OSD_OSDWIN0MD);
 418                 break;
 419         case WIN_VID0:
 420                 winmd |= (h_zoom << OSD_VIDWINMD_VHZ0_SHIFT);
 421                 winmd |= (v_zoom << OSD_VIDWINMD_VVZ0_SHIFT);
 422                 osd_modify(sd, OSD_VIDWINMD_VHZ0 | OSD_VIDWINMD_VVZ0, winmd,
 423                           OSD_VIDWINMD);
 424                 break;
 425         case WIN_OSD1:
 426                 winmd |= (h_zoom << OSD_OSDWIN1MD_OHZ1_SHIFT);
 427                 winmd |= (v_zoom << OSD_OSDWIN1MD_OVZ1_SHIFT);
 428                 osd_modify(sd, OSD_OSDWIN1MD_OHZ1 | OSD_OSDWIN1MD_OVZ1, winmd,
 429                           OSD_OSDWIN1MD);
 430                 break;
 431         case WIN_VID1:
 432                 winmd |= (h_zoom << OSD_VIDWINMD_VHZ1_SHIFT);
 433                 winmd |= (v_zoom << OSD_VIDWINMD_VVZ1_SHIFT);
 434                 osd_modify(sd, OSD_VIDWINMD_VHZ1 | OSD_VIDWINMD_VVZ1, winmd,
 435                           OSD_VIDWINMD);
 436                 break;
 437         }
 438 }
 439
 440 static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
 441 {
 442         switch (layer) {
 443         case WIN_OSD0:
 444                 osd_clear(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
 445                 break;
 446         case WIN_VID0:
 447                 osd_clear(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
 448                 break;
 449         case WIN_OSD1:
 450                 /* disable attribute mode as well as disabling the window */
 451                 osd_clear(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
 452                           OSD_OSDWIN1MD);
 453                 break;
 454         case WIN_VID1:
 455                 osd_clear(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
 456                 break;
 457         }
 458 }
 459
 460 static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
 461 {
 462         struct osd_state *osd = sd;
 463         struct osd_window_state *win = &osd->win[layer];
 464         unsigned long flags;
 465
 466         spin_lock_irqsave(&osd->lock, flags);
 467
 468         if (!win->is_enabled) {
 469                 spin_unlock_irqrestore(&osd->lock, flags);
 470                 return;
 471         }
 472         win->is_enabled = 0;
 473
 474         _osd_disable_layer(sd, layer);
 475
 476         spin_unlock_irqrestore(&osd->lock, flags);
 477 }
 478
 479 static void _osd_enable_attribute_mode(struct osd_state *sd)
 480 {
 481         /* enable attribute mode for OSD1 */
 482         osd_set(sd, OSD_OSDWIN1MD_OASW, OSD_OSDWIN1MD);
 483 }
 484
 485 static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer)
 486 {
 487         switch (layer) {
 488         case WIN_OSD0:
 489                 osd_set(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
 490                 break;
 491         case WIN_VID0:
 492                 osd_set(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
 493                 break;
 494         case WIN_OSD1:
 495                 /* enable OSD1 and disable attribute mode */
 496                 osd_modify(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
 497                           OSD_OSDWIN1MD_OACT1, OSD_OSDWIN1MD);
 498                 break;
 499         case WIN_VID1:
 500                 osd_set(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
 501                 break;
 502         }
 503 }
 504
 505 static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer,
 506                             int otherwin)
 507 {
 508         struct osd_state *osd = sd;
 509         struct osd_window_state *win = &osd->win[layer];
 510         struct osd_layer_config *cfg = &win->lconfig;
 511         unsigned long flags;
 512
 513         spin_lock_irqsave(&osd->lock, flags);
 514
 515         /*
 516          * use otherwin flag to know this is the other vid window
 517          * in YUV420 mode, if is, skip this check
 518          */
 519         if (!otherwin && (!win->is_allocated ||
 520                         !win->fb_base_phys ||
 521                         !cfg->line_length ||
 522                         !cfg->xsize ||
 523                         !cfg->ysize)) {
 524                 spin_unlock_irqrestore(&osd->lock, flags);
 525                 return -1;
 526         }
 527
 528         if (win->is_enabled) {
 529                 spin_unlock_irqrestore(&osd->lock, flags);
 530                 return 0;
 531         }
 532         win->is_enabled = 1;
 533
 534         if (cfg->pixfmt != PIXFMT_OSD_ATTR)
 535                 _osd_enable_layer(sd, layer);
 536         else {
 537                 _osd_enable_attribute_mode(sd);
 538                 _osd_set_blink_attribute(sd, osd->is_blinking, osd->blink);
 539         }
 540
 541         spin_unlock_irqrestore(&osd->lock, flags);
 542
 543         return 0;
 544 }
 545
 546 #define OSD_SRC_ADDR_HIGH4      0x7800000
 547 #define OSD_SRC_ADDR_HIGH7      0x7F0000
 548 #define OSD_SRCADD_OFSET_SFT    23
 549 #define OSD_SRCADD_ADD_SFT      16
 550 #define OSD_WINADL_MASK         0xFFFF
 551 #define OSD_WINOFST_MASK        0x1000
 552 #define VPBE_REG_BASE           0x80000000
 553
 554 static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer,
 555                              unsigned long fb_base_phys,
 556                              unsigned long cbcr_ofst)
 557 {
 558
 559         if (sd->vpbe_type == VPBE_VERSION_1) {
 560                 switch (layer) {
 561                 case WIN_OSD0:
 562                         osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR);
 563                         break;
 564                 case WIN_VID0:
 565                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
 566                         break;
 567                 case WIN_OSD1:
 568                         osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR);
 569                         break;
 570                 case WIN_VID1:
 571                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR);
 572                         break;
 573               }
 574         } else if (sd->vpbe_type == VPBE_VERSION_3) {
 575                 unsigned long fb_offset_32 =
 576                     (fb_base_phys - VPBE_REG_BASE) >> 5;
 577
 578                 switch (layer) {
 579                 case WIN_OSD0:
 580                         osd_modify(sd, OSD_OSDWINADH_O0AH,
 581                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 582                                                    OSD_OSDWINADH_O0AH_SHIFT),
 583                                   OSD_OSDWINADH);
 584                         osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL,
 585                                   OSD_OSDWIN0ADL);
 586                         break;
 587                 case WIN_VID0:
 588                         osd_modify(sd, OSD_VIDWINADH_V0AH,
 589                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 590                                                    OSD_VIDWINADH_V0AH_SHIFT),
 591                                   OSD_VIDWINADH);
 592                         osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL,
 593                                   OSD_VIDWIN0ADL);
 594                         break;
 595                 case WIN_OSD1:
 596                         osd_modify(sd, OSD_OSDWINADH_O1AH,
 597                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 598                                                    OSD_OSDWINADH_O1AH_SHIFT),
 599                                   OSD_OSDWINADH);
 600                         osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL,
 601                                   OSD_OSDWIN1ADL);
 602                         break;
 603                 case WIN_VID1:
 604                         osd_modify(sd, OSD_VIDWINADH_V1AH,
 605                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 606                                                    OSD_VIDWINADH_V1AH_SHIFT),
 607                                   OSD_VIDWINADH);
 608                         osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL,
 609                                   OSD_VIDWIN1ADL);
 610                         break;
 611                 }
 612         } else if (sd->vpbe_type == VPBE_VERSION_2) {
 613                 struct osd_window_state *win = &sd->win[layer];
 614                 unsigned long fb_offset_32, cbcr_offset_32;
 615
 616                 fb_offset_32 = fb_base_phys - VPBE_REG_BASE;
 617                 if (cbcr_ofst)
 618                         cbcr_offset_32 = cbcr_ofst;
 619                 else
 620                         cbcr_offset_32 = win->lconfig.line_length *
 621                                          win->lconfig.ysize;
 622                 cbcr_offset_32 += fb_offset_32;
 623                 fb_offset_32 = fb_offset_32 >> 5;
 624                 cbcr_offset_32 = cbcr_offset_32 >> 5;
 625                 /*
 626                  * DM365: start address is 27-bit long address b26 - b23 are
 627                  * in offset register b12 - b9, and * bit 26 has to be '1'
 628                  */
 629                 if (win->lconfig.pixfmt == PIXFMT_NV12) {
 630                         switch (layer) {
 631                         case WIN_VID0:
 632                         case WIN_VID1:
 633                                 /* Y is in VID0 */
 634                                 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
 635                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 636                                          (OSD_SRCADD_OFSET_SFT -
 637                                          OSD_WINOFST_AH_SHIFT)) |
 638                                          OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
 639                                 osd_modify(sd, OSD_VIDWINADH_V0AH,
 640                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 641                                           (OSD_SRCADD_ADD_SFT -
 642                                           OSD_VIDWINADH_V0AH_SHIFT),
 643                                            OSD_VIDWINADH);
 644                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 645                                           OSD_VIDWIN0ADL);
 646                                 /* CbCr is in VID1 */
 647                                 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
 648                                          ((cbcr_offset_32 &
 649                                          OSD_SRC_ADDR_HIGH4) >>
 650                                          (OSD_SRCADD_OFSET_SFT -
 651                                          OSD_WINOFST_AH_SHIFT)) |
 652                                          OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
 653                                 osd_modify(sd, OSD_VIDWINADH_V1AH,
 654                                           (cbcr_offset_32 &
 655                                           OSD_SRC_ADDR_HIGH7) >>
 656                                           (OSD_SRCADD_ADD_SFT -
 657                                           OSD_VIDWINADH_V1AH_SHIFT),
 658                                           OSD_VIDWINADH);
 659                                 osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK,
 660                                           OSD_VIDWIN1ADL);
 661                                 break;
 662                         default:
 663                                 break;
 664                         }
 665                 }
 666
 667                 switch (layer) {
 668                 case WIN_OSD0:
 669                         osd_modify(sd, OSD_OSDWIN0OFST_O0AH,
 670                                  ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 671                                  (OSD_SRCADD_OFSET_SFT -
 672                                  OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
 673                                   OSD_OSDWIN0OFST);
 674                         osd_modify(sd, OSD_OSDWINADH_O0AH,
 675                                  (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 676                                  (OSD_SRCADD_ADD_SFT -
 677                                  OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH);
 678                         osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 679                                         OSD_OSDWIN0ADL);
 680                         break;
 681                 case WIN_VID0:
 682                         if (win->lconfig.pixfmt != PIXFMT_NV12) {
 683                                 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
 684                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 685                                          (OSD_SRCADD_OFSET_SFT -
 686                                          OSD_WINOFST_AH_SHIFT)) |
 687                                          OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
 688                                 osd_modify(sd, OSD_VIDWINADH_V0AH,
 689                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 690                                           (OSD_SRCADD_ADD_SFT -
 691                                           OSD_VIDWINADH_V0AH_SHIFT),
 692                                           OSD_VIDWINADH);
 693                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 694                                           OSD_VIDWIN0ADL);
 695                         }
 696                         break;
 697                 case WIN_OSD1:
 698                         osd_modify(sd, OSD_OSDWIN1OFST_O1AH,
 699                                  ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 700                                  (OSD_SRCADD_OFSET_SFT -
 701                                  OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
 702                                   OSD_OSDWIN1OFST);
 703                         osd_modify(sd, OSD_OSDWINADH_O1AH,
 704                                   (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 705                                   (OSD_SRCADD_ADD_SFT -
 706                                   OSD_OSDWINADH_O1AH_SHIFT),
 707                                   OSD_OSDWINADH);
 708                         osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 709                                         OSD_OSDWIN1ADL);
 710                         break;
 711                 case WIN_VID1:
 712                         if (win->lconfig.pixfmt != PIXFMT_NV12) {
 713                                 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
 714                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 715                                          (OSD_SRCADD_OFSET_SFT -
 716                                          OSD_WINOFST_AH_SHIFT)) |
 717                                          OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
 718                                 osd_modify(sd, OSD_VIDWINADH_V1AH,
 719                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 720                                           (OSD_SRCADD_ADD_SFT -
 721                                           OSD_VIDWINADH_V1AH_SHIFT),
 722                                           OSD_VIDWINADH);
 723                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 724                                           OSD_VIDWIN1ADL);
 725                         }
 726                         break;
 727                 }
 728         }
 729 }
 730
 731 static void osd_start_layer(struct osd_state *sd, enum osd_layer layer,
 732                             unsigned long fb_base_phys,
 733                             unsigned long cbcr_ofst)
 734 {
 735         struct osd_state *osd = sd;
 736         struct osd_window_state *win = &osd->win[layer];
 737         struct osd_layer_config *cfg = &win->lconfig;
 738         unsigned long flags;
 739
 740         spin_lock_irqsave(&osd->lock, flags);
 741
 742         win->fb_base_phys = fb_base_phys & ~0x1F;
 743         _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst);
 744
 745         if (layer == WIN_VID0) {
 746                 osd->pingpong =
 747                     _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
 748                                                        win->fb_base_phys,
 749                                                        cfg);
 750         }
 751
 752         spin_unlock_irqrestore(&osd->lock, flags);
 753 }
 754
 755 static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer,
 756                                  struct osd_layer_config *lconfig)
 757 {
 758         struct osd_state *osd = sd;
 759         struct osd_window_state *win = &osd->win[layer];
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&osd->lock, flags);
 763
 764         *lconfig = win->lconfig;
 765
 766         spin_unlock_irqrestore(&osd->lock, flags);
 767 }
 768
 769 /**
 770  * try_layer_config() - Try a specific configuration for the layer
 771  * @sd  - ptr to struct osd_state
 772  * @layer - layer to configure
 773  * @lconfig - layer configuration to try
 774  *
 775  * If the requested lconfig is completely rejected and the value of lconfig on
 776  * exit is the current lconfig, then try_layer_config() returns 1.  Otherwise,
 777  * try_layer_config() returns 0.  A return value of 0 does not necessarily mean
 778  * that the value of lconfig on exit is identical to the value of lconfig on
 779  * entry, but merely that it represents a change from the current lconfig.
 780  */
 781 static int try_layer_config(struct osd_state *sd, enum osd_layer layer,
 782                             struct osd_layer_config *lconfig)
 783 {
 784         struct osd_state *osd = sd;
 785         struct osd_window_state *win = &osd->win[layer];
 786         int bad_config = 0;
 787
 788         /* verify that the pixel format is compatible with the layer */
 789         switch (lconfig->pixfmt) {
 790         case PIXFMT_1BPP:
 791         case PIXFMT_2BPP:
 792         case PIXFMT_4BPP:
 793         case PIXFMT_8BPP:
 794         case PIXFMT_RGB565:
 795                 if (osd->vpbe_type == VPBE_VERSION_1)
 796                         bad_config = !is_vid_win(layer);
 797                 break;
 798         case PIXFMT_YCbCrI:
 799         case PIXFMT_YCrCbI:
 800                 bad_config = !is_vid_win(layer);
 801                 break;
 802         case PIXFMT_RGB888:
 803                 if (osd->vpbe_type == VPBE_VERSION_1)
 804                         bad_config = !is_vid_win(layer);
 805                 else if ((osd->vpbe_type == VPBE_VERSION_3) ||
 806                          (osd->vpbe_type == VPBE_VERSION_2))
 807                         bad_config = !is_osd_win(layer);
 808                 break;
 809         case PIXFMT_NV12:
 810                 if (osd->vpbe_type != VPBE_VERSION_2)
 811                         bad_config = 1;
 812                 else
 813                         bad_config = is_osd_win(layer);
 814                 break;
 815         case PIXFMT_OSD_ATTR:
 816                 bad_config = (layer != WIN_OSD1);
 817                 break;
 818         default:
 819                 bad_config = 1;
 820                 break;
 821         }
 822         if (bad_config) {
 823                 /*
 824                  * The requested pixel format is incompatible with the layer,
 825                  * so keep the current layer configuration.
 826                  */
 827                 *lconfig = win->lconfig;
 828                 return bad_config;
 829         }
 830
 831         /* DM6446: */
 832         /* only one OSD window at a time can use RGB pixel formats */
 833           if ((osd->vpbe_type == VPBE_VERSION_1) &&
 834                   is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) {
 835                 enum osd_pix_format pixfmt;
 836                 if (layer == WIN_OSD0)
 837                         pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt;
 838                 else
 839                         pixfmt = osd->win[WIN_OSD0].lconfig.pixfmt;
 840
 841                 if (is_rgb_pixfmt(pixfmt)) {
 842                         /*
 843                          * The other OSD window is already configured for an
 844                          * RGB, so keep the current layer configuration.
 845                          */
 846                         *lconfig = win->lconfig;
 847                         return 1;
 848                 }
 849         }
 850
 851         /* DM6446: only one video window at a time can use RGB888 */
 852         if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) &&
 853                 lconfig->pixfmt == PIXFMT_RGB888) {
 854                 enum osd_pix_format pixfmt;
 855
 856                 if (layer == WIN_VID0)
 857                         pixfmt = osd->win[WIN_VID1].lconfig.pixfmt;
 858                 else
 859                         pixfmt = osd->win[WIN_VID0].lconfig.pixfmt;
 860
 861                 if (pixfmt == PIXFMT_RGB888) {
 862                         /*
 863                          * The other video window is already configured for
 864                          * RGB888, so keep the current layer configuration.
 865                          */
 866                         *lconfig = win->lconfig;
 867                         return 1;
 868                 }
 869         }
 870
 871         /* window dimensions must be non-zero */
 872         if (!lconfig->line_length || !lconfig->xsize || !lconfig->ysize) {
 873                 *lconfig = win->lconfig;
 874                 return 1;
 875         }
 876
 877         /* round line_length up to a multiple of 32 */
 878         lconfig->line_length = ((lconfig->line_length + 31) / 32) * 32;
 879         lconfig->line_length =
 880             min(lconfig->line_length, (unsigned)MAX_LINE_LENGTH);
 881         lconfig->xsize = min(lconfig->xsize, (unsigned)MAX_WIN_SIZE);
 882         lconfig->ysize = min(lconfig->ysize, (unsigned)MAX_WIN_SIZE);
 883         lconfig->xpos = min(lconfig->xpos, (unsigned)MAX_WIN_SIZE);
 884         lconfig->ypos = min(lconfig->ypos, (unsigned)MAX_WIN_SIZE);
 885         lconfig->interlaced = (lconfig->interlaced != 0);
 886         if (lconfig->interlaced) {
 887                 /* ysize and ypos must be even for interlaced displays */
 888                 lconfig->ysize &= ~1;
 889                 lconfig->ypos &= ~1;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static void _osd_disable_vid_rgb888(struct osd_state *sd)
 896 {
 897         /*
 898          * The DM6446 supports RGB888 pixel format in a single video window.
 899          * This routine disables RGB888 pixel format for both video windows.
 900          * The caller must ensure that neither video window is currently
 901          * configured for RGB888 pixel format.
 902          */
 903         if (sd->vpbe_type == VPBE_VERSION_1)
 904                 osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL);
 905 }
 906
 907 static void _osd_enable_vid_rgb888(struct osd_state *sd,
 908                                    enum osd_layer layer)
 909 {
 910         /*
 911          * The DM6446 supports RGB888 pixel format in a single video window.
 912          * This routine enables RGB888 pixel format for the specified video
 913          * window.  The caller must ensure that the other video window is not
 914          * currently configured for RGB888 pixel format, as this routine will
 915          * disable RGB888 pixel format for the other window.
 916          */
 917         if (sd->vpbe_type == VPBE_VERSION_1) {
 918                 if (layer == WIN_VID0)
 919                         osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 920                                   OSD_MISCCTL_RGBEN, OSD_MISCCTL);
 921                 else if (layer == WIN_VID1)
 922                         osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 923                                   OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 924                                   OSD_MISCCTL);
 925         }
 926 }
 927
 928 static void _osd_set_cbcr_order(struct osd_state *sd,
 929                                 enum osd_pix_format pixfmt)
 930 {
 931         /*
 932          * The caller must ensure that all windows using YC pixfmt use the same
 933          * Cb/Cr order.
 934          */
 935         if (pixfmt == PIXFMT_YCbCrI)
 936                 osd_clear(sd, OSD_MODE_CS, OSD_MODE);
 937         else if (pixfmt == PIXFMT_YCrCbI)
 938                 osd_set(sd, OSD_MODE_CS, OSD_MODE);
 939 }
 940
 941 static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
 942                                   const struct osd_layer_config *lconfig)
 943 {
 944         u32 winmd = 0, winmd_mask = 0, bmw = 0;
 945
 946         _osd_set_cbcr_order(sd, lconfig->pixfmt);
 947
 948         switch (layer) {
 949         case WIN_OSD0:
 950                 if (sd->vpbe_type == VPBE_VERSION_1) {
 951                         winmd_mask |= OSD_OSDWIN0MD_RGB0E;
 952                         if (lconfig->pixfmt == PIXFMT_RGB565)
 953                                 winmd |= OSD_OSDWIN0MD_RGB0E;
 954                 } else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 955                   (sd->vpbe_type == VPBE_VERSION_2)) {
 956                         winmd_mask |= OSD_OSDWIN0MD_BMP0MD;
 957                         switch (lconfig->pixfmt) {
 958                         case PIXFMT_RGB565:
 959                                         winmd |= (1 <<
 960                                         OSD_OSDWIN0MD_BMP0MD_SHIFT);
 961                                         break;
 962                         case PIXFMT_RGB888:
 963                                 winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
 964                                 _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0);
 965                                 break;
 966                         case PIXFMT_YCbCrI:
 967                         case PIXFMT_YCrCbI:
 968                                 winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
 969                                 break;
 970                         default:
 971                                 break;
 972                         }
 973                 }
 974
 975                 winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0;
 976
 977                 switch (lconfig->pixfmt) {
 978                 case PIXFMT_1BPP:
 979                         bmw = 0;
 980                         break;
 981                 case PIXFMT_2BPP:
 982                         bmw = 1;
 983                         break;
 984                 case PIXFMT_4BPP:
 985                         bmw = 2;
 986                         break;
 987                 case PIXFMT_8BPP:
 988                         bmw = 3;
 989                         break;
 990                 default:
 991                         break;
 992                 }
 993                 winmd |= (bmw << OSD_OSDWIN0MD_BMW0_SHIFT);
 994
 995                 if (lconfig->interlaced)
 996                         winmd |= OSD_OSDWIN0MD_OFF0;
 997
 998                 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN0MD);
 999                 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN0OFST);
1000                 osd_write(sd, lconfig->xpos, OSD_OSDWIN0XP);
1001                 osd_write(sd, lconfig->xsize, OSD_OSDWIN0XL);
1002                 if (lconfig->interlaced) {
1003                         osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN0YP);
1004                         osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN0YL);
1005                 } else {
1006                         osd_write(sd, lconfig->ypos, OSD_OSDWIN0YP);
1007                         osd_write(sd, lconfig->ysize, OSD_OSDWIN0YL);
1008                 }
1009                 break;
1010         case WIN_VID0:
1011                 winmd_mask |= OSD_VIDWINMD_VFF0;
1012                 if (lconfig->interlaced)
1013                         winmd |= OSD_VIDWINMD_VFF0;
1014
1015                 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1016                 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN0OFST);
1017                 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1018                 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1019                 /*
1020                  * For YUV420P format the register contents are
1021                  * duplicated in both VID registers
1022                  */
1023                 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1024                                 (lconfig->pixfmt == PIXFMT_NV12)) {
1025                         /* other window also */
1026                         if (lconfig->interlaced) {
1027                                 winmd_mask |= OSD_VIDWINMD_VFF1;
1028                                 winmd |= OSD_VIDWINMD_VFF1;
1029                                 osd_modify(sd, winmd_mask, winmd,
1030                                           OSD_VIDWINMD);
1031                         }
1032
1033                         osd_modify(sd, OSD_MISCCTL_S420D,
1034                                     OSD_MISCCTL_S420D, OSD_MISCCTL);
1035                         osd_write(sd, lconfig->line_length >> 5,
1036                                   OSD_VIDWIN1OFST);
1037                         osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1038                         osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1039                         /*
1040                           * if NV21 pixfmt and line length not 32B
1041                           * aligned (e.g. NTSC), Need to set window
1042                           * X pixel size to be 32B aligned as well
1043                           */
1044                         if (lconfig->xsize % 32) {
1045                                 osd_write(sd,
1046                                           ((lconfig->xsize + 31) & ~31),
1047                                           OSD_VIDWIN1XL);
1048                                 osd_write(sd,
1049                                           ((lconfig->xsize + 31) & ~31),
1050                                           OSD_VIDWIN0XL);
1051                         }
1052                 } else if ((sd->vpbe_type == VPBE_VERSION_2) &&
1053                                 (lconfig->pixfmt != PIXFMT_NV12)) {
1054                         osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
1055                                                 OSD_MISCCTL);
1056                 }
1057
1058                 if (lconfig->interlaced) {
1059                         osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP);
1060                         osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL);
1061                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1062                                 lconfig->pixfmt == PIXFMT_NV12) {
1063                                 osd_write(sd, lconfig->ypos >> 1,
1064                                           OSD_VIDWIN1YP);
1065                                 osd_write(sd, lconfig->ysize >> 1,
1066                                           OSD_VIDWIN1YL);
1067                         }
1068                 } else {
1069                         osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1070                         osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1071                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1072                                 lconfig->pixfmt == PIXFMT_NV12) {
1073                                 osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1074                                 osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1075                         }
1076                 }
1077                 break;
1078         case WIN_OSD1:
1079                 /*
1080                  * The caller must ensure that OSD1 is disabled prior to
1081                  * switching from a normal mode to attribute mode or from
1082                  * attribute mode to a normal mode.
1083                  */
1084                 if (lconfig->pixfmt == PIXFMT_OSD_ATTR) {
1085                         if (sd->vpbe_type == VPBE_VERSION_1) {
1086                                 winmd_mask |= OSD_OSDWIN1MD_ATN1E |
1087                                 OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 |
1088                                 OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1;
1089                         } else {
1090                                 winmd_mask |= OSD_OSDWIN1MD_BMP1MD |
1091                                 OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 |
1092                                 OSD_OSDWIN1MD_TE1;
1093                         }
1094                 } else {
1095                         if (sd->vpbe_type == VPBE_VERSION_1) {
1096                                 winmd_mask |= OSD_OSDWIN1MD_RGB1E;
1097                                 if (lconfig->pixfmt == PIXFMT_RGB565)
1098                                         winmd |= OSD_OSDWIN1MD_RGB1E;
1099                         } else if ((sd->vpbe_type == VPBE_VERSION_3)
1100                                    || (sd->vpbe_type == VPBE_VERSION_2)) {
1101                                 winmd_mask |= OSD_OSDWIN1MD_BMP1MD;
1102                                 switch (lconfig->pixfmt) {
1103                                 case PIXFMT_RGB565:
1104                                         winmd |=
1105                                             (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1106                                         break;
1107                                 case PIXFMT_RGB888:
1108                                         winmd |=
1109                                             (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1110                                         _osd_enable_rgb888_pixblend(sd,
1111                                                         OSDWIN_OSD1);
1112                                         break;
1113                                 case PIXFMT_YCbCrI:
1114                                 case PIXFMT_YCrCbI:
1115                                         winmd |=
1116                                             (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1117                                         break;
1118                                 default:
1119                                         break;
1120                                 }
1121                         }
1122
1123                         winmd_mask |= OSD_OSDWIN1MD_BMW1;
1124                         switch (lconfig->pixfmt) {
1125                         case PIXFMT_1BPP:
1126                                 bmw = 0;
1127                                 break;
1128                         case PIXFMT_2BPP:
1129                                 bmw = 1;
1130                                 break;
1131                         case PIXFMT_4BPP:
1132                                 bmw = 2;
1133                                 break;
1134                         case PIXFMT_8BPP:
1135                                 bmw = 3;
1136                                 break;
1137                         default:
1138                                 break;
1139                         }
1140                         winmd |= (bmw << OSD_OSDWIN1MD_BMW1_SHIFT);
1141                 }
1142
1143                 winmd_mask |= OSD_OSDWIN1MD_OFF1;
1144                 if (lconfig->interlaced)
1145                         winmd |= OSD_OSDWIN1MD_OFF1;
1146
1147                 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN1MD);
1148                 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN1OFST);
1149                 osd_write(sd, lconfig->xpos, OSD_OSDWIN1XP);
1150                 osd_write(sd, lconfig->xsize, OSD_OSDWIN1XL);
1151                 if (lconfig->interlaced) {
1152                         osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN1YP);
1153                         osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN1YL);
1154                 } else {
1155                         osd_write(sd, lconfig->ypos, OSD_OSDWIN1YP);
1156                         osd_write(sd, lconfig->ysize, OSD_OSDWIN1YL);
1157                 }
1158                 break;
1159         case WIN_VID1:
1160                 winmd_mask |= OSD_VIDWINMD_VFF1;
1161                 if (lconfig->interlaced)
1162                         winmd |= OSD_VIDWINMD_VFF1;
1163
1164                 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1165                 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN1OFST);
1166                 osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1167                 osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1168                 /*
1169                  * For YUV420P format the register contents are
1170                  * duplicated in both VID registers
1171                  */
1172                 if (sd->vpbe_type == VPBE_VERSION_2) {
1173                         if (lconfig->pixfmt == PIXFMT_NV12) {
1174                                 /* other window also */
1175                                 if (lconfig->interlaced) {
1176                                         winmd_mask |= OSD_VIDWINMD_VFF0;
1177                                         winmd |= OSD_VIDWINMD_VFF0;
1178                                         osd_modify(sd, winmd_mask, winmd,
1179                                                   OSD_VIDWINMD);
1180                                 }
1181                                 osd_modify(sd, OSD_MISCCTL_S420D,
1182                                            OSD_MISCCTL_S420D, OSD_MISCCTL);
1183                                 osd_write(sd, lconfig->line_length >> 5,
1184                                           OSD_VIDWIN0OFST);
1185                                 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1186                                 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1187                         } else {
1188                                 osd_modify(sd, OSD_MISCCTL_S420D,
1189                                            ~OSD_MISCCTL_S420D, OSD_MISCCTL);
1190                         }
1191                 }
1192
1193                 if (lconfig->interlaced) {
1194                         osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP);
1195                         osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL);
1196                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1197                                 lconfig->pixfmt == PIXFMT_NV12) {
1198                                 osd_write(sd, lconfig->ypos >> 1,
1199                                           OSD_VIDWIN0YP);
1200                                 osd_write(sd, lconfig->ysize >> 1,
1201                                           OSD_VIDWIN0YL);
1202                         }
1203                 } else {
1204                         osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1205                         osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1206                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1207                                 lconfig->pixfmt == PIXFMT_NV12) {
1208                                 osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1209                                 osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1210                         }
1211                 }
1212                 break;
1213         }
1214 }
1215
1216 static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
1217                                 struct osd_layer_config *lconfig)
1218 {
1219         struct osd_state *osd = sd;
1220         struct osd_window_state *win = &osd->win[layer];
1221         struct osd_layer_config *cfg = &win->lconfig;
1222         unsigned long flags;
1223         int reject_config;
1224
1225         spin_lock_irqsave(&osd->lock, flags);
1226
1227         reject_config = try_layer_config(sd, layer, lconfig);
1228         if (reject_config) {
1229                 spin_unlock_irqrestore(&osd->lock, flags);
1230                 return reject_config;
1231         }
1232
1233         /* update the current Cb/Cr order */
1234         if (is_yc_pixfmt(lconfig->pixfmt))
1235                 osd->yc_pixfmt = lconfig->pixfmt;
1236
1237         /*
1238          * If we are switching OSD1 from normal mode to attribute mode or from
1239          * attribute mode to normal mode, then we must disable the window.
1240          */
1241         if (layer == WIN_OSD1) {
1242                 if (((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1243                   (cfg->pixfmt != PIXFMT_OSD_ATTR)) ||
1244                   ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1245                   (cfg->pixfmt == PIXFMT_OSD_ATTR))) {
1246                         win->is_enabled = 0;
1247                         _osd_disable_layer(sd, layer);
1248                 }
1249         }
1250
1251         _osd_set_layer_config(sd, layer, lconfig);
1252
1253         if (layer == WIN_OSD1) {
1254                 struct osd_osdwin_state *osdwin_state =
1255                     &osd->osdwin[OSDWIN_OSD1];
1256
1257                 if ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1258                   (cfg->pixfmt == PIXFMT_OSD_ATTR)) {
1259                         /*
1260                          * We just switched OSD1 from attribute mode to normal
1261                          * mode, so we must initialize the CLUT select, the
1262                          * blend factor, transparency colorkey enable, and
1263                          * attenuation enable (DM6446 only) bits in the
1264                          * OSDWIN1MD register.
1265                          */
1266                         _osd_set_osd_clut(sd, OSDWIN_OSD1,
1267                                                    osdwin_state->clut);
1268                         _osd_set_blending_factor(sd, OSDWIN_OSD1,
1269                                                           osdwin_state->blend);
1270                         if (osdwin_state->colorkey_blending) {
1271                                 _osd_enable_color_key(sd, OSDWIN_OSD1,
1272                                                                osdwin_state->
1273                                                                colorkey,
1274                                                                lconfig->pixfmt);
1275                         } else
1276                                 _osd_disable_color_key(sd, OSDWIN_OSD1);
1277                         _osd_set_rec601_attenuation(sd, OSDWIN_OSD1,
1278                                                     osdwin_state->
1279                                                     rec601_attenuation);
1280                 } else if ((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1281                   (cfg->pixfmt != PIXFMT_OSD_ATTR)) {
1282                         /*
1283                          * We just switched OSD1 from normal mode to attribute
1284                          * mode, so we must initialize the blink enable and
1285                          * blink interval bits in the OSDATRMD register.
1286                          */
1287                         _osd_set_blink_attribute(sd, osd->is_blinking,
1288                                                           osd->blink);
1289                 }
1290         }
1291
1292         /*
1293          * If we just switched to a 1-, 2-, or 4-bits-per-pixel bitmap format
1294          * then configure a default palette map.
1295          */
1296         if ((lconfig->pixfmt != cfg->pixfmt) &&
1297           ((lconfig->pixfmt == PIXFMT_1BPP) ||
1298           (lconfig->pixfmt == PIXFMT_2BPP) ||
1299           (lconfig->pixfmt == PIXFMT_4BPP))) {
1300                 enum osd_win_layer osdwin =
1301                     ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1);
1302                 struct osd_osdwin_state *osdwin_state =
1303                     &osd->osdwin[osdwin];
1304                 unsigned char clut_index;
1305                 unsigned char clut_entries = 0;
1306
1307                 switch (lconfig->pixfmt) {
1308                 case PIXFMT_1BPP:
1309                         clut_entries = 2;
1310                         break;
1311                 case PIXFMT_2BPP:
1312                         clut_entries = 4;
1313                         break;
1314                 case PIXFMT_4BPP:
1315                         clut_entries = 16;
1316                         break;
1317                 default:
1318                         break;
1319                 }
1320                 /*
1321                  * The default palette map maps the pixel value to the clut
1322                  * index, i.e. pixel value 0 maps to clut entry 0, pixel value
1323                  * 1 maps to clut entry 1, etc.
1324                  */
1325                 for (clut_index = 0; clut_index < 16; clut_index++) {
1326                         osdwin_state->palette_map[clut_index] = clut_index;
1327                         if (clut_index < clut_entries) {
1328                                 _osd_set_palette_map(sd, osdwin, clut_index,
1329                                                      clut_index,
1330                                                      lconfig->pixfmt);
1331                         }
1332                 }
1333         }
1334
1335         *cfg = *lconfig;
1336         /* DM6446: configure the RGB888 enable and window selection */
1337         if (osd->win[WIN_VID0].lconfig.pixfmt == PIXFMT_RGB888)
1338                 _osd_enable_vid_rgb888(sd, WIN_VID0);
1339         else if (osd->win[WIN_VID1].lconfig.pixfmt == PIXFMT_RGB888)
1340                 _osd_enable_vid_rgb888(sd, WIN_VID1);
1341         else
1342                 _osd_disable_vid_rgb888(sd);
1343
1344         if (layer == WIN_VID0) {
1345                 osd->pingpong =
1346                     _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
1347                                                        win->fb_base_phys,
1348                                                        cfg);
1349         }
1350
1351         spin_unlock_irqrestore(&osd->lock, flags);
1352
1353         return 0;
1354 }
1355
1356 static void osd_init_layer(struct osd_state *sd, enum osd_layer layer)
1357 {
1358         struct osd_state *osd = sd;
1359         struct osd_window_state *win = &osd->win[layer];
1360         enum osd_win_layer osdwin;
1361         struct osd_osdwin_state *osdwin_state;
1362         struct osd_layer_config *cfg = &win->lconfig;
1363         unsigned long flags;
1364
1365         spin_lock_irqsave(&osd->lock, flags);
1366
1367         win->is_enabled = 0;
1368         _osd_disable_layer(sd, layer);
1369
1370         win->h_zoom = ZOOM_X1;
1371         win->v_zoom = ZOOM_X1;
1372         _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom);
1373
1374         win->fb_base_phys = 0;
1375         _osd_start_layer(sd, layer, win->fb_base_phys, 0);
1376
1377         cfg->line_length = 0;
1378         cfg->xsize = 0;
1379         cfg->ysize = 0;
1380         cfg->xpos = 0;
1381         cfg->ypos = 0;
1382         cfg->interlaced = 0;
1383         switch (layer) {
1384         case WIN_OSD0:
1385         case WIN_OSD1:
1386                 osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1;
1387                 osdwin_state = &osd->osdwin[osdwin];
1388                 /*
1389                  * Other code relies on the fact that OSD windows default to a
1390                  * bitmap pixel format when they are deallocated, so don't
1391                  * change this default pixel format.
1392                  */
1393                 cfg->pixfmt = PIXFMT_8BPP;
1394                 _osd_set_layer_config(sd, layer, cfg);
1395                 osdwin_state->clut = RAM_CLUT;
1396                 _osd_set_osd_clut(sd, osdwin, osdwin_state->clut);
1397                 osdwin_state->colorkey_blending = 0;
1398                 _osd_disable_color_key(sd, osdwin);
1399                 osdwin_state->blend = OSD_8_VID_0;
1400                 _osd_set_blending_factor(sd, osdwin, osdwin_state->blend);
1401                 osdwin_state->rec601_attenuation = 0;
1402                 _osd_set_rec601_attenuation(sd, osdwin,
1403                                                      osdwin_state->
1404                                                      rec601_attenuation);
1405                 if (osdwin == OSDWIN_OSD1) {
1406                         osd->is_blinking = 0;
1407                         osd->blink = BLINK_X1;
1408                 }
1409                 break;
1410         case WIN_VID0:
1411         case WIN_VID1:
1412                 cfg->pixfmt = osd->yc_pixfmt;
1413                 _osd_set_layer_config(sd, layer, cfg);
1414                 break;
1415         }
1416
1417         spin_unlock_irqrestore(&osd->lock, flags);
1418 }
1419
1420 static void osd_release_layer(struct osd_state *sd, enum osd_layer layer)
1421 {
1422         struct osd_state *osd = sd;
1423         struct osd_window_state *win = &osd->win[layer];
1424         unsigned long flags;
1425
1426         spin_lock_irqsave(&osd->lock, flags);
1427
1428         if (!win->is_allocated) {
1429                 spin_unlock_irqrestore(&osd->lock, flags);
1430                 return;
1431         }
1432
1433         spin_unlock_irqrestore(&osd->lock, flags);
1434         osd_init_layer(sd, layer);
1435         spin_lock_irqsave(&osd->lock, flags);
1436
1437         win->is_allocated = 0;
1438
1439         spin_unlock_irqrestore(&osd->lock, flags);
1440 }
1441
1442 static int osd_request_layer(struct osd_state *sd, enum osd_layer layer)
1443 {
1444         struct osd_state *osd = sd;
1445         struct osd_window_state *win = &osd->win[layer];
1446         unsigned long flags;
1447
1448         spin_lock_irqsave(&osd->lock, flags);
1449
1450         if (win->is_allocated) {
1451                 spin_unlock_irqrestore(&osd->lock, flags);
1452                 return -1;
1453         }
1454         win->is_allocated = 1;
1455
1456         spin_unlock_irqrestore(&osd->lock, flags);
1457
1458         return 0;
1459 }
1460
1461 static void _osd_init(struct osd_state *sd)
1462 {
1463         osd_write(sd, 0, OSD_MODE);
1464         osd_write(sd, 0, OSD_VIDWINMD);
1465         osd_write(sd, 0, OSD_OSDWIN0MD);
1466         osd_write(sd, 0, OSD_OSDWIN1MD);
1467         osd_write(sd, 0, OSD_RECTCUR);
1468         osd_write(sd, 0, OSD_MISCCTL);
1469         if (sd->vpbe_type == VPBE_VERSION_3) {
1470                 osd_write(sd, 0, OSD_VBNDRY);
1471                 osd_write(sd, 0, OSD_EXTMODE);
1472                 osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL);
1473         }
1474 }
1475
1476 static void osd_set_left_margin(struct osd_state *sd, u32 val)
1477 {
1478         osd_write(sd, val, OSD_BASEPX);
1479 }
1480
1481 static void osd_set_top_margin(struct osd_state *sd, u32 val)
1482 {
1483         osd_write(sd, val, OSD_BASEPY);
1484 }
1485
1486 static int osd_initialize(struct osd_state *osd)
1487 {
1488         if (osd == NULL)
1489                 return -ENODEV;
1490         _osd_init(osd);
1491
1492         /* set default Cb/Cr order */
1493         osd->yc_pixfmt = PIXFMT_YCbCrI;
1494
1495         if (osd->vpbe_type == VPBE_VERSION_3) {
1496                 /*
1497                  * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0
1498                  * on the DM6446, so make ROM_CLUT1 the default on the DM355.
1499                  */
1500                 osd->rom_clut = ROM_CLUT1;
1501         }
1502
1503         _osd_set_field_inversion(osd, osd->field_inversion);
1504         _osd_set_rom_clut(osd, osd->rom_clut);
1505
1506         osd_init_layer(osd, WIN_OSD0);
1507         osd_init_layer(osd, WIN_VID0);
1508         osd_init_layer(osd, WIN_OSD1);
1509         osd_init_layer(osd, WIN_VID1);
1510
1511         return 0;
1512 }
1513
1514 static const struct vpbe_osd_ops osd_ops = {
1515         .initialize = osd_initialize,
1516         .request_layer = osd_request_layer,
1517         .release_layer = osd_release_layer,
1518         .enable_layer = osd_enable_layer,
1519         .disable_layer = osd_disable_layer,
1520         .set_layer_config = osd_set_layer_config,
1521         .get_layer_config = osd_get_layer_config,
1522         .start_layer = osd_start_layer,
1523         .set_left_margin = osd_set_left_margin,
1524         .set_top_margin = osd_set_top_margin,
1525 };
1526
1527 static int osd_probe(struct platform_device *pdev)
1528 {
1529         struct osd_platform_data *pdata;
1530         struct osd_state *osd;
1531         struct resource *res;
1532         int ret = 0;
1533
1534         osd = kzalloc(sizeof(struct osd_state), GFP_KERNEL);
1535         if (osd == NULL)
1536                 return -ENOMEM;
1537
1538         osd->dev = &pdev->dev;
1539         pdata = (struct osd_platform_data *)pdev->dev.platform_data;
1540         osd->vpbe_type = (enum vpbe_version)pdata->vpbe_type;
1541         if (NULL == pdev->dev.platform_data) {
1542                 dev_err(osd->dev, "No platform data defined for OSD"
1543                         " sub device\n");
1544                 ret = -ENOENT;
1545                 goto free_mem;
1546         }
1547
1548         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549         if (!res) {
1550                 dev_err(osd->dev, "Unable to get OSD register address map\n");
1551                 ret = -ENODEV;
1552                 goto free_mem;
1553         }
1554         osd->osd_base_phys = res->start;
1555         osd->osd_size = resource_size(res);
1556         if (!request_mem_region(osd->osd_base_phys, osd->osd_size,
1557                                 MODULE_NAME)) {
1558                 dev_err(osd->dev, "Unable to reserve OSD MMIO region\n");
1559                 ret = -ENODEV;
1560                 goto free_mem;
1561         }
1562         osd->osd_base = (unsigned long)ioremap_nocache(res->start,
1563                                                         osd->osd_size);
1564         if (!osd->osd_base) {
1565                 dev_err(osd->dev, "Unable to map the OSD region\n");
1566                 ret = -ENODEV;
1567                 goto release_mem_region;
1568         }
1569         spin_lock_init(&osd->lock);
1570         osd->ops = osd_ops;
1571         platform_set_drvdata(pdev, osd);
1572         dev_notice(osd->dev, "OSD sub device probe success\n");
1573         return ret;
1574
1575 release_mem_region:
1576         release_mem_region(osd->osd_base_phys, osd->osd_size);
1577 free_mem:
1578         kfree(osd);
1579         return ret;
1580 }
1581
1582 static int osd_remove(struct platform_device *pdev)
1583 {
1584         struct osd_state *osd = platform_get_drvdata(pdev);
1585
1586         iounmap((void *)osd->osd_base);
1587         release_mem_region(osd->osd_base_phys, osd->osd_size);
1588         kfree(osd);
1589         return 0;
1590 }
1591
1592 static struct platform_driver osd_driver = {
1593         .probe          = osd_probe,
1594         .remove         = osd_remove,
1595         .driver         = {
1596                 .name   = MODULE_NAME,
1597                 .owner  = THIS_MODULE,
1598         },
1599 };
1600
1601 module_platform_driver(osd_driver);
1602
1603 MODULE_LICENSE("GPL");
1604 MODULE_DESCRIPTION("DaVinci OSD Manager Driver");
1605 MODULE_AUTHOR("Texas Instruments");