2 * vpif - Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiveing video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/spinlock.h>
24 #include <linux/kernel.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <mach/hardware.h>
32 MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
33 MODULE_LICENSE("GPL");
35 #define VPIF_CH0_MAX_MODES (22)
36 #define VPIF_CH1_MAX_MODES (02)
37 #define VPIF_CH2_MAX_MODES (15)
38 #define VPIF_CH3_MAX_MODES (02)
40 static resource_size_t res_len
;
41 static struct resource
*res
;
44 void __iomem
*vpif_base
;
48 * ch_params: video standard configuration parameters for vpif
49 * The table must include all presets from supported subdevices.
51 const struct vpif_channel_config_params ch_params
[] = {
68 .dv_preset
= V4L2_DV_480P59_94
,
85 .dv_preset
= V4L2_DV_576P50
,
102 .dv_preset
= V4L2_DV_720P50
,
119 .dv_preset
= V4L2_DV_720P60
,
139 .dv_preset
= V4L2_DV_1080I50
,
159 .dv_preset
= V4L2_DV_1080I60
,
176 .dv_preset
= V4L2_DV_1080P60
,
198 .stdid
= V4L2_STD_525_60
,
201 .name
= "PAL_BDGHIK",
218 .stdid
= V4L2_STD_625_50
,
222 const unsigned int vpif_ch_params_count
= ARRAY_SIZE(ch_params
);
224 static inline void vpif_wr_bit(u32 reg
, u32 bit
, u32 val
)
227 vpif_set_bit(reg
, bit
);
229 vpif_clr_bit(reg
, bit
);
232 /* This structure is used to keep track of VPIF size register's offsets */
233 struct vpif_registers
{
234 u32 h_cfg
, v_cfg_00
, v_cfg_01
, v_cfg_02
, v_cfg
, ch_ctrl
;
235 u32 line_offset
, vanc0_strt
, vanc0_size
, vanc1_strt
;
236 u32 vanc1_size
, width_mask
, len_mask
;
240 static const struct vpif_registers vpifregs
[VPIF_NUM_CHANNELS
] = {
243 VPIF_CH0_H_CFG
, VPIF_CH0_V_CFG_00
, VPIF_CH0_V_CFG_01
,
244 VPIF_CH0_V_CFG_02
, VPIF_CH0_V_CFG_03
, VPIF_CH0_CTRL
,
245 VPIF_CH0_IMG_ADD_OFST
, 0, 0, 0, 0, 0x1FFF, 0xFFF,
250 VPIF_CH1_H_CFG
, VPIF_CH1_V_CFG_00
, VPIF_CH1_V_CFG_01
,
251 VPIF_CH1_V_CFG_02
, VPIF_CH1_V_CFG_03
, VPIF_CH1_CTRL
,
252 VPIF_CH1_IMG_ADD_OFST
, 0, 0, 0, 0, 0x1FFF, 0xFFF,
257 VPIF_CH2_H_CFG
, VPIF_CH2_V_CFG_00
, VPIF_CH2_V_CFG_01
,
258 VPIF_CH2_V_CFG_02
, VPIF_CH2_V_CFG_03
, VPIF_CH2_CTRL
,
259 VPIF_CH2_IMG_ADD_OFST
, VPIF_CH2_VANC0_STRT
, VPIF_CH2_VANC0_SIZE
,
260 VPIF_CH2_VANC1_STRT
, VPIF_CH2_VANC1_SIZE
, 0x7FF, 0x7FF,
265 VPIF_CH3_H_CFG
, VPIF_CH3_V_CFG_00
, VPIF_CH3_V_CFG_01
,
266 VPIF_CH3_V_CFG_02
, VPIF_CH3_V_CFG_03
, VPIF_CH3_CTRL
,
267 VPIF_CH3_IMG_ADD_OFST
, VPIF_CH3_VANC0_STRT
, VPIF_CH3_VANC0_SIZE
,
268 VPIF_CH3_VANC1_STRT
, VPIF_CH3_VANC1_SIZE
, 0x7FF, 0x7FF,
273 /* vpif_set_mode_info:
274 * This function is used to set horizontal and vertical config parameters
275 * As per the standard in the channel, configure the values of L1, L3,
276 * L5, L7 L9, L11 in VPIF Register , also write width and height
278 static void vpif_set_mode_info(const struct vpif_channel_config_params
*config
,
279 u8 channel_id
, u8 config_channel_id
)
283 value
= (config
->eav2sav
& vpifregs
[config_channel_id
].width_mask
);
284 value
<<= VPIF_CH_LEN_SHIFT
;
285 value
|= (config
->sav2eav
& vpifregs
[config_channel_id
].width_mask
);
286 regw(value
, vpifregs
[channel_id
].h_cfg
);
288 value
= (config
->l1
& vpifregs
[config_channel_id
].len_mask
);
289 value
<<= VPIF_CH_LEN_SHIFT
;
290 value
|= (config
->l3
& vpifregs
[config_channel_id
].len_mask
);
291 regw(value
, vpifregs
[channel_id
].v_cfg_00
);
293 value
= (config
->l5
& vpifregs
[config_channel_id
].len_mask
);
294 value
<<= VPIF_CH_LEN_SHIFT
;
295 value
|= (config
->l7
& vpifregs
[config_channel_id
].len_mask
);
296 regw(value
, vpifregs
[channel_id
].v_cfg_01
);
298 value
= (config
->l9
& vpifregs
[config_channel_id
].len_mask
);
299 value
<<= VPIF_CH_LEN_SHIFT
;
300 value
|= (config
->l11
& vpifregs
[config_channel_id
].len_mask
);
301 regw(value
, vpifregs
[channel_id
].v_cfg_02
);
303 value
= (config
->vsize
& vpifregs
[config_channel_id
].len_mask
);
304 regw(value
, vpifregs
[channel_id
].v_cfg
);
307 /* config_vpif_params
308 * Function to set the parameters of a channel
309 * Mainly modifies the channel ciontrol register
310 * It sets frame format, yc mux mode
312 static void config_vpif_params(struct vpif_params
*vpifparams
,
313 u8 channel_id
, u8 found
)
315 const struct vpif_channel_config_params
*config
= &vpifparams
->std_info
;
316 u32 value
, ch_nip
, reg
;
321 end
= channel_id
+ found
;
323 for (i
= start
; i
< end
; i
++) {
324 reg
= vpifregs
[i
].ch_ctrl
;
326 ch_nip
= VPIF_CAPTURE_CH_NIP
;
328 ch_nip
= VPIF_DISPLAY_CH_NIP
;
330 vpif_wr_bit(reg
, ch_nip
, config
->frm_fmt
);
331 vpif_wr_bit(reg
, VPIF_CH_YC_MUX_BIT
, config
->ycmux_mode
);
332 vpif_wr_bit(reg
, VPIF_CH_INPUT_FIELD_FRAME_BIT
,
333 vpifparams
->video_params
.storage_mode
);
335 /* Set raster scanning SDR Format */
336 vpif_clr_bit(reg
, VPIF_CH_SDR_FMT_BIT
);
337 vpif_wr_bit(reg
, VPIF_CH_DATA_MODE_BIT
, config
->capture_format
);
339 if (channel_id
> 1) /* Set the Pixel enable bit */
340 vpif_set_bit(reg
, VPIF_DISPLAY_PIX_EN_BIT
);
341 else if (config
->capture_format
) {
342 /* Set the polarity of various pins */
343 vpif_wr_bit(reg
, VPIF_CH_FID_POLARITY_BIT
,
344 vpifparams
->iface
.fid_pol
);
345 vpif_wr_bit(reg
, VPIF_CH_V_VALID_POLARITY_BIT
,
346 vpifparams
->iface
.vd_pol
);
347 vpif_wr_bit(reg
, VPIF_CH_H_VALID_POLARITY_BIT
,
348 vpifparams
->iface
.hd_pol
);
353 VPIF_CH_DATA_WIDTH_BIT
);
354 value
|= ((vpifparams
->params
.data_sz
) <<
355 VPIF_CH_DATA_WIDTH_BIT
);
359 /* Write the pitch in the driver */
360 regw((vpifparams
->video_params
.hpitch
),
361 vpifregs
[i
].line_offset
);
365 /* vpif_set_video_params
366 * This function is used to set video parameters in VPIF register
368 int vpif_set_video_params(struct vpif_params
*vpifparams
, u8 channel_id
)
370 const struct vpif_channel_config_params
*config
= &vpifparams
->std_info
;
373 vpif_set_mode_info(config
, channel_id
, channel_id
);
374 if (!config
->ycmux_mode
) {
375 /* YC are on separate channels (HDTV formats) */
376 vpif_set_mode_info(config
, channel_id
+ 1, channel_id
);
380 config_vpif_params(vpifparams
, channel_id
, found
);
382 regw(0x80, VPIF_REQ_SIZE
);
383 regw(0x01, VPIF_EMULATION_CTRL
);
387 EXPORT_SYMBOL(vpif_set_video_params
);
389 void vpif_set_vbi_display_params(struct vpif_vbi_params
*vbiparams
,
394 value
= 0x3F8 & (vbiparams
->hstart0
);
395 value
|= 0x3FFFFFF & ((vbiparams
->vstart0
) << 16);
396 regw(value
, vpifregs
[channel_id
].vanc0_strt
);
398 value
= 0x3F8 & (vbiparams
->hstart1
);
399 value
|= 0x3FFFFFF & ((vbiparams
->vstart1
) << 16);
400 regw(value
, vpifregs
[channel_id
].vanc1_strt
);
402 value
= 0x3F8 & (vbiparams
->hsize0
);
403 value
|= 0x3FFFFFF & ((vbiparams
->vsize0
) << 16);
404 regw(value
, vpifregs
[channel_id
].vanc0_size
);
406 value
= 0x3F8 & (vbiparams
->hsize1
);
407 value
|= 0x3FFFFFF & ((vbiparams
->vsize1
) << 16);
408 regw(value
, vpifregs
[channel_id
].vanc1_size
);
411 EXPORT_SYMBOL(vpif_set_vbi_display_params
);
413 int vpif_channel_getfid(u8 channel_id
)
415 return (regr(vpifregs
[channel_id
].ch_ctrl
) & VPIF_CH_FID_MASK
)
416 >> VPIF_CH_FID_SHIFT
;
418 EXPORT_SYMBOL(vpif_channel_getfid
);
420 static int __init
vpif_probe(struct platform_device
*pdev
)
424 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
428 res_len
= resource_size(res
);
430 res
= request_mem_region(res
->start
, res_len
, res
->name
);
434 vpif_base
= ioremap(res
->start
, res_len
);
440 vpif_clk
= clk_get(&pdev
->dev
, "vpif");
441 if (IS_ERR(vpif_clk
)) {
442 status
= PTR_ERR(vpif_clk
);
445 clk_enable(vpif_clk
);
447 spin_lock_init(&vpif_lock
);
448 dev_info(&pdev
->dev
, "vpif probe success\n");
454 release_mem_region(res
->start
, res_len
);
458 static int __devexit
vpif_remove(struct platform_device
*pdev
)
461 clk_disable(vpif_clk
);
466 release_mem_region(res
->start
, res_len
);
471 static int vpif_suspend(struct device
*dev
)
473 clk_disable(vpif_clk
);
477 static int vpif_resume(struct device
*dev
)
479 clk_enable(vpif_clk
);
483 static const struct dev_pm_ops vpif_pm
= {
484 .suspend
= vpif_suspend
,
485 .resume
= vpif_resume
,
488 #define vpif_pm_ops (&vpif_pm)
490 #define vpif_pm_ops NULL
493 static struct platform_driver vpif_driver
= {
496 .owner
= THIS_MODULE
,
499 .remove
= __devexit_p(vpif_remove
),
503 static void vpif_exit(void)
505 platform_driver_unregister(&vpif_driver
);
508 static int __init
vpif_init(void)
510 return platform_driver_register(&vpif_driver
);
512 subsys_initcall(vpif_init
);
513 module_exit(vpif_exit
);