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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / mtd / nand / nand_base.c
blobc429abd00b87092c83a0c3bd21f70afeee99267a
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <linux/io.h>
50 #include <linux/mtd/partitions.h>
51
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61 };
62
63 static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69 };
70
71 static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80 };
81
82 static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94 };
95
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102 /*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106 DEFINE_LED_TRIGGER(nand_led_trigger);
107
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110 {
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
123 ret = -EINVAL;
124 }
125
126 return ret;
127 }
128
129 /**
130 * nand_release_device - [GENERIC] release chip
131 * @mtd: MTD device structure
132 *
133 * Deselect, release chip lock and wake up anyone waiting on the device.
134 */
135 static void nand_release_device(struct mtd_info *mtd)
136 {
137 struct nand_chip *chip = mtd->priv;
138
139 /* De-select the NAND device */
140 chip->select_chip(mtd, -1);
141
142 /* Release the controller and the chip */
143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
148 }
149
150 /**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
152 * @mtd: MTD device structure
153 *
154 * Default read function for 8bit buswidth
155 */
156 static uint8_t nand_read_byte(struct mtd_info *mtd)
157 {
158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
160 }
161
162 /**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
165 * @mtd: MTD device structure
166 *
167 * Default read function for 16bit buswidth with endianness conversion.
168 *
169 */
170 static uint8_t nand_read_byte16(struct mtd_info *mtd)
171 {
172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
174 }
175
176 /**
177 * nand_read_word - [DEFAULT] read one word from the chip
178 * @mtd: MTD device structure
179 *
180 * Default read function for 16bit buswidth without endianness conversion.
181 */
182 static u16 nand_read_word(struct mtd_info *mtd)
183 {
184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
186 }
187
188 /**
189 * nand_select_chip - [DEFAULT] control CE line
190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
192 *
193 * Default select function for 1 chip devices.
194 */
195 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
196 {
197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
200 case -1:
201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
202 break;
203 case 0:
204 break;
205
206 default:
207 BUG();
208 }
209 }
210
211 /**
212 * nand_write_buf - [DEFAULT] write buffer to chip
213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
216 *
217 * Default write function for 8bit buswidth.
218 */
219 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
220 {
221 int i;
222 struct nand_chip *chip = mtd->priv;
223
224 for (i = 0; i < len; i++)
225 writeb(buf[i], chip->IO_ADDR_W);
226 }
227
228 /**
229 * nand_read_buf - [DEFAULT] read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
233 *
234 * Default read function for 8bit buswidth.
235 */
236 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
237 {
238 int i;
239 struct nand_chip *chip = mtd->priv;
240
241 for (i = 0; i < len; i++)
242 buf[i] = readb(chip->IO_ADDR_R);
243 }
244
245 /**
246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
250 *
251 * Default verify function for 8bit buswidth.
252 */
253 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
254 {
255 int i;
256 struct nand_chip *chip = mtd->priv;
257
258 for (i = 0; i < len; i++)
259 if (buf[i] != readb(chip->IO_ADDR_R))
260 return -EFAULT;
261 return 0;
262 }
263
264 /**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
269 *
270 * Default write function for 16bit buswidth.
271 */
272 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
273 {
274 int i;
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
277 len >>= 1;
278
279 for (i = 0; i < len; i++)
280 writew(p[i], chip->IO_ADDR_W);
281
282 }
283
284 /**
285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
289 *
290 * Default read function for 16bit buswidth.
291 */
292 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
293 {
294 int i;
295 struct nand_chip *chip = mtd->priv;
296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
299 for (i = 0; i < len; i++)
300 p[i] = readw(chip->IO_ADDR_R);
301 }
302
303 /**
304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
308 *
309 * Default verify function for 16bit buswidth.
310 */
311 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
312 {
313 int i;
314 struct nand_chip *chip = mtd->priv;
315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
318 for (i = 0; i < len; i++)
319 if (p[i] != readw(chip->IO_ADDR_R))
320 return -EFAULT;
321
322 return 0;
323 }
324
325 /**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
330 *
331 * Check, if the block is bad.
332 */
333 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334 {
335 int page, chipnr, res = 0, i = 0;
336 struct nand_chip *chip = mtd->priv;
337 u16 bad;
338
339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
340 ofs += mtd->erasesize - mtd->writesize;
341
342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
344 if (getchip) {
345 chipnr = (int)(ofs >> chip->chip_shift);
346
347 nand_get_device(chip, mtd, FL_READING);
348
349 /* Select the NAND device */
350 chip->select_chip(mtd, chipnr);
351 }
352
353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
370 else
371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
376
377 if (getchip)
378 nand_release_device(mtd);
379
380 return res;
381 }
382
383 /**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
385 * @mtd: MTD device structure
386 * @ofs: offset from device start
387 *
388 * This is the default implementation, which can be overridden by a hardware
389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
397 */
398 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399 {
400 struct nand_chip *chip = mtd->priv;
401 uint8_t buf[2] = { 0, 0 };
402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
404
405 if (write_oob) {
406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
416 /* Get block number */
417 block = (int)(ofs >> chip->bbt_erase_shift);
418 /* Mark block bad in memory-based BBT */
419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
421
422 /* Write bad block marker to OOB */
423 if (write_oob) {
424 struct mtd_oob_ops ops;
425 loff_t wr_ofs = ofs;
426
427 nand_get_device(chip, mtd, FL_WRITING);
428
429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
438 ops.mode = MTD_OPS_PLACE_OOB;
439
440 /* Write to first/last page(s) if necessary */
441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
443 do {
444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
447
448 i++;
449 wr_ofs += mtd->writesize;
450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
451
452 nand_release_device(mtd);
453 }
454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
462 if (!ret)
463 mtd->ecc_stats.badblocks++;
464
465 return ret;
466 }
467
468 /**
469 * nand_check_wp - [GENERIC] check if the chip is write protected
470 * @mtd: MTD device structure
471 *
472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
474 */
475 static int nand_check_wp(struct mtd_info *mtd)
476 {
477 struct nand_chip *chip = mtd->priv;
478
479 /* Broken xD cards report WP despite being writable */
480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
483 /* Check the WP bit */
484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
486 }
487
488 /**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
498 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
500 {
501 struct nand_chip *chip = mtd->priv;
502
503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
505
506 /* Return info from the table */
507 return nand_isbad_bbt(mtd, ofs, allowbbt);
508 }
509
510 /**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
512 * @mtd: MTD device structure
513 * @timeo: Timeout
514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519 {
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530 }
531
532 /* Wait for the ready pin, after a command. The timeout is caught later. */
533 void nand_wait_ready(struct mtd_info *mtd)
534 {
535 struct nand_chip *chip = mtd->priv;
536 unsigned long timeo = jiffies + 2;
537
538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
542 led_trigger_event(nand_led_trigger, LED_FULL);
543 /* Wait until command is processed or timeout occurs */
544 do {
545 if (chip->dev_ready(mtd))
546 break;
547 touch_softlockup_watchdog();
548 } while (time_before(jiffies, timeo));
549 led_trigger_event(nand_led_trigger, LED_OFF);
550 }
551 EXPORT_SYMBOL_GPL(nand_wait_ready);
552
553 /**
554 * nand_command - [DEFAULT] Send command to NAND device
555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
559 *
560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
562 */
563 static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
565 {
566 register struct nand_chip *chip = mtd->priv;
567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
568
569 /* Write out the command to the device */
570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
573 if (column >= mtd->writesize) {
574 /* OOB area */
575 column -= mtd->writesize;
576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
584 chip->cmd_ctrl(mtd, readcmd, ctrl);
585 ctrl &= ~NAND_CTRL_CHANGE;
586 }
587 chip->cmd_ctrl(mtd, command, ctrl);
588
589 /* Address cycle, when necessary */
590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
594 if (chip->options & NAND_BUSWIDTH_16)
595 column >>= 1;
596 chip->cmd_ctrl(mtd, column, ctrl);
597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
600 chip->cmd_ctrl(mtd, page_addr, ctrl);
601 ctrl &= ~NAND_CTRL_CHANGE;
602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
603 /* One more address cycle for devices > 32MiB */
604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
606 }
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
608
609 /*
610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
612 */
613 switch (command) {
614
615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
623 if (chip->dev_ready)
624 break;
625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
632 return;
633
634 /* This applies to read commands */
635 default:
636 /*
637 * If we don't have access to the busy pin, we apply the given
638 * command delay
639 */
640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
642 return;
643 }
644 }
645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
649 ndelay(100);
650
651 nand_wait_ready(mtd);
652 }
653
654 /**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
660 *
661 * Send command to NAND device. This is the version for the new large page
662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
664 */
665 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
667 {
668 register struct nand_chip *chip = mtd->priv;
669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
672 column += mtd->writesize;
673 command = NAND_CMD_READ0;
674 }
675
676 /* Command latch cycle */
677 chip->cmd_ctrl(mtd, command & 0xff,
678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
679
680 if (column != -1 || page_addr != -1) {
681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
686 if (chip->options & NAND_BUSWIDTH_16)
687 column >>= 1;
688 chip->cmd_ctrl(mtd, column, ctrl);
689 ctrl &= ~NAND_CTRL_CHANGE;
690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
691 }
692 if (page_addr != -1) {
693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
695 NAND_NCE | NAND_ALE);
696 /* One more address cycle for devices > 128MiB */
697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
699 NAND_NCE | NAND_ALE);
700 }
701 }
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
703
704 /*
705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
707 */
708 switch (command) {
709
710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
715 case NAND_CMD_RNDIN:
716 case NAND_CMD_STATUS:
717 case NAND_CMD_DEPLETE1:
718 return;
719
720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
725 /* Read error status commands require only a short delay */
726 udelay(chip->chip_delay);
727 return;
728
729 case NAND_CMD_RESET:
730 if (chip->dev_ready)
731 break;
732 udelay(chip->chip_delay);
733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
739 return;
740
741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
749 case NAND_CMD_READ0:
750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
754
755 /* This applies to read commands */
756 default:
757 /*
758 * If we don't have access to the busy pin, we apply the given
759 * command delay.
760 */
761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
763 return;
764 }
765 }
766
767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
771 ndelay(100);
772
773 nand_wait_ready(mtd);
774 }
775
776 /**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
781 *
782 * Used when in panic, no locks are taken.
783 */
784 static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786 {
787 /* Hardware controller shared among independent devices */
788 chip->controller->active = chip;
789 chip->state = new_state;
790 }
791
792 /**
793 * nand_get_device - [GENERIC] Get chip for selected access
794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
797 *
798 * Get the device and lock it for exclusive access
799 */
800 static int
801 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
802 {
803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
805 DECLARE_WAITQUEUE(wait, current);
806 retry:
807 spin_lock(lock);
808
809 /* Hardware controller shared among independent devices */
810 if (!chip->controller->active)
811 chip->controller->active = chip;
812
813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
815 spin_unlock(lock);
816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
823 }
824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
830 goto retry;
831 }
832
833 /**
834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
841 * an oops through mtdoops.
842 */
843 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845 {
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
856 }
857 }
858
859 /**
860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
863 *
864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
867 */
868 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
869 {
870
871 unsigned long timeo = jiffies;
872 int status, state = chip->state;
873
874 if (state == FL_ERASING)
875 timeo += (HZ * 400) / 1000;
876 else
877 timeo += (HZ * 20) / 1000;
878
879 led_trigger_event(nand_led_trigger, LED_FULL);
880
881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
885 ndelay(100);
886
887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
889 else
890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
891
892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
904 }
905 }
906 led_trigger_event(nand_led_trigger, LED_OFF);
907
908 status = (int)chip->read_byte(mtd);
909 return status;
910 }
911
912 /**
913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
921 *
922 * Returs unlock status.
923 */
924 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926 {
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
944 pr_debug("%s: error status = 0x%08x\n",
945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950 }
951
952 /**
953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
957 *
958 * Returns unlock status.
959 */
960 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961 {
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
985 pr_debug("%s: device is write protected!\n",
986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993 out:
994 nand_release_device(mtd);
995
996 return ret;
997 }
998 EXPORT_SYMBOL(nand_unlock);
999
1000 /**
1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
1005 *
1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
1010 *
1011 * Returns lock status.
1012 */
1013 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014 {
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
1034 pr_debug("%s: device is write protected!\n",
1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
1049 pr_debug("%s: error status = 0x%08x\n",
1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057 out:
1058 nand_release_device(mtd);
1059
1060 return ret;
1061 }
1062 EXPORT_SYMBOL(nand_lock);
1063
1064 /**
1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1069 * @oob_required: caller requires OOB data read to chip->oob_poi
1070 * @page: page number to read
1071 *
1072 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1073 */
1074 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1075 uint8_t *buf, int oob_required, int page)
1076 {
1077 chip->read_buf(mtd, buf, mtd->writesize);
1078 if (oob_required)
1079 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1080 return 0;
1081 }
1082
1083 /**
1084 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1085 * @mtd: mtd info structure
1086 * @chip: nand chip info structure
1087 * @buf: buffer to store read data
1088 * @oob_required: caller requires OOB data read to chip->oob_poi
1089 * @page: page number to read
1090 *
1091 * We need a special oob layout and handling even when OOB isn't used.
1092 */
1093 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1094 struct nand_chip *chip, uint8_t *buf,
1095 int oob_required, int page)
1096 {
1097 int eccsize = chip->ecc.size;
1098 int eccbytes = chip->ecc.bytes;
1099 uint8_t *oob = chip->oob_poi;
1100 int steps, size;
1101
1102 for (steps = chip->ecc.steps; steps > 0; steps--) {
1103 chip->read_buf(mtd, buf, eccsize);
1104 buf += eccsize;
1105
1106 if (chip->ecc.prepad) {
1107 chip->read_buf(mtd, oob, chip->ecc.prepad);
1108 oob += chip->ecc.prepad;
1109 }
1110
1111 chip->read_buf(mtd, oob, eccbytes);
1112 oob += eccbytes;
1113
1114 if (chip->ecc.postpad) {
1115 chip->read_buf(mtd, oob, chip->ecc.postpad);
1116 oob += chip->ecc.postpad;
1117 }
1118 }
1119
1120 size = mtd->oobsize - (oob - chip->oob_poi);
1121 if (size)
1122 chip->read_buf(mtd, oob, size);
1123
1124 return 0;
1125 }
1126
1127 /**
1128 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1129 * @mtd: mtd info structure
1130 * @chip: nand chip info structure
1131 * @buf: buffer to store read data
1132 * @oob_required: caller requires OOB data read to chip->oob_poi
1133 * @page: page number to read
1134 */
1135 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1136 uint8_t *buf, int oob_required, int page)
1137 {
1138 int i, eccsize = chip->ecc.size;
1139 int eccbytes = chip->ecc.bytes;
1140 int eccsteps = chip->ecc.steps;
1141 uint8_t *p = buf;
1142 uint8_t *ecc_calc = chip->buffers->ecccalc;
1143 uint8_t *ecc_code = chip->buffers->ecccode;
1144 uint32_t *eccpos = chip->ecc.layout->eccpos;
1145 unsigned int max_bitflips = 0;
1146
1147 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1148
1149 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1150 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1151
1152 for (i = 0; i < chip->ecc.total; i++)
1153 ecc_code[i] = chip->oob_poi[eccpos[i]];
1154
1155 eccsteps = chip->ecc.steps;
1156 p = buf;
1157
1158 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1159 int stat;
1160
1161 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1162 if (stat < 0) {
1163 mtd->ecc_stats.failed++;
1164 } else {
1165 mtd->ecc_stats.corrected += stat;
1166 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1167 }
1168 }
1169 return max_bitflips;
1170 }
1171
1172 /**
1173 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1174 * @mtd: mtd info structure
1175 * @chip: nand chip info structure
1176 * @data_offs: offset of requested data within the page
1177 * @readlen: data length
1178 * @bufpoi: buffer to store read data
1179 */
1180 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1181 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1182 {
1183 int start_step, end_step, num_steps;
1184 uint32_t *eccpos = chip->ecc.layout->eccpos;
1185 uint8_t *p;
1186 int data_col_addr, i, gaps = 0;
1187 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1188 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1189 int index = 0;
1190 unsigned int max_bitflips = 0;
1191
1192 /* Column address within the page aligned to ECC size (256bytes) */
1193 start_step = data_offs / chip->ecc.size;
1194 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1195 num_steps = end_step - start_step + 1;
1196
1197 /* Data size aligned to ECC ecc.size */
1198 datafrag_len = num_steps * chip->ecc.size;
1199 eccfrag_len = num_steps * chip->ecc.bytes;
1200
1201 data_col_addr = start_step * chip->ecc.size;
1202 /* If we read not a page aligned data */
1203 if (data_col_addr != 0)
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1205
1206 p = bufpoi + data_col_addr;
1207 chip->read_buf(mtd, p, datafrag_len);
1208
1209 /* Calculate ECC */
1210 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1211 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1212
1213 /*
1214 * The performance is faster if we position offsets according to
1215 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1216 */
1217 for (i = 0; i < eccfrag_len - 1; i++) {
1218 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1219 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1220 gaps = 1;
1221 break;
1222 }
1223 }
1224 if (gaps) {
1225 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1226 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1227 } else {
1228 /*
1229 * Send the command to read the particular ECC bytes take care
1230 * about buswidth alignment in read_buf.
1231 */
1232 index = start_step * chip->ecc.bytes;
1233
1234 aligned_pos = eccpos[index] & ~(busw - 1);
1235 aligned_len = eccfrag_len;
1236 if (eccpos[index] & (busw - 1))
1237 aligned_len++;
1238 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1239 aligned_len++;
1240
1241 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1242 mtd->writesize + aligned_pos, -1);
1243 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1244 }
1245
1246 for (i = 0; i < eccfrag_len; i++)
1247 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1248
1249 p = bufpoi + data_col_addr;
1250 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1251 int stat;
1252
1253 stat = chip->ecc.correct(mtd, p,
1254 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1255 if (stat < 0) {
1256 mtd->ecc_stats.failed++;
1257 } else {
1258 mtd->ecc_stats.corrected += stat;
1259 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1260 }
1261 }
1262 return max_bitflips;
1263 }
1264
1265 /**
1266 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1267 * @mtd: mtd info structure
1268 * @chip: nand chip info structure
1269 * @buf: buffer to store read data
1270 * @oob_required: caller requires OOB data read to chip->oob_poi
1271 * @page: page number to read
1272 *
1273 * Not for syndrome calculating ECC controllers which need a special oob layout.
1274 */
1275 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1276 uint8_t *buf, int oob_required, int page)
1277 {
1278 int i, eccsize = chip->ecc.size;
1279 int eccbytes = chip->ecc.bytes;
1280 int eccsteps = chip->ecc.steps;
1281 uint8_t *p = buf;
1282 uint8_t *ecc_calc = chip->buffers->ecccalc;
1283 uint8_t *ecc_code = chip->buffers->ecccode;
1284 uint32_t *eccpos = chip->ecc.layout->eccpos;
1285 unsigned int max_bitflips = 0;
1286
1287 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1291 }
1292 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1293
1294 for (i = 0; i < chip->ecc.total; i++)
1295 ecc_code[i] = chip->oob_poi[eccpos[i]];
1296
1297 eccsteps = chip->ecc.steps;
1298 p = buf;
1299
1300 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1301 int stat;
1302
1303 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1304 if (stat < 0) {
1305 mtd->ecc_stats.failed++;
1306 } else {
1307 mtd->ecc_stats.corrected += stat;
1308 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1309 }
1310 }
1311 return max_bitflips;
1312 }
1313
1314 /**
1315 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @buf: buffer to store read data
1319 * @oob_required: caller requires OOB data read to chip->oob_poi
1320 * @page: page number to read
1321 *
1322 * Hardware ECC for large page chips, require OOB to be read first. For this
1323 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1324 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1325 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1326 * the data area, by overwriting the NAND manufacturer bad block markings.
1327 */
1328 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1329 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1330 {
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
1335 uint8_t *ecc_code = chip->buffers->ecccode;
1336 uint32_t *eccpos = chip->ecc.layout->eccpos;
1337 uint8_t *ecc_calc = chip->buffers->ecccalc;
1338 unsigned int max_bitflips = 0;
1339
1340 /* Read the OOB area first */
1341 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1342 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1343 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1344
1345 for (i = 0; i < chip->ecc.total; i++)
1346 ecc_code[i] = chip->oob_poi[eccpos[i]];
1347
1348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1349 int stat;
1350
1351 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352 chip->read_buf(mtd, p, eccsize);
1353 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1354
1355 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1356 if (stat < 0) {
1357 mtd->ecc_stats.failed++;
1358 } else {
1359 mtd->ecc_stats.corrected += stat;
1360 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1361 }
1362 }
1363 return max_bitflips;
1364 }
1365
1366 /**
1367 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @buf: buffer to store read data
1371 * @oob_required: caller requires OOB data read to chip->oob_poi
1372 * @page: page number to read
1373 *
1374 * The hw generator calculates the error syndrome automatically. Therefore we
1375 * need a special oob layout and handling.
1376 */
1377 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1378 uint8_t *buf, int oob_required, int page)
1379 {
1380 int i, eccsize = chip->ecc.size;
1381 int eccbytes = chip->ecc.bytes;
1382 int eccsteps = chip->ecc.steps;
1383 uint8_t *p = buf;
1384 uint8_t *oob = chip->oob_poi;
1385 unsigned int max_bitflips = 0;
1386
1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1388 int stat;
1389
1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1392
1393 if (chip->ecc.prepad) {
1394 chip->read_buf(mtd, oob, chip->ecc.prepad);
1395 oob += chip->ecc.prepad;
1396 }
1397
1398 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1399 chip->read_buf(mtd, oob, eccbytes);
1400 stat = chip->ecc.correct(mtd, p, oob, NULL);
1401
1402 if (stat < 0) {
1403 mtd->ecc_stats.failed++;
1404 } else {
1405 mtd->ecc_stats.corrected += stat;
1406 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1407 }
1408
1409 oob += eccbytes;
1410
1411 if (chip->ecc.postpad) {
1412 chip->read_buf(mtd, oob, chip->ecc.postpad);
1413 oob += chip->ecc.postpad;
1414 }
1415 }
1416
1417 /* Calculate remaining oob bytes */
1418 i = mtd->oobsize - (oob - chip->oob_poi);
1419 if (i)
1420 chip->read_buf(mtd, oob, i);
1421
1422 return max_bitflips;
1423 }
1424
1425 /**
1426 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1427 * @chip: nand chip structure
1428 * @oob: oob destination address
1429 * @ops: oob ops structure
1430 * @len: size of oob to transfer
1431 */
1432 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1433 struct mtd_oob_ops *ops, size_t len)
1434 {
1435 switch (ops->mode) {
1436
1437 case MTD_OPS_PLACE_OOB:
1438 case MTD_OPS_RAW:
1439 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1440 return oob + len;
1441
1442 case MTD_OPS_AUTO_OOB: {
1443 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1444 uint32_t boffs = 0, roffs = ops->ooboffs;
1445 size_t bytes = 0;
1446
1447 for (; free->length && len; free++, len -= bytes) {
1448 /* Read request not from offset 0? */
1449 if (unlikely(roffs)) {
1450 if (roffs >= free->length) {
1451 roffs -= free->length;
1452 continue;
1453 }
1454 boffs = free->offset + roffs;
1455 bytes = min_t(size_t, len,
1456 (free->length - roffs));
1457 roffs = 0;
1458 } else {
1459 bytes = min_t(size_t, len, free->length);
1460 boffs = free->offset;
1461 }
1462 memcpy(oob, chip->oob_poi + boffs, bytes);
1463 oob += bytes;
1464 }
1465 return oob;
1466 }
1467 default:
1468 BUG();
1469 }
1470 return NULL;
1471 }
1472
1473 /**
1474 * nand_do_read_ops - [INTERN] Read data with ECC
1475 * @mtd: MTD device structure
1476 * @from: offset to read from
1477 * @ops: oob ops structure
1478 *
1479 * Internal function. Called with chip held.
1480 */
1481 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1482 struct mtd_oob_ops *ops)
1483 {
1484 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1485 struct nand_chip *chip = mtd->priv;
1486 struct mtd_ecc_stats stats;
1487 int ret = 0;
1488 uint32_t readlen = ops->len;
1489 uint32_t oobreadlen = ops->ooblen;
1490 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1491 mtd->oobavail : mtd->oobsize;
1492
1493 uint8_t *bufpoi, *oob, *buf;
1494 unsigned int max_bitflips = 0;
1495
1496 stats = mtd->ecc_stats;
1497
1498 chipnr = (int)(from >> chip->chip_shift);
1499 chip->select_chip(mtd, chipnr);
1500
1501 realpage = (int)(from >> chip->page_shift);
1502 page = realpage & chip->pagemask;
1503
1504 col = (int)(from & (mtd->writesize - 1));
1505
1506 buf = ops->datbuf;
1507 oob = ops->oobbuf;
1508 oob_required = oob ? 1 : 0;
1509
1510 while (1) {
1511 bytes = min(mtd->writesize - col, readlen);
1512 aligned = (bytes == mtd->writesize);
1513
1514 /* Is the current page in the buffer? */
1515 if (realpage != chip->pagebuf || oob) {
1516 bufpoi = aligned ? buf : chip->buffers->databuf;
1517
1518 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1519
1520 /*
1521 * Now read the page into the buffer. Absent an error,
1522 * the read methods return max bitflips per ecc step.
1523 */
1524 if (unlikely(ops->mode == MTD_OPS_RAW))
1525 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1526 oob_required,
1527 page);
1528 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1529 ret = chip->ecc.read_subpage(mtd, chip,
1530 col, bytes, bufpoi);
1531 else
1532 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1533 oob_required, page);
1534 if (ret < 0) {
1535 if (!aligned)
1536 /* Invalidate page cache */
1537 chip->pagebuf = -1;
1538 break;
1539 }
1540
1541 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1542
1543 /* Transfer not aligned data */
1544 if (!aligned) {
1545 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1546 !(mtd->ecc_stats.failed - stats.failed) &&
1547 (ops->mode != MTD_OPS_RAW)) {
1548 chip->pagebuf = realpage;
1549 chip->pagebuf_bitflips = ret;
1550 } else {
1551 /* Invalidate page cache */
1552 chip->pagebuf = -1;
1553 }
1554 memcpy(buf, chip->buffers->databuf + col, bytes);
1555 }
1556
1557 buf += bytes;
1558
1559 if (unlikely(oob)) {
1560 int toread = min(oobreadlen, max_oobsize);
1561
1562 if (toread) {
1563 oob = nand_transfer_oob(chip,
1564 oob, ops, toread);
1565 oobreadlen -= toread;
1566 }
1567 }
1568
1569 if (!(chip->options & NAND_NO_READRDY)) {
1570 /* Apply delay or wait for ready/busy pin */
1571 if (!chip->dev_ready)
1572 udelay(chip->chip_delay);
1573 else
1574 nand_wait_ready(mtd);
1575 }
1576 } else {
1577 memcpy(buf, chip->buffers->databuf + col, bytes);
1578 buf += bytes;
1579 max_bitflips = max_t(unsigned int, max_bitflips,
1580 chip->pagebuf_bitflips);
1581 }
1582
1583 readlen -= bytes;
1584
1585 if (!readlen)
1586 break;
1587
1588 /* For subsequent reads align to page boundary */
1589 col = 0;
1590 /* Increment page address */
1591 realpage++;
1592
1593 page = realpage & chip->pagemask;
1594 /* Check, if we cross a chip boundary */
1595 if (!page) {
1596 chipnr++;
1597 chip->select_chip(mtd, -1);
1598 chip->select_chip(mtd, chipnr);
1599 }
1600 }
1601
1602 ops->retlen = ops->len - (size_t) readlen;
1603 if (oob)
1604 ops->oobretlen = ops->ooblen - oobreadlen;
1605
1606 if (ret < 0)
1607 return ret;
1608
1609 if (mtd->ecc_stats.failed - stats.failed)
1610 return -EBADMSG;
1611
1612 return max_bitflips;
1613 }
1614
1615 /**
1616 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1617 * @mtd: MTD device structure
1618 * @from: offset to read from
1619 * @len: number of bytes to read
1620 * @retlen: pointer to variable to store the number of read bytes
1621 * @buf: the databuffer to put data
1622 *
1623 * Get hold of the chip and call nand_do_read.
1624 */
1625 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1626 size_t *retlen, uint8_t *buf)
1627 {
1628 struct nand_chip *chip = mtd->priv;
1629 struct mtd_oob_ops ops;
1630 int ret;
1631
1632 nand_get_device(chip, mtd, FL_READING);
1633 ops.len = len;
1634 ops.datbuf = buf;
1635 ops.oobbuf = NULL;
1636 ops.mode = 0;
1637 ret = nand_do_read_ops(mtd, from, &ops);
1638 *retlen = ops.retlen;
1639 nand_release_device(mtd);
1640 return ret;
1641 }
1642
1643 /**
1644 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1645 * @mtd: mtd info structure
1646 * @chip: nand chip info structure
1647 * @page: page number to read
1648 */
1649 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1650 int page)
1651 {
1652 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1653 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1654 return 0;
1655 }
1656
1657 /**
1658 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1659 * with syndromes
1660 * @mtd: mtd info structure
1661 * @chip: nand chip info structure
1662 * @page: page number to read
1663 */
1664 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1665 int page)
1666 {
1667 uint8_t *buf = chip->oob_poi;
1668 int length = mtd->oobsize;
1669 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1670 int eccsize = chip->ecc.size;
1671 uint8_t *bufpoi = buf;
1672 int i, toread, sndrnd = 0, pos;
1673
1674 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1675 for (i = 0; i < chip->ecc.steps; i++) {
1676 if (sndrnd) {
1677 pos = eccsize + i * (eccsize + chunk);
1678 if (mtd->writesize > 512)
1679 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1680 else
1681 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1682 } else
1683 sndrnd = 1;
1684 toread = min_t(int, length, chunk);
1685 chip->read_buf(mtd, bufpoi, toread);
1686 bufpoi += toread;
1687 length -= toread;
1688 }
1689 if (length > 0)
1690 chip->read_buf(mtd, bufpoi, length);
1691
1692 return 0;
1693 }
1694
1695 /**
1696 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1697 * @mtd: mtd info structure
1698 * @chip: nand chip info structure
1699 * @page: page number to write
1700 */
1701 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1702 int page)
1703 {
1704 int status = 0;
1705 const uint8_t *buf = chip->oob_poi;
1706 int length = mtd->oobsize;
1707
1708 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1709 chip->write_buf(mtd, buf, length);
1710 /* Send command to program the OOB data */
1711 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1712
1713 status = chip->waitfunc(mtd, chip);
1714
1715 return status & NAND_STATUS_FAIL ? -EIO : 0;
1716 }
1717
1718 /**
1719 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1720 * with syndrome - only for large page flash
1721 * @mtd: mtd info structure
1722 * @chip: nand chip info structure
1723 * @page: page number to write
1724 */
1725 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1726 struct nand_chip *chip, int page)
1727 {
1728 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1729 int eccsize = chip->ecc.size, length = mtd->oobsize;
1730 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1731 const uint8_t *bufpoi = chip->oob_poi;
1732
1733 /*
1734 * data-ecc-data-ecc ... ecc-oob
1735 * or
1736 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1737 */
1738 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1739 pos = steps * (eccsize + chunk);
1740 steps = 0;
1741 } else
1742 pos = eccsize;
1743
1744 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1745 for (i = 0; i < steps; i++) {
1746 if (sndcmd) {
1747 if (mtd->writesize <= 512) {
1748 uint32_t fill = 0xFFFFFFFF;
1749
1750 len = eccsize;
1751 while (len > 0) {
1752 int num = min_t(int, len, 4);
1753 chip->write_buf(mtd, (uint8_t *)&fill,
1754 num);
1755 len -= num;
1756 }
1757 } else {
1758 pos = eccsize + i * (eccsize + chunk);
1759 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1760 }
1761 } else
1762 sndcmd = 1;
1763 len = min_t(int, length, chunk);
1764 chip->write_buf(mtd, bufpoi, len);
1765 bufpoi += len;
1766 length -= len;
1767 }
1768 if (length > 0)
1769 chip->write_buf(mtd, bufpoi, length);
1770
1771 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1772 status = chip->waitfunc(mtd, chip);
1773
1774 return status & NAND_STATUS_FAIL ? -EIO : 0;
1775 }
1776
1777 /**
1778 * nand_do_read_oob - [INTERN] NAND read out-of-band
1779 * @mtd: MTD device structure
1780 * @from: offset to read from
1781 * @ops: oob operations description structure
1782 *
1783 * NAND read out-of-band data from the spare area.
1784 */
1785 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1786 struct mtd_oob_ops *ops)
1787 {
1788 int page, realpage, chipnr;
1789 struct nand_chip *chip = mtd->priv;
1790 struct mtd_ecc_stats stats;
1791 int readlen = ops->ooblen;
1792 int len;
1793 uint8_t *buf = ops->oobbuf;
1794 int ret = 0;
1795
1796 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1797 __func__, (unsigned long long)from, readlen);
1798
1799 stats = mtd->ecc_stats;
1800
1801 if (ops->mode == MTD_OPS_AUTO_OOB)
1802 len = chip->ecc.layout->oobavail;
1803 else
1804 len = mtd->oobsize;
1805
1806 if (unlikely(ops->ooboffs >= len)) {
1807 pr_debug("%s: attempt to start read outside oob\n",
1808 __func__);
1809 return -EINVAL;
1810 }
1811
1812 /* Do not allow reads past end of device */
1813 if (unlikely(from >= mtd->size ||
1814 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1815 (from >> chip->page_shift)) * len)) {
1816 pr_debug("%s: attempt to read beyond end of device\n",
1817 __func__);
1818 return -EINVAL;
1819 }
1820
1821 chipnr = (int)(from >> chip->chip_shift);
1822 chip->select_chip(mtd, chipnr);
1823
1824 /* Shift to get page */
1825 realpage = (int)(from >> chip->page_shift);
1826 page = realpage & chip->pagemask;
1827
1828 while (1) {
1829 if (ops->mode == MTD_OPS_RAW)
1830 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1831 else
1832 ret = chip->ecc.read_oob(mtd, chip, page);
1833
1834 if (ret < 0)
1835 break;
1836
1837 len = min(len, readlen);
1838 buf = nand_transfer_oob(chip, buf, ops, len);
1839
1840 if (!(chip->options & NAND_NO_READRDY)) {
1841 /* Apply delay or wait for ready/busy pin */
1842 if (!chip->dev_ready)
1843 udelay(chip->chip_delay);
1844 else
1845 nand_wait_ready(mtd);
1846 }
1847
1848 readlen -= len;
1849 if (!readlen)
1850 break;
1851
1852 /* Increment page address */
1853 realpage++;
1854
1855 page = realpage & chip->pagemask;
1856 /* Check, if we cross a chip boundary */
1857 if (!page) {
1858 chipnr++;
1859 chip->select_chip(mtd, -1);
1860 chip->select_chip(mtd, chipnr);
1861 }
1862 }
1863
1864 ops->oobretlen = ops->ooblen - readlen;
1865
1866 if (ret < 0)
1867 return ret;
1868
1869 if (mtd->ecc_stats.failed - stats.failed)
1870 return -EBADMSG;
1871
1872 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1873 }
1874
1875 /**
1876 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1877 * @mtd: MTD device structure
1878 * @from: offset to read from
1879 * @ops: oob operation description structure
1880 *
1881 * NAND read data and/or out-of-band data.
1882 */
1883 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1884 struct mtd_oob_ops *ops)
1885 {
1886 struct nand_chip *chip = mtd->priv;
1887 int ret = -ENOTSUPP;
1888
1889 ops->retlen = 0;
1890
1891 /* Do not allow reads past end of device */
1892 if (ops->datbuf && (from + ops->len) > mtd->size) {
1893 pr_debug("%s: attempt to read beyond end of device\n",
1894 __func__);
1895 return -EINVAL;
1896 }
1897
1898 nand_get_device(chip, mtd, FL_READING);
1899
1900 switch (ops->mode) {
1901 case MTD_OPS_PLACE_OOB:
1902 case MTD_OPS_AUTO_OOB:
1903 case MTD_OPS_RAW:
1904 break;
1905
1906 default:
1907 goto out;
1908 }
1909
1910 if (!ops->datbuf)
1911 ret = nand_do_read_oob(mtd, from, ops);
1912 else
1913 ret = nand_do_read_ops(mtd, from, ops);
1914
1915 out:
1916 nand_release_device(mtd);
1917 return ret;
1918 }
1919
1920
1921 /**
1922 * nand_write_page_raw - [INTERN] raw page write function
1923 * @mtd: mtd info structure
1924 * @chip: nand chip info structure
1925 * @buf: data buffer
1926 * @oob_required: must write chip->oob_poi to OOB
1927 *
1928 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1929 */
1930 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1931 const uint8_t *buf, int oob_required)
1932 {
1933 chip->write_buf(mtd, buf, mtd->writesize);
1934 if (oob_required)
1935 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1936 }
1937
1938 /**
1939 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1940 * @mtd: mtd info structure
1941 * @chip: nand chip info structure
1942 * @buf: data buffer
1943 * @oob_required: must write chip->oob_poi to OOB
1944 *
1945 * We need a special oob layout and handling even when ECC isn't checked.
1946 */
1947 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1948 struct nand_chip *chip,
1949 const uint8_t *buf, int oob_required)
1950 {
1951 int eccsize = chip->ecc.size;
1952 int eccbytes = chip->ecc.bytes;
1953 uint8_t *oob = chip->oob_poi;
1954 int steps, size;
1955
1956 for (steps = chip->ecc.steps; steps > 0; steps--) {
1957 chip->write_buf(mtd, buf, eccsize);
1958 buf += eccsize;
1959
1960 if (chip->ecc.prepad) {
1961 chip->write_buf(mtd, oob, chip->ecc.prepad);
1962 oob += chip->ecc.prepad;
1963 }
1964
1965 chip->read_buf(mtd, oob, eccbytes);
1966 oob += eccbytes;
1967
1968 if (chip->ecc.postpad) {
1969 chip->write_buf(mtd, oob, chip->ecc.postpad);
1970 oob += chip->ecc.postpad;
1971 }
1972 }
1973
1974 size = mtd->oobsize - (oob - chip->oob_poi);
1975 if (size)
1976 chip->write_buf(mtd, oob, size);
1977 }
1978 /**
1979 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1980 * @mtd: mtd info structure
1981 * @chip: nand chip info structure
1982 * @buf: data buffer
1983 * @oob_required: must write chip->oob_poi to OOB
1984 */
1985 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1986 const uint8_t *buf, int oob_required)
1987 {
1988 int i, eccsize = chip->ecc.size;
1989 int eccbytes = chip->ecc.bytes;
1990 int eccsteps = chip->ecc.steps;
1991 uint8_t *ecc_calc = chip->buffers->ecccalc;
1992 const uint8_t *p = buf;
1993 uint32_t *eccpos = chip->ecc.layout->eccpos;
1994
1995 /* Software ECC calculation */
1996 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1997 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1998
1999 for (i = 0; i < chip->ecc.total; i++)
2000 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2001
2002 chip->ecc.write_page_raw(mtd, chip, buf, 1);
2003 }
2004
2005 /**
2006 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2007 * @mtd: mtd info structure
2008 * @chip: nand chip info structure
2009 * @buf: data buffer
2010 * @oob_required: must write chip->oob_poi to OOB
2011 */
2012 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2013 const uint8_t *buf, int oob_required)
2014 {
2015 int i, eccsize = chip->ecc.size;
2016 int eccbytes = chip->ecc.bytes;
2017 int eccsteps = chip->ecc.steps;
2018 uint8_t *ecc_calc = chip->buffers->ecccalc;
2019 const uint8_t *p = buf;
2020 uint32_t *eccpos = chip->ecc.layout->eccpos;
2021
2022 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2023 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2024 chip->write_buf(mtd, p, eccsize);
2025 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2026 }
2027
2028 for (i = 0; i < chip->ecc.total; i++)
2029 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2030
2031 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2032 }
2033
2034 /**
2035 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2036 * @mtd: mtd info structure
2037 * @chip: nand chip info structure
2038 * @buf: data buffer
2039 * @oob_required: must write chip->oob_poi to OOB
2040 *
2041 * The hw generator calculates the error syndrome automatically. Therefore we
2042 * need a special oob layout and handling.
2043 */
2044 static void nand_write_page_syndrome(struct mtd_info *mtd,
2045 struct nand_chip *chip,
2046 const uint8_t *buf, int oob_required)
2047 {
2048 int i, eccsize = chip->ecc.size;
2049 int eccbytes = chip->ecc.bytes;
2050 int eccsteps = chip->ecc.steps;
2051 const uint8_t *p = buf;
2052 uint8_t *oob = chip->oob_poi;
2053
2054 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2055
2056 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2057 chip->write_buf(mtd, p, eccsize);
2058
2059 if (chip->ecc.prepad) {
2060 chip->write_buf(mtd, oob, chip->ecc.prepad);
2061 oob += chip->ecc.prepad;
2062 }
2063
2064 chip->ecc.calculate(mtd, p, oob);
2065 chip->write_buf(mtd, oob, eccbytes);
2066 oob += eccbytes;
2067
2068 if (chip->ecc.postpad) {
2069 chip->write_buf(mtd, oob, chip->ecc.postpad);
2070 oob += chip->ecc.postpad;
2071 }
2072 }
2073
2074 /* Calculate remaining oob bytes */
2075 i = mtd->oobsize - (oob - chip->oob_poi);
2076 if (i)
2077 chip->write_buf(mtd, oob, i);
2078 }
2079
2080 /**
2081 * nand_write_page - [REPLACEABLE] write one page
2082 * @mtd: MTD device structure
2083 * @chip: NAND chip descriptor
2084 * @buf: the data to write
2085 * @oob_required: must write chip->oob_poi to OOB
2086 * @page: page number to write
2087 * @cached: cached programming
2088 * @raw: use _raw version of write_page
2089 */
2090 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2091 const uint8_t *buf, int oob_required, int page,
2092 int cached, int raw)
2093 {
2094 int status;
2095
2096 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2097
2098 if (unlikely(raw))
2099 chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
2100 else
2101 chip->ecc.write_page(mtd, chip, buf, oob_required);
2102
2103 /*
2104 * Cached progamming disabled for now. Not sure if it's worth the
2105 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2106 */
2107 cached = 0;
2108
2109 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2110
2111 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2112 status = chip->waitfunc(mtd, chip);
2113 /*
2114 * See if operation failed and additional status checks are
2115 * available.
2116 */
2117 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2118 status = chip->errstat(mtd, chip, FL_WRITING, status,
2119 page);
2120
2121 if (status & NAND_STATUS_FAIL)
2122 return -EIO;
2123 } else {
2124 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2125 status = chip->waitfunc(mtd, chip);
2126 }
2127
2128 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2129 /* Send command to read back the data */
2130 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2131
2132 if (chip->verify_buf(mtd, buf, mtd->writesize))
2133 return -EIO;
2134
2135 /* Make sure the next page prog is preceded by a status read */
2136 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2137 #endif
2138 return 0;
2139 }
2140
2141 /**
2142 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2143 * @mtd: MTD device structure
2144 * @oob: oob data buffer
2145 * @len: oob data write length
2146 * @ops: oob ops structure
2147 */
2148 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2149 struct mtd_oob_ops *ops)
2150 {
2151 struct nand_chip *chip = mtd->priv;
2152
2153 /*
2154 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2155 * data from a previous OOB read.
2156 */
2157 memset(chip->oob_poi, 0xff, mtd->oobsize);
2158
2159 switch (ops->mode) {
2160
2161 case MTD_OPS_PLACE_OOB:
2162 case MTD_OPS_RAW:
2163 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2164 return oob + len;
2165
2166 case MTD_OPS_AUTO_OOB: {
2167 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2168 uint32_t boffs = 0, woffs = ops->ooboffs;
2169 size_t bytes = 0;
2170
2171 for (; free->length && len; free++, len -= bytes) {
2172 /* Write request not from offset 0? */
2173 if (unlikely(woffs)) {
2174 if (woffs >= free->length) {
2175 woffs -= free->length;
2176 continue;
2177 }
2178 boffs = free->offset + woffs;
2179 bytes = min_t(size_t, len,
2180 (free->length - woffs));
2181 woffs = 0;
2182 } else {
2183 bytes = min_t(size_t, len, free->length);
2184 boffs = free->offset;
2185 }
2186 memcpy(chip->oob_poi + boffs, oob, bytes);
2187 oob += bytes;
2188 }
2189 return oob;
2190 }
2191 default:
2192 BUG();
2193 }
2194 return NULL;
2195 }
2196
2197 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2198
2199 /**
2200 * nand_do_write_ops - [INTERN] NAND write with ECC
2201 * @mtd: MTD device structure
2202 * @to: offset to write to
2203 * @ops: oob operations description structure
2204 *
2205 * NAND write with ECC.
2206 */
2207 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2208 struct mtd_oob_ops *ops)
2209 {
2210 int chipnr, realpage, page, blockmask, column;
2211 struct nand_chip *chip = mtd->priv;
2212 uint32_t writelen = ops->len;
2213
2214 uint32_t oobwritelen = ops->ooblen;
2215 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2216 mtd->oobavail : mtd->oobsize;
2217
2218 uint8_t *oob = ops->oobbuf;
2219 uint8_t *buf = ops->datbuf;
2220 int ret, subpage;
2221 int oob_required = oob ? 1 : 0;
2222
2223 ops->retlen = 0;
2224 if (!writelen)
2225 return 0;
2226
2227 /* Reject writes, which are not page aligned */
2228 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2229 pr_notice("%s: attempt to write non page aligned data\n",
2230 __func__);
2231 return -EINVAL;
2232 }
2233
2234 column = to & (mtd->writesize - 1);
2235 subpage = column || (writelen & (mtd->writesize - 1));
2236
2237 if (subpage && oob)
2238 return -EINVAL;
2239
2240 chipnr = (int)(to >> chip->chip_shift);
2241 chip->select_chip(mtd, chipnr);
2242
2243 /* Check, if it is write protected */
2244 if (nand_check_wp(mtd))
2245 return -EIO;
2246
2247 realpage = (int)(to >> chip->page_shift);
2248 page = realpage & chip->pagemask;
2249 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2250
2251 /* Invalidate the page cache, when we write to the cached page */
2252 if (to <= (chip->pagebuf << chip->page_shift) &&
2253 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2254 chip->pagebuf = -1;
2255
2256 /* Don't allow multipage oob writes with offset */
2257 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2258 return -EINVAL;
2259
2260 while (1) {
2261 int bytes = mtd->writesize;
2262 int cached = writelen > bytes && page != blockmask;
2263 uint8_t *wbuf = buf;
2264
2265 /* Partial page write? */
2266 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2267 cached = 0;
2268 bytes = min_t(int, bytes - column, (int) writelen);
2269 chip->pagebuf = -1;
2270 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2271 memcpy(&chip->buffers->databuf[column], buf, bytes);
2272 wbuf = chip->buffers->databuf;
2273 }
2274
2275 if (unlikely(oob)) {
2276 size_t len = min(oobwritelen, oobmaxlen);
2277 oob = nand_fill_oob(mtd, oob, len, ops);
2278 oobwritelen -= len;
2279 } else {
2280 /* We still need to erase leftover OOB data */
2281 memset(chip->oob_poi, 0xff, mtd->oobsize);
2282 }
2283
2284 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2285 cached, (ops->mode == MTD_OPS_RAW));
2286 if (ret)
2287 break;
2288
2289 writelen -= bytes;
2290 if (!writelen)
2291 break;
2292
2293 column = 0;
2294 buf += bytes;
2295 realpage++;
2296
2297 page = realpage & chip->pagemask;
2298 /* Check, if we cross a chip boundary */
2299 if (!page) {
2300 chipnr++;
2301 chip->select_chip(mtd, -1);
2302 chip->select_chip(mtd, chipnr);
2303 }
2304 }
2305
2306 ops->retlen = ops->len - writelen;
2307 if (unlikely(oob))
2308 ops->oobretlen = ops->ooblen;
2309 return ret;
2310 }
2311
2312 /**
2313 * panic_nand_write - [MTD Interface] NAND write with ECC
2314 * @mtd: MTD device structure
2315 * @to: offset to write to
2316 * @len: number of bytes to write
2317 * @retlen: pointer to variable to store the number of written bytes
2318 * @buf: the data to write
2319 *
2320 * NAND write with ECC. Used when performing writes in interrupt context, this
2321 * may for example be called by mtdoops when writing an oops while in panic.
2322 */
2323 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2324 size_t *retlen, const uint8_t *buf)
2325 {
2326 struct nand_chip *chip = mtd->priv;
2327 struct mtd_oob_ops ops;
2328 int ret;
2329
2330 /* Wait for the device to get ready */
2331 panic_nand_wait(mtd, chip, 400);
2332
2333 /* Grab the device */
2334 panic_nand_get_device(chip, mtd, FL_WRITING);
2335
2336 ops.len = len;
2337 ops.datbuf = (uint8_t *)buf;
2338 ops.oobbuf = NULL;
2339 ops.mode = 0;
2340
2341 ret = nand_do_write_ops(mtd, to, &ops);
2342
2343 *retlen = ops.retlen;
2344 return ret;
2345 }
2346
2347 /**
2348 * nand_write - [MTD Interface] NAND write with ECC
2349 * @mtd: MTD device structure
2350 * @to: offset to write to
2351 * @len: number of bytes to write
2352 * @retlen: pointer to variable to store the number of written bytes
2353 * @buf: the data to write
2354 *
2355 * NAND write with ECC.
2356 */
2357 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2358 size_t *retlen, const uint8_t *buf)
2359 {
2360 struct nand_chip *chip = mtd->priv;
2361 struct mtd_oob_ops ops;
2362 int ret;
2363
2364 nand_get_device(chip, mtd, FL_WRITING);
2365 ops.len = len;
2366 ops.datbuf = (uint8_t *)buf;
2367 ops.oobbuf = NULL;
2368 ops.mode = 0;
2369 ret = nand_do_write_ops(mtd, to, &ops);
2370 *retlen = ops.retlen;
2371 nand_release_device(mtd);
2372 return ret;
2373 }
2374
2375 /**
2376 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2377 * @mtd: MTD device structure
2378 * @to: offset to write to
2379 * @ops: oob operation description structure
2380 *
2381 * NAND write out-of-band.
2382 */
2383 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2384 struct mtd_oob_ops *ops)
2385 {
2386 int chipnr, page, status, len;
2387 struct nand_chip *chip = mtd->priv;
2388
2389 pr_debug("%s: to = 0x%08x, len = %i\n",
2390 __func__, (unsigned int)to, (int)ops->ooblen);
2391
2392 if (ops->mode == MTD_OPS_AUTO_OOB)
2393 len = chip->ecc.layout->oobavail;
2394 else
2395 len = mtd->oobsize;
2396
2397 /* Do not allow write past end of page */
2398 if ((ops->ooboffs + ops->ooblen) > len) {
2399 pr_debug("%s: attempt to write past end of page\n",
2400 __func__);
2401 return -EINVAL;
2402 }
2403
2404 if (unlikely(ops->ooboffs >= len)) {
2405 pr_debug("%s: attempt to start write outside oob\n",
2406 __func__);
2407 return -EINVAL;
2408 }
2409
2410 /* Do not allow write past end of device */
2411 if (unlikely(to >= mtd->size ||
2412 ops->ooboffs + ops->ooblen >
2413 ((mtd->size >> chip->page_shift) -
2414 (to >> chip->page_shift)) * len)) {
2415 pr_debug("%s: attempt to write beyond end of device\n",
2416 __func__);
2417 return -EINVAL;
2418 }
2419
2420 chipnr = (int)(to >> chip->chip_shift);
2421 chip->select_chip(mtd, chipnr);
2422
2423 /* Shift to get page */
2424 page = (int)(to >> chip->page_shift);
2425
2426 /*
2427 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2428 * of my DiskOnChip 2000 test units) will clear the whole data page too
2429 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2430 * it in the doc2000 driver in August 1999. dwmw2.
2431 */
2432 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2433
2434 /* Check, if it is write protected */
2435 if (nand_check_wp(mtd))
2436 return -EROFS;
2437
2438 /* Invalidate the page cache, if we write to the cached page */
2439 if (page == chip->pagebuf)
2440 chip->pagebuf = -1;
2441
2442 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2443
2444 if (ops->mode == MTD_OPS_RAW)
2445 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2446 else
2447 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2448
2449 if (status)
2450 return status;
2451
2452 ops->oobretlen = ops->ooblen;
2453
2454 return 0;
2455 }
2456
2457 /**
2458 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2459 * @mtd: MTD device structure
2460 * @to: offset to write to
2461 * @ops: oob operation description structure
2462 */
2463 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2464 struct mtd_oob_ops *ops)
2465 {
2466 struct nand_chip *chip = mtd->priv;
2467 int ret = -ENOTSUPP;
2468
2469 ops->retlen = 0;
2470
2471 /* Do not allow writes past end of device */
2472 if (ops->datbuf && (to + ops->len) > mtd->size) {
2473 pr_debug("%s: attempt to write beyond end of device\n",
2474 __func__);
2475 return -EINVAL;
2476 }
2477
2478 nand_get_device(chip, mtd, FL_WRITING);
2479
2480 switch (ops->mode) {
2481 case MTD_OPS_PLACE_OOB:
2482 case MTD_OPS_AUTO_OOB:
2483 case MTD_OPS_RAW:
2484 break;
2485
2486 default:
2487 goto out;
2488 }
2489
2490 if (!ops->datbuf)
2491 ret = nand_do_write_oob(mtd, to, ops);
2492 else
2493 ret = nand_do_write_ops(mtd, to, ops);
2494
2495 out:
2496 nand_release_device(mtd);
2497 return ret;
2498 }
2499
2500 /**
2501 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2502 * @mtd: MTD device structure
2503 * @page: the page address of the block which will be erased
2504 *
2505 * Standard erase command for NAND chips.
2506 */
2507 static void single_erase_cmd(struct mtd_info *mtd, int page)
2508 {
2509 struct nand_chip *chip = mtd->priv;
2510 /* Send commands to erase a block */
2511 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2512 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2513 }
2514
2515 /**
2516 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2517 * @mtd: MTD device structure
2518 * @page: the page address of the block which will be erased
2519 *
2520 * AND multi block erase command function. Erase 4 consecutive blocks.
2521 */
2522 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2523 {
2524 struct nand_chip *chip = mtd->priv;
2525 /* Send commands to erase a block */
2526 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2527 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2528 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2529 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2530 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2531 }
2532
2533 /**
2534 * nand_erase - [MTD Interface] erase block(s)
2535 * @mtd: MTD device structure
2536 * @instr: erase instruction
2537 *
2538 * Erase one ore more blocks.
2539 */
2540 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2541 {
2542 return nand_erase_nand(mtd, instr, 0);
2543 }
2544
2545 #define BBT_PAGE_MASK 0xffffff3f
2546 /**
2547 * nand_erase_nand - [INTERN] erase block(s)
2548 * @mtd: MTD device structure
2549 * @instr: erase instruction
2550 * @allowbbt: allow erasing the bbt area
2551 *
2552 * Erase one ore more blocks.
2553 */
2554 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2555 int allowbbt)
2556 {
2557 int page, status, pages_per_block, ret, chipnr;
2558 struct nand_chip *chip = mtd->priv;
2559 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2560 unsigned int bbt_masked_page = 0xffffffff;
2561 loff_t len;
2562
2563 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2564 __func__, (unsigned long long)instr->addr,
2565 (unsigned long long)instr->len);
2566
2567 if (check_offs_len(mtd, instr->addr, instr->len))
2568 return -EINVAL;
2569
2570 /* Grab the lock and see if the device is available */
2571 nand_get_device(chip, mtd, FL_ERASING);
2572
2573 /* Shift to get first page */
2574 page = (int)(instr->addr >> chip->page_shift);
2575 chipnr = (int)(instr->addr >> chip->chip_shift);
2576
2577 /* Calculate pages in each block */
2578 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2579
2580 /* Select the NAND device */
2581 chip->select_chip(mtd, chipnr);
2582
2583 /* Check, if it is write protected */
2584 if (nand_check_wp(mtd)) {
2585 pr_debug("%s: device is write protected!\n",
2586 __func__);
2587 instr->state = MTD_ERASE_FAILED;
2588 goto erase_exit;
2589 }
2590
2591 /*
2592 * If BBT requires refresh, set the BBT page mask to see if the BBT
2593 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2594 * can not be matched. This is also done when the bbt is actually
2595 * erased to avoid recursive updates.
2596 */
2597 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2598 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2599
2600 /* Loop through the pages */
2601 len = instr->len;
2602
2603 instr->state = MTD_ERASING;
2604
2605 while (len) {
2606 /* Check if we have a bad block, we do not erase bad blocks! */
2607 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2608 chip->page_shift, 0, allowbbt)) {
2609 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2610 __func__, page);
2611 instr->state = MTD_ERASE_FAILED;
2612 goto erase_exit;
2613 }
2614
2615 /*
2616 * Invalidate the page cache, if we erase the block which
2617 * contains the current cached page.
2618 */
2619 if (page <= chip->pagebuf && chip->pagebuf <
2620 (page + pages_per_block))
2621 chip->pagebuf = -1;
2622
2623 chip->erase_cmd(mtd, page & chip->pagemask);
2624
2625 status = chip->waitfunc(mtd, chip);
2626
2627 /*
2628 * See if operation failed and additional status checks are
2629 * available
2630 */
2631 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2632 status = chip->errstat(mtd, chip, FL_ERASING,
2633 status, page);
2634
2635 /* See if block erase succeeded */
2636 if (status & NAND_STATUS_FAIL) {
2637 pr_debug("%s: failed erase, page 0x%08x\n",
2638 __func__, page);
2639 instr->state = MTD_ERASE_FAILED;
2640 instr->fail_addr =
2641 ((loff_t)page << chip->page_shift);
2642 goto erase_exit;
2643 }
2644
2645 /*
2646 * If BBT requires refresh, set the BBT rewrite flag to the
2647 * page being erased.
2648 */
2649 if (bbt_masked_page != 0xffffffff &&
2650 (page & BBT_PAGE_MASK) == bbt_masked_page)
2651 rewrite_bbt[chipnr] =
2652 ((loff_t)page << chip->page_shift);
2653
2654 /* Increment page address and decrement length */
2655 len -= (1 << chip->phys_erase_shift);
2656 page += pages_per_block;
2657
2658 /* Check, if we cross a chip boundary */
2659 if (len && !(page & chip->pagemask)) {
2660 chipnr++;
2661 chip->select_chip(mtd, -1);
2662 chip->select_chip(mtd, chipnr);
2663
2664 /*
2665 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2666 * page mask to see if this BBT should be rewritten.
2667 */
2668 if (bbt_masked_page != 0xffffffff &&
2669 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2670 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2671 BBT_PAGE_MASK;
2672 }
2673 }
2674 instr->state = MTD_ERASE_DONE;
2675
2676 erase_exit:
2677
2678 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2679
2680 /* Deselect and wake up anyone waiting on the device */
2681 nand_release_device(mtd);
2682
2683 /* Do call back function */
2684 if (!ret)
2685 mtd_erase_callback(instr);
2686
2687 /*
2688 * If BBT requires refresh and erase was successful, rewrite any
2689 * selected bad block tables.
2690 */
2691 if (bbt_masked_page == 0xffffffff || ret)
2692 return ret;
2693
2694 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2695 if (!rewrite_bbt[chipnr])
2696 continue;
2697 /* Update the BBT for chip */
2698 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2699 __func__, chipnr, rewrite_bbt[chipnr],
2700 chip->bbt_td->pages[chipnr]);
2701 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2702 }
2703
2704 /* Return more or less happy */
2705 return ret;
2706 }
2707
2708 /**
2709 * nand_sync - [MTD Interface] sync
2710 * @mtd: MTD device structure
2711 *
2712 * Sync is actually a wait for chip ready function.
2713 */
2714 static void nand_sync(struct mtd_info *mtd)
2715 {
2716 struct nand_chip *chip = mtd->priv;
2717
2718 pr_debug("%s: called\n", __func__);
2719
2720 /* Grab the lock and see if the device is available */
2721 nand_get_device(chip, mtd, FL_SYNCING);
2722 /* Release it and go back */
2723 nand_release_device(mtd);
2724 }
2725
2726 /**
2727 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2728 * @mtd: MTD device structure
2729 * @offs: offset relative to mtd start
2730 */
2731 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2732 {
2733 return nand_block_checkbad(mtd, offs, 1, 0);
2734 }
2735
2736 /**
2737 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2738 * @mtd: MTD device structure
2739 * @ofs: offset relative to mtd start
2740 */
2741 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2742 {
2743 struct nand_chip *chip = mtd->priv;
2744 int ret;
2745
2746 ret = nand_block_isbad(mtd, ofs);
2747 if (ret) {
2748 /* If it was bad already, return success and do nothing */
2749 if (ret > 0)
2750 return 0;
2751 return ret;
2752 }
2753
2754 return chip->block_markbad(mtd, ofs);
2755 }
2756
2757 /**
2758 * nand_suspend - [MTD Interface] Suspend the NAND flash
2759 * @mtd: MTD device structure
2760 */
2761 static int nand_suspend(struct mtd_info *mtd)
2762 {
2763 struct nand_chip *chip = mtd->priv;
2764
2765 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2766 }
2767
2768 /**
2769 * nand_resume - [MTD Interface] Resume the NAND flash
2770 * @mtd: MTD device structure
2771 */
2772 static void nand_resume(struct mtd_info *mtd)
2773 {
2774 struct nand_chip *chip = mtd->priv;
2775
2776 if (chip->state == FL_PM_SUSPENDED)
2777 nand_release_device(mtd);
2778 else
2779 pr_err("%s called for a chip which is not in suspended state\n",
2780 __func__);
2781 }
2782
2783 /* Set default functions */
2784 static void nand_set_defaults(struct nand_chip *chip, int busw)
2785 {
2786 /* check for proper chip_delay setup, set 20us if not */
2787 if (!chip->chip_delay)
2788 chip->chip_delay = 20;
2789
2790 /* check, if a user supplied command function given */
2791 if (chip->cmdfunc == NULL)
2792 chip->cmdfunc = nand_command;
2793
2794 /* check, if a user supplied wait function given */
2795 if (chip->waitfunc == NULL)
2796 chip->waitfunc = nand_wait;
2797
2798 if (!chip->select_chip)
2799 chip->select_chip = nand_select_chip;
2800 if (!chip->read_byte)
2801 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2802 if (!chip->read_word)
2803 chip->read_word = nand_read_word;
2804 if (!chip->block_bad)
2805 chip->block_bad = nand_block_bad;
2806 if (!chip->block_markbad)
2807 chip->block_markbad = nand_default_block_markbad;
2808 if (!chip->write_buf)
2809 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2810 if (!chip->read_buf)
2811 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2812 if (!chip->verify_buf)
2813 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2814 if (!chip->scan_bbt)
2815 chip->scan_bbt = nand_default_bbt;
2816
2817 if (!chip->controller) {
2818 chip->controller = &chip->hwcontrol;
2819 spin_lock_init(&chip->controller->lock);
2820 init_waitqueue_head(&chip->controller->wq);
2821 }
2822
2823 }
2824
2825 /* Sanitize ONFI strings so we can safely print them */
2826 static void sanitize_string(uint8_t *s, size_t len)
2827 {
2828 ssize_t i;
2829
2830 /* Null terminate */
2831 s[len - 1] = 0;
2832
2833 /* Remove non printable chars */
2834 for (i = 0; i < len - 1; i++) {
2835 if (s[i] < ' ' || s[i] > 127)
2836 s[i] = '?';
2837 }
2838
2839 /* Remove trailing spaces */
2840 strim(s);
2841 }
2842
2843 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2844 {
2845 int i;
2846 while (len--) {
2847 crc ^= *p++ << 8;
2848 for (i = 0; i < 8; i++)
2849 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2850 }
2851
2852 return crc;
2853 }
2854
2855 /*
2856 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2857 */
2858 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2859 int *busw)
2860 {
2861 struct nand_onfi_params *p = &chip->onfi_params;
2862 int i;
2863 int val;
2864
2865 /* Try ONFI for unknown chip or LP */
2866 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2867 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2868 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2869 return 0;
2870
2871 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2872 for (i = 0; i < 3; i++) {
2873 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2874 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2875 le16_to_cpu(p->crc)) {
2876 pr_info("ONFI param page %d valid\n", i);
2877 break;
2878 }
2879 }
2880
2881 if (i == 3)
2882 return 0;
2883
2884 /* Check version */
2885 val = le16_to_cpu(p->revision);
2886 if (val & (1 << 5))
2887 chip->onfi_version = 23;
2888 else if (val & (1 << 4))
2889 chip->onfi_version = 22;
2890 else if (val & (1 << 3))
2891 chip->onfi_version = 21;
2892 else if (val & (1 << 2))
2893 chip->onfi_version = 20;
2894 else if (val & (1 << 1))
2895 chip->onfi_version = 10;
2896 else
2897 chip->onfi_version = 0;
2898
2899 if (!chip->onfi_version) {
2900 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2901 return 0;
2902 }
2903
2904 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2905 sanitize_string(p->model, sizeof(p->model));
2906 if (!mtd->name)
2907 mtd->name = p->model;
2908 mtd->writesize = le32_to_cpu(p->byte_per_page);
2909 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2910 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2911 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2912 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2913 *busw = 0;
2914 if (le16_to_cpu(p->features) & 1)
2915 *busw = NAND_BUSWIDTH_16;
2916
2917 chip->options |= NAND_NO_READRDY;
2918
2919 pr_info("ONFI flash detected\n");
2920 return 1;
2921 }
2922
2923 /*
2924 * Get the flash and manufacturer id and lookup if the type is supported.
2925 */
2926 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2927 struct nand_chip *chip,
2928 int busw,
2929 int *maf_id, int *dev_id,
2930 struct nand_flash_dev *type)
2931 {
2932 int i, maf_idx;
2933 u8 id_data[8];
2934 int ret;
2935
2936 /* Select the device */
2937 chip->select_chip(mtd, 0);
2938
2939 /*
2940 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2941 * after power-up.
2942 */
2943 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2944
2945 /* Send the command for reading device ID */
2946 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2947
2948 /* Read manufacturer and device IDs */
2949 *maf_id = chip->read_byte(mtd);
2950 *dev_id = chip->read_byte(mtd);
2951
2952 /*
2953 * Try again to make sure, as some systems the bus-hold or other
2954 * interface concerns can cause random data which looks like a
2955 * possibly credible NAND flash to appear. If the two results do
2956 * not match, ignore the device completely.
2957 */
2958
2959 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2960
2961 for (i = 0; i < 2; i++)
2962 id_data[i] = chip->read_byte(mtd);
2963
2964 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2965 pr_info("%s: second ID read did not match "
2966 "%02x,%02x against %02x,%02x\n", __func__,
2967 *maf_id, *dev_id, id_data[0], id_data[1]);
2968 return ERR_PTR(-ENODEV);
2969 }
2970
2971 if (!type)
2972 type = nand_flash_ids;
2973
2974 for (; type->name != NULL; type++)
2975 if (*dev_id == type->id)
2976 break;
2977
2978 chip->onfi_version = 0;
2979 if (!type->name || !type->pagesize) {
2980 /* Check is chip is ONFI compliant */
2981 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2982 if (ret)
2983 goto ident_done;
2984 }
2985
2986 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2987
2988 /* Read entire ID string */
2989
2990 for (i = 0; i < 8; i++)
2991 id_data[i] = chip->read_byte(mtd);
2992
2993 if (!type->name)
2994 return ERR_PTR(-ENODEV);
2995
2996 if (!mtd->name)
2997 mtd->name = type->name;
2998
2999 chip->chipsize = (uint64_t)type->chipsize << 20;
3000
3001 if (!type->pagesize && chip->init_size) {
3002 /* Set the pagesize, oobsize, erasesize by the driver */
3003 busw = chip->init_size(mtd, chip, id_data);
3004 } else if (!type->pagesize) {
3005 int extid;
3006 /* The 3rd id byte holds MLC / multichip data */
3007 chip->cellinfo = id_data[2];
3008 /* The 4th id byte is the important one */
3009 extid = id_data[3];
3010
3011 /*
3012 * Field definitions are in the following datasheets:
3013 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3014 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
3015 *
3016 * Check for wraparound + Samsung ID + nonzero 6th byte
3017 * to decide what to do.
3018 */
3019 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3020 id_data[0] == NAND_MFR_SAMSUNG &&
3021 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3022 id_data[5] != 0x00) {
3023 /* Calc pagesize */
3024 mtd->writesize = 2048 << (extid & 0x03);
3025 extid >>= 2;
3026 /* Calc oobsize */
3027 switch (extid & 0x03) {
3028 case 1:
3029 mtd->oobsize = 128;
3030 break;
3031 case 2:
3032 mtd->oobsize = 218;
3033 break;
3034 case 3:
3035 mtd->oobsize = 400;
3036 break;
3037 default:
3038 mtd->oobsize = 436;
3039 break;
3040 }
3041 extid >>= 2;
3042 /* Calc blocksize */
3043 mtd->erasesize = (128 * 1024) <<
3044 (((extid >> 1) & 0x04) | (extid & 0x03));
3045 busw = 0;
3046 } else {
3047 /* Calc pagesize */
3048 mtd->writesize = 1024 << (extid & 0x03);
3049 extid >>= 2;
3050 /* Calc oobsize */
3051 mtd->oobsize = (8 << (extid & 0x01)) *
3052 (mtd->writesize >> 9);
3053 extid >>= 2;
3054 /* Calc blocksize. Blocksize is multiples of 64KiB */
3055 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3056 extid >>= 2;
3057 /* Get buswidth information */
3058 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3059 }
3060 } else {
3061 /*
3062 * Old devices have chip data hardcoded in the device id table.
3063 */
3064 mtd->erasesize = type->erasesize;
3065 mtd->writesize = type->pagesize;
3066 mtd->oobsize = mtd->writesize / 32;
3067 busw = type->options & NAND_BUSWIDTH_16;
3068
3069 /*
3070 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3071 * some Spansion chips have erasesize that conflicts with size
3072 * listed in nand_ids table.
3073 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3074 */
3075 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3076 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3077 id_data[7] == 0x00 && mtd->writesize == 512) {
3078 mtd->erasesize = 128 * 1024;
3079 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3080 }
3081 }
3082 /* Get chip options */
3083 chip->options |= type->options;
3084
3085 /*
3086 * Check if chip is not a Samsung device. Do not clear the
3087 * options for chips which do not have an extended id.
3088 */
3089 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3090 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3091 ident_done:
3092
3093 /* Try to identify manufacturer */
3094 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3095 if (nand_manuf_ids[maf_idx].id == *maf_id)
3096 break;
3097 }
3098
3099 /*
3100 * Check, if buswidth is correct. Hardware drivers should set
3101 * chip correct!
3102 */
3103 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3104 pr_info("NAND device: Manufacturer ID:"
3105 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3106 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3107 pr_warn("NAND bus width %d instead %d bit\n",
3108 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3109 busw ? 16 : 8);
3110 return ERR_PTR(-EINVAL);
3111 }
3112
3113 /* Calculate the address shift from the page size */
3114 chip->page_shift = ffs(mtd->writesize) - 1;
3115 /* Convert chipsize to number of pages per chip -1 */
3116 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3117
3118 chip->bbt_erase_shift = chip->phys_erase_shift =
3119 ffs(mtd->erasesize) - 1;
3120 if (chip->chipsize & 0xffffffff)
3121 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3122 else {
3123 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3124 chip->chip_shift += 32 - 1;
3125 }
3126
3127 chip->badblockbits = 8;
3128
3129 /* Set the bad block position */
3130 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3131 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3132 else
3133 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3134
3135 /*
3136 * Bad block marker is stored in the last page of each block
3137 * on Samsung and Hynix MLC devices; stored in first two pages
3138 * of each block on Micron devices with 2KiB pages and on
3139 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3140 * All others scan only the first page.
3141 */
3142 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3143 (*maf_id == NAND_MFR_SAMSUNG ||
3144 *maf_id == NAND_MFR_HYNIX))
3145 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3146 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3147 (*maf_id == NAND_MFR_SAMSUNG ||
3148 *maf_id == NAND_MFR_HYNIX ||
3149 *maf_id == NAND_MFR_TOSHIBA ||
3150 *maf_id == NAND_MFR_AMD ||
3151 *maf_id == NAND_MFR_MACRONIX)) ||
3152 (mtd->writesize == 2048 &&
3153 *maf_id == NAND_MFR_MICRON))
3154 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3155
3156 /* Check for AND chips with 4 page planes */
3157 if (chip->options & NAND_4PAGE_ARRAY)
3158 chip->erase_cmd = multi_erase_cmd;
3159 else
3160 chip->erase_cmd = single_erase_cmd;
3161
3162 /* Do not replace user supplied command function! */
3163 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3164 chip->cmdfunc = nand_command_lp;
3165
3166 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3167 " page size: %d, OOB size: %d\n",
3168 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3169 chip->onfi_version ? chip->onfi_params.model : type->name,
3170 mtd->writesize, mtd->oobsize);
3171
3172 return type;
3173 }
3174
3175 /**
3176 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3177 * @mtd: MTD device structure
3178 * @maxchips: number of chips to scan for
3179 * @table: alternative NAND ID table
3180 *
3181 * This is the first phase of the normal nand_scan() function. It reads the
3182 * flash ID and sets up MTD fields accordingly.
3183 *
3184 * The mtd->owner field must be set to the module of the caller.
3185 */
3186 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3187 struct nand_flash_dev *table)
3188 {
3189 int i, busw, nand_maf_id, nand_dev_id;
3190 struct nand_chip *chip = mtd->priv;
3191 struct nand_flash_dev *type;
3192
3193 /* Get buswidth to select the correct functions */
3194 busw = chip->options & NAND_BUSWIDTH_16;
3195 /* Set the default functions */
3196 nand_set_defaults(chip, busw);
3197
3198 /* Read the flash type */
3199 type = nand_get_flash_type(mtd, chip, busw,
3200 &nand_maf_id, &nand_dev_id, table);
3201
3202 if (IS_ERR(type)) {
3203 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3204 pr_warn("No NAND device found\n");
3205 chip->select_chip(mtd, -1);
3206 return PTR_ERR(type);
3207 }
3208
3209 /* Check for a chip array */
3210 for (i = 1; i < maxchips; i++) {
3211 chip->select_chip(mtd, i);
3212 /* See comment in nand_get_flash_type for reset */
3213 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3214 /* Send the command for reading device ID */
3215 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3216 /* Read manufacturer and device IDs */
3217 if (nand_maf_id != chip->read_byte(mtd) ||
3218 nand_dev_id != chip->read_byte(mtd))
3219 break;
3220 }
3221 if (i > 1)
3222 pr_info("%d NAND chips detected\n", i);
3223
3224 /* Store the number of chips and calc total size for mtd */
3225 chip->numchips = i;
3226 mtd->size = i * chip->chipsize;
3227
3228 return 0;
3229 }
3230 EXPORT_SYMBOL(nand_scan_ident);
3231
3232
3233 /**
3234 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3235 * @mtd: MTD device structure
3236 *
3237 * This is the second phase of the normal nand_scan() function. It fills out
3238 * all the uninitialized function pointers with the defaults and scans for a
3239 * bad block table if appropriate.
3240 */
3241 int nand_scan_tail(struct mtd_info *mtd)
3242 {
3243 int i;
3244 struct nand_chip *chip = mtd->priv;
3245
3246 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3247 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3248 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3249
3250 if (!(chip->options & NAND_OWN_BUFFERS))
3251 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3252 if (!chip->buffers)
3253 return -ENOMEM;
3254
3255 /* Set the internal oob buffer location, just after the page data */
3256 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3257
3258 /*
3259 * If no default placement scheme is given, select an appropriate one.
3260 */
3261 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3262 switch (mtd->oobsize) {
3263 case 8:
3264 chip->ecc.layout = &nand_oob_8;
3265 break;
3266 case 16:
3267 chip->ecc.layout = &nand_oob_16;
3268 break;
3269 case 64:
3270 chip->ecc.layout = &nand_oob_64;
3271 break;
3272 case 128:
3273 chip->ecc.layout = &nand_oob_128;
3274 break;
3275 default:
3276 pr_warn("No oob scheme defined for oobsize %d\n",
3277 mtd->oobsize);
3278 BUG();
3279 }
3280 }
3281
3282 if (!chip->write_page)
3283 chip->write_page = nand_write_page;
3284
3285 /*
3286 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3287 * selected and we have 256 byte pagesize fallback to software ECC
3288 */
3289
3290 switch (chip->ecc.mode) {
3291 case NAND_ECC_HW_OOB_FIRST:
3292 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3293 if (!chip->ecc.calculate || !chip->ecc.correct ||
3294 !chip->ecc.hwctl) {
3295 pr_warn("No ECC functions supplied; "
3296 "hardware ECC not possible\n");
3297 BUG();
3298 }
3299 if (!chip->ecc.read_page)
3300 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3301
3302 case NAND_ECC_HW:
3303 /* Use standard hwecc read page function? */
3304 if (!chip->ecc.read_page)
3305 chip->ecc.read_page = nand_read_page_hwecc;
3306 if (!chip->ecc.write_page)
3307 chip->ecc.write_page = nand_write_page_hwecc;
3308 if (!chip->ecc.read_page_raw)
3309 chip->ecc.read_page_raw = nand_read_page_raw;
3310 if (!chip->ecc.write_page_raw)
3311 chip->ecc.write_page_raw = nand_write_page_raw;
3312 if (!chip->ecc.read_oob)
3313 chip->ecc.read_oob = nand_read_oob_std;
3314 if (!chip->ecc.write_oob)
3315 chip->ecc.write_oob = nand_write_oob_std;
3316
3317 case NAND_ECC_HW_SYNDROME:
3318 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3319 !chip->ecc.hwctl) &&
3320 (!chip->ecc.read_page ||
3321 chip->ecc.read_page == nand_read_page_hwecc ||
3322 !chip->ecc.write_page ||
3323 chip->ecc.write_page == nand_write_page_hwecc)) {
3324 pr_warn("No ECC functions supplied; "
3325 "hardware ECC not possible\n");
3326 BUG();
3327 }
3328 /* Use standard syndrome read/write page function? */
3329 if (!chip->ecc.read_page)
3330 chip->ecc.read_page = nand_read_page_syndrome;
3331 if (!chip->ecc.write_page)
3332 chip->ecc.write_page = nand_write_page_syndrome;
3333 if (!chip->ecc.read_page_raw)
3334 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3335 if (!chip->ecc.write_page_raw)
3336 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3337 if (!chip->ecc.read_oob)
3338 chip->ecc.read_oob = nand_read_oob_syndrome;
3339 if (!chip->ecc.write_oob)
3340 chip->ecc.write_oob = nand_write_oob_syndrome;
3341
3342 if (mtd->writesize >= chip->ecc.size) {
3343 if (!chip->ecc.strength) {
3344 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3345 BUG();
3346 }
3347 break;
3348 }
3349 pr_warn("%d byte HW ECC not possible on "
3350 "%d byte page size, fallback to SW ECC\n",
3351 chip->ecc.size, mtd->writesize);
3352 chip->ecc.mode = NAND_ECC_SOFT;
3353
3354 case NAND_ECC_SOFT:
3355 chip->ecc.calculate = nand_calculate_ecc;
3356 chip->ecc.correct = nand_correct_data;
3357 chip->ecc.read_page = nand_read_page_swecc;
3358 chip->ecc.read_subpage = nand_read_subpage;
3359 chip->ecc.write_page = nand_write_page_swecc;
3360 chip->ecc.read_page_raw = nand_read_page_raw;
3361 chip->ecc.write_page_raw = nand_write_page_raw;
3362 chip->ecc.read_oob = nand_read_oob_std;
3363 chip->ecc.write_oob = nand_write_oob_std;
3364 if (!chip->ecc.size)
3365 chip->ecc.size = 256;
3366 chip->ecc.bytes = 3;
3367 chip->ecc.strength = 1;
3368 break;
3369
3370 case NAND_ECC_SOFT_BCH:
3371 if (!mtd_nand_has_bch()) {
3372 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3373 BUG();
3374 }
3375 chip->ecc.calculate = nand_bch_calculate_ecc;
3376 chip->ecc.correct = nand_bch_correct_data;
3377 chip->ecc.read_page = nand_read_page_swecc;
3378 chip->ecc.read_subpage = nand_read_subpage;
3379 chip->ecc.write_page = nand_write_page_swecc;
3380 chip->ecc.read_page_raw = nand_read_page_raw;
3381 chip->ecc.write_page_raw = nand_write_page_raw;
3382 chip->ecc.read_oob = nand_read_oob_std;
3383 chip->ecc.write_oob = nand_write_oob_std;
3384 /*
3385 * Board driver should supply ecc.size and ecc.bytes values to
3386 * select how many bits are correctable; see nand_bch_init()
3387 * for details. Otherwise, default to 4 bits for large page
3388 * devices.
3389 */
3390 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3391 chip->ecc.size = 512;
3392 chip->ecc.bytes = 7;
3393 }
3394 chip->ecc.priv = nand_bch_init(mtd,
3395 chip->ecc.size,
3396 chip->ecc.bytes,
3397 &chip->ecc.layout);
3398 if (!chip->ecc.priv) {
3399 pr_warn("BCH ECC initialization failed!\n");
3400 BUG();
3401 }
3402 chip->ecc.strength =
3403 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3404 break;
3405
3406 case NAND_ECC_NONE:
3407 pr_warn("NAND_ECC_NONE selected by board driver. "
3408 "This is not recommended!\n");
3409 chip->ecc.read_page = nand_read_page_raw;
3410 chip->ecc.write_page = nand_write_page_raw;
3411 chip->ecc.read_oob = nand_read_oob_std;
3412 chip->ecc.read_page_raw = nand_read_page_raw;
3413 chip->ecc.write_page_raw = nand_write_page_raw;
3414 chip->ecc.write_oob = nand_write_oob_std;
3415 chip->ecc.size = mtd->writesize;
3416 chip->ecc.bytes = 0;
3417 chip->ecc.strength = 0;
3418 break;
3419
3420 default:
3421 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3422 BUG();
3423 }
3424
3425 /* For many systems, the standard OOB write also works for raw */
3426 if (!chip->ecc.read_oob_raw)
3427 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3428 if (!chip->ecc.write_oob_raw)
3429 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3430
3431 /*
3432 * The number of bytes available for a client to place data into
3433 * the out of band area.
3434 */
3435 chip->ecc.layout->oobavail = 0;
3436 for (i = 0; chip->ecc.layout->oobfree[i].length
3437 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3438 chip->ecc.layout->oobavail +=
3439 chip->ecc.layout->oobfree[i].length;
3440 mtd->oobavail = chip->ecc.layout->oobavail;
3441
3442 /*
3443 * Set the number of read / write steps for one page depending on ECC
3444 * mode.
3445 */
3446 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3447 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3448 pr_warn("Invalid ECC parameters\n");
3449 BUG();
3450 }
3451 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3452
3453 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3454 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3455 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3456 switch (chip->ecc.steps) {
3457 case 2:
3458 mtd->subpage_sft = 1;
3459 break;
3460 case 4:
3461 case 8:
3462 case 16:
3463 mtd->subpage_sft = 2;
3464 break;
3465 }
3466 }
3467 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3468
3469 /* Initialize state */
3470 chip->state = FL_READY;
3471
3472 /* De-select the device */
3473 chip->select_chip(mtd, -1);
3474
3475 /* Invalidate the pagebuffer reference */
3476 chip->pagebuf = -1;
3477
3478 /* Fill in remaining MTD driver data */
3479 mtd->type = MTD_NANDFLASH;
3480 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3481 MTD_CAP_NANDFLASH;
3482 mtd->_erase = nand_erase;
3483 mtd->_point = NULL;
3484 mtd->_unpoint = NULL;
3485 mtd->_read = nand_read;
3486 mtd->_write = nand_write;
3487 mtd->_panic_write = panic_nand_write;
3488 mtd->_read_oob = nand_read_oob;
3489 mtd->_write_oob = nand_write_oob;
3490 mtd->_sync = nand_sync;
3491 mtd->_lock = NULL;
3492 mtd->_unlock = NULL;
3493 mtd->_suspend = nand_suspend;
3494 mtd->_resume = nand_resume;
3495 mtd->_block_isbad = nand_block_isbad;
3496 mtd->_block_markbad = nand_block_markbad;
3497 mtd->writebufsize = mtd->writesize;
3498
3499 /* propagate ecc info to mtd_info */
3500 mtd->ecclayout = chip->ecc.layout;
3501 mtd->ecc_strength = chip->ecc.strength;
3502 /*
3503 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3504 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3505 * properly set.
3506 */
3507 if (!mtd->bitflip_threshold)
3508 mtd->bitflip_threshold = mtd->ecc_strength;
3509
3510 /* Check, if we should skip the bad block table scan */
3511 if (chip->options & NAND_SKIP_BBTSCAN)
3512 return 0;
3513
3514 /* Build bad block table */
3515 return chip->scan_bbt(mtd);
3516 }
3517 EXPORT_SYMBOL(nand_scan_tail);
3518
3519 /*
3520 * is_module_text_address() isn't exported, and it's mostly a pointless
3521 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3522 * to call us from in-kernel code if the core NAND support is modular.
3523 */
3524 #ifdef MODULE
3525 #define caller_is_module() (1)
3526 #else
3527 #define caller_is_module() \
3528 is_module_text_address((unsigned long)__builtin_return_address(0))
3529 #endif
3530
3531 /**
3532 * nand_scan - [NAND Interface] Scan for the NAND device
3533 * @mtd: MTD device structure
3534 * @maxchips: number of chips to scan for
3535 *
3536 * This fills out all the uninitialized function pointers with the defaults.
3537 * The flash ID is read and the mtd/chip structures are filled with the
3538 * appropriate values. The mtd->owner field must be set to the module of the
3539 * caller.
3540 */
3541 int nand_scan(struct mtd_info *mtd, int maxchips)
3542 {
3543 int ret;
3544
3545 /* Many callers got this wrong, so check for it for a while... */
3546 if (!mtd->owner && caller_is_module()) {
3547 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3548 BUG();
3549 }
3550
3551 ret = nand_scan_ident(mtd, maxchips, NULL);
3552 if (!ret)
3553 ret = nand_scan_tail(mtd);
3554 return ret;
3555 }
3556 EXPORT_SYMBOL(nand_scan);
3557
3558 /**
3559 * nand_release - [NAND Interface] Free resources held by the NAND device
3560 * @mtd: MTD device structure
3561 */
3562 void nand_release(struct mtd_info *mtd)
3563 {
3564 struct nand_chip *chip = mtd->priv;
3565
3566 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3567 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3568
3569 mtd_device_unregister(mtd);
3570
3571 /* Free bad block table memory */
3572 kfree(chip->bbt);
3573 if (!(chip->options & NAND_OWN_BUFFERS))
3574 kfree(chip->buffers);
3575
3576 /* Free bad block descriptor memory */
3577 if (chip->badblock_pattern && chip->badblock_pattern->options
3578 & NAND_BBT_DYNAMICSTRUCT)
3579 kfree(chip->badblock_pattern);
3580 }
3581 EXPORT_SYMBOL_GPL(nand_release);
3582
3583 static int __init nand_base_init(void)
3584 {
3585 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3586 return 0;
3587 }
3588
3589 static void __exit nand_base_exit(void)
3590 {
3591 led_trigger_unregister_simple(nand_led_trigger);
3592 }
3593
3594 module_init(nand_base_init);
3595 module_exit(nand_base_exit);
3596
3597 MODULE_LICENSE("GPL");
3598 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3599 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3600 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux ARM platform port for MOXA ART SoC