drivers/net/ethernet/broadcom/cnic_defs.h

   1
   2 /* cnic.c: Broadcom CNIC core network driver.
   3  *
   4  * Copyright (c) 2006-2012 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef CNIC_DEFS_H
  13 #define CNIC_DEFS_H
  14
  15 /* KWQ (kernel work queue) request op codes */
  16 #define L2_KWQE_OPCODE_VALUE_FLUSH                  (4)
  17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE       (8)
  18
  19 #define L4_KWQE_OPCODE_VALUE_CONNECT1               (50)
  20 #define L4_KWQE_OPCODE_VALUE_CONNECT2               (51)
  21 #define L4_KWQE_OPCODE_VALUE_CONNECT3               (52)
  22 #define L4_KWQE_OPCODE_VALUE_RESET                  (53)
  23 #define L4_KWQE_OPCODE_VALUE_CLOSE                  (54)
  24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET          (60)
  25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP               (61)
  26
  27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG             (1)
  28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG              (9)
  29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG              (14)
  30
  31 #define L5CM_RAMROD_CMD_ID_BASE                 (0x80)
  32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT          (L5CM_RAMROD_CMD_ID_BASE + 3)
  33 #define L5CM_RAMROD_CMD_ID_CLOSE                (L5CM_RAMROD_CMD_ID_BASE + 12)
  34 #define L5CM_RAMROD_CMD_ID_ABORT                (L5CM_RAMROD_CMD_ID_BASE + 13)
  35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE      (L5CM_RAMROD_CMD_ID_BASE + 14)
  36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD    (L5CM_RAMROD_CMD_ID_BASE + 15)
  37
  38 #define FCOE_RAMROD_CMD_ID_INIT_FUNC            (FCOE_KCQE_OPCODE_INIT_FUNC)
  39 #define FCOE_RAMROD_CMD_ID_DESTROY_FUNC         (FCOE_KCQE_OPCODE_DESTROY_FUNC)
  40 #define FCOE_RAMROD_CMD_ID_STAT_FUNC            (FCOE_KCQE_OPCODE_STAT_FUNC)
  41 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN         (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
  42 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN          (FCOE_KCQE_OPCODE_ENABLE_CONN)
  43 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN         (FCOE_KCQE_OPCODE_DISABLE_CONN)
  44 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN         (FCOE_KCQE_OPCODE_DESTROY_CONN)
  45 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN       (0x81)
  46
  47 /* KCQ (kernel completion queue) response op codes */
  48 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP             (53)
  49 #define L4_KCQE_OPCODE_VALUE_RESET_COMP             (54)
  50 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE          (55)
  51 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE       (56)
  52 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED         (57)
  53 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED         (58)
  54 #define L4_KCQE_OPCODE_VALUE_INIT_ULP               (61)
  55
  56 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG             (1)
  57 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG              (9)
  58 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG              (14)
  59
  60 /* KCQ (kernel completion queue) completion status */
  61 #define L4_KCQE_COMPLETION_STATUS_SUCCESS           (0)
  62 #define L4_KCQE_COMPLETION_STATUS_NIC_ERROR         (4)
  63 #define L4_KCQE_COMPLETION_STATUS_PARITY_ERROR      (0x81)
  64 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT           (0x93)
  65
  66 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL    (0x83)
  67 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG      (0x89)
  68
  69 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0)
  70 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH              (0xa1)
  71
  72 #define L4_LAYER_CODE (4)
  73 #define L2_LAYER_CODE (2)
  74
  75 /*
  76  * L4 KCQ CQE
  77  */
  78 struct l4_kcq {
  79         u32 cid;
  80         u32 pg_cid;
  81         u32 conn_id;
  82         u32 pg_host_opaque;
  83 #if defined(__BIG_ENDIAN)
  84         u16 status;
  85         u16 reserved1;
  86 #elif defined(__LITTLE_ENDIAN)
  87         u16 reserved1;
  88         u16 status;
  89 #endif
  90         u32 reserved2[2];
  91 #if defined(__BIG_ENDIAN)
  92         u8 flags;
  93 #define L4_KCQ_RESERVED3 (0x7<<0)
  94 #define L4_KCQ_RESERVED3_SHIFT 0
  95 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
  96 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
  97 #define L4_KCQ_LAYER_CODE (0x7<<4)
  98 #define L4_KCQ_LAYER_CODE_SHIFT 4
  99 #define L4_KCQ_RESERVED4 (0x1<<7)
 100 #define L4_KCQ_RESERVED4_SHIFT 7
 101         u8 op_code;
 102         u16 qe_self_seq;
 103 #elif defined(__LITTLE_ENDIAN)
 104         u16 qe_self_seq;
 105         u8 op_code;
 106         u8 flags;
 107 #define L4_KCQ_RESERVED3 (0xF<<0)
 108 #define L4_KCQ_RESERVED3_SHIFT 0
 109 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
 110 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
 111 #define L4_KCQ_LAYER_CODE (0x7<<4)
 112 #define L4_KCQ_LAYER_CODE_SHIFT 4
 113 #define L4_KCQ_RESERVED4 (0x1<<7)
 114 #define L4_KCQ_RESERVED4_SHIFT 7
 115 #endif
 116 };
 117
 118
 119 /*
 120  * L4 KCQ CQE PG upload
 121  */
 122 struct l4_kcq_upload_pg {
 123         u32 pg_cid;
 124 #if defined(__BIG_ENDIAN)
 125         u16 pg_status;
 126         u16 pg_ipid_count;
 127 #elif defined(__LITTLE_ENDIAN)
 128         u16 pg_ipid_count;
 129         u16 pg_status;
 130 #endif
 131         u32 reserved1[5];
 132 #if defined(__BIG_ENDIAN)
 133         u8 flags;
 134 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
 135 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
 136 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
 137 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
 138 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
 139 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
 140         u8 op_code;
 141         u16 qe_self_seq;
 142 #elif defined(__LITTLE_ENDIAN)
 143         u16 qe_self_seq;
 144         u8 op_code;
 145         u8 flags;
 146 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
 147 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
 148 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
 149 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
 150 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
 151 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
 152 #endif
 153 };
 154
 155
 156 /*
 157  * Gracefully close the connection request
 158  */
 159 struct l4_kwq_close_req {
 160 #if defined(__BIG_ENDIAN)
 161         u8 flags;
 162 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
 163 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
 164 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
 165 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
 166 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
 167 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
 168         u8 op_code;
 169         u16 reserved0;
 170 #elif defined(__LITTLE_ENDIAN)
 171         u16 reserved0;
 172         u8 op_code;
 173         u8 flags;
 174 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
 175 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
 176 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
 177 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
 178 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
 179 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
 180 #endif
 181         u32 cid;
 182         u32 reserved2[6];
 183 };
 184
 185
 186 /*
 187  * The first request to be passed in order to establish connection in option2
 188  */
 189 struct l4_kwq_connect_req1 {
 190 #if defined(__BIG_ENDIAN)
 191         u8 flags;
 192 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
 193 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
 194 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
 195 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
 196 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
 197 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
 198         u8 op_code;
 199         u8 reserved0;
 200         u8 conn_flags;
 201 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
 202 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
 203 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
 204 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
 205 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
 206 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
 207 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
 208 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
 209 #elif defined(__LITTLE_ENDIAN)
 210         u8 conn_flags;
 211 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
 212 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
 213 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
 214 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
 215 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
 216 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
 217 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
 218 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
 219         u8 reserved0;
 220         u8 op_code;
 221         u8 flags;
 222 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
 223 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
 224 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
 225 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
 226 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
 227 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
 228 #endif
 229         u32 cid;
 230         u32 pg_cid;
 231         u32 src_ip;
 232         u32 dst_ip;
 233 #if defined(__BIG_ENDIAN)
 234         u16 dst_port;
 235         u16 src_port;
 236 #elif defined(__LITTLE_ENDIAN)
 237         u16 src_port;
 238         u16 dst_port;
 239 #endif
 240 #if defined(__BIG_ENDIAN)
 241         u8 rsrv1[3];
 242         u8 tcp_flags;
 243 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
 244 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
 245 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
 246 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
 247 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
 248 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
 249 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
 250 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
 251 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
 252 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
 253 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
 254 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
 255 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
 256 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
 257 #elif defined(__LITTLE_ENDIAN)
 258         u8 tcp_flags;
 259 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
 260 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
 261 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
 262 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
 263 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
 264 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
 265 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
 266 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
 267 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
 268 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
 269 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
 270 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
 271 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
 272 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
 273         u8 rsrv1[3];
 274 #endif
 275         u32 rsrv2;
 276 };
 277
 278
 279 /*
 280  * The second ( optional )request to be passed in order to establish
 281  * connection in option2 - for IPv6 only
 282  */
 283 struct l4_kwq_connect_req2 {
 284 #if defined(__BIG_ENDIAN)
 285         u8 flags;
 286 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
 287 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
 288 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
 289 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
 290 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
 291 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
 292         u8 op_code;
 293         u8 reserved0;
 294         u8 rsrv;
 295 #elif defined(__LITTLE_ENDIAN)
 296         u8 rsrv;
 297         u8 reserved0;
 298         u8 op_code;
 299         u8 flags;
 300 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
 301 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
 302 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
 303 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
 304 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
 305 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
 306 #endif
 307         u32 reserved2;
 308         u32 src_ip_v6_2;
 309         u32 src_ip_v6_3;
 310         u32 src_ip_v6_4;
 311         u32 dst_ip_v6_2;
 312         u32 dst_ip_v6_3;
 313         u32 dst_ip_v6_4;
 314 };
 315
 316
 317 /*
 318  * The third ( and last )request to be passed in order to establish
 319  * connection in option2
 320  */
 321 struct l4_kwq_connect_req3 {
 322 #if defined(__BIG_ENDIAN)
 323         u8 flags;
 324 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
 325 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
 326 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
 327 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
 328 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
 329 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
 330         u8 op_code;
 331         u16 reserved0;
 332 #elif defined(__LITTLE_ENDIAN)
 333         u16 reserved0;
 334         u8 op_code;
 335         u8 flags;
 336 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
 337 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
 338 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
 339 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
 340 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
 341 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
 342 #endif
 343         u32 ka_timeout;
 344         u32 ka_interval ;
 345 #if defined(__BIG_ENDIAN)
 346         u8 snd_seq_scale;
 347         u8 ttl;
 348         u8 tos;
 349         u8 ka_max_probe_count;
 350 #elif defined(__LITTLE_ENDIAN)
 351         u8 ka_max_probe_count;
 352         u8 tos;
 353         u8 ttl;
 354         u8 snd_seq_scale;
 355 #endif
 356 #if defined(__BIG_ENDIAN)
 357         u16 pmtu;
 358         u16 mss;
 359 #elif defined(__LITTLE_ENDIAN)
 360         u16 mss;
 361         u16 pmtu;
 362 #endif
 363         u32 rcv_buf;
 364         u32 snd_buf;
 365         u32 seed;
 366 };
 367
 368
 369 /*
 370  * a KWQE request to offload a PG connection
 371  */
 372 struct l4_kwq_offload_pg {
 373 #if defined(__BIG_ENDIAN)
 374         u8 flags;
 375 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
 376 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
 377 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
 378 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
 379 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
 380 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
 381         u8 op_code;
 382         u16 reserved0;
 383 #elif defined(__LITTLE_ENDIAN)
 384         u16 reserved0;
 385         u8 op_code;
 386         u8 flags;
 387 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
 388 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
 389 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
 390 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
 391 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
 392 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
 393 #endif
 394 #if defined(__BIG_ENDIAN)
 395         u8 l2hdr_nbytes;
 396         u8 pg_flags;
 397 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
 398 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
 399 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
 400 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
 401 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
 402 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
 403         u8 da0;
 404         u8 da1;
 405 #elif defined(__LITTLE_ENDIAN)
 406         u8 da1;
 407         u8 da0;
 408         u8 pg_flags;
 409 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
 410 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
 411 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
 412 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
 413 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
 414 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
 415         u8 l2hdr_nbytes;
 416 #endif
 417 #if defined(__BIG_ENDIAN)
 418         u8 da2;
 419         u8 da3;
 420         u8 da4;
 421         u8 da5;
 422 #elif defined(__LITTLE_ENDIAN)
 423         u8 da5;
 424         u8 da4;
 425         u8 da3;
 426         u8 da2;
 427 #endif
 428 #if defined(__BIG_ENDIAN)
 429         u8 sa0;
 430         u8 sa1;
 431         u8 sa2;
 432         u8 sa3;
 433 #elif defined(__LITTLE_ENDIAN)
 434         u8 sa3;
 435         u8 sa2;
 436         u8 sa1;
 437         u8 sa0;
 438 #endif
 439 #if defined(__BIG_ENDIAN)
 440         u8 sa4;
 441         u8 sa5;
 442         u16 etype;
 443 #elif defined(__LITTLE_ENDIAN)
 444         u16 etype;
 445         u8 sa5;
 446         u8 sa4;
 447 #endif
 448 #if defined(__BIG_ENDIAN)
 449         u16 vlan_tag;
 450         u16 ipid_start;
 451 #elif defined(__LITTLE_ENDIAN)
 452         u16 ipid_start;
 453         u16 vlan_tag;
 454 #endif
 455 #if defined(__BIG_ENDIAN)
 456         u16 ipid_count;
 457         u16 reserved3;
 458 #elif defined(__LITTLE_ENDIAN)
 459         u16 reserved3;
 460         u16 ipid_count;
 461 #endif
 462         u32 host_opaque;
 463 };
 464
 465
 466 /*
 467  * Abortively close the connection request
 468  */
 469 struct l4_kwq_reset_req {
 470 #if defined(__BIG_ENDIAN)
 471         u8 flags;
 472 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
 473 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
 474 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
 475 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
 476 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
 477 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
 478         u8 op_code;
 479         u16 reserved0;
 480 #elif defined(__LITTLE_ENDIAN)
 481         u16 reserved0;
 482         u8 op_code;
 483         u8 flags;
 484 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
 485 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
 486 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
 487 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
 488 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
 489 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
 490 #endif
 491         u32 cid;
 492         u32 reserved2[6];
 493 };
 494
 495
 496 /*
 497  * a KWQE request to update a PG connection
 498  */
 499 struct l4_kwq_update_pg {
 500 #if defined(__BIG_ENDIAN)
 501         u8 flags;
 502 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
 503 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
 504 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
 505 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
 506 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
 507 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
 508         u8 opcode;
 509         u16 oper16;
 510 #elif defined(__LITTLE_ENDIAN)
 511         u16 oper16;
 512         u8 opcode;
 513         u8 flags;
 514 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
 515 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
 516 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
 517 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
 518 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
 519 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
 520 #endif
 521         u32 pg_cid;
 522         u32 pg_host_opaque;
 523 #if defined(__BIG_ENDIAN)
 524         u8 pg_valids;
 525 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
 526 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
 527 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
 528 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
 529 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
 530 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
 531         u8 pg_unused_a;
 532         u16 pg_ipid_count;
 533 #elif defined(__LITTLE_ENDIAN)
 534         u16 pg_ipid_count;
 535         u8 pg_unused_a;
 536         u8 pg_valids;
 537 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
 538 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
 539 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
 540 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
 541 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
 542 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
 543 #endif
 544 #if defined(__BIG_ENDIAN)
 545         u16 reserverd3;
 546         u8 da0;
 547         u8 da1;
 548 #elif defined(__LITTLE_ENDIAN)
 549         u8 da1;
 550         u8 da0;
 551         u16 reserverd3;
 552 #endif
 553 #if defined(__BIG_ENDIAN)
 554         u8 da2;
 555         u8 da3;
 556         u8 da4;
 557         u8 da5;
 558 #elif defined(__LITTLE_ENDIAN)
 559         u8 da5;
 560         u8 da4;
 561         u8 da3;
 562         u8 da2;
 563 #endif
 564         u32 reserved4;
 565         u32 reserved5;
 566 };
 567
 568
 569 /*
 570  * a KWQE request to upload a PG or L4 context
 571  */
 572 struct l4_kwq_upload {
 573 #if defined(__BIG_ENDIAN)
 574         u8 flags;
 575 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
 576 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
 577 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
 578 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
 579 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
 580 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
 581         u8 opcode;
 582         u16 oper16;
 583 #elif defined(__LITTLE_ENDIAN)
 584         u16 oper16;
 585         u8 opcode;
 586         u8 flags;
 587 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
 588 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
 589 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
 590 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
 591 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
 592 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
 593 #endif
 594         u32 cid;
 595         u32 reserved2[6];
 596 };
 597
 598 /*
 599  * bnx2x structures
 600  */
 601
 602 /*
 603  * The iscsi aggregative context of Cstorm
 604  */
 605 struct cstorm_iscsi_ag_context {
 606         u32 agg_vars1;
 607 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0)
 608 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
 609 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8)
 610 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
 611 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9)
 612 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
 613 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10)
 614 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
 615 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11)
 616 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
 617 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12)
 618 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
 619 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13)
 620 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
 621 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14)
 622 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
 623 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16)
 624 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
 625 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18)
 626 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
 627 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19)
 628 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
 629 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20)
 630 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
 631 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21)
 632 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
 633 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22)
 634 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
 635 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23)
 636 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
 637 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26)
 638 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
 639 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28)
 640 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
 641 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30)
 642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
 643 #if defined(__BIG_ENDIAN)
 644         u8 __aux1_th;
 645         u8 __aux1_val;
 646         u16 __agg_vars2;
 647 #elif defined(__LITTLE_ENDIAN)
 648         u16 __agg_vars2;
 649         u8 __aux1_val;
 650         u8 __aux1_th;
 651 #endif
 652         u32 rel_seq;
 653         u32 rel_seq_th;
 654 #if defined(__BIG_ENDIAN)
 655         u16 hq_cons;
 656         u16 hq_prod;
 657 #elif defined(__LITTLE_ENDIAN)
 658         u16 hq_prod;
 659         u16 hq_cons;
 660 #endif
 661 #if defined(__BIG_ENDIAN)
 662         u8 __reserved62;
 663         u8 __reserved61;
 664         u8 __reserved60;
 665         u8 __reserved59;
 666 #elif defined(__LITTLE_ENDIAN)
 667         u8 __reserved59;
 668         u8 __reserved60;
 669         u8 __reserved61;
 670         u8 __reserved62;
 671 #endif
 672 #if defined(__BIG_ENDIAN)
 673         u16 __reserved64;
 674         u16 cq_u_prod;
 675 #elif defined(__LITTLE_ENDIAN)
 676         u16 cq_u_prod;
 677         u16 __reserved64;
 678 #endif
 679         u32 __cq_u_prod1;
 680 #if defined(__BIG_ENDIAN)
 681         u16 __agg_vars3;
 682         u16 cq_u_pend;
 683 #elif defined(__LITTLE_ENDIAN)
 684         u16 cq_u_pend;
 685         u16 __agg_vars3;
 686 #endif
 687 #if defined(__BIG_ENDIAN)
 688         u16 __aux2_th;
 689         u16 aux2_val;
 690 #elif defined(__LITTLE_ENDIAN)
 691         u16 aux2_val;
 692         u16 __aux2_th;
 693 #endif
 694 };
 695
 696 /*
 697  * The fcoe extra aggregative context section of Tstorm
 698  */
 699 struct tstorm_fcoe_extra_ag_context_section {
 700         u32 __agg_val1;
 701 #if defined(__BIG_ENDIAN)
 702         u8 __tcp_agg_vars2;
 703         u8 __agg_val3;
 704         u16 __agg_val2;
 705 #elif defined(__LITTLE_ENDIAN)
 706         u16 __agg_val2;
 707         u8 __agg_val3;
 708         u8 __tcp_agg_vars2;
 709 #endif
 710 #if defined(__BIG_ENDIAN)
 711         u16 __agg_val5;
 712         u8 __agg_val6;
 713         u8 __tcp_agg_vars3;
 714 #elif defined(__LITTLE_ENDIAN)
 715         u8 __tcp_agg_vars3;
 716         u8 __agg_val6;
 717         u16 __agg_val5;
 718 #endif
 719         u32 __lcq_prod;
 720         u32 rtt_seq;
 721         u32 rtt_time;
 722         u32 __reserved66;
 723         u32 wnd_right_edge;
 724         u32 tcp_agg_vars1;
 725 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
 726 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
 727 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
 728 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
 729 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
 730 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
 731 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
 732 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
 733 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
 734 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
 735 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
 736 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
 737 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
 738 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
 739 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
 740 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
 741 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
 742 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
 743 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
 744 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
 745 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
 746 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
 747 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
 748 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
 749 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
 750 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
 751 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
 752 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
 753 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
 754 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
 755 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
 756 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
 757 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
 758 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
 759 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
 760 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
 761 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
 762 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
 763 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
 764 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
 765 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
 766 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
 767         u32 snd_max;
 768         u32 __lcq_cons;
 769         u32 __reserved2;
 770 };
 771
 772 /*
 773  * The fcoe aggregative context of Tstorm
 774  */
 775 struct tstorm_fcoe_ag_context {
 776 #if defined(__BIG_ENDIAN)
 777         u16 ulp_credit;
 778         u8 agg_vars1;
 779 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 780 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 781 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 782 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 783 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 784 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 785 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 786 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 787 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
 788 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
 789 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 790 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 791 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
 792 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
 793         u8 state;
 794 #elif defined(__LITTLE_ENDIAN)
 795         u8 state;
 796         u8 agg_vars1;
 797 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 798 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 799 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 800 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 801 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 802 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 803 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 804 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 805 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
 806 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
 807 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 808 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 809 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
 810 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
 811         u16 ulp_credit;
 812 #endif
 813 #if defined(__BIG_ENDIAN)
 814         u16 __agg_val4;
 815         u16 agg_vars2;
 816 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
 817 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
 818 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
 819 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
 820 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
 821 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
 822 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
 823 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
 824 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
 825 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
 826 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
 827 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
 828 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
 829 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
 830 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
 831 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
 832 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
 833 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
 834 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
 835 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
 836 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
 837 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
 838 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
 839 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
 840 #elif defined(__LITTLE_ENDIAN)
 841         u16 agg_vars2;
 842 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
 843 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
 844 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
 845 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
 846 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
 847 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
 848 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
 849 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
 850 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
 851 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
 852 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
 853 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
 854 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
 855 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
 856 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
 857 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
 858 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
 859 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
 860 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
 861 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
 862 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
 863 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
 864 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
 865 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
 866         u16 __agg_val4;
 867 #endif
 868         struct tstorm_fcoe_extra_ag_context_section __extra_section;
 869 };
 870
 871
 872
 873 /*
 874  * The tcp aggregative context section of Tstorm
 875  */
 876 struct tstorm_tcp_tcp_ag_context_section {
 877         u32 __agg_val1;
 878 #if defined(__BIG_ENDIAN)
 879         u8 __tcp_agg_vars2;
 880         u8 __agg_val3;
 881         u16 __agg_val2;
 882 #elif defined(__LITTLE_ENDIAN)
 883         u16 __agg_val2;
 884         u8 __agg_val3;
 885         u8 __tcp_agg_vars2;
 886 #endif
 887 #if defined(__BIG_ENDIAN)
 888         u16 __agg_val5;
 889         u8 __agg_val6;
 890         u8 __tcp_agg_vars3;
 891 #elif defined(__LITTLE_ENDIAN)
 892         u8 __tcp_agg_vars3;
 893         u8 __agg_val6;
 894         u16 __agg_val5;
 895 #endif
 896         u32 snd_nxt;
 897         u32 rtt_seq;
 898         u32 rtt_time;
 899         u32 __reserved66;
 900         u32 wnd_right_edge;
 901         u32 tcp_agg_vars1;
 902 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
 903 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
 904 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
 905 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
 906 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
 907 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
 908 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
 909 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
 910 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
 911 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
 912 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
 913 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
 914 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
 915 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
 916 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
 917 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
 918 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
 919 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
 920 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
 921 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
 922 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
 923 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
 924 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
 925 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
 926 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
 927 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
 928 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
 929 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
 930 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
 931 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
 932 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
 933 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
 934 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
 935 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
 936 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
 937 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
 938 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
 939 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
 940 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
 941 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
 942 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
 943 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
 944         u32 snd_max;
 945         u32 snd_una;
 946         u32 __reserved2;
 947 };
 948
 949 /*
 950  * The iscsi aggregative context of Tstorm
 951  */
 952 struct tstorm_iscsi_ag_context {
 953 #if defined(__BIG_ENDIAN)
 954         u16 ulp_credit;
 955         u8 agg_vars1;
 956 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 957 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 958 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 959 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 960 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 961 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 962 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 963 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 964 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
 965 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
 966 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 967 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 968 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
 969 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
 970         u8 state;
 971 #elif defined(__LITTLE_ENDIAN)
 972         u8 state;
 973         u8 agg_vars1;
 974 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 975 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 976 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 977 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 978 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 979 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 980 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 981 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 982 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
 983 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
 984 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 985 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 986 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
 987 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
 988         u16 ulp_credit;
 989 #endif
 990 #if defined(__BIG_ENDIAN)
 991         u16 __agg_val4;
 992         u16 agg_vars2;
 993 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
 994 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
 995 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
 996 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
 997 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
 998 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
 999 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1000 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1001 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1002 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1003 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1004 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1005 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1006 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1007 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1008 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1009 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1010 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1011 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1012 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1013 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1014 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1015 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1016 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1017 #elif defined(__LITTLE_ENDIAN)
1018         u16 agg_vars2;
1019 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
1020 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
1021 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
1022 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
1023 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
1024 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
1025 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1026 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1027 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1028 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1029 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1030 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1031 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1032 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1033 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1034 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1035 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1036 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1037 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1038 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1039 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1040 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1041 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1042 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1043         u16 __agg_val4;
1044 #endif
1045         struct tstorm_tcp_tcp_ag_context_section tcp;
1046 };
1047
1048
1049
1050 /*
1051  * The fcoe aggregative context of Ustorm
1052  */
1053 struct ustorm_fcoe_ag_context {
1054 #if defined(__BIG_ENDIAN)
1055         u8 __aux_counter_flags;
1056         u8 agg_vars2;
1057 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1058 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1059 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1060 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1061 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1062 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1063 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1064 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1065         u8 agg_vars1;
1066 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1067 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1068 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1069 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1070 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1071 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1072 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1073 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1074 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1075 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1076 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1077 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1078         u8 state;
1079 #elif defined(__LITTLE_ENDIAN)
1080         u8 state;
1081         u8 agg_vars1;
1082 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1083 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1084 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1085 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1086 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1087 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1088 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1089 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1090 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1091 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1092 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1093 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1094         u8 agg_vars2;
1095 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1096 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1097 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1098 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1099 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1100 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1101 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1102 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1103         u8 __aux_counter_flags;
1104 #endif
1105 #if defined(__BIG_ENDIAN)
1106         u8 cdu_usage;
1107         u8 agg_misc2;
1108         u16 pbf_tx_seq_ack;
1109 #elif defined(__LITTLE_ENDIAN)
1110         u16 pbf_tx_seq_ack;
1111         u8 agg_misc2;
1112         u8 cdu_usage;
1113 #endif
1114         u32 agg_misc4;
1115 #if defined(__BIG_ENDIAN)
1116         u8 agg_val3_th;
1117         u8 agg_val3;
1118         u16 agg_misc3;
1119 #elif defined(__LITTLE_ENDIAN)
1120         u16 agg_misc3;
1121         u8 agg_val3;
1122         u8 agg_val3_th;
1123 #endif
1124         u32 expired_task_id;
1125         u32 agg_misc4_th;
1126 #if defined(__BIG_ENDIAN)
1127         u16 cq_prod;
1128         u16 cq_cons;
1129 #elif defined(__LITTLE_ENDIAN)
1130         u16 cq_cons;
1131         u16 cq_prod;
1132 #endif
1133 #if defined(__BIG_ENDIAN)
1134         u16 __reserved2;
1135         u8 decision_rules;
1136 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1137 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1138 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1139 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1140 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1141 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1142 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1143 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1144         u8 decision_rule_enable_bits;
1145 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1146 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1147 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1148 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1149 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1150 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1151 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1152 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1153 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1154 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1155 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1156 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1157 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1158 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1159 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1160 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1161 #elif defined(__LITTLE_ENDIAN)
1162         u8 decision_rule_enable_bits;
1163 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1164 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1165 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1166 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1167 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1168 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1169 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1170 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1171 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1172 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1173 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1174 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1175 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1176 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1177 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1178 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1179         u8 decision_rules;
1180 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1181 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1182 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1183 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1184 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1185 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1186 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1187 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1188         u16 __reserved2;
1189 #endif
1190 };
1191
1192
1193 /*
1194  * The iscsi aggregative context of Ustorm
1195  */
1196 struct ustorm_iscsi_ag_context {
1197 #if defined(__BIG_ENDIAN)
1198         u8 __aux_counter_flags;
1199         u8 agg_vars2;
1200 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1201 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1202 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1203 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1204 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1205 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1206 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1207 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1208         u8 agg_vars1;
1209 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1210 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1211 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1212 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1213 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1214 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1215 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1216 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1217 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1218 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1219 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1220 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1221         u8 state;
1222 #elif defined(__LITTLE_ENDIAN)
1223         u8 state;
1224         u8 agg_vars1;
1225 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1226 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1227 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1228 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1229 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1230 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1231 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1232 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1233 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1234 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1235 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1236 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1237         u8 agg_vars2;
1238 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1239 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1240 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1241 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1242 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1243 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1244 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1245 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1246         u8 __aux_counter_flags;
1247 #endif
1248 #if defined(__BIG_ENDIAN)
1249         u8 cdu_usage;
1250         u8 agg_misc2;
1251         u16 __cq_local_comp_itt_val;
1252 #elif defined(__LITTLE_ENDIAN)
1253         u16 __cq_local_comp_itt_val;
1254         u8 agg_misc2;
1255         u8 cdu_usage;
1256 #endif
1257         u32 agg_misc4;
1258 #if defined(__BIG_ENDIAN)
1259         u8 agg_val3_th;
1260         u8 agg_val3;
1261         u16 agg_misc3;
1262 #elif defined(__LITTLE_ENDIAN)
1263         u16 agg_misc3;
1264         u8 agg_val3;
1265         u8 agg_val3_th;
1266 #endif
1267         u32 agg_val1;
1268         u32 agg_misc4_th;
1269 #if defined(__BIG_ENDIAN)
1270         u16 agg_val2_th;
1271         u16 agg_val2;
1272 #elif defined(__LITTLE_ENDIAN)
1273         u16 agg_val2;
1274         u16 agg_val2_th;
1275 #endif
1276 #if defined(__BIG_ENDIAN)
1277         u16 __reserved2;
1278         u8 decision_rules;
1279 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1280 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1281 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1282 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1283 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1284 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1285 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1286 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1287         u8 decision_rule_enable_bits;
1288 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1289 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1290 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1291 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1292 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1293 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1294 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1295 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1296 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1297 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1298 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1299 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1300 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1301 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1302 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1303 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1304 #elif defined(__LITTLE_ENDIAN)
1305         u8 decision_rule_enable_bits;
1306 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1307 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1308 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1309 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1310 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1311 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1312 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1313 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1314 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1315 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1316 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1317 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1318 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1319 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1320 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1321 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1322         u8 decision_rules;
1323 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1324 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1325 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1326 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1327 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1328 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1329 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1330 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1331         u16 __reserved2;
1332 #endif
1333 };
1334
1335
1336 /*
1337  * The fcoe aggregative context section of Xstorm
1338  */
1339 struct xstorm_fcoe_extra_ag_context_section {
1340 #if defined(__BIG_ENDIAN)
1341         u8 tcp_agg_vars1;
1342 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1343 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1344 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1345 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1346 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1347 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1348 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1349 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1350 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1351 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1352         u8 __reserved_da_cnt;
1353         u16 __mtu;
1354 #elif defined(__LITTLE_ENDIAN)
1355         u16 __mtu;
1356         u8 __reserved_da_cnt;
1357         u8 tcp_agg_vars1;
1358 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1359 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1360 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1361 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1362 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1363 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1364 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1365 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1366 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1367 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1368 #endif
1369         u32 snd_nxt;
1370         u32 __xfrqe_bd_addr_lo;
1371         u32 __xfrqe_bd_addr_hi;
1372         u32 __xfrqe_data1;
1373 #if defined(__BIG_ENDIAN)
1374         u8 __agg_val8_th;
1375         u8 __tx_dest;
1376         u16 tcp_agg_vars2;
1377 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1378 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1379 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1380 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1381 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1382 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1383 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1384 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1385 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1386 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1387 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1388 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1389 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1390 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1391 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1392 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1393 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1394 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1395 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1396 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1397 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1398 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1399 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1400 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1401 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1402 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1403 #elif defined(__LITTLE_ENDIAN)
1404         u16 tcp_agg_vars2;
1405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1407 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1408 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1409 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1410 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1415 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1416 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1417 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1418 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1419 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1420 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1423 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1424 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1425 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1426 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1427 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1428 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1429 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1430 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1431         u8 __tx_dest;
1432         u8 __agg_val8_th;
1433 #endif
1434         u32 __sq_base_addr_lo;
1435         u32 __sq_base_addr_hi;
1436         u32 __xfrq_base_addr_lo;
1437         u32 __xfrq_base_addr_hi;
1438 #if defined(__BIG_ENDIAN)
1439         u16 __xfrq_cons;
1440         u16 __xfrq_prod;
1441 #elif defined(__LITTLE_ENDIAN)
1442         u16 __xfrq_prod;
1443         u16 __xfrq_cons;
1444 #endif
1445 #if defined(__BIG_ENDIAN)
1446         u8 __tcp_agg_vars5;
1447         u8 __tcp_agg_vars4;
1448         u8 __tcp_agg_vars3;
1449         u8 __reserved_force_pure_ack_cnt;
1450 #elif defined(__LITTLE_ENDIAN)
1451         u8 __reserved_force_pure_ack_cnt;
1452         u8 __tcp_agg_vars3;
1453         u8 __tcp_agg_vars4;
1454         u8 __tcp_agg_vars5;
1455 #endif
1456         u32 __tcp_agg_vars6;
1457 #if defined(__BIG_ENDIAN)
1458         u16 __xfrqe_mng;
1459         u16 __tcp_agg_vars7;
1460 #elif defined(__LITTLE_ENDIAN)
1461         u16 __tcp_agg_vars7;
1462         u16 __xfrqe_mng;
1463 #endif
1464         u32 __xfrqe_data0;
1465         u32 __agg_val10_th;
1466 #if defined(__BIG_ENDIAN)
1467         u16 __reserved3;
1468         u8 __reserved2;
1469         u8 __da_only_cnt;
1470 #elif defined(__LITTLE_ENDIAN)
1471         u8 __da_only_cnt;
1472         u8 __reserved2;
1473         u16 __reserved3;
1474 #endif
1475 };
1476
1477 /*
1478  * The fcoe aggregative context of Xstorm
1479  */
1480 struct xstorm_fcoe_ag_context {
1481 #if defined(__BIG_ENDIAN)
1482         u16 agg_val1;
1483         u8 agg_vars1;
1484 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1485 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1486 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1487 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1488 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1489 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1490 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1491 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1492 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1493 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1494 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1495 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1496 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1497 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1498 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1499 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1500         u8 __state;
1501 #elif defined(__LITTLE_ENDIAN)
1502         u8 __state;
1503         u8 agg_vars1;
1504 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1505 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1506 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1507 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1508 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1509 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1510 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1511 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1512 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1513 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1514 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1515 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1516 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1517 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1518 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1519 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1520         u16 agg_val1;
1521 #endif
1522 #if defined(__BIG_ENDIAN)
1523         u8 cdu_reserved;
1524         u8 __agg_vars4;
1525         u8 agg_vars3;
1526 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1527 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1528 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1529 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1530         u8 agg_vars2;
1531 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1532 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1533 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1534 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1535 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1536 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1537 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1538 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1539 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1540 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1541 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1542 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1543 #elif defined(__LITTLE_ENDIAN)
1544         u8 agg_vars2;
1545 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1546 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1547 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1548 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1549 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1550 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1551 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1552 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1553 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1554 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1555 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1556 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1557         u8 agg_vars3;
1558 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1559 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1560 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1561 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1562         u8 __agg_vars4;
1563         u8 cdu_reserved;
1564 #endif
1565         u32 more_to_send;
1566 #if defined(__BIG_ENDIAN)
1567         u16 agg_vars5;
1568 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1569 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1570 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1571 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1572 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1573 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1574 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1575 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1576         u16 sq_cons;
1577 #elif defined(__LITTLE_ENDIAN)
1578         u16 sq_cons;
1579         u16 agg_vars5;
1580 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1581 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1582 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1583 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1584 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1585 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1586 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1587 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1588 #endif
1589         struct xstorm_fcoe_extra_ag_context_section __extra_section;
1590 #if defined(__BIG_ENDIAN)
1591         u16 agg_vars7;
1592 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1593 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1594 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1595 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1596 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1597 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1598 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1599 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1600 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1601 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1602 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1603 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1604 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1605 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1606 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1607 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1608 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1609 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1610 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1611 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1612 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1613 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1614         u8 agg_val3_th;
1615         u8 agg_vars6;
1616 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1617 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1618 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1619 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1620 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1621 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1622 #elif defined(__LITTLE_ENDIAN)
1623         u8 agg_vars6;
1624 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1625 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1626 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1627 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1628 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1629 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1630         u8 agg_val3_th;
1631         u16 agg_vars7;
1632 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1633 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1634 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1635 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1636 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1637 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1638 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1639 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1640 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1641 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1642 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1643 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1644 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1645 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1646 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1647 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1648 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1649 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1650 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1651 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1652 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1653 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1654 #endif
1655 #if defined(__BIG_ENDIAN)
1656         u16 __agg_val11_th;
1657         u16 __agg_val11;
1658 #elif defined(__LITTLE_ENDIAN)
1659         u16 __agg_val11;
1660         u16 __agg_val11_th;
1661 #endif
1662 #if defined(__BIG_ENDIAN)
1663         u8 __reserved1;
1664         u8 __agg_val6_th;
1665         u16 __agg_val9;
1666 #elif defined(__LITTLE_ENDIAN)
1667         u16 __agg_val9;
1668         u8 __agg_val6_th;
1669         u8 __reserved1;
1670 #endif
1671 #if defined(__BIG_ENDIAN)
1672         u16 confq_cons;
1673         u16 confq_prod;
1674 #elif defined(__LITTLE_ENDIAN)
1675         u16 confq_prod;
1676         u16 confq_cons;
1677 #endif
1678         u32 agg_vars8;
1679 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
1680 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
1681 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
1682 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
1683 #if defined(__BIG_ENDIAN)
1684         u16 __cache_wqe_db;
1685         u16 sq_prod;
1686 #elif defined(__LITTLE_ENDIAN)
1687         u16 sq_prod;
1688         u16 __cache_wqe_db;
1689 #endif
1690 #if defined(__BIG_ENDIAN)
1691         u8 agg_val3;
1692         u8 agg_val6;
1693         u8 agg_val5_th;
1694         u8 agg_val5;
1695 #elif defined(__LITTLE_ENDIAN)
1696         u8 agg_val5;
1697         u8 agg_val5_th;
1698         u8 agg_val6;
1699         u8 agg_val3;
1700 #endif
1701 #if defined(__BIG_ENDIAN)
1702         u16 __agg_misc1;
1703         u16 agg_limit1;
1704 #elif defined(__LITTLE_ENDIAN)
1705         u16 agg_limit1;
1706         u16 __agg_misc1;
1707 #endif
1708         u32 completion_seq;
1709         u32 confq_pbl_base_lo;
1710         u32 confq_pbl_base_hi;
1711 };
1712
1713
1714
1715 /*
1716  * The tcp aggregative context section of Xstorm
1717  */
1718 struct xstorm_tcp_tcp_ag_context_section {
1719 #if defined(__BIG_ENDIAN)
1720         u8 tcp_agg_vars1;
1721 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1722 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1723 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1724 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1725 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1726 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1727 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1728 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1729 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1730 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1731         u8 __da_cnt;
1732         u16 mss;
1733 #elif defined(__LITTLE_ENDIAN)
1734         u16 mss;
1735         u8 __da_cnt;
1736         u8 tcp_agg_vars1;
1737 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1738 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1739 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1740 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1741 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1742 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1743 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1744 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1745 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1746 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1747 #endif
1748         u32 snd_nxt;
1749         u32 tx_wnd;
1750         u32 snd_una;
1751         u32 local_adv_wnd;
1752 #if defined(__BIG_ENDIAN)
1753         u8 __agg_val8_th;
1754         u8 __tx_dest;
1755         u16 tcp_agg_vars2;
1756 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1757 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1758 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1759 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1760 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1761 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1762 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1763 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1764 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1765 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1766 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1767 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1768 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1769 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1770 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1771 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1772 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1773 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1774 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1775 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1776 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1777 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1778 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1779 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1780 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1781 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1782 #elif defined(__LITTLE_ENDIAN)
1783         u16 tcp_agg_vars2;
1784 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1785 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1787 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1788 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1789 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1790 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1791 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1792 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1794 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1795 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1796 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1797 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1798 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1799 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1803 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1804 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1805 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1806 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1807 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1808 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1809 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1810         u8 __tx_dest;
1811         u8 __agg_val8_th;
1812 #endif
1813         u32 ack_to_far_end;
1814         u32 rto_timer;
1815         u32 ka_timer;
1816         u32 ts_to_echo;
1817 #if defined(__BIG_ENDIAN)
1818         u16 __agg_val7_th;
1819         u16 __agg_val7;
1820 #elif defined(__LITTLE_ENDIAN)
1821         u16 __agg_val7;
1822         u16 __agg_val7_th;
1823 #endif
1824 #if defined(__BIG_ENDIAN)
1825         u8 __tcp_agg_vars5;
1826         u8 __tcp_agg_vars4;
1827         u8 __tcp_agg_vars3;
1828         u8 __force_pure_ack_cnt;
1829 #elif defined(__LITTLE_ENDIAN)
1830         u8 __force_pure_ack_cnt;
1831         u8 __tcp_agg_vars3;
1832         u8 __tcp_agg_vars4;
1833         u8 __tcp_agg_vars5;
1834 #endif
1835         u32 tcp_agg_vars6;
1836 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
1837 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
1838 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
1839 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
1840 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
1841 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
1842 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
1843 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
1844 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
1845 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
1846 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
1847 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
1848 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
1849 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
1850 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
1851 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
1852 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
1853 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
1854 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
1855 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
1856 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
1857 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
1858 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
1859 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
1860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
1861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
1862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
1863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
1864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
1865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
1866 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
1867 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
1868 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
1869 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
1870 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
1871 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
1872 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
1873 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
1874 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
1875 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
1876 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
1877 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
1878 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
1879 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
1880 #if defined(__BIG_ENDIAN)
1881         u16 __agg_misc6;
1882         u16 __tcp_agg_vars7;
1883 #elif defined(__LITTLE_ENDIAN)
1884         u16 __tcp_agg_vars7;
1885         u16 __agg_misc6;
1886 #endif
1887         u32 __agg_val10;
1888         u32 __agg_val10_th;
1889 #if defined(__BIG_ENDIAN)
1890         u16 __reserved3;
1891         u8 __reserved2;
1892         u8 __da_only_cnt;
1893 #elif defined(__LITTLE_ENDIAN)
1894         u8 __da_only_cnt;
1895         u8 __reserved2;
1896         u16 __reserved3;
1897 #endif
1898 };
1899
1900 /*
1901  * The iscsi aggregative context of Xstorm
1902  */
1903 struct xstorm_iscsi_ag_context {
1904 #if defined(__BIG_ENDIAN)
1905         u16 agg_val1;
1906         u8 agg_vars1;
1907 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1908 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1909 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1910 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1911 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1912 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1913 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1914 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1915 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1916 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1917 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1918 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1919 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1920 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1921 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1922 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1923         u8 state;
1924 #elif defined(__LITTLE_ENDIAN)
1925         u8 state;
1926         u8 agg_vars1;
1927 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1928 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1929 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1930 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1931 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1932 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1933 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1934 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1935 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1936 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1937 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1938 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1939 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1940 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1941 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1942 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1943         u16 agg_val1;
1944 #endif
1945 #if defined(__BIG_ENDIAN)
1946         u8 cdu_reserved;
1947         u8 __agg_vars4;
1948         u8 agg_vars3;
1949 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1950 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1951 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
1952 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
1953         u8 agg_vars2;
1954 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1955 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1956 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1957 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1958 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1959 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1960 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1961 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1962 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1963 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1964 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1965 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1966 #elif defined(__LITTLE_ENDIAN)
1967         u8 agg_vars2;
1968 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1969 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1970 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1971 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1972 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1973 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1974 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1975 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1976 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1977 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1978 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1979 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1980         u8 agg_vars3;
1981 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1982 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1983 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
1984 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
1985         u8 __agg_vars4;
1986         u8 cdu_reserved;
1987 #endif
1988         u32 more_to_send;
1989 #if defined(__BIG_ENDIAN)
1990         u16 agg_vars5;
1991 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1992 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1993 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1994 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1995 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1996 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1997 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
1998 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
1999         u16 sq_cons;
2000 #elif defined(__LITTLE_ENDIAN)
2001         u16 sq_cons;
2002         u16 agg_vars5;
2003 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2004 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2005 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2006 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2007 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2008 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2009 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2010 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2011 #endif
2012         struct xstorm_tcp_tcp_ag_context_section tcp;
2013 #if defined(__BIG_ENDIAN)
2014         u16 agg_vars7;
2015 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2016 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2017 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2018 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2019 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2020 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2021 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2022 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2023 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2024 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2025 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2026 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2027 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2028 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2029 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2030 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2031 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2032 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2033 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2034 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2035 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2036 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2037         u8 agg_val3_th;
2038         u8 agg_vars6;
2039 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2040 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2041 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2042 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2043 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2044 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2045 #elif defined(__LITTLE_ENDIAN)
2046         u8 agg_vars6;
2047 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2048 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2049 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2050 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2051 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2052 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2053         u8 agg_val3_th;
2054         u16 agg_vars7;
2055 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2056 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2057 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2058 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2059 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2060 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2061 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2062 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2063 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2064 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2065 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2066 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2067 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2068 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2069 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2070 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2071 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2072 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2073 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2074 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2075 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2076 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2077 #endif
2078 #if defined(__BIG_ENDIAN)
2079         u16 __agg_val11_th;
2080         u16 __gen_data;
2081 #elif defined(__LITTLE_ENDIAN)
2082         u16 __gen_data;
2083         u16 __agg_val11_th;
2084 #endif
2085 #if defined(__BIG_ENDIAN)
2086         u8 __reserved1;
2087         u8 __agg_val6_th;
2088         u16 __agg_val9;
2089 #elif defined(__LITTLE_ENDIAN)
2090         u16 __agg_val9;
2091         u8 __agg_val6_th;
2092         u8 __reserved1;
2093 #endif
2094 #if defined(__BIG_ENDIAN)
2095         u16 hq_prod;
2096         u16 hq_cons;
2097 #elif defined(__LITTLE_ENDIAN)
2098         u16 hq_cons;
2099         u16 hq_prod;
2100 #endif
2101         u32 agg_vars8;
2102 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2103 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
2104 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2105 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
2106 #if defined(__BIG_ENDIAN)
2107         u16 r2tq_prod;
2108         u16 sq_prod;
2109 #elif defined(__LITTLE_ENDIAN)
2110         u16 sq_prod;
2111         u16 r2tq_prod;
2112 #endif
2113 #if defined(__BIG_ENDIAN)
2114         u8 agg_val3;
2115         u8 agg_val6;
2116         u8 agg_val5_th;
2117         u8 agg_val5;
2118 #elif defined(__LITTLE_ENDIAN)
2119         u8 agg_val5;
2120         u8 agg_val5_th;
2121         u8 agg_val6;
2122         u8 agg_val3;
2123 #endif
2124 #if defined(__BIG_ENDIAN)
2125         u16 __agg_misc1;
2126         u16 agg_limit1;
2127 #elif defined(__LITTLE_ENDIAN)
2128         u16 agg_limit1;
2129         u16 __agg_misc1;
2130 #endif
2131         u32 hq_cons_tcp_seq;
2132         u32 exp_stat_sn;
2133         u32 rst_seq_num;
2134 };
2135
2136
2137 /*
2138  * The L5cm aggregative context of XStorm
2139  */
2140 struct xstorm_l5cm_ag_context {
2141 #if defined(__BIG_ENDIAN)
2142         u16 agg_val1;
2143         u8 agg_vars1;
2144 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2145 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2146 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2147 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2148 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2149 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2150 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2151 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2152 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2153 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2154 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2155 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2156 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2157 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2158 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2159 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2160         u8 state;
2161 #elif defined(__LITTLE_ENDIAN)
2162         u8 state;
2163         u8 agg_vars1;
2164 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2165 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2166 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2167 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2168 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2169 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2170 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2171 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2172 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2173 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2174 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2175 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2176 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2177 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2178 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2179 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2180         u16 agg_val1;
2181 #endif
2182 #if defined(__BIG_ENDIAN)
2183         u8 cdu_reserved;
2184         u8 __agg_vars4;
2185         u8 agg_vars3;
2186 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2187 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2188 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2189 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2190         u8 agg_vars2;
2191 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2192 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2193 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2194 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2195 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2196 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2197 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2198 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2199 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2200 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2201 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2202 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2203 #elif defined(__LITTLE_ENDIAN)
2204         u8 agg_vars2;
2205 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2206 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2207 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2208 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2209 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2210 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2211 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2212 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2213 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2214 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2215 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2216 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2217         u8 agg_vars3;
2218 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2219 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2220 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2221 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2222         u8 __agg_vars4;
2223         u8 cdu_reserved;
2224 #endif
2225         u32 more_to_send;
2226 #if defined(__BIG_ENDIAN)
2227         u16 agg_vars5;
2228 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2229 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2230 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2231 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2232 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2233 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2234 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2235 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2236         u16 agg_val4_th;
2237 #elif defined(__LITTLE_ENDIAN)
2238         u16 agg_val4_th;
2239         u16 agg_vars5;
2240 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2241 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2242 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2243 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2244 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2245 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2246 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2247 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2248 #endif
2249         struct xstorm_tcp_tcp_ag_context_section tcp;
2250 #if defined(__BIG_ENDIAN)
2251         u16 agg_vars7;
2252 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2253 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2254 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2255 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2256 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2257 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2258 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2259 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2260 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2261 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2262 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2263 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2264 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2265 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2266 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2267 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2268 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2269 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2270 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2271 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2272 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2273 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2274         u8 agg_val3_th;
2275         u8 agg_vars6;
2276 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2277 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2278 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2279 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2280 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2281 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2282 #elif defined(__LITTLE_ENDIAN)
2283         u8 agg_vars6;
2284 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2285 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2286 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2287 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2288 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2289 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2290         u8 agg_val3_th;
2291         u16 agg_vars7;
2292 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2293 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2294 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2295 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2296 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2297 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2298 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2299 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2300 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2301 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2302 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2303 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2304 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2305 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2306 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2307 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2308 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2309 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2310 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2311 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2312 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2313 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2314 #endif
2315 #if defined(__BIG_ENDIAN)
2316         u16 __agg_val11_th;
2317         u16 __gen_data;
2318 #elif defined(__LITTLE_ENDIAN)
2319         u16 __gen_data;
2320         u16 __agg_val11_th;
2321 #endif
2322 #if defined(__BIG_ENDIAN)
2323         u8 __reserved1;
2324         u8 __agg_val6_th;
2325         u16 __agg_val9;
2326 #elif defined(__LITTLE_ENDIAN)
2327         u16 __agg_val9;
2328         u8 __agg_val6_th;
2329         u8 __reserved1;
2330 #endif
2331 #if defined(__BIG_ENDIAN)
2332         u16 agg_val2_th;
2333         u16 agg_val2;
2334 #elif defined(__LITTLE_ENDIAN)
2335         u16 agg_val2;
2336         u16 agg_val2_th;
2337 #endif
2338         u32 agg_vars8;
2339 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2340 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2_SHIFT 0
2341 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2342 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3_SHIFT 24
2343 #if defined(__BIG_ENDIAN)
2344         u16 agg_misc0;
2345         u16 agg_val4;
2346 #elif defined(__LITTLE_ENDIAN)
2347         u16 agg_val4;
2348         u16 agg_misc0;
2349 #endif
2350 #if defined(__BIG_ENDIAN)
2351         u8 agg_val3;
2352         u8 agg_val6;
2353         u8 agg_val5_th;
2354         u8 agg_val5;
2355 #elif defined(__LITTLE_ENDIAN)
2356         u8 agg_val5;
2357         u8 agg_val5_th;
2358         u8 agg_val6;
2359         u8 agg_val3;
2360 #endif
2361 #if defined(__BIG_ENDIAN)
2362         u16 __agg_misc1;
2363         u16 agg_limit1;
2364 #elif defined(__LITTLE_ENDIAN)
2365         u16 agg_limit1;
2366         u16 __agg_misc1;
2367 #endif
2368         u32 completion_seq;
2369         u32 agg_misc4;
2370         u32 rst_seq_num;
2371 };
2372
2373 /*
2374  * ABTS info $$KEEP_ENDIANNESS$$
2375  */
2376 struct fcoe_abts_info {
2377         __le16 aborted_task_id;
2378         __le16 reserved0;
2379         __le32 reserved1;
2380 };
2381
2382
2383 /*
2384  * Fixed size structure in order to plant it in Union structure
2385  * $$KEEP_ENDIANNESS$$
2386  */
2387 struct fcoe_abts_rsp_union {
2388         u8 r_ctl;
2389         u8 rsrv[3];
2390         __le32 abts_rsp_payload[7];
2391 };
2392
2393
2394 /*
2395  * 4 regs size $$KEEP_ENDIANNESS$$
2396  */
2397 struct fcoe_bd_ctx {
2398         __le32 buf_addr_hi;
2399         __le32 buf_addr_lo;
2400         __le16 buf_len;
2401         __le16 rsrv0;
2402         __le16 flags;
2403         __le16 rsrv1;
2404 };
2405
2406
2407 /*
2408  * FCoE cached sges context $$KEEP_ENDIANNESS$$
2409  */
2410 struct fcoe_cached_sge_ctx {
2411         struct regpair cur_buf_addr;
2412         __le16 cur_buf_rem;
2413         __le16 second_buf_rem;
2414         struct regpair second_buf_addr;
2415 };
2416
2417
2418 /*
2419  * Cleanup info $$KEEP_ENDIANNESS$$
2420  */
2421 struct fcoe_cleanup_info {
2422         __le16 cleaned_task_id;
2423         __le16 rolled_tx_seq_cnt;
2424         __le32 rolled_tx_data_offset;
2425 };
2426
2427
2428 /*
2429  * Fcp RSP flags $$KEEP_ENDIANNESS$$
2430  */
2431 struct fcoe_fcp_rsp_flags {
2432         u8 flags;
2433 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
2434 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
2435 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
2436 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
2437 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
2438 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
2439 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
2440 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
2441 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
2442 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
2443 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
2444 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
2445 };
2446
2447 /*
2448  * Fcp RSP payload $$KEEP_ENDIANNESS$$
2449  */
2450 struct fcoe_fcp_rsp_payload {
2451         struct regpair reserved0;
2452         __le32 fcp_resid;
2453         u8 scsi_status_code;
2454         struct fcoe_fcp_rsp_flags fcp_flags;
2455         __le16 retry_delay_timer;
2456         __le32 fcp_rsp_len;
2457         __le32 fcp_sns_len;
2458 };
2459
2460 /*
2461  * Fixed size structure in order to plant it in Union structure
2462  * $$KEEP_ENDIANNESS$$
2463  */
2464 struct fcoe_fcp_rsp_union {
2465         struct fcoe_fcp_rsp_payload payload;
2466         struct regpair reserved0;
2467 };
2468
2469 /*
2470  * FC header $$KEEP_ENDIANNESS$$
2471  */
2472 struct fcoe_fc_hdr {
2473         u8 s_id[3];
2474         u8 cs_ctl;
2475         u8 d_id[3];
2476         u8 r_ctl;
2477         __le16 seq_cnt;
2478         u8 df_ctl;
2479         u8 seq_id;
2480         u8 f_ctl[3];
2481         u8 type;
2482         __le32 parameters;
2483         __le16 rx_id;
2484         __le16 ox_id;
2485 };
2486
2487 /*
2488  * FC header union $$KEEP_ENDIANNESS$$
2489  */
2490 struct fcoe_mp_rsp_union {
2491         struct fcoe_fc_hdr fc_hdr;
2492         __le32 mp_payload_len;
2493         __le32 rsrv;
2494 };
2495
2496 /*
2497  * Completion information $$KEEP_ENDIANNESS$$
2498  */
2499 union fcoe_comp_flow_info {
2500         struct fcoe_fcp_rsp_union fcp_rsp;
2501         struct fcoe_abts_rsp_union abts_rsp;
2502         struct fcoe_mp_rsp_union mp_rsp;
2503         __le32 opaque[8];
2504 };
2505
2506
2507 /*
2508  * External ABTS info $$KEEP_ENDIANNESS$$
2509  */
2510 struct fcoe_ext_abts_info {
2511         __le32 rsrv0[6];
2512         struct fcoe_abts_info ctx;
2513 };
2514
2515
2516 /*
2517  * External cleanup info $$KEEP_ENDIANNESS$$
2518  */
2519 struct fcoe_ext_cleanup_info {
2520         __le32 rsrv0[6];
2521         struct fcoe_cleanup_info ctx;
2522 };
2523
2524
2525 /*
2526  * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
2527  */
2528 struct fcoe_fw_tx_seq_ctx {
2529         __le32 data_offset;
2530         __le16 seq_cnt;
2531         __le16 rsrv0;
2532 };
2533
2534 /*
2535  * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
2536  */
2537 struct fcoe_ext_fw_tx_seq_ctx {
2538         __le32 rsrv0[6];
2539         struct fcoe_fw_tx_seq_ctx ctx;
2540 };
2541
2542
2543 /*
2544  * FCoE multiple sges context $$KEEP_ENDIANNESS$$
2545  */
2546 struct fcoe_mul_sges_ctx {
2547         struct regpair cur_sge_addr;
2548         __le16 cur_sge_off;
2549         u8 cur_sge_idx;
2550         u8 sgl_size;
2551 };
2552
2553 /*
2554  * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
2555  */
2556 struct fcoe_ext_mul_sges_ctx {
2557         struct fcoe_mul_sges_ctx mul_sgl;
2558         struct regpair rsrv0;
2559 };
2560
2561
2562 /*
2563  * FCP CMD payload $$KEEP_ENDIANNESS$$
2564  */
2565 struct fcoe_fcp_cmd_payload {
2566         __le32 opaque[8];
2567 };
2568
2569
2570
2571
2572
2573 /*
2574  * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
2575  */
2576 struct fcoe_fcp_xfr_rdy_payload {
2577         __le32 burst_len;
2578         __le32 data_ro;
2579 };
2580
2581
2582 /*
2583  * FC frame $$KEEP_ENDIANNESS$$
2584  */
2585 struct fcoe_fc_frame {
2586         struct fcoe_fc_hdr fc_hdr;
2587         __le32 reserved0[2];
2588 };
2589
2590
2591
2592
2593 /*
2594  * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
2595  */
2596 union fcoe_kcqe_params {
2597         __le32 reserved0[4];
2598 };
2599
2600 /*
2601  * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
2602  */
2603 struct fcoe_kcqe {
2604         __le32 fcoe_conn_id;
2605         __le32 completion_status;
2606         __le32 fcoe_conn_context_id;
2607         union fcoe_kcqe_params params;
2608         __le16 qe_self_seq;
2609         u8 op_code;
2610         u8 flags;
2611 #define FCOE_KCQE_RESERVED0 (0x7<<0)
2612 #define FCOE_KCQE_RESERVED0_SHIFT 0
2613 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
2614 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
2615 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
2616 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
2617 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
2618 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
2619 };
2620
2621
2622
2623 /*
2624  * FCoE KWQE header $$KEEP_ENDIANNESS$$
2625  */
2626 struct fcoe_kwqe_header {
2627         u8 op_code;
2628         u8 flags;
2629 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
2630 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
2631 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
2632 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
2633 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
2634 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
2635 };
2636
2637 /*
2638  * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
2639  */
2640 struct fcoe_kwqe_init1 {
2641         __le16 num_tasks;
2642         struct fcoe_kwqe_header hdr;
2643         __le32 task_list_pbl_addr_lo;
2644         __le32 task_list_pbl_addr_hi;
2645         __le32 dummy_buffer_addr_lo;
2646         __le32 dummy_buffer_addr_hi;
2647         __le16 sq_num_wqes;
2648         __le16 rq_num_wqes;
2649         __le16 rq_buffer_log_size;
2650         __le16 cq_num_wqes;
2651         __le16 mtu;
2652         u8 num_sessions_log;
2653         u8 flags;
2654 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
2655 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
2656 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
2657 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
2658 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
2659 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
2660 };
2661
2662 /*
2663  * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
2664  */
2665 struct fcoe_kwqe_init2 {
2666         u8 hsi_major_version;
2667         u8 hsi_minor_version;
2668         struct fcoe_kwqe_header hdr;
2669         __le32 hash_tbl_pbl_addr_lo;
2670         __le32 hash_tbl_pbl_addr_hi;
2671         __le32 t2_hash_tbl_addr_lo;
2672         __le32 t2_hash_tbl_addr_hi;
2673         __le32 t2_ptr_hash_tbl_addr_lo;
2674         __le32 t2_ptr_hash_tbl_addr_hi;
2675         __le32 free_list_count;
2676 };
2677
2678 /*
2679  * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
2680  */
2681 struct fcoe_kwqe_init3 {
2682         __le16 reserved0;
2683         struct fcoe_kwqe_header hdr;
2684         __le32 error_bit_map_lo;
2685         __le32 error_bit_map_hi;
2686         u8 perf_config;
2687         u8 reserved21[3];
2688         __le32 reserved2[4];
2689 };
2690
2691 /*
2692  * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
2693  */
2694 struct fcoe_kwqe_conn_offload1 {
2695         __le16 fcoe_conn_id;
2696         struct fcoe_kwqe_header hdr;
2697         __le32 sq_addr_lo;
2698         __le32 sq_addr_hi;
2699         __le32 rq_pbl_addr_lo;
2700         __le32 rq_pbl_addr_hi;
2701         __le32 rq_first_pbe_addr_lo;
2702         __le32 rq_first_pbe_addr_hi;
2703         __le16 rq_prod;
2704         __le16 reserved0;
2705 };
2706
2707 /*
2708  * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
2709  */
2710 struct fcoe_kwqe_conn_offload2 {
2711         __le16 tx_max_fc_pay_len;
2712         struct fcoe_kwqe_header hdr;
2713         __le32 cq_addr_lo;
2714         __le32 cq_addr_hi;
2715         __le32 xferq_addr_lo;
2716         __le32 xferq_addr_hi;
2717         __le32 conn_db_addr_lo;
2718         __le32 conn_db_addr_hi;
2719         __le32 reserved1;
2720 };
2721
2722 /*
2723  * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
2724  */
2725 struct fcoe_kwqe_conn_offload3 {
2726         __le16 vlan_tag;
2727 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
2728 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
2729 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
2730 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
2731 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
2732 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
2733         struct fcoe_kwqe_header hdr;
2734         u8 s_id[3];
2735         u8 tx_max_conc_seqs_c3;
2736         u8 d_id[3];
2737         u8 flags;
2738 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
2739 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
2740 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
2741 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
2742 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
2743 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
2744 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
2745 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
2746 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
2747 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
2748 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
2749 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
2750 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
2751 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
2752 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
2753 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
2754         __le32 reserved;
2755         __le32 confq_first_pbe_addr_lo;
2756         __le32 confq_first_pbe_addr_hi;
2757         __le16 tx_total_conc_seqs;
2758         __le16 rx_max_fc_pay_len;
2759         __le16 rx_total_conc_seqs;
2760         u8 rx_max_conc_seqs_c3;
2761         u8 rx_open_seqs_exch_c3;
2762 };
2763
2764 /*
2765  * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
2766  */
2767 struct fcoe_kwqe_conn_offload4 {
2768         u8 e_d_tov_timer_val;
2769         u8 reserved2;
2770         struct fcoe_kwqe_header hdr;
2771         u8 src_mac_addr_lo[2];
2772         u8 src_mac_addr_mid[2];
2773         u8 src_mac_addr_hi[2];
2774         u8 dst_mac_addr_hi[2];
2775         u8 dst_mac_addr_lo[2];
2776         u8 dst_mac_addr_mid[2];
2777         __le32 lcq_addr_lo;
2778         __le32 lcq_addr_hi;
2779         __le32 confq_pbl_base_addr_lo;
2780         __le32 confq_pbl_base_addr_hi;
2781 };
2782
2783 /*
2784  * FCoE connection enable request $$KEEP_ENDIANNESS$$
2785  */
2786 struct fcoe_kwqe_conn_enable_disable {
2787         __le16 reserved0;
2788         struct fcoe_kwqe_header hdr;
2789         u8 src_mac_addr_lo[2];
2790         u8 src_mac_addr_mid[2];
2791         u8 src_mac_addr_hi[2];
2792         u16 vlan_tag;
2793 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
2794 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
2795 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
2796 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
2797 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
2798 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
2799         u8 dst_mac_addr_lo[2];
2800         u8 dst_mac_addr_mid[2];
2801         u8 dst_mac_addr_hi[2];
2802         __le16 reserved1;
2803         u8 s_id[3];
2804         u8 vlan_flag;
2805         u8 d_id[3];
2806         u8 reserved3;
2807         __le32 context_id;
2808         __le32 conn_id;
2809         __le32 reserved4;
2810 };
2811
2812 /*
2813  * FCoE connection destroy request $$KEEP_ENDIANNESS$$
2814  */
2815 struct fcoe_kwqe_conn_destroy {
2816         __le16 reserved0;
2817         struct fcoe_kwqe_header hdr;
2818         __le32 context_id;
2819         __le32 conn_id;
2820         __le32 reserved1[5];
2821 };
2822
2823 /*
2824  * FCoe destroy request $$KEEP_ENDIANNESS$$
2825  */
2826 struct fcoe_kwqe_destroy {
2827         __le16 reserved0;
2828         struct fcoe_kwqe_header hdr;
2829         __le32 reserved1[7];
2830 };
2831
2832 /*
2833  * FCoe statistics request $$KEEP_ENDIANNESS$$
2834  */
2835 struct fcoe_kwqe_stat {
2836         __le16 reserved0;
2837         struct fcoe_kwqe_header hdr;
2838         __le32 stat_params_addr_lo;
2839         __le32 stat_params_addr_hi;
2840         __le32 reserved1[5];
2841 };
2842
2843 /*
2844  * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
2845  */
2846 union fcoe_kwqe {
2847         struct fcoe_kwqe_init1 init1;
2848         struct fcoe_kwqe_init2 init2;
2849         struct fcoe_kwqe_init3 init3;
2850         struct fcoe_kwqe_conn_offload1 conn_offload1;
2851         struct fcoe_kwqe_conn_offload2 conn_offload2;
2852         struct fcoe_kwqe_conn_offload3 conn_offload3;
2853         struct fcoe_kwqe_conn_offload4 conn_offload4;
2854         struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
2855         struct fcoe_kwqe_conn_destroy conn_destroy;
2856         struct fcoe_kwqe_destroy destroy;
2857         struct fcoe_kwqe_stat statistics;
2858 };
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875 /*
2876  * TX SGL context $$KEEP_ENDIANNESS$$
2877  */
2878 union fcoe_sgl_union_ctx {
2879         struct fcoe_cached_sge_ctx cached_sge;
2880         struct fcoe_ext_mul_sges_ctx sgl;
2881         __le32 opaque[5];
2882 };
2883
2884 /*
2885  * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
2886  */
2887 struct fcoe_read_flow_info {
2888         union fcoe_sgl_union_ctx sgl_ctx;
2889         __le32 rsrv0[3];
2890 };
2891
2892
2893 /*
2894  * Fcoe stat context $$KEEP_ENDIANNESS$$
2895  */
2896 struct fcoe_s_stat_ctx {
2897         u8 flags;
2898 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
2899 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
2900 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
2901 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
2902 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
2903 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
2904 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
2905 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
2906 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
2907 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
2908 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
2909 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
2910 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
2911 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
2912 };
2913
2914 /*
2915  * Fcoe rx seq context $$KEEP_ENDIANNESS$$
2916  */
2917 struct fcoe_rx_seq_ctx {
2918         u8 seq_id;
2919         struct fcoe_s_stat_ctx s_stat;
2920         __le16 seq_cnt;
2921         __le32 low_exp_ro;
2922         __le32 high_exp_ro;
2923 };
2924
2925
2926 /*
2927  * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
2928  */
2929 union fcoe_rx_wr_union_ctx {
2930         struct fcoe_read_flow_info read_info;
2931         union fcoe_comp_flow_info comp_info;
2932         __le32 opaque[8];
2933 };
2934
2935
2936
2937 /*
2938  * FCoE SQ element $$KEEP_ENDIANNESS$$
2939  */
2940 struct fcoe_sqe {
2941         __le16 wqe;
2942 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
2943 #define FCOE_SQE_TASK_ID_SHIFT 0
2944 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
2945 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
2946 };
2947
2948
2949
2950 /*
2951  * 14 regs $$KEEP_ENDIANNESS$$
2952  */
2953 struct fcoe_tce_tx_only {
2954         union fcoe_sgl_union_ctx sgl_ctx;
2955         __le32 rsrv0;
2956 };
2957
2958 /*
2959  * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
2960  */
2961 union fcoe_tx_wr_rx_rd_union_ctx {
2962         struct fcoe_fc_frame tx_frame;
2963         struct fcoe_fcp_cmd_payload fcp_cmd;
2964         struct fcoe_ext_cleanup_info cleanup;
2965         struct fcoe_ext_abts_info abts;
2966         struct fcoe_ext_fw_tx_seq_ctx tx_seq;
2967         __le32 opaque[8];
2968 };
2969
2970 /*
2971  * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
2972  */
2973 struct fcoe_tce_tx_wr_rx_rd_const {
2974         u8 init_flags;
2975 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
2976 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
2977 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
2978 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
2979 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
2980 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
2981 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
2982 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
2983 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
2984 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
2985         u8 tx_flags;
2986 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
2987 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
2988 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
2989 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
2990 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
2991 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
2992 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
2993 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
2994 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7)
2995 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7
2996         __le16 rsrv3;
2997         __le32 verify_tx_seq;
2998 };
2999
3000 /*
3001  * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
3002  */
3003 struct fcoe_tce_tx_wr_rx_rd {
3004         union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
3005         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3006 };
3007
3008 /*
3009  * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
3010  */
3011 struct fcoe_tce_rx_wr_tx_rd_const {
3012         __le32 data_2_trns;
3013         __le32 init_flags;
3014 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
3015 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
3016 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
3017 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
3018 };
3019
3020 /*
3021  * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
3022  */
3023 struct fcoe_tce_rx_wr_tx_rd_var {
3024         __le16 rx_flags;
3025 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
3026 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
3027 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
3028 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
3029 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
3030 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
3031 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
3032 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
3033 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
3034 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
3035 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
3036 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
3037 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
3038 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
3039 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
3040 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
3041         __le16 rx_id;
3042         struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
3043 };
3044
3045 /*
3046  * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
3047  */
3048 struct fcoe_tce_rx_wr_tx_rd {
3049         struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
3050         struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
3051 };
3052
3053 /*
3054  * tce_rx_only $$KEEP_ENDIANNESS$$
3055  */
3056 struct fcoe_tce_rx_only {
3057         struct fcoe_rx_seq_ctx rx_seq_ctx;
3058         union fcoe_rx_wr_union_ctx union_ctx;
3059 };
3060
3061 /*
3062  * task_ctx_entry $$KEEP_ENDIANNESS$$
3063  */
3064 struct fcoe_task_ctx_entry {
3065         struct fcoe_tce_tx_only txwr_only;
3066         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3067         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3068         struct fcoe_tce_rx_only rxwr_only;
3069 };
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080 /*
3081  * FCoE XFRQ element $$KEEP_ENDIANNESS$$
3082  */
3083 struct fcoe_xfrqe {
3084         __le16 wqe;
3085 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
3086 #define FCOE_XFRQE_TASK_ID_SHIFT 0
3087 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
3088 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
3089 };
3090
3091
3092 /*
3093  * Cached SGEs $$KEEP_ENDIANNESS$$
3094  */
3095 struct common_fcoe_sgl {
3096         struct fcoe_bd_ctx sge[3];
3097 };
3098
3099
3100 /*
3101  * FCoE SQ\XFRQ element
3102  */
3103 struct fcoe_cached_wqe {
3104         struct fcoe_sqe sqe;
3105         struct fcoe_xfrqe xfrqe;
3106 };
3107
3108
3109 /*
3110  * FCoE connection enable\disable params passed by driver to FW in FCoE enable
3111  * ramrod $$KEEP_ENDIANNESS$$
3112  */
3113 struct fcoe_conn_enable_disable_ramrod_params {
3114         struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
3115 };
3116
3117
3118 /*
3119  * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
3120  * $$KEEP_ENDIANNESS$$
3121  */
3122 struct fcoe_conn_offload_ramrod_params {
3123         struct fcoe_kwqe_conn_offload1 offload_kwqe1;
3124         struct fcoe_kwqe_conn_offload2 offload_kwqe2;
3125         struct fcoe_kwqe_conn_offload3 offload_kwqe3;
3126         struct fcoe_kwqe_conn_offload4 offload_kwqe4;
3127 };
3128
3129
3130 struct ustorm_fcoe_mng_ctx {
3131 #if defined(__BIG_ENDIAN)
3132         u8 mid_seq_proc_flag;
3133         u8 tce_in_cam_flag;
3134         u8 tce_on_ior_flag;
3135         u8 en_cached_tce_flag;
3136 #elif defined(__LITTLE_ENDIAN)
3137         u8 en_cached_tce_flag;
3138         u8 tce_on_ior_flag;
3139         u8 tce_in_cam_flag;
3140         u8 mid_seq_proc_flag;
3141 #endif
3142 #if defined(__BIG_ENDIAN)
3143         u8 tce_cam_addr;
3144         u8 cached_conn_flag;
3145         u16 rsrv0;
3146 #elif defined(__LITTLE_ENDIAN)
3147         u16 rsrv0;
3148         u8 cached_conn_flag;
3149         u8 tce_cam_addr;
3150 #endif
3151 #if defined(__BIG_ENDIAN)
3152         u16 dma_tce_ram_addr;
3153         u16 tce_ram_addr;
3154 #elif defined(__LITTLE_ENDIAN)
3155         u16 tce_ram_addr;
3156         u16 dma_tce_ram_addr;
3157 #endif
3158 #if defined(__BIG_ENDIAN)
3159         u16 ox_id;
3160         u16 wr_done_seq;
3161 #elif defined(__LITTLE_ENDIAN)
3162         u16 wr_done_seq;
3163         u16 ox_id;
3164 #endif
3165         struct regpair task_addr;
3166 };
3167
3168 /*
3169  * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and
3170  * used in FCoE context section
3171  */
3172 struct ustorm_fcoe_params {
3173 #if defined(__BIG_ENDIAN)
3174         u16 fcoe_conn_id;
3175         u16 flags;
3176 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3177 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3178 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3179 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3180 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3181 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3182 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3183 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3184 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3185 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3186 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3187 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3188 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3189 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3190 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3191 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3192 #elif defined(__LITTLE_ENDIAN)
3193         u16 flags;
3194 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3195 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3196 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3197 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3198 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3199 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3200 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3201 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3202 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3203 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3204 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3205 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3206 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3207 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3208 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3209 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3210         u16 fcoe_conn_id;
3211 #endif
3212 #if defined(__BIG_ENDIAN)
3213         u8 hc_csdm_byte_en;
3214         u8 func_id;
3215         u8 port_id;
3216         u8 vnic_id;
3217 #elif defined(__LITTLE_ENDIAN)
3218         u8 vnic_id;
3219         u8 port_id;
3220         u8 func_id;
3221         u8 hc_csdm_byte_en;
3222 #endif
3223 #if defined(__BIG_ENDIAN)
3224         u16 rx_total_conc_seqs;
3225         u16 rx_max_fc_pay_len;
3226 #elif defined(__LITTLE_ENDIAN)
3227         u16 rx_max_fc_pay_len;
3228         u16 rx_total_conc_seqs;
3229 #endif
3230 #if defined(__BIG_ENDIAN)
3231         u8 task_pbe_idx_off;
3232         u8 task_in_page_log_size;
3233         u16 rx_max_conc_seqs;
3234 #elif defined(__LITTLE_ENDIAN)
3235         u16 rx_max_conc_seqs;
3236         u8 task_in_page_log_size;
3237         u8 task_pbe_idx_off;
3238 #endif
3239 };
3240
3241 /*
3242  * FCoE 16-bits index structure
3243  */
3244 struct fcoe_idx16_fields {
3245         u16 fields;
3246 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
3247 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
3248 #define FCOE_IDX16_FIELDS_MSB (0x1<<15)
3249 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15
3250 };
3251
3252 /*
3253  * FCoE 16-bits index union
3254  */
3255 union fcoe_idx16_field_union {
3256         struct fcoe_idx16_fields fields;
3257         u16 val;
3258 };
3259
3260 /*
3261  * Parameters required for placement according to SGL
3262  */
3263 struct ustorm_fcoe_data_place_mng {
3264 #if defined(__BIG_ENDIAN)
3265         u16 sge_off;
3266         u8 num_sges;
3267         u8 sge_idx;
3268 #elif defined(__LITTLE_ENDIAN)
3269         u8 sge_idx;
3270         u8 num_sges;
3271         u16 sge_off;
3272 #endif
3273 };
3274
3275 /*
3276  * Parameters required for placement according to SGL
3277  */
3278 struct ustorm_fcoe_data_place {
3279         struct ustorm_fcoe_data_place_mng cached_mng;
3280         struct fcoe_bd_ctx cached_sge[2];
3281 };
3282
3283 /*
3284  * TX processing shall write and RX processing shall read from this section
3285  */
3286 union fcoe_u_tce_tx_wr_rx_rd_union {
3287         struct fcoe_abts_info abts;
3288         struct fcoe_cleanup_info cleanup;
3289         struct fcoe_fw_tx_seq_ctx tx_seq_ctx;
3290         u32 opaque[2];
3291 };
3292
3293 /*
3294  * TX processing shall write and RX processing shall read from this section
3295  */
3296 struct fcoe_u_tce_tx_wr_rx_rd {
3297         union fcoe_u_tce_tx_wr_rx_rd_union union_ctx;
3298         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3299 };
3300
3301 struct ustorm_fcoe_tce {
3302         struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd;
3303         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3304         struct fcoe_tce_rx_only rxwr;
3305 };
3306
3307 struct ustorm_fcoe_cache_ctx {
3308         u32 rsrv0;
3309         struct ustorm_fcoe_data_place data_place;
3310         struct ustorm_fcoe_tce tce;
3311 };
3312
3313 /*
3314  * Ustorm FCoE Storm Context
3315  */
3316 struct ustorm_fcoe_st_context {
3317         struct ustorm_fcoe_mng_ctx mng_ctx;
3318         struct ustorm_fcoe_params fcoe_params;
3319         struct regpair cq_base_addr;
3320         struct regpair rq_pbl_base;
3321         struct regpair rq_cur_page_addr;
3322         struct regpair confq_pbl_base_addr;
3323         struct regpair conn_db_base;
3324         struct regpair xfrq_base_addr;
3325         struct regpair lcq_base_addr;
3326 #if defined(__BIG_ENDIAN)
3327         union fcoe_idx16_field_union rq_cons;
3328         union fcoe_idx16_field_union rq_prod;
3329 #elif defined(__LITTLE_ENDIAN)
3330         union fcoe_idx16_field_union rq_prod;
3331         union fcoe_idx16_field_union rq_cons;
3332 #endif
3333 #if defined(__BIG_ENDIAN)
3334         u16 xfrq_prod;
3335         u16 cq_cons;
3336 #elif defined(__LITTLE_ENDIAN)
3337         u16 cq_cons;
3338         u16 xfrq_prod;
3339 #endif
3340 #if defined(__BIG_ENDIAN)
3341         u16 lcq_cons;
3342         u16 hc_cram_address;
3343 #elif defined(__LITTLE_ENDIAN)
3344         u16 hc_cram_address;
3345         u16 lcq_cons;
3346 #endif
3347 #if defined(__BIG_ENDIAN)
3348         u16 sq_xfrq_lcq_confq_size;
3349         u16 confq_prod;
3350 #elif defined(__LITTLE_ENDIAN)
3351         u16 confq_prod;
3352         u16 sq_xfrq_lcq_confq_size;
3353 #endif
3354 #if defined(__BIG_ENDIAN)
3355         u8 hc_csdm_agg_int;
3356         u8 rsrv2;
3357         u8 available_rqes;
3358         u8 sp_q_flush_cnt;
3359 #elif defined(__LITTLE_ENDIAN)
3360         u8 sp_q_flush_cnt;
3361         u8 available_rqes;
3362         u8 rsrv2;
3363         u8 hc_csdm_agg_int;
3364 #endif
3365 #if defined(__BIG_ENDIAN)
3366         u16 num_pend_tasks;
3367         u16 pbf_ack_ram_addr;
3368 #elif defined(__LITTLE_ENDIAN)
3369         u16 pbf_ack_ram_addr;
3370         u16 num_pend_tasks;
3371 #endif
3372         struct ustorm_fcoe_cache_ctx cache_ctx;
3373 };
3374
3375 /*
3376  * The FCoE non-aggregative context of Tstorm
3377  */
3378 struct tstorm_fcoe_st_context {
3379         struct regpair reserved0;
3380         struct regpair reserved1;
3381 };
3382
3383 /*
3384  * Ethernet context section
3385  */
3386 struct xstorm_fcoe_eth_context_section {
3387 #if defined(__BIG_ENDIAN)
3388         u8 remote_addr_4;
3389         u8 remote_addr_5;
3390         u8 local_addr_0;
3391         u8 local_addr_1;
3392 #elif defined(__LITTLE_ENDIAN)
3393         u8 local_addr_1;
3394         u8 local_addr_0;
3395         u8 remote_addr_5;
3396         u8 remote_addr_4;
3397 #endif
3398 #if defined(__BIG_ENDIAN)
3399         u8 remote_addr_0;
3400         u8 remote_addr_1;
3401         u8 remote_addr_2;
3402         u8 remote_addr_3;
3403 #elif defined(__LITTLE_ENDIAN)
3404         u8 remote_addr_3;
3405         u8 remote_addr_2;
3406         u8 remote_addr_1;
3407         u8 remote_addr_0;
3408 #endif
3409 #if defined(__BIG_ENDIAN)
3410         u16 reserved_vlan_type;
3411         u16 params;
3412 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3413 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3414 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3415 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3416 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3417 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3418 #elif defined(__LITTLE_ENDIAN)
3419         u16 params;
3420 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3421 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3422 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3423 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3424 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3425 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3426         u16 reserved_vlan_type;
3427 #endif
3428 #if defined(__BIG_ENDIAN)
3429         u8 local_addr_2;
3430         u8 local_addr_3;
3431         u8 local_addr_4;
3432         u8 local_addr_5;
3433 #elif defined(__LITTLE_ENDIAN)
3434         u8 local_addr_5;
3435         u8 local_addr_4;
3436         u8 local_addr_3;
3437         u8 local_addr_2;
3438 #endif
3439 };
3440
3441 /*
3442  * Flags used in FCoE context section - 1 byte
3443  */
3444 struct xstorm_fcoe_context_flags {
3445         u8 flags;
3446 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
3447 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
3448 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
3449 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
3450 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3)
3451 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
3452 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
3453 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
3454 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
3455 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
3456 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
3457 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
3458 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7)
3459 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
3460 };
3461
3462 struct xstorm_fcoe_tce {
3463         struct fcoe_tce_tx_only txwr;
3464         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3465 };
3466
3467 /*
3468  * FCP_DATA parameters required for transmission
3469  */
3470 struct xstorm_fcoe_fcp_data {
3471         u32 io_rem;
3472 #if defined(__BIG_ENDIAN)
3473         u16 cached_sge_off;
3474         u8 cached_num_sges;
3475         u8 cached_sge_idx;
3476 #elif defined(__LITTLE_ENDIAN)
3477         u8 cached_sge_idx;
3478         u8 cached_num_sges;
3479         u16 cached_sge_off;
3480 #endif
3481         u32 buf_addr_hi_0;
3482         u32 buf_addr_lo_0;
3483 #if defined(__BIG_ENDIAN)
3484         u16 num_of_pending_tasks;
3485         u16 buf_len_0;
3486 #elif defined(__LITTLE_ENDIAN)
3487         u16 buf_len_0;
3488         u16 num_of_pending_tasks;
3489 #endif
3490         u32 buf_addr_hi_1;
3491         u32 buf_addr_lo_1;
3492 #if defined(__BIG_ENDIAN)
3493         u16 task_pbe_idx_off;
3494         u16 buf_len_1;
3495 #elif defined(__LITTLE_ENDIAN)
3496         u16 buf_len_1;
3497         u16 task_pbe_idx_off;
3498 #endif
3499         u32 buf_addr_hi_2;
3500         u32 buf_addr_lo_2;
3501 #if defined(__BIG_ENDIAN)
3502         u16 ox_id;
3503         u16 buf_len_2;
3504 #elif defined(__LITTLE_ENDIAN)
3505         u16 buf_len_2;
3506         u16 ox_id;
3507 #endif
3508 };
3509
3510 /*
3511  * vlan configuration
3512  */
3513 struct xstorm_fcoe_vlan_conf {
3514         u8 vlan_conf;
3515 #define XSTORM_FCOE_VLAN_CONF_PRIORITY (0x7<<0)
3516 #define XSTORM_FCOE_VLAN_CONF_PRIORITY_SHIFT 0
3517 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3)
3518 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
3519 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0xF<<4)
3520 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 4
3521 };
3522
3523 /*
3524  * FCoE 16-bits vlan structure
3525  */
3526 struct fcoe_vlan_fields {
3527         u16 fields;
3528 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
3529 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
3530 #define FCOE_VLAN_FIELDS_CLI (0x1<<12)
3531 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
3532 #define FCOE_VLAN_FIELDS_PRI (0x7<<13)
3533 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
3534 };
3535
3536 /*
3537  * FCoE 16-bits vlan union
3538  */
3539 union fcoe_vlan_field_union {
3540         struct fcoe_vlan_fields fields;
3541         u16 val;
3542 };
3543
3544 /*
3545  * FCoE 16-bits vlan, vif union
3546  */
3547 union fcoe_vlan_vif_field_union {
3548         union fcoe_vlan_field_union vlan;
3549         u16 vif;
3550 };
3551
3552 /*
3553  * FCoE context section
3554  */
3555 struct xstorm_fcoe_context_section {
3556 #if defined(__BIG_ENDIAN)
3557         u8 cs_ctl;
3558         u8 s_id[3];
3559 #elif defined(__LITTLE_ENDIAN)
3560         u8 s_id[3];
3561         u8 cs_ctl;
3562 #endif
3563 #if defined(__BIG_ENDIAN)
3564         u8 rctl;
3565         u8 d_id[3];
3566 #elif defined(__LITTLE_ENDIAN)
3567         u8 d_id[3];
3568         u8 rctl;
3569 #endif
3570 #if defined(__BIG_ENDIAN)
3571         u16 sq_xfrq_lcq_confq_size;
3572         u16 tx_max_fc_pay_len;
3573 #elif defined(__LITTLE_ENDIAN)
3574         u16 tx_max_fc_pay_len;
3575         u16 sq_xfrq_lcq_confq_size;
3576 #endif
3577         u32 lcq_prod;
3578 #if defined(__BIG_ENDIAN)
3579         u8 port_id;
3580         u8 func_id;
3581         u8 seq_id;
3582         struct xstorm_fcoe_context_flags tx_flags;
3583 #elif defined(__LITTLE_ENDIAN)
3584         struct xstorm_fcoe_context_flags tx_flags;
3585         u8 seq_id;
3586         u8 func_id;
3587         u8 port_id;
3588 #endif
3589 #if defined(__BIG_ENDIAN)
3590         u16 mtu;
3591         u8 func_mode;
3592         u8 vnic_id;
3593 #elif defined(__LITTLE_ENDIAN)
3594         u8 vnic_id;
3595         u8 func_mode;
3596         u16 mtu;
3597 #endif
3598         struct regpair confq_curr_page_addr;
3599         struct fcoe_cached_wqe cached_wqe[8];
3600         struct regpair lcq_base_addr;
3601         struct xstorm_fcoe_tce tce;
3602         struct xstorm_fcoe_fcp_data fcp_data;
3603 #if defined(__BIG_ENDIAN)
3604         u8 tx_max_conc_seqs_c3;
3605         u8 vlan_flag;
3606         u8 dcb_val;
3607         u8 data_pb_cmd_size;
3608 #elif defined(__LITTLE_ENDIAN)
3609         u8 data_pb_cmd_size;
3610         u8 dcb_val;
3611         u8 vlan_flag;
3612         u8 tx_max_conc_seqs_c3;
3613 #endif
3614 #if defined(__BIG_ENDIAN)
3615         u16 fcoe_tx_stat_params_ram_addr;
3616         u16 fcoe_tx_fc_seq_ram_addr;
3617 #elif defined(__LITTLE_ENDIAN)
3618         u16 fcoe_tx_fc_seq_ram_addr;
3619         u16 fcoe_tx_stat_params_ram_addr;
3620 #endif
3621 #if defined(__BIG_ENDIAN)
3622         u8 fcp_cmd_line_credit;
3623         u8 eth_hdr_size;
3624         u16 pbf_addr;
3625 #elif defined(__LITTLE_ENDIAN)
3626         u16 pbf_addr;
3627         u8 eth_hdr_size;
3628         u8 fcp_cmd_line_credit;
3629 #endif
3630 #if defined(__BIG_ENDIAN)
3631         union fcoe_vlan_vif_field_union multi_func_val;
3632         u8 page_log_size;
3633         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3634 #elif defined(__LITTLE_ENDIAN)
3635         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3636         u8 page_log_size;
3637         union fcoe_vlan_vif_field_union multi_func_val;
3638 #endif
3639 #if defined(__BIG_ENDIAN)
3640         u16 fcp_cmd_frame_size;
3641         u16 pbf_addr_ff;
3642 #elif defined(__LITTLE_ENDIAN)
3643         u16 pbf_addr_ff;
3644         u16 fcp_cmd_frame_size;
3645 #endif
3646 #if defined(__BIG_ENDIAN)
3647         u8 vlan_num;
3648         u8 cos;
3649         u8 cache_xfrq_cons;
3650         u8 cache_sq_cons;
3651 #elif defined(__LITTLE_ENDIAN)
3652         u8 cache_sq_cons;
3653         u8 cache_xfrq_cons;
3654         u8 cos;
3655         u8 vlan_num;
3656 #endif
3657         u32 verify_tx_seq;
3658 };
3659
3660 /*
3661  * Xstorm FCoE Storm Context
3662  */
3663 struct xstorm_fcoe_st_context {
3664         struct xstorm_fcoe_eth_context_section eth;
3665         struct xstorm_fcoe_context_section fcoe;
3666 };
3667
3668 /*
3669  * Fcoe connection context
3670  */
3671 struct fcoe_context {
3672         struct ustorm_fcoe_st_context ustorm_st_context;
3673         struct tstorm_fcoe_st_context tstorm_st_context;
3674         struct xstorm_fcoe_ag_context xstorm_ag_context;
3675         struct tstorm_fcoe_ag_context tstorm_ag_context;
3676         struct ustorm_fcoe_ag_context ustorm_ag_context;
3677         struct timers_block_context timers_context;
3678         struct xstorm_fcoe_st_context xstorm_st_context;
3679 };
3680
3681 /*
3682  * FCoE init params passed by driver to FW in FCoE init ramrod
3683  * $$KEEP_ENDIANNESS$$
3684  */
3685 struct fcoe_init_ramrod_params {
3686         struct fcoe_kwqe_init1 init_kwqe1;
3687         struct fcoe_kwqe_init2 init_kwqe2;
3688         struct fcoe_kwqe_init3 init_kwqe3;
3689         struct regpair eq_pbl_base;
3690         __le32 eq_pbl_size;
3691         __le32 reserved2;
3692         __le16 eq_prod;
3693         __le16 sb_num;
3694         u8 sb_id;
3695         u8 reserved0;
3696         __le16 reserved1;
3697 };
3698
3699 /*
3700  * FCoE statistics params buffer passed by driver to FW in FCoE statistics
3701  * ramrod $$KEEP_ENDIANNESS$$
3702  */
3703 struct fcoe_stat_ramrod_params {
3704         struct fcoe_kwqe_stat stat_kwqe;
3705 };
3706
3707 /*
3708  * CQ DB CQ producer and pending completion counter
3709  */
3710 struct iscsi_cq_db_prod_pnd_cmpltn_cnt {
3711 #if defined(__BIG_ENDIAN)
3712         u16 cntr;
3713         u16 prod;
3714 #elif defined(__LITTLE_ENDIAN)
3715         u16 prod;
3716         u16 cntr;
3717 #endif
3718 };
3719
3720 /*
3721  * CQ DB pending completion ITT array
3722  */
3723 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr {
3724         struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8];
3725 };
3726
3727 /*
3728  * Cstorm CQ sequence to notify array, updated by driver
3729  */
3730 struct iscsi_cq_db_sqn_2_notify_arr {
3731         u16 sqn[8];
3732 };
3733
3734 /*
3735  * Cstorm iSCSI Storm Context
3736  */
3737 struct cstorm_iscsi_st_context {
3738         struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr;
3739         struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr;
3740         struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr;
3741         struct regpair hq_pbl_base;
3742         struct regpair hq_curr_pbe;
3743         struct regpair task_pbl_base;
3744         struct regpair cq_db_base;
3745 #if defined(__BIG_ENDIAN)
3746         u16 hq_bd_itt;
3747         u16 iscsi_conn_id;
3748 #elif defined(__LITTLE_ENDIAN)
3749         u16 iscsi_conn_id;
3750         u16 hq_bd_itt;
3751 #endif
3752         u32 hq_bd_data_segment_len;
3753         u32 hq_bd_buffer_offset;
3754 #if defined(__BIG_ENDIAN)
3755         u8 rsrv;
3756         u8 cq_proc_en_bit_map;
3757         u8 cq_pend_comp_itt_valid_bit_map;
3758         u8 hq_bd_opcode;
3759 #elif defined(__LITTLE_ENDIAN)
3760         u8 hq_bd_opcode;
3761         u8 cq_pend_comp_itt_valid_bit_map;
3762         u8 cq_proc_en_bit_map;
3763         u8 rsrv;
3764 #endif
3765         u32 hq_tcp_seq;
3766 #if defined(__BIG_ENDIAN)
3767         u16 flags;
3768 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3769 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3770 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3771 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3772 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3773 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3774 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3775 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3776 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3777 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3778 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3779 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3780         u16 hq_cons;
3781 #elif defined(__LITTLE_ENDIAN)
3782         u16 hq_cons;
3783         u16 flags;
3784 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3785 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3786 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3787 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3788 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3789 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3790 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3791 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3792 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3793 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3794 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3795 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3796 #endif
3797         struct regpair rsrv1;
3798 };
3799
3800
3801 /*
3802  * SCSI read/write SQ WQE
3803  */
3804 struct iscsi_cmd_pdu_hdr_little_endian {
3805 #if defined(__BIG_ENDIAN)
3806         u8 opcode;
3807         u8 op_attr;
3808 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3809 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3810 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3811 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3812 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3813 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3814 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3815 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3816 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3817 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3818         u16 rsrv0;
3819 #elif defined(__LITTLE_ENDIAN)
3820         u16 rsrv0;
3821         u8 op_attr;
3822 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3823 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3824 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3825 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3826 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3827 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3828 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3829 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3830 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3831 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3832         u8 opcode;
3833 #endif
3834         u32 data_fields;
3835 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
3836 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
3837 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
3838 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
3839         struct regpair lun;
3840         u32 itt;
3841         u32 expected_data_transfer_length;
3842         u32 cmd_sn;
3843         u32 exp_stat_sn;
3844         u32 scsi_command_block[4];
3845 };
3846
3847
3848 /*
3849  * Buffer per connection, used in Tstorm
3850  */
3851 struct iscsi_conn_buf {
3852         struct regpair reserved[8];
3853 };
3854
3855
3856 /*
3857  * iSCSI context region, used only in iSCSI
3858  */
3859 struct ustorm_iscsi_rq_db {
3860         struct regpair pbl_base;
3861         struct regpair curr_pbe;
3862 };
3863
3864 /*
3865  * iSCSI context region, used only in iSCSI
3866  */
3867 struct ustorm_iscsi_r2tq_db {
3868         struct regpair pbl_base;
3869         struct regpair curr_pbe;
3870 };
3871
3872 /*
3873  * iSCSI context region, used only in iSCSI
3874  */
3875 struct ustorm_iscsi_cq_db {
3876 #if defined(__BIG_ENDIAN)
3877         u16 cq_sn;
3878         u16 prod;
3879 #elif defined(__LITTLE_ENDIAN)
3880         u16 prod;
3881         u16 cq_sn;
3882 #endif
3883         struct regpair curr_pbe;
3884 };
3885
3886 /*
3887  * iSCSI context region, used only in iSCSI
3888  */
3889 struct rings_db {
3890         struct ustorm_iscsi_rq_db rq;
3891         struct ustorm_iscsi_r2tq_db r2tq;
3892         struct ustorm_iscsi_cq_db cq[8];
3893 #if defined(__BIG_ENDIAN)
3894         u16 rq_prod;
3895         u16 r2tq_prod;
3896 #elif defined(__LITTLE_ENDIAN)
3897         u16 r2tq_prod;
3898         u16 rq_prod;
3899 #endif
3900         struct regpair cq_pbl_base;
3901 };
3902
3903 /*
3904  * iSCSI context region, used only in iSCSI
3905  */
3906 struct ustorm_iscsi_placement_db {
3907         u32 sgl_base_lo;
3908         u32 sgl_base_hi;
3909         u32 local_sge_0_address_hi;
3910         u32 local_sge_0_address_lo;
3911 #if defined(__BIG_ENDIAN)
3912         u16 curr_sge_offset;
3913         u16 local_sge_0_size;
3914 #elif defined(__LITTLE_ENDIAN)
3915         u16 local_sge_0_size;
3916         u16 curr_sge_offset;
3917 #endif
3918         u32 local_sge_1_address_hi;
3919         u32 local_sge_1_address_lo;
3920 #if defined(__BIG_ENDIAN)
3921         u8 exp_padding_2b;
3922         u8 nal_len_3b;
3923         u16 local_sge_1_size;
3924 #elif defined(__LITTLE_ENDIAN)
3925         u16 local_sge_1_size;
3926         u8 nal_len_3b;
3927         u8 exp_padding_2b;
3928 #endif
3929 #if defined(__BIG_ENDIAN)
3930         u8 sgl_size;
3931         u8 local_sge_index_2b;
3932         u16 reserved7;
3933 #elif defined(__LITTLE_ENDIAN)
3934         u16 reserved7;
3935         u8 local_sge_index_2b;
3936         u8 sgl_size;
3937 #endif
3938         u32 rem_pdu;
3939         u32 place_db_bitfield_1;
3940 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)
3941 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
3942 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24)
3943 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
3944         u32 place_db_bitfield_2;
3945 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)
3946 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
3947 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24)
3948 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
3949         u32 nal;
3950 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)
3951 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
3952 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24)
3953 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
3954 };
3955
3956 /*
3957  * Ustorm iSCSI Storm Context
3958  */
3959 struct ustorm_iscsi_st_context {
3960         u32 exp_stat_sn;
3961         u32 exp_data_sn;
3962         struct rings_db ring;
3963         struct regpair task_pbl_base;
3964         struct regpair tce_phy_addr;
3965         struct ustorm_iscsi_placement_db place_db;
3966         u32 reserved8;
3967         u32 rem_rcv_len;
3968 #if defined(__BIG_ENDIAN)
3969         u16 hdr_itt;
3970         u16 iscsi_conn_id;
3971 #elif defined(__LITTLE_ENDIAN)
3972         u16 iscsi_conn_id;
3973         u16 hdr_itt;
3974 #endif
3975         u32 nal_bytes;
3976 #if defined(__BIG_ENDIAN)
3977         u8 hdr_second_byte_union;
3978         u8 bitfield_0;
3979 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
3980 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
3981 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
3982 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
3983 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
3984 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
3985 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
3986 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
3987         u8 task_pdu_cache_index;
3988         u8 task_pbe_cache_index;
3989 #elif defined(__LITTLE_ENDIAN)
3990         u8 task_pbe_cache_index;
3991         u8 task_pdu_cache_index;
3992         u8 bitfield_0;
3993 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
3994 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
3995 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
3996 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
3997 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
3998 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
3999 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
4000 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
4001         u8 hdr_second_byte_union;
4002 #endif
4003 #if defined(__BIG_ENDIAN)
4004         u16 reserved3;
4005         u8 reserved2;
4006         u8 acDecrement;
4007 #elif defined(__LITTLE_ENDIAN)
4008         u8 acDecrement;
4009         u8 reserved2;
4010         u16 reserved3;
4011 #endif
4012         u32 task_stat;
4013 #if defined(__BIG_ENDIAN)
4014         u8 hdr_opcode;
4015         u8 num_cqs;
4016         u16 reserved5;
4017 #elif defined(__LITTLE_ENDIAN)
4018         u16 reserved5;
4019         u8 num_cqs;
4020         u8 hdr_opcode;
4021 #endif
4022         u32 negotiated_rx;
4023 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)
4024 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
4025 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24)
4026 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
4027         u32 negotiated_rx_and_flags;
4028 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)
4029 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
4030 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24)
4031 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
4032 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25)
4033 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
4034 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26)
4035 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
4036 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27)
4037 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
4038 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28)
4039 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
4040 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29)
4041 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
4042 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31)
4043 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
4044 };
4045
4046 /*
4047  * TCP context region, shared in TOE, RDMA and ISCSI
4048  */
4049 struct tstorm_tcp_st_context_section {
4050         u32 flags1;
4051 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)
4052 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
4053 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24)
4054 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
4055 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25)
4056 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
4057 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26)
4058 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
4059 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27)
4060 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
4061 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28)
4062 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
4063 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29)
4064 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
4065 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30)
4066 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
4067 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31)
4068 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
4069         u32 flags2;
4070 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)
4071 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
4072 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24)
4073 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
4074 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25)
4075 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
4076 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26)
4077 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
4078 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27)
4079 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
4080 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28)
4081 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
4082 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29)
4083 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
4084 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30)
4085 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
4086 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31)
4087 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
4088 #if defined(__BIG_ENDIAN)
4089         u16 mss;
4090         u8 tcp_sm_state;
4091         u8 rto_exp;
4092 #elif defined(__LITTLE_ENDIAN)
4093         u8 rto_exp;
4094         u8 tcp_sm_state;
4095         u16 mss;
4096 #endif
4097         u32 rcv_nxt;
4098         u32 timestamp_recent;
4099         u32 timestamp_recent_time;
4100         u32 cwnd;
4101         u32 ss_thresh;
4102         u32 cwnd_accum;
4103         u32 prev_seg_seq;
4104         u32 expected_rel_seq;
4105         u32 recover;
4106 #if defined(__BIG_ENDIAN)
4107         u8 retransmit_count;
4108         u8 ka_max_probe_count;
4109         u8 persist_probe_count;
4110         u8 ka_probe_count;
4111 #elif defined(__LITTLE_ENDIAN)
4112         u8 ka_probe_count;
4113         u8 persist_probe_count;
4114         u8 ka_max_probe_count;
4115         u8 retransmit_count;
4116 #endif
4117 #if defined(__BIG_ENDIAN)
4118         u8 statistics_counter_id;
4119         u8 ooo_support_mode;
4120         u8 snd_wnd_scale;
4121         u8 dup_ack_count;
4122 #elif defined(__LITTLE_ENDIAN)
4123         u8 dup_ack_count;
4124         u8 snd_wnd_scale;
4125         u8 ooo_support_mode;
4126         u8 statistics_counter_id;
4127 #endif
4128         u32 retransmit_start_time;
4129         u32 ka_timeout;
4130         u32 ka_interval;
4131         u32 isle_start_seq;
4132         u32 isle_end_seq;
4133 #if defined(__BIG_ENDIAN)
4134         u16 second_isle_address;
4135         u16 recent_seg_wnd;
4136 #elif defined(__LITTLE_ENDIAN)
4137         u16 recent_seg_wnd;
4138         u16 second_isle_address;
4139 #endif
4140 #if defined(__BIG_ENDIAN)
4141         u8 max_isles_ever_happened;
4142         u8 isles_number;
4143         u16 last_isle_address;
4144 #elif defined(__LITTLE_ENDIAN)
4145         u16 last_isle_address;
4146         u8 isles_number;
4147         u8 max_isles_ever_happened;
4148 #endif
4149         u32 max_rt_time;
4150 #if defined(__BIG_ENDIAN)
4151         u16 lsb_mac_address;
4152         u16 vlan_id;
4153 #elif defined(__LITTLE_ENDIAN)
4154         u16 vlan_id;
4155         u16 lsb_mac_address;
4156 #endif
4157 #if defined(__BIG_ENDIAN)
4158         u16 msb_mac_address;
4159         u16 mid_mac_address;
4160 #elif defined(__LITTLE_ENDIAN)
4161         u16 mid_mac_address;
4162         u16 msb_mac_address;
4163 #endif
4164         u32 rightmost_received_seq;
4165 };
4166
4167 /*
4168  * Termination variables
4169  */
4170 struct iscsi_term_vars {
4171         u8 BitMap;
4172 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0)
4173 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
4174 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
4175 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
4176 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
4177 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
4178 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6)
4179 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
4180 #define ISCSI_TERM_VARS_RSRV (0x1<<7)
4181 #define ISCSI_TERM_VARS_RSRV_SHIFT 7
4182 };
4183
4184 /*
4185  * iSCSI context region, used only in iSCSI
4186  */
4187 struct tstorm_iscsi_st_context_section {
4188         u32 nalPayload;
4189         u32 b2nh;
4190 #if defined(__BIG_ENDIAN)
4191         u16 rq_cons;
4192         u8 flags;
4193 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4194 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4195 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4196 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4197 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4198 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4199 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4200 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4201 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4202 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4203 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4204 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4205 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4206 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4207         u8 hdr_bytes_2_fetch;
4208 #elif defined(__LITTLE_ENDIAN)
4209         u8 hdr_bytes_2_fetch;
4210         u8 flags;
4211 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4212 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4213 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4214 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4215 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4216 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4217 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4218 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4219 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4220 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4221 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4222 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4223 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4224 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4225         u16 rq_cons;
4226 #endif
4227         struct regpair rq_db_phy_addr;
4228 #if defined(__BIG_ENDIAN)
4229         struct iscsi_term_vars term_vars;
4230         u8 rsrv1;
4231         u16 iscsi_conn_id;
4232 #elif defined(__LITTLE_ENDIAN)
4233         u16 iscsi_conn_id;
4234         u8 rsrv1;
4235         struct iscsi_term_vars term_vars;
4236 #endif
4237         u32 process_nxt;
4238 };
4239
4240 /*
4241  * The iSCSI non-aggregative context of Tstorm
4242  */
4243 struct tstorm_iscsi_st_context {
4244         struct tstorm_tcp_st_context_section tcp;
4245         struct tstorm_iscsi_st_context_section iscsi;
4246 };
4247
4248 /*
4249  * Ethernet context section, shared in TOE, RDMA and ISCSI
4250  */
4251 struct xstorm_eth_context_section {
4252 #if defined(__BIG_ENDIAN)
4253         u8 remote_addr_4;
4254         u8 remote_addr_5;
4255         u8 local_addr_0;
4256         u8 local_addr_1;
4257 #elif defined(__LITTLE_ENDIAN)
4258         u8 local_addr_1;
4259         u8 local_addr_0;
4260         u8 remote_addr_5;
4261         u8 remote_addr_4;
4262 #endif
4263 #if defined(__BIG_ENDIAN)
4264         u8 remote_addr_0;
4265         u8 remote_addr_1;
4266         u8 remote_addr_2;
4267         u8 remote_addr_3;
4268 #elif defined(__LITTLE_ENDIAN)
4269         u8 remote_addr_3;
4270         u8 remote_addr_2;
4271         u8 remote_addr_1;
4272         u8 remote_addr_0;
4273 #endif
4274 #if defined(__BIG_ENDIAN)
4275         u16 reserved_vlan_type;
4276         u16 vlan_params;
4277 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4278 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4279 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4280 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4281 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4282 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4283 #elif defined(__LITTLE_ENDIAN)
4284         u16 vlan_params;
4285 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4286 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4287 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4288 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4289 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4290 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4291         u16 reserved_vlan_type;
4292 #endif
4293 #if defined(__BIG_ENDIAN)
4294         u8 local_addr_2;
4295         u8 local_addr_3;
4296         u8 local_addr_4;
4297         u8 local_addr_5;
4298 #elif defined(__LITTLE_ENDIAN)
4299         u8 local_addr_5;
4300         u8 local_addr_4;
4301         u8 local_addr_3;
4302         u8 local_addr_2;
4303 #endif
4304 };
4305
4306 /*
4307  * IpV4 context section, shared in TOE, RDMA and ISCSI
4308  */
4309 struct xstorm_ip_v4_context_section {
4310 #if defined(__BIG_ENDIAN)
4311         u16 __pbf_hdr_cmd_rsvd_id;
4312         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4313 #elif defined(__LITTLE_ENDIAN)
4314         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4315         u16 __pbf_hdr_cmd_rsvd_id;
4316 #endif
4317 #if defined(__BIG_ENDIAN)
4318         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4319         u8 tos;
4320         u16 __pbf_hdr_cmd_rsvd_length;
4321 #elif defined(__LITTLE_ENDIAN)
4322         u16 __pbf_hdr_cmd_rsvd_length;
4323         u8 tos;
4324         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4325 #endif
4326         u32 ip_local_addr;
4327 #if defined(__BIG_ENDIAN)
4328         u8 ttl;
4329         u8 __pbf_hdr_cmd_rsvd_protocol;
4330         u16 __pbf_hdr_cmd_rsvd_csum;
4331 #elif defined(__LITTLE_ENDIAN)
4332         u16 __pbf_hdr_cmd_rsvd_csum;
4333         u8 __pbf_hdr_cmd_rsvd_protocol;
4334         u8 ttl;
4335 #endif
4336         u32 __pbf_hdr_cmd_rsvd_1;
4337         u32 ip_remote_addr;
4338 };
4339
4340 /*
4341  * context section, shared in TOE, RDMA and ISCSI
4342  */
4343 struct xstorm_padded_ip_v4_context_section {
4344         struct xstorm_ip_v4_context_section ip_v4;
4345         u32 reserved1[4];
4346 };
4347
4348 /*
4349  * IpV6 context section, shared in TOE, RDMA and ISCSI
4350  */
4351 struct xstorm_ip_v6_context_section {
4352 #if defined(__BIG_ENDIAN)
4353         u16 pbf_hdr_cmd_rsvd_payload_len;
4354         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4355         u8 hop_limit;
4356 #elif defined(__LITTLE_ENDIAN)
4357         u8 hop_limit;
4358         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4359         u16 pbf_hdr_cmd_rsvd_payload_len;
4360 #endif
4361         u32 priority_flow_label;
4362 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0)
4363 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
4364 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20)
4365 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
4366 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28)
4367 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
4368         u32 ip_local_addr_lo_hi;
4369         u32 ip_local_addr_lo_lo;
4370         u32 ip_local_addr_hi_hi;
4371         u32 ip_local_addr_hi_lo;
4372         u32 ip_remote_addr_lo_hi;
4373         u32 ip_remote_addr_lo_lo;
4374         u32 ip_remote_addr_hi_hi;
4375         u32 ip_remote_addr_hi_lo;
4376 };
4377
4378 union xstorm_ip_context_section_types {
4379         struct xstorm_padded_ip_v4_context_section padded_ip_v4;
4380         struct xstorm_ip_v6_context_section ip_v6;
4381 };
4382
4383 /*
4384  * TCP context section, shared in TOE, RDMA and ISCSI
4385  */
4386 struct xstorm_tcp_context_section {
4387         u32 snd_max;
4388 #if defined(__BIG_ENDIAN)
4389         u16 remote_port;
4390         u16 local_port;
4391 #elif defined(__LITTLE_ENDIAN)
4392         u16 local_port;
4393         u16 remote_port;
4394 #endif
4395 #if defined(__BIG_ENDIAN)
4396         u8 original_nagle_1b;
4397         u8 ts_enabled;
4398         u16 tcp_params;
4399 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4400 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4401 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4402 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4403 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4404 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4405 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4406 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4407 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4408 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4409 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4410 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4411 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4412 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4413 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4414 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4415 #elif defined(__LITTLE_ENDIAN)
4416         u16 tcp_params;
4417 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4418 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4419 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4420 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4421 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4422 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4423 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4424 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4425 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4426 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4427 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4428 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4429 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4430 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4431 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4432 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4433         u8 ts_enabled;
4434         u8 original_nagle_1b;
4435 #endif
4436 #if defined(__BIG_ENDIAN)
4437         u16 pseudo_csum;
4438         u16 window_scaling_factor;
4439 #elif defined(__LITTLE_ENDIAN)
4440         u16 window_scaling_factor;
4441         u16 pseudo_csum;
4442 #endif
4443 #if defined(__BIG_ENDIAN)
4444         u16 reserved2;
4445         u8 statistics_counter_id;
4446         u8 statistics_params;
4447 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4448 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4449 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4450 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4451 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4452 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4453 #elif defined(__LITTLE_ENDIAN)
4454         u8 statistics_params;
4455 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4456 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4457 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4458 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4459 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4460 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4461         u8 statistics_counter_id;
4462         u16 reserved2;
4463 #endif
4464         u32 ts_time_diff;
4465         u32 __next_timer_expir;
4466 };
4467
4468 /*
4469  * Common context section, shared in TOE, RDMA and ISCSI
4470  */
4471 struct xstorm_common_context_section {
4472         struct xstorm_eth_context_section ethernet;
4473         union xstorm_ip_context_section_types ip_union;
4474         struct xstorm_tcp_context_section tcp;
4475 #if defined(__BIG_ENDIAN)
4476         u8 __dcb_val;
4477         u8 flags;
4478 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4479 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4480 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4481 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4482 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4483 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4484 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4485 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4486         u8 reserved;
4487         u8 ip_version_1b;
4488 #elif defined(__LITTLE_ENDIAN)
4489         u8 ip_version_1b;
4490         u8 reserved;
4491         u8 flags;
4492 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4493 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4494 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4495 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4496 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4497 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4498 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4499 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4500         u8 __dcb_val;
4501 #endif
4502 };
4503
4504 /*
4505  * Flags used in ISCSI context section
4506  */
4507 struct xstorm_iscsi_context_flags {
4508         u8 flags;
4509 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0)
4510 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
4511 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1)
4512 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
4513 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2)
4514 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
4515 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3)
4516 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
4517 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4)
4518 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
4519 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5)
4520 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
4521 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6)
4522 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
4523 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7)
4524 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
4525 };
4526
4527 struct iscsi_task_context_entry_x {
4528         u32 data_out_buffer_offset;
4529         u32 itt;
4530         u32 data_sn;
4531 };
4532
4533 struct iscsi_task_context_entry_xuc_x_write_only {
4534         u32 tx_r2t_sn;
4535 };
4536
4537 struct iscsi_task_context_entry_xuc_xu_write_both {
4538         u32 sgl_base_lo;
4539         u32 sgl_base_hi;
4540 #if defined(__BIG_ENDIAN)
4541         u8 sgl_size;
4542         u8 sge_index;
4543         u16 sge_offset;
4544 #elif defined(__LITTLE_ENDIAN)
4545         u16 sge_offset;
4546         u8 sge_index;
4547         u8 sgl_size;
4548 #endif
4549 };
4550
4551 /*
4552  * iSCSI context section
4553  */
4554 struct xstorm_iscsi_context_section {
4555         u32 first_burst_length;
4556         u32 max_send_pdu_length;
4557         struct regpair sq_pbl_base;
4558         struct regpair sq_curr_pbe;
4559         struct regpair hq_pbl_base;
4560         struct regpair hq_curr_pbe_base;
4561         struct regpair r2tq_pbl_base;
4562         struct regpair r2tq_curr_pbe_base;
4563         struct regpair task_pbl_base;
4564 #if defined(__BIG_ENDIAN)
4565         u16 data_out_count;
4566         struct xstorm_iscsi_context_flags flags;
4567         u8 task_pbl_cache_idx;
4568 #elif defined(__LITTLE_ENDIAN)
4569         u8 task_pbl_cache_idx;
4570         struct xstorm_iscsi_context_flags flags;
4571         u16 data_out_count;
4572 #endif
4573         u32 seq_more_2_send;
4574         u32 pdu_more_2_send;
4575         struct iscsi_task_context_entry_x temp_tce_x;
4576         struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr;
4577         struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr;
4578         struct regpair lun;
4579         u32 exp_data_transfer_len_ttt;
4580         u32 pdu_data_2_rxmit;
4581         u32 rxmit_bytes_2_dr;
4582 #if defined(__BIG_ENDIAN)
4583         u16 rxmit_sge_offset;
4584         u16 hq_rxmit_cons;
4585 #elif defined(__LITTLE_ENDIAN)
4586         u16 hq_rxmit_cons;
4587         u16 rxmit_sge_offset;
4588 #endif
4589 #if defined(__BIG_ENDIAN)
4590         u16 r2tq_cons;
4591         u8 rxmit_flags;
4592 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4593 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4594 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4595 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4596 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4597 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4598 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4599 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4600 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4601 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4602 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4603 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4604 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4605 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4606         u8 rxmit_sge_idx;
4607 #elif defined(__LITTLE_ENDIAN)
4608         u8 rxmit_sge_idx;
4609         u8 rxmit_flags;
4610 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4611 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4612 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4613 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4614 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4615 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4616 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4617 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4618 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4619 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4620 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4621 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4622 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4623 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4624         u16 r2tq_cons;
4625 #endif
4626         u32 hq_rxmit_tcp_seq;
4627 };
4628
4629 /*
4630  * Xstorm iSCSI Storm Context
4631  */
4632 struct xstorm_iscsi_st_context {
4633         struct xstorm_common_context_section common;
4634         struct xstorm_iscsi_context_section iscsi;
4635 };
4636
4637 /*
4638  * Iscsi connection context
4639  */
4640 struct iscsi_context {
4641         struct ustorm_iscsi_st_context ustorm_st_context;
4642         struct tstorm_iscsi_st_context tstorm_st_context;
4643         struct xstorm_iscsi_ag_context xstorm_ag_context;
4644         struct tstorm_iscsi_ag_context tstorm_ag_context;
4645         struct cstorm_iscsi_ag_context cstorm_ag_context;
4646         struct ustorm_iscsi_ag_context ustorm_ag_context;
4647         struct timers_block_context timers_context;
4648         struct regpair upb_context;
4649         struct xstorm_iscsi_st_context xstorm_st_context;
4650         struct regpair xpb_context;
4651         struct cstorm_iscsi_st_context cstorm_st_context;
4652 };
4653
4654
4655 /*
4656  * PDU header of an iSCSI DATA-OUT
4657  */
4658 struct iscsi_data_pdu_hdr_little_endian {
4659 #if defined(__BIG_ENDIAN)
4660         u8 opcode;
4661         u8 op_attr;
4662 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4663 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4664 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4665 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4666         u16 rsrv0;
4667 #elif defined(__LITTLE_ENDIAN)
4668         u16 rsrv0;
4669         u8 op_attr;
4670 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4671 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4672 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4673 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4674         u8 opcode;
4675 #endif
4676         u32 data_fields;
4677 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4678 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4679 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4680 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4681         struct regpair lun;
4682         u32 itt;
4683         u32 ttt;
4684         u32 rsrv2;
4685         u32 exp_stat_sn;
4686         u32 rsrv3;
4687         u32 data_sn;
4688         u32 buffer_offset;
4689         u32 rsrv4;
4690 };
4691
4692
4693 /*
4694  * PDU header of an iSCSI login request
4695  */
4696 struct iscsi_login_req_hdr_little_endian {
4697 #if defined(__BIG_ENDIAN)
4698         u8 opcode;
4699         u8 op_attr;
4700 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4701 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4702 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4703 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4704 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4705 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4706 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4707 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4708 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4709 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4710         u8 version_max;
4711         u8 version_min;
4712 #elif defined(__LITTLE_ENDIAN)
4713         u8 version_min;
4714         u8 version_max;
4715         u8 op_attr;
4716 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4717 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4718 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4719 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4720 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4721 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4722 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4723 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4724 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4725 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4726         u8 opcode;
4727 #endif
4728         u32 data_fields;
4729 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4730 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4731 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4732 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4733         u32 isid_lo;
4734 #if defined(__BIG_ENDIAN)
4735         u16 isid_hi;
4736         u16 tsih;
4737 #elif defined(__LITTLE_ENDIAN)
4738         u16 tsih;
4739         u16 isid_hi;
4740 #endif
4741         u32 itt;
4742 #if defined(__BIG_ENDIAN)
4743         u16 cid;
4744         u16 rsrv1;
4745 #elif defined(__LITTLE_ENDIAN)
4746         u16 rsrv1;
4747         u16 cid;
4748 #endif
4749         u32 cmd_sn;
4750         u32 exp_stat_sn;
4751         u32 rsrv2[4];
4752 };
4753
4754 /*
4755  * PDU header of an iSCSI logout request
4756  */
4757 struct iscsi_logout_req_hdr_little_endian {
4758 #if defined(__BIG_ENDIAN)
4759         u8 opcode;
4760         u8 op_attr;
4761 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4762 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4763 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4764 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4765         u16 rsrv0;
4766 #elif defined(__LITTLE_ENDIAN)
4767         u16 rsrv0;
4768         u8 op_attr;
4769 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4770 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4771 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4772 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4773         u8 opcode;
4774 #endif
4775         u32 data_fields;
4776 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4777 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4778 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4779 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4780         u32 rsrv2[2];
4781         u32 itt;
4782 #if defined(__BIG_ENDIAN)
4783         u16 cid;
4784         u16 rsrv1;
4785 #elif defined(__LITTLE_ENDIAN)
4786         u16 rsrv1;
4787         u16 cid;
4788 #endif
4789         u32 cmd_sn;
4790         u32 exp_stat_sn;
4791         u32 rsrv3[4];
4792 };
4793
4794 /*
4795  * PDU header of an iSCSI TMF request
4796  */
4797 struct iscsi_tmf_req_hdr_little_endian {
4798 #if defined(__BIG_ENDIAN)
4799         u8 opcode;
4800         u8 op_attr;
4801 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4802 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4803 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4804 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4805         u16 rsrv0;
4806 #elif defined(__LITTLE_ENDIAN)
4807         u16 rsrv0;
4808         u8 op_attr;
4809 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4810 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4811 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4812 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4813         u8 opcode;
4814 #endif
4815         u32 data_fields;
4816 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4817 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4818 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4819 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4820         struct regpair lun;
4821         u32 itt;
4822         u32 referenced_task_tag;
4823         u32 cmd_sn;
4824         u32 exp_stat_sn;
4825         u32 ref_cmd_sn;
4826         u32 exp_data_sn;
4827         u32 rsrv2[2];
4828 };
4829
4830 /*
4831  * PDU header of an iSCSI Text request
4832  */
4833 struct iscsi_text_req_hdr_little_endian {
4834 #if defined(__BIG_ENDIAN)
4835         u8 opcode;
4836         u8 op_attr;
4837 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4838 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4839 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4840 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4841 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4842 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4843         u16 rsrv0;
4844 #elif defined(__LITTLE_ENDIAN)
4845         u16 rsrv0;
4846         u8 op_attr;
4847 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4848 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4849 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4850 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4851 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4852 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4853         u8 opcode;
4854 #endif
4855         u32 data_fields;
4856 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4857 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4858 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4859 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4860         struct regpair lun;
4861         u32 itt;
4862         u32 ttt;
4863         u32 cmd_sn;
4864         u32 exp_stat_sn;
4865         u32 rsrv3[4];
4866 };
4867
4868 /*
4869  * PDU header of an iSCSI Nop-Out
4870  */
4871 struct iscsi_nop_out_hdr_little_endian {
4872 #if defined(__BIG_ENDIAN)
4873         u8 opcode;
4874         u8 op_attr;
4875 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4876 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4877 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4878 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4879         u16 rsrv0;
4880 #elif defined(__LITTLE_ENDIAN)
4881         u16 rsrv0;
4882         u8 op_attr;
4883 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4884 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4885 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4886 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4887         u8 opcode;
4888 #endif
4889         u32 data_fields;
4890 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4891 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4892 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4893 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4894         struct regpair lun;
4895         u32 itt;
4896         u32 ttt;
4897         u32 cmd_sn;
4898         u32 exp_stat_sn;
4899         u32 rsrv3[4];
4900 };
4901
4902 /*
4903  * iscsi pdu headers in little endian form.
4904  */
4905 union iscsi_pdu_headers_little_endian {
4906         u32 fullHeaderSize[12];
4907         struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr;
4908         struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr;
4909         struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr;
4910         struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr;
4911         struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr;
4912         struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr;
4913         struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr;
4914 };
4915
4916 struct iscsi_hq_bd {
4917         union iscsi_pdu_headers_little_endian pdu_header;
4918 #if defined(__BIG_ENDIAN)
4919         u16 reserved1;
4920         u16 lcl_cmp_flg;
4921 #elif defined(__LITTLE_ENDIAN)
4922         u16 lcl_cmp_flg;
4923         u16 reserved1;
4924 #endif
4925         u32 sgl_base_lo;
4926         u32 sgl_base_hi;
4927 #if defined(__BIG_ENDIAN)
4928         u8 sgl_size;
4929         u8 sge_index;
4930         u16 sge_offset;
4931 #elif defined(__LITTLE_ENDIAN)
4932         u16 sge_offset;
4933         u8 sge_index;
4934         u8 sgl_size;
4935 #endif
4936 };
4937
4938
4939 /*
4940  * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$
4941  */
4942 struct iscsi_l2_ooo_data {
4943         __le32 iscsi_cid;
4944         u8 drop_isle;
4945         u8 drop_size;
4946         u8 ooo_opcode;
4947         u8 ooo_isle;
4948         u8 reserved[8];
4949 };
4950
4951
4952
4953
4954
4955
4956 struct iscsi_task_context_entry_xuc_c_write_only {
4957         u32 total_data_acked;
4958 };
4959
4960 struct iscsi_task_context_r2t_table_entry {
4961         u32 ttt;
4962         u32 desired_data_len;
4963 };
4964
4965 struct iscsi_task_context_entry_xuc_u_write_only {
4966         u32 exp_r2t_sn;
4967         struct iscsi_task_context_r2t_table_entry r2t_table[4];
4968 #if defined(__BIG_ENDIAN)
4969         u16 data_in_count;
4970         u8 cq_id;
4971         u8 valid_1b;
4972 #elif defined(__LITTLE_ENDIAN)
4973         u8 valid_1b;
4974         u8 cq_id;
4975         u16 data_in_count;
4976 #endif
4977 };
4978
4979 struct iscsi_task_context_entry_xuc {
4980         struct iscsi_task_context_entry_xuc_c_write_only write_c;
4981         u32 exp_data_transfer_len;
4982         struct iscsi_task_context_entry_xuc_x_write_only write_x;
4983         u32 lun_lo;
4984         struct iscsi_task_context_entry_xuc_xu_write_both write_xu;
4985         u32 lun_hi;
4986         struct iscsi_task_context_entry_xuc_u_write_only write_u;
4987 };
4988
4989 struct iscsi_task_context_entry_u {
4990         u32 exp_r2t_buff_offset;
4991         u32 rem_rcv_len;
4992         u32 exp_data_sn;
4993 };
4994
4995 struct iscsi_task_context_entry {
4996         struct iscsi_task_context_entry_x tce_x;
4997 #if defined(__BIG_ENDIAN)
4998         u16 data_out_count;
4999         u16 rsrv0;
5000 #elif defined(__LITTLE_ENDIAN)
5001         u16 rsrv0;
5002         u16 data_out_count;
5003 #endif
5004         struct iscsi_task_context_entry_xuc tce_xuc;
5005         struct iscsi_task_context_entry_u tce_u;
5006         u32 rsrv1[7];
5007 };
5008
5009
5010
5011
5012
5013
5014
5015
5016 struct iscsi_task_context_entry_xuc_x_init_only {
5017         struct regpair lun;
5018         u32 exp_data_transfer_len;
5019 };
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037 /*
5038  * ipv6 structure
5039  */
5040 struct ip_v6_addr {
5041         u32 ip_addr_lo_lo;
5042         u32 ip_addr_lo_hi;
5043         u32 ip_addr_hi_lo;
5044         u32 ip_addr_hi_hi;
5045 };
5046
5047
5048
5049 /*
5050  * l5cm- connection identification params
5051  */
5052 struct l5cm_conn_addr_params {
5053         u32 pmtu;
5054 #if defined(__BIG_ENDIAN)
5055         u8 remote_addr_3;
5056         u8 remote_addr_2;
5057         u8 remote_addr_1;
5058         u8 remote_addr_0;
5059 #elif defined(__LITTLE_ENDIAN)
5060         u8 remote_addr_0;
5061         u8 remote_addr_1;
5062         u8 remote_addr_2;
5063         u8 remote_addr_3;
5064 #endif
5065 #if defined(__BIG_ENDIAN)
5066         u16 params;
5067 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5068 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5069 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5070 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5071         u8 remote_addr_5;
5072         u8 remote_addr_4;
5073 #elif defined(__LITTLE_ENDIAN)
5074         u8 remote_addr_4;
5075         u8 remote_addr_5;
5076         u16 params;
5077 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5078 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5079 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5080 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5081 #endif
5082         struct ip_v6_addr local_ip_addr;
5083         struct ip_v6_addr remote_ip_addr;
5084         u32 ipv6_flow_label_20b;
5085         u32 reserved1;
5086 #if defined(__BIG_ENDIAN)
5087         u16 remote_tcp_port;
5088         u16 local_tcp_port;
5089 #elif defined(__LITTLE_ENDIAN)
5090         u16 local_tcp_port;
5091         u16 remote_tcp_port;
5092 #endif
5093 };
5094
5095 /*
5096  * l5cm-xstorm connection buffer
5097  */
5098 struct l5cm_xstorm_conn_buffer {
5099 #if defined(__BIG_ENDIAN)
5100         u16 rsrv1;
5101         u16 params;
5102 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5103 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5104 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5105 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5106 #elif defined(__LITTLE_ENDIAN)
5107         u16 params;
5108 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5109 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5110 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5111 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5112         u16 rsrv1;
5113 #endif
5114 #if defined(__BIG_ENDIAN)
5115         u16 mss;
5116         u16 pseudo_header_checksum;
5117 #elif defined(__LITTLE_ENDIAN)
5118         u16 pseudo_header_checksum;
5119         u16 mss;
5120 #endif
5121         u32 rcv_buf;
5122         u32 rsrv2;
5123         struct regpair context_addr;
5124 };
5125
5126 /*
5127  * l5cm-tstorm connection buffer
5128  */
5129 struct l5cm_tstorm_conn_buffer {
5130         u32 rsrv1[2];
5131 #if defined(__BIG_ENDIAN)
5132         u16 params;
5133 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5134 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5135 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5136 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5137         u8 ka_max_probe_count;
5138         u8 ka_enable;
5139 #elif defined(__LITTLE_ENDIAN)
5140         u8 ka_enable;
5141         u8 ka_max_probe_count;
5142         u16 params;
5143 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5144 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5145 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5146 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5147 #endif
5148         u32 ka_timeout;
5149         u32 ka_interval;
5150         u32 max_rt_time;
5151 };
5152
5153 /*
5154  * l5cm connection buffer for active side
5155  */
5156 struct l5cm_active_conn_buffer {
5157         struct l5cm_conn_addr_params conn_addr_buf;
5158         struct l5cm_xstorm_conn_buffer xstorm_conn_buffer;
5159         struct l5cm_tstorm_conn_buffer tstorm_conn_buffer;
5160 };
5161
5162
5163
5164 /*
5165  * The l5cm opaque buffer passed in add new connection ramrod passive side
5166  */
5167 struct l5cm_hash_input_string {
5168         u32 __opaque1;
5169 #if defined(__BIG_ENDIAN)
5170         u16 __opaque3;
5171         u16 __opaque2;
5172 #elif defined(__LITTLE_ENDIAN)
5173         u16 __opaque2;
5174         u16 __opaque3;
5175 #endif
5176         struct ip_v6_addr __opaque4;
5177         struct ip_v6_addr __opaque5;
5178         u32 __opaque6;
5179         u32 __opaque7[5];
5180 };
5181
5182
5183 /*
5184  * syn cookie component
5185  */
5186 struct l5cm_syn_cookie_comp {
5187         u32 __opaque;
5188 };
5189
5190 /*
5191  * data related to listeners of a TCP port
5192  */
5193 struct l5cm_port_listener_data {
5194         u8 params;
5195 #define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0)
5196 #define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0
5197 #define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1)
5198 #define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1
5199 #define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5)
5200 #define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5
5201 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6)
5202 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6
5203 #define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7)
5204 #define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7
5205 };
5206
5207 /*
5208  * Opaque structure passed from U to X when final ack arrives
5209  */
5210 struct l5cm_opaque_buf {
5211         u32 __opaque1;
5212         u32 __opaque2;
5213         u32 __opaque3;
5214         u32 __opaque4;
5215         struct l5cm_syn_cookie_comp __opaque5;
5216 #if defined(__BIG_ENDIAN)
5217         u16 rsrv2;
5218         u8 rsrv;
5219         struct l5cm_port_listener_data __opaque6;
5220 #elif defined(__LITTLE_ENDIAN)
5221         struct l5cm_port_listener_data __opaque6;
5222         u8 rsrv;
5223         u16 rsrv2;
5224 #endif
5225 };
5226
5227
5228 /*
5229  * l5cm slow path element
5230  */
5231 struct l5cm_packet_size {
5232         u32 size;
5233         u32 rsrv;
5234 };
5235
5236
5237 /*
5238  * The final-ack union structure in PCS entry after final ack arrived
5239  */
5240 struct l5cm_pcse_ack {
5241         struct l5cm_xstorm_conn_buffer tx_socket_params;
5242         struct l5cm_opaque_buf opaque_buf;
5243         struct l5cm_tstorm_conn_buffer rx_socket_params;
5244 };
5245
5246
5247 /*
5248  * The syn union structure in PCS entry after syn arrived
5249  */
5250 struct l5cm_pcse_syn {
5251         struct l5cm_opaque_buf opaque_buf;
5252         u32 rsrv[12];
5253 };
5254
5255
5256 /*
5257  * pcs entry data for passive connections
5258  */
5259 struct l5cm_pcs_attributes {
5260 #if defined(__BIG_ENDIAN)
5261         u16 pcs_id;
5262         u8 status;
5263         u8 flags;
5264 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5265 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5266 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5267 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5268 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5269 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5270 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5271 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5272 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5273 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5274 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5275 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5276 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5277 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5278 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5279 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5280 #elif defined(__LITTLE_ENDIAN)
5281         u8 flags;
5282 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5283 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5284 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5285 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5286 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5287 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5288 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5289 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5290 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5291 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5292 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5293 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5294 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5295 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5296 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5297 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5298         u8 status;
5299         u16 pcs_id;
5300 #endif
5301 };
5302
5303
5304 union l5cm_seg_params {
5305         struct l5cm_pcse_syn syn_seg_params;
5306         struct l5cm_pcse_ack ack_seg_params;
5307 };
5308
5309 /*
5310  * pcs entry data for passive connections
5311  */
5312 struct l5cm_pcs_hdr {
5313         struct l5cm_hash_input_string hash_input_string;
5314         struct l5cm_conn_addr_params conn_addr_buf;
5315         u32 cid;
5316         u32 hash_result;
5317         union l5cm_seg_params seg_params;
5318         struct l5cm_pcs_attributes att;
5319 #if defined(__BIG_ENDIAN)
5320         u16 rsrv;
5321         u16 rx_seg_size;
5322 #elif defined(__LITTLE_ENDIAN)
5323         u16 rx_seg_size;
5324         u16 rsrv;
5325 #endif
5326 };
5327
5328 /*
5329  * pcs entry for passive connections
5330  */
5331 struct l5cm_pcs_entry {
5332         struct l5cm_pcs_hdr hdr;
5333         u8 rx_segment[1516];
5334 };
5335
5336
5337
5338
5339 /*
5340  * l5cm connection parameters
5341  */
5342 union l5cm_reduce_param_union {
5343         u32 opaque1;
5344         u32 opaque2;
5345 };
5346
5347 /*
5348  * l5cm connection parameters
5349  */
5350 struct l5cm_reduce_conn {
5351         union l5cm_reduce_param_union opaque1;
5352         u32 opaque2;
5353 };
5354
5355 /*
5356  * l5cm slow path element
5357  */
5358 union l5cm_specific_data {
5359         u8 protocol_data[8];
5360         struct regpair phy_address;
5361         struct l5cm_packet_size packet_size;
5362         struct l5cm_reduce_conn reduced_conn;
5363 };
5364
5365 /*
5366  * l5 slow path element
5367  */
5368 struct l5cm_spe {
5369         struct spe_hdr hdr;
5370         union l5cm_specific_data data;
5371 };
5372
5373
5374
5375
5376 /*
5377  * Termination variables
5378  */
5379 struct l5cm_term_vars {
5380         u8 BitMap;
5381 #define L5CM_TERM_VARS_TCP_STATE (0xF<<0)
5382 #define L5CM_TERM_VARS_TCP_STATE_SHIFT 0
5383 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
5384 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
5385 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
5386 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
5387 #define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6)
5388 #define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6
5389 #define L5CM_TERM_VARS_RSRV (0x1<<7)
5390 #define L5CM_TERM_VARS_RSRV_SHIFT 7
5391 };
5392
5393
5394
5395
5396 /*
5397  * Tstorm Tcp flags
5398  */
5399 struct tstorm_l5cm_tcp_flags {
5400         u16 flags;
5401 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0)
5402 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
5403 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12)
5404 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12
5405 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13)
5406 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
5407 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14)
5408 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
5409 };
5410
5411
5412 /*
5413  * Xstorm Tcp flags
5414  */
5415 struct xstorm_l5cm_tcp_flags {
5416         u8 flags;
5417 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0)
5418 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0
5419 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1)
5420 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1
5421 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2)
5422 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2
5423 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3)
5424 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3
5425 };
5426
5427
5428
5429 /*
5430  * Out-of-order states
5431  */
5432 enum tcp_ooo_event {
5433         TCP_EVENT_ADD_PEN = 0,
5434         TCP_EVENT_ADD_NEW_ISLE = 1,
5435         TCP_EVENT_ADD_ISLE_RIGHT = 2,
5436         TCP_EVENT_ADD_ISLE_LEFT = 3,
5437         TCP_EVENT_JOIN = 4,
5438         TCP_EVENT_NOP = 5,
5439         MAX_TCP_OOO_EVENT
5440 };
5441
5442
5443 /*
5444  * OOO support modes
5445  */
5446 enum tcp_tstorm_ooo {
5447         TCP_TSTORM_OOO_DROP_AND_PROC_ACK = 0,
5448         TCP_TSTORM_OOO_SEND_PURE_ACK = 1,
5449         TCP_TSTORM_OOO_SUPPORTED = 2,
5450         MAX_TCP_TSTORM_OOO
5451 };
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461 #endif /* __5710_HSI_CNIC_LE__ */