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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / ethernet / dec / tulip / dmfe.c
blob4d6fe604fa64b920d58b05f3989a365355f951c3
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
66 #define DRV_NAME "dmfe"
67 #define DRV_VERSION "1.36.4"
68 #define DRV_RELDATE "2002-01-17"
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/ptrace.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/ethtool.h>
84 #include <linux/skbuff.h>
85 #include <linux/delay.h>
86 #include <linux/spinlock.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89
90 #include <asm/processor.h>
91 #include <asm/io.h>
92 #include <asm/dma.h>
93 #include <asm/uaccess.h>
94 #include <asm/irq.h>
95
96 #ifdef CONFIG_TULIP_DM910X
97 #include <linux/of.h>
98 #endif
99
100
101 /* Board/System/Debug information/definition ---------------- */
102 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107 #define DM9102_IO_SIZE 0x80
108 #define DM9102A_IO_SIZE 0x100
109 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115 #define TX_BUF_ALLOC 0x600
116 #define RX_ALLOC_SIZE 0x620
117 #define DM910X_RESET 1
118 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119 #define CR6_DEFAULT 0x00080000 /* HD */
120 #define CR7_DEFAULT 0x180c1
121 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123 #define MAX_PACKET_SIZE 1514
124 #define DMFE_MAX_MULTICAST 14
125 #define RX_COPY_SIZE 100
126 #define MAX_CHECK_PACKET 0x8000
127 #define DM9801_NOISE_FLOOR 8
128 #define DM9802_NOISE_FLOOR 5
129
130 #define DMFE_WOL_LINKCHANGE 0x20000000
131 #define DMFE_WOL_SAMPLEPACKET 0x10000000
132 #define DMFE_WOL_MAGICPACKET 0x08000000
133
134
135 #define DMFE_10MHF 0
136 #define DMFE_100MHF 1
137 #define DMFE_10MFD 4
138 #define DMFE_100MFD 5
139 #define DMFE_AUTO 8
140 #define DMFE_1M_HPNA 0x10
141
142 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
153 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
154 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
155 #define dr32(reg) ioread32(ioaddr + (reg))
156 #define dr16(reg) ioread16(ioaddr + (reg))
157 #define dr8(reg) ioread8(ioaddr + (reg))
158
159 #define DMFE_DBUG(dbug_now, msg, value) \
160 do { \
161 if (dmfe_debug || (dbug_now)) \
162 pr_err("%s %lx\n", \
163 (msg), (long) (value)); \
164 } while (0)
165
166 #define SHOW_MEDIA_TYPE(mode) \
167 pr_info("Change Speed to %sMhz %s duplex\n" , \
168 (mode & 1) ? "100":"10", \
169 (mode & 4) ? "full":"half");
170
171
172 /* CR9 definition: SROM/MII */
173 #define CR9_SROM_READ 0x4800
174 #define CR9_SRCS 0x1
175 #define CR9_SRCLK 0x2
176 #define CR9_CRDOUT 0x8
177 #define SROM_DATA_0 0x0
178 #define SROM_DATA_1 0x4
179 #define PHY_DATA_1 0x20000
180 #define PHY_DATA_0 0x00000
181 #define MDCLKH 0x10000
182
183 #define PHY_POWER_DOWN 0x800
184
185 #define SROM_V41_CODE 0x14
186
187 #define __CHK_IO_SIZE(pci_id, dev_rev) \
188 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
189 DM9102A_IO_SIZE: DM9102_IO_SIZE)
190
191 #define CHK_IO_SIZE(pci_dev) \
192 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
193 (pci_dev)->revision))
194
195 /* Sten Check */
196 #define DEVICE net_device
197
198 /* Structure/enum declaration ------------------------------- */
199 struct tx_desc {
200 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
201 char *tx_buf_ptr; /* Data for us */
202 struct tx_desc *next_tx_desc;
203 } __attribute__(( aligned(32) ));
204
205 struct rx_desc {
206 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
207 struct sk_buff *rx_skb_ptr; /* Data for us */
208 struct rx_desc *next_rx_desc;
209 } __attribute__(( aligned(32) ));
210
211 struct dmfe_board_info {
212 u32 chip_id; /* Chip vendor/Device ID */
213 u8 chip_revision; /* Chip revision */
214 struct net_device *next_dev; /* next device */
215 struct pci_dev *pdev; /* PCI device */
216 spinlock_t lock;
217
218 void __iomem *ioaddr; /* I/O base address */
219 u32 cr0_data;
220 u32 cr5_data;
221 u32 cr6_data;
222 u32 cr7_data;
223 u32 cr15_data;
224
225 /* pointer for memory physical address */
226 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
227 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
228 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
229 dma_addr_t first_tx_desc_dma;
230 dma_addr_t first_rx_desc_dma;
231
232 /* descriptor pointer */
233 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
234 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
235 unsigned char *desc_pool_ptr; /* descriptor pool memory */
236 struct tx_desc *first_tx_desc;
237 struct tx_desc *tx_insert_ptr;
238 struct tx_desc *tx_remove_ptr;
239 struct rx_desc *first_rx_desc;
240 struct rx_desc *rx_insert_ptr;
241 struct rx_desc *rx_ready_ptr; /* packet come pointer */
242 unsigned long tx_packet_cnt; /* transmitted packet count */
243 unsigned long tx_queue_cnt; /* wait to send packet count */
244 unsigned long rx_avail_cnt; /* available rx descriptor count */
245 unsigned long interval_rx_cnt; /* rx packet count a callback time */
246
247 u16 HPNA_command; /* For HPNA register 16 */
248 u16 HPNA_timer; /* For HPNA remote device check */
249 u16 dbug_cnt;
250 u16 NIC_capability; /* NIC media capability */
251 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
252
253 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
254 u8 chip_type; /* Keep DM9102A chip type */
255 u8 media_mode; /* user specify media mode */
256 u8 op_mode; /* real work media mode */
257 u8 phy_addr;
258 u8 wait_reset; /* Hardware failed, need to reset */
259 u8 dm910x_chk_mode; /* Operating mode check */
260 u8 first_in_callback; /* Flag to record state */
261 u8 wol_mode; /* user WOL settings */
262 struct timer_list timer;
263
264 /* Driver defined statistic counter */
265 unsigned long tx_fifo_underrun;
266 unsigned long tx_loss_carrier;
267 unsigned long tx_no_carrier;
268 unsigned long tx_late_collision;
269 unsigned long tx_excessive_collision;
270 unsigned long tx_jabber_timeout;
271 unsigned long reset_count;
272 unsigned long reset_cr8;
273 unsigned long reset_fatal;
274 unsigned long reset_TXtimeout;
275
276 /* NIC SROM data */
277 unsigned char srom[128];
278 };
279
280 enum dmfe_offsets {
281 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
282 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
283 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
284 DCR15 = 0x78
285 };
286
287 enum dmfe_CR6_bits {
288 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
289 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
290 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
291 };
292
293 /* Global variable declaration ----------------------------- */
294 static int __devinitdata printed_version;
295 static const char version[] __devinitconst =
296 "Davicom DM9xxx net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
297
298 static int dmfe_debug;
299 static unsigned char dmfe_media_mode = DMFE_AUTO;
300 static u32 dmfe_cr6_user_set;
301
302 /* For module input parameter */
303 static int debug;
304 static u32 cr6set;
305 static unsigned char mode = 8;
306 static u8 chkmode = 1;
307 static u8 HPNA_mode; /* Default: Low Power/High Speed */
308 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
309 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
310 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
311 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
312 4: TX pause packet */
313
314
315 /* function declaration ------------------------------------- */
316 static int dmfe_open(struct DEVICE *);
317 static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
318 static int dmfe_stop(struct DEVICE *);
319 static void dmfe_set_filter_mode(struct DEVICE *);
320 static const struct ethtool_ops netdev_ethtool_ops;
321 static u16 read_srom_word(void __iomem *, int);
322 static irqreturn_t dmfe_interrupt(int , void *);
323 #ifdef CONFIG_NET_POLL_CONTROLLER
324 static void poll_dmfe (struct net_device *dev);
325 #endif
326 static void dmfe_descriptor_init(struct net_device *);
327 static void allocate_rx_buffer(struct net_device *);
328 static void update_cr6(u32, void __iomem *);
329 static void send_filter_frame(struct DEVICE *);
330 static void dm9132_id_table(struct DEVICE *);
331 static u16 phy_read(void __iomem *, u8, u8, u32);
332 static void phy_write(void __iomem *, u8, u8, u16, u32);
333 static void phy_write_1bit(void __iomem *, u32);
334 static u16 phy_read_1bit(void __iomem *);
335 static u8 dmfe_sense_speed(struct dmfe_board_info *);
336 static void dmfe_process_mode(struct dmfe_board_info *);
337 static void dmfe_timer(unsigned long);
338 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
339 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
340 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
341 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
342 static void dmfe_dynamic_reset(struct DEVICE *);
343 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
344 static void dmfe_init_dm910x(struct DEVICE *);
345 static void dmfe_parse_srom(struct dmfe_board_info *);
346 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
347 static void dmfe_program_DM9802(struct dmfe_board_info *);
348 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
349 static void dmfe_set_phyxcer(struct dmfe_board_info *);
350
351 /* DM910X network board routine ---------------------------- */
352
353 static const struct net_device_ops netdev_ops = {
354 .ndo_open = dmfe_open,
355 .ndo_stop = dmfe_stop,
356 .ndo_start_xmit = dmfe_start_xmit,
357 .ndo_set_rx_mode = dmfe_set_filter_mode,
358 .ndo_change_mtu = eth_change_mtu,
359 .ndo_set_mac_address = eth_mac_addr,
360 .ndo_validate_addr = eth_validate_addr,
361 #ifdef CONFIG_NET_POLL_CONTROLLER
362 .ndo_poll_controller = poll_dmfe,
363 #endif
364 };
365
366 /*
367 * Search DM910X board ,allocate space and register it
368 */
369
370 static int __devinit dmfe_init_one (struct pci_dev *pdev,
371 const struct pci_device_id *ent)
372 {
373 struct dmfe_board_info *db; /* board information structure */
374 struct net_device *dev;
375 u32 pci_pmr;
376 int i, err;
377
378 DMFE_DBUG(0, "dmfe_init_one()", 0);
379
380 if (!printed_version++)
381 pr_info("%s\n", version);
382
383 /*
384 * SPARC on-board DM910x chips should be handled by the main
385 * tulip driver, except for early DM9100s.
386 */
387 #ifdef CONFIG_TULIP_DM910X
388 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
389 ent->driver_data == PCI_DM9102_ID) {
390 struct device_node *dp = pci_device_to_OF_node(pdev);
391
392 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
393 pr_info("skipping on-board DM910x (use tulip)\n");
394 return -ENODEV;
395 }
396 }
397 #endif
398
399 /* Init network device */
400 dev = alloc_etherdev(sizeof(*db));
401 if (dev == NULL)
402 return -ENOMEM;
403 SET_NETDEV_DEV(dev, &pdev->dev);
404
405 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
406 pr_warn("32-bit PCI DMA not available\n");
407 err = -ENODEV;
408 goto err_out_free;
409 }
410
411 /* Enable Master/IO access, Disable memory access */
412 err = pci_enable_device(pdev);
413 if (err)
414 goto err_out_free;
415
416 if (!pci_resource_start(pdev, 0)) {
417 pr_err("I/O base is zero\n");
418 err = -ENODEV;
419 goto err_out_disable;
420 }
421
422 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
423 pr_err("Allocated I/O size too small\n");
424 err = -ENODEV;
425 goto err_out_disable;
426 }
427
428 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
429
430 /* Set Latency Timer 80h */
431 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
432 Need a PCI quirk.. */
433
434 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
435 #endif
436
437 if (pci_request_regions(pdev, DRV_NAME)) {
438 pr_err("Failed to request PCI regions\n");
439 err = -ENODEV;
440 goto err_out_disable;
441 }
442
443 /* Init system & device */
444 db = netdev_priv(dev);
445
446 /* Allocate Tx/Rx descriptor memory */
447 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
448 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
449 if (!db->desc_pool_ptr)
450 goto err_out_res;
451
452 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
453 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
454 if (!db->buf_pool_ptr)
455 goto err_out_free_desc;
456
457 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
458 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
459 db->buf_pool_start = db->buf_pool_ptr;
460 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
461
462 db->chip_id = ent->driver_data;
463 /* IO type range. */
464 db->ioaddr = pci_iomap(pdev, 0, 0);
465 if (!db->ioaddr)
466 goto err_out_free_buf;
467
468 db->chip_revision = pdev->revision;
469 db->wol_mode = 0;
470
471 db->pdev = pdev;
472
473 pci_set_drvdata(pdev, dev);
474 dev->netdev_ops = &netdev_ops;
475 dev->ethtool_ops = &netdev_ethtool_ops;
476 netif_carrier_off(dev);
477 spin_lock_init(&db->lock);
478
479 pci_read_config_dword(pdev, 0x50, &pci_pmr);
480 pci_pmr &= 0x70000;
481 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
482 db->chip_type = 1; /* DM9102A E3 */
483 else
484 db->chip_type = 0;
485
486 /* read 64 word srom data */
487 for (i = 0; i < 64; i++) {
488 ((__le16 *) db->srom)[i] =
489 cpu_to_le16(read_srom_word(db->ioaddr, i));
490 }
491
492 /* Set Node address */
493 for (i = 0; i < 6; i++)
494 dev->dev_addr[i] = db->srom[20 + i];
495
496 err = register_netdev (dev);
497 if (err)
498 goto err_out_unmap;
499
500 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
501 ent->driver_data >> 16,
502 pci_name(pdev), dev->dev_addr, pdev->irq);
503
504 pci_set_master(pdev);
505
506 return 0;
507
508 err_out_unmap:
509 pci_iounmap(pdev, db->ioaddr);
510 err_out_free_buf:
511 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
512 db->buf_pool_ptr, db->buf_pool_dma_ptr);
513 err_out_free_desc:
514 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
515 db->desc_pool_ptr, db->desc_pool_dma_ptr);
516 err_out_res:
517 pci_release_regions(pdev);
518 err_out_disable:
519 pci_disable_device(pdev);
520 err_out_free:
521 pci_set_drvdata(pdev, NULL);
522 free_netdev(dev);
523
524 return err;
525 }
526
527
528 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
529 {
530 struct net_device *dev = pci_get_drvdata(pdev);
531 struct dmfe_board_info *db = netdev_priv(dev);
532
533 DMFE_DBUG(0, "dmfe_remove_one()", 0);
534
535 if (dev) {
536
537 unregister_netdev(dev);
538 pci_iounmap(db->pdev, db->ioaddr);
539 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
540 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
541 db->desc_pool_dma_ptr);
542 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
543 db->buf_pool_ptr, db->buf_pool_dma_ptr);
544 pci_release_regions(pdev);
545 free_netdev(dev); /* free board information */
546
547 pci_set_drvdata(pdev, NULL);
548 }
549
550 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
551 }
552
553
554 /*
555 * Open the interface.
556 * The interface is opened whenever "ifconfig" actives it.
557 */
558
559 static int dmfe_open(struct DEVICE *dev)
560 {
561 struct dmfe_board_info *db = netdev_priv(dev);
562 const int irq = db->pdev->irq;
563 int ret;
564
565 DMFE_DBUG(0, "dmfe_open", 0);
566
567 ret = request_irq(irq, dmfe_interrupt, IRQF_SHARED, dev->name, dev);
568 if (ret)
569 return ret;
570
571 /* system variable init */
572 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
573 db->tx_packet_cnt = 0;
574 db->tx_queue_cnt = 0;
575 db->rx_avail_cnt = 0;
576 db->wait_reset = 0;
577
578 db->first_in_callback = 0;
579 db->NIC_capability = 0xf; /* All capability*/
580 db->PHY_reg4 = 0x1e0;
581
582 /* CR6 operation mode decision */
583 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
584 (db->chip_revision >= 0x30) ) {
585 db->cr6_data |= DMFE_TXTH_256;
586 db->cr0_data = CR0_DEFAULT;
587 db->dm910x_chk_mode=4; /* Enter the normal mode */
588 } else {
589 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
590 db->cr0_data = 0;
591 db->dm910x_chk_mode = 1; /* Enter the check mode */
592 }
593
594 /* Initialize DM910X board */
595 dmfe_init_dm910x(dev);
596
597 /* Active System Interface */
598 netif_wake_queue(dev);
599
600 /* set and active a timer process */
601 init_timer(&db->timer);
602 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
603 db->timer.data = (unsigned long)dev;
604 db->timer.function = dmfe_timer;
605 add_timer(&db->timer);
606
607 return 0;
608 }
609
610
611 /* Initialize DM910X board
612 * Reset DM910X board
613 * Initialize TX/Rx descriptor chain structure
614 * Send the set-up frame
615 * Enable Tx/Rx machine
616 */
617
618 static void dmfe_init_dm910x(struct DEVICE *dev)
619 {
620 struct dmfe_board_info *db = netdev_priv(dev);
621 void __iomem *ioaddr = db->ioaddr;
622
623 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
624
625 /* Reset DM910x MAC controller */
626 dw32(DCR0, DM910X_RESET); /* RESET MAC */
627 udelay(100);
628 dw32(DCR0, db->cr0_data);
629 udelay(5);
630
631 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
632 db->phy_addr = 1;
633
634 /* Parser SROM and media mode */
635 dmfe_parse_srom(db);
636 db->media_mode = dmfe_media_mode;
637
638 /* RESET Phyxcer Chip by GPR port bit 7 */
639 dw32(DCR12, 0x180); /* Let bit 7 output port */
640 if (db->chip_id == PCI_DM9009_ID) {
641 dw32(DCR12, 0x80); /* Issue RESET signal */
642 mdelay(300); /* Delay 300 ms */
643 }
644 dw32(DCR12, 0x0); /* Clear RESET signal */
645
646 /* Process Phyxcer Media Mode */
647 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
648 dmfe_set_phyxcer(db);
649
650 /* Media Mode Process */
651 if ( !(db->media_mode & DMFE_AUTO) )
652 db->op_mode = db->media_mode; /* Force Mode */
653
654 /* Initialize Transmit/Receive decriptor and CR3/4 */
655 dmfe_descriptor_init(dev);
656
657 /* Init CR6 to program DM910x operation */
658 update_cr6(db->cr6_data, ioaddr);
659
660 /* Send setup frame */
661 if (db->chip_id == PCI_DM9132_ID)
662 dm9132_id_table(dev); /* DM9132 */
663 else
664 send_filter_frame(dev); /* DM9102/DM9102A */
665
666 /* Init CR7, interrupt active bit */
667 db->cr7_data = CR7_DEFAULT;
668 dw32(DCR7, db->cr7_data);
669
670 /* Init CR15, Tx jabber and Rx watchdog timer */
671 dw32(DCR15, db->cr15_data);
672
673 /* Enable DM910X Tx/Rx function */
674 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
675 update_cr6(db->cr6_data, ioaddr);
676 }
677
678
679 /*
680 * Hardware start transmission.
681 * Send a packet to media from the upper layer.
682 */
683
684 static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
685 struct DEVICE *dev)
686 {
687 struct dmfe_board_info *db = netdev_priv(dev);
688 void __iomem *ioaddr = db->ioaddr;
689 struct tx_desc *txptr;
690 unsigned long flags;
691
692 DMFE_DBUG(0, "dmfe_start_xmit", 0);
693
694 /* Too large packet check */
695 if (skb->len > MAX_PACKET_SIZE) {
696 pr_err("big packet = %d\n", (u16)skb->len);
697 dev_kfree_skb(skb);
698 return NETDEV_TX_OK;
699 }
700
701 /* Resource flag check */
702 netif_stop_queue(dev);
703
704 spin_lock_irqsave(&db->lock, flags);
705
706 /* No Tx resource check, it never happen nromally */
707 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
708 spin_unlock_irqrestore(&db->lock, flags);
709 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
710 return NETDEV_TX_BUSY;
711 }
712
713 /* Disable NIC interrupt */
714 dw32(DCR7, 0);
715
716 /* transmit this packet */
717 txptr = db->tx_insert_ptr;
718 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
719 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
720
721 /* Point to next transmit free descriptor */
722 db->tx_insert_ptr = txptr->next_tx_desc;
723
724 /* Transmit Packet Process */
725 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
726 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
727 db->tx_packet_cnt++; /* Ready to send */
728 dw32(DCR1, 0x1); /* Issue Tx polling */
729 dev->trans_start = jiffies; /* saved time stamp */
730 } else {
731 db->tx_queue_cnt++; /* queue TX packet */
732 dw32(DCR1, 0x1); /* Issue Tx polling */
733 }
734
735 /* Tx resource check */
736 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
737 netif_wake_queue(dev);
738
739 /* Restore CR7 to enable interrupt */
740 spin_unlock_irqrestore(&db->lock, flags);
741 dw32(DCR7, db->cr7_data);
742
743 /* free this SKB */
744 dev_kfree_skb(skb);
745
746 return NETDEV_TX_OK;
747 }
748
749
750 /*
751 * Stop the interface.
752 * The interface is stopped when it is brought.
753 */
754
755 static int dmfe_stop(struct DEVICE *dev)
756 {
757 struct dmfe_board_info *db = netdev_priv(dev);
758 void __iomem *ioaddr = db->ioaddr;
759
760 DMFE_DBUG(0, "dmfe_stop", 0);
761
762 /* disable system */
763 netif_stop_queue(dev);
764
765 /* deleted timer */
766 del_timer_sync(&db->timer);
767
768 /* Reset & stop DM910X board */
769 dw32(DCR0, DM910X_RESET);
770 udelay(100);
771 phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
772
773 /* free interrupt */
774 free_irq(db->pdev->irq, dev);
775
776 /* free allocated rx buffer */
777 dmfe_free_rxbuffer(db);
778
779 #if 0
780 /* show statistic counter */
781 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
782 db->tx_fifo_underrun, db->tx_excessive_collision,
783 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
784 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
785 db->reset_fatal, db->reset_TXtimeout);
786 #endif
787
788 return 0;
789 }
790
791
792 /*
793 * DM9102 insterrupt handler
794 * receive the packet to upper layer, free the transmitted packet
795 */
796
797 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
798 {
799 struct DEVICE *dev = dev_id;
800 struct dmfe_board_info *db = netdev_priv(dev);
801 void __iomem *ioaddr = db->ioaddr;
802 unsigned long flags;
803
804 DMFE_DBUG(0, "dmfe_interrupt()", 0);
805
806 spin_lock_irqsave(&db->lock, flags);
807
808 /* Got DM910X status */
809 db->cr5_data = dr32(DCR5);
810 dw32(DCR5, db->cr5_data);
811 if ( !(db->cr5_data & 0xc1) ) {
812 spin_unlock_irqrestore(&db->lock, flags);
813 return IRQ_HANDLED;
814 }
815
816 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
817 dw32(DCR7, 0);
818
819 /* Check system status */
820 if (db->cr5_data & 0x2000) {
821 /* system bus error happen */
822 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
823 db->reset_fatal++;
824 db->wait_reset = 1; /* Need to RESET */
825 spin_unlock_irqrestore(&db->lock, flags);
826 return IRQ_HANDLED;
827 }
828
829 /* Received the coming packet */
830 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
831 dmfe_rx_packet(dev, db);
832
833 /* reallocate rx descriptor buffer */
834 if (db->rx_avail_cnt<RX_DESC_CNT)
835 allocate_rx_buffer(dev);
836
837 /* Free the transmitted descriptor */
838 if ( db->cr5_data & 0x01)
839 dmfe_free_tx_pkt(dev, db);
840
841 /* Mode Check */
842 if (db->dm910x_chk_mode & 0x2) {
843 db->dm910x_chk_mode = 0x4;
844 db->cr6_data |= 0x100;
845 update_cr6(db->cr6_data, ioaddr);
846 }
847
848 /* Restore CR7 to enable interrupt mask */
849 dw32(DCR7, db->cr7_data);
850
851 spin_unlock_irqrestore(&db->lock, flags);
852 return IRQ_HANDLED;
853 }
854
855
856 #ifdef CONFIG_NET_POLL_CONTROLLER
857 /*
858 * Polling 'interrupt' - used by things like netconsole to send skbs
859 * without having to re-enable interrupts. It's not called while
860 * the interrupt routine is executing.
861 */
862
863 static void poll_dmfe (struct net_device *dev)
864 {
865 struct dmfe_board_info *db = netdev_priv(dev);
866 const int irq = db->pdev->irq;
867
868 /* disable_irq here is not very nice, but with the lockless
869 interrupt handler we have no other choice. */
870 disable_irq(irq);
871 dmfe_interrupt (irq, dev);
872 enable_irq(irq);
873 }
874 #endif
875
876 /*
877 * Free TX resource after TX complete
878 */
879
880 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
881 {
882 struct tx_desc *txptr;
883 void __iomem *ioaddr = db->ioaddr;
884 u32 tdes0;
885
886 txptr = db->tx_remove_ptr;
887 while(db->tx_packet_cnt) {
888 tdes0 = le32_to_cpu(txptr->tdes0);
889 if (tdes0 & 0x80000000)
890 break;
891
892 /* A packet sent completed */
893 db->tx_packet_cnt--;
894 dev->stats.tx_packets++;
895
896 /* Transmit statistic counter */
897 if ( tdes0 != 0x7fffffff ) {
898 dev->stats.collisions += (tdes0 >> 3) & 0xf;
899 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
900 if (tdes0 & TDES0_ERR_MASK) {
901 dev->stats.tx_errors++;
902
903 if (tdes0 & 0x0002) { /* UnderRun */
904 db->tx_fifo_underrun++;
905 if ( !(db->cr6_data & CR6_SFT) ) {
906 db->cr6_data = db->cr6_data | CR6_SFT;
907 update_cr6(db->cr6_data, ioaddr);
908 }
909 }
910 if (tdes0 & 0x0100)
911 db->tx_excessive_collision++;
912 if (tdes0 & 0x0200)
913 db->tx_late_collision++;
914 if (tdes0 & 0x0400)
915 db->tx_no_carrier++;
916 if (tdes0 & 0x0800)
917 db->tx_loss_carrier++;
918 if (tdes0 & 0x4000)
919 db->tx_jabber_timeout++;
920 }
921 }
922
923 txptr = txptr->next_tx_desc;
924 }/* End of while */
925
926 /* Update TX remove pointer to next */
927 db->tx_remove_ptr = txptr;
928
929 /* Send the Tx packet in queue */
930 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
931 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
932 db->tx_packet_cnt++; /* Ready to send */
933 db->tx_queue_cnt--;
934 dw32(DCR1, 0x1); /* Issue Tx polling */
935 dev->trans_start = jiffies; /* saved time stamp */
936 }
937
938 /* Resource available check */
939 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
940 netif_wake_queue(dev); /* Active upper layer, send again */
941 }
942
943
944 /*
945 * Calculate the CRC valude of the Rx packet
946 * flag = 1 : return the reverse CRC (for the received packet CRC)
947 * 0 : return the normal CRC (for Hash Table index)
948 */
949
950 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
951 {
952 u32 crc = crc32(~0, Data, Len);
953 if (flag) crc = ~crc;
954 return crc;
955 }
956
957
958 /*
959 * Receive the come packet and pass to upper layer
960 */
961
962 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
963 {
964 struct rx_desc *rxptr;
965 struct sk_buff *skb, *newskb;
966 int rxlen;
967 u32 rdes0;
968
969 rxptr = db->rx_ready_ptr;
970
971 while(db->rx_avail_cnt) {
972 rdes0 = le32_to_cpu(rxptr->rdes0);
973 if (rdes0 & 0x80000000) /* packet owner check */
974 break;
975
976 db->rx_avail_cnt--;
977 db->interval_rx_cnt++;
978
979 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
980 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
981
982 if ( (rdes0 & 0x300) != 0x300) {
983 /* A packet without First/Last flag */
984 /* reuse this SKB */
985 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
986 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
987 } else {
988 /* A packet with First/Last flag */
989 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
990
991 /* error summary bit check */
992 if (rdes0 & 0x8000) {
993 /* This is a error packet */
994 dev->stats.rx_errors++;
995 if (rdes0 & 1)
996 dev->stats.rx_fifo_errors++;
997 if (rdes0 & 2)
998 dev->stats.rx_crc_errors++;
999 if (rdes0 & 0x80)
1000 dev->stats.rx_length_errors++;
1001 }
1002
1003 if ( !(rdes0 & 0x8000) ||
1004 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1005 skb = rxptr->rx_skb_ptr;
1006
1007 /* Received Packet CRC check need or not */
1008 if ( (db->dm910x_chk_mode & 1) &&
1009 (cal_CRC(skb->data, rxlen, 1) !=
1010 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1011 /* Found a error received packet */
1012 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1013 db->dm910x_chk_mode = 3;
1014 } else {
1015 /* Good packet, send to upper layer */
1016 /* Shorst packet used new SKB */
1017 if ((rxlen < RX_COPY_SIZE) &&
1018 ((newskb = netdev_alloc_skb(dev, rxlen + 2))
1019 != NULL)) {
1020
1021 skb = newskb;
1022 /* size less than COPY_SIZE, allocate a rxlen SKB */
1023 skb_reserve(skb, 2); /* 16byte align */
1024 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1025 skb_put(skb, rxlen),
1026 rxlen);
1027 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1028 } else
1029 skb_put(skb, rxlen);
1030
1031 skb->protocol = eth_type_trans(skb, dev);
1032 netif_rx(skb);
1033 dev->stats.rx_packets++;
1034 dev->stats.rx_bytes += rxlen;
1035 }
1036 } else {
1037 /* Reuse SKB buffer when the packet is error */
1038 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1039 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1040 }
1041 }
1042
1043 rxptr = rxptr->next_rx_desc;
1044 }
1045
1046 db->rx_ready_ptr = rxptr;
1047 }
1048
1049 /*
1050 * Set DM910X multicast address
1051 */
1052
1053 static void dmfe_set_filter_mode(struct DEVICE * dev)
1054 {
1055 struct dmfe_board_info *db = netdev_priv(dev);
1056 unsigned long flags;
1057 int mc_count = netdev_mc_count(dev);
1058
1059 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1060 spin_lock_irqsave(&db->lock, flags);
1061
1062 if (dev->flags & IFF_PROMISC) {
1063 DMFE_DBUG(0, "Enable PROM Mode", 0);
1064 db->cr6_data |= CR6_PM | CR6_PBF;
1065 update_cr6(db->cr6_data, db->ioaddr);
1066 spin_unlock_irqrestore(&db->lock, flags);
1067 return;
1068 }
1069
1070 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1071 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1072 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1073 db->cr6_data |= CR6_PAM;
1074 spin_unlock_irqrestore(&db->lock, flags);
1075 return;
1076 }
1077
1078 DMFE_DBUG(0, "Set multicast address", mc_count);
1079 if (db->chip_id == PCI_DM9132_ID)
1080 dm9132_id_table(dev); /* DM9132 */
1081 else
1082 send_filter_frame(dev); /* DM9102/DM9102A */
1083 spin_unlock_irqrestore(&db->lock, flags);
1084 }
1085
1086 /*
1087 * Ethtool interace
1088 */
1089
1090 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1091 struct ethtool_drvinfo *info)
1092 {
1093 struct dmfe_board_info *np = netdev_priv(dev);
1094
1095 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1096 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1097 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1098 }
1099
1100 static int dmfe_ethtool_set_wol(struct net_device *dev,
1101 struct ethtool_wolinfo *wolinfo)
1102 {
1103 struct dmfe_board_info *db = netdev_priv(dev);
1104
1105 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1106 WAKE_ARP | WAKE_MAGICSECURE))
1107 return -EOPNOTSUPP;
1108
1109 db->wol_mode = wolinfo->wolopts;
1110 return 0;
1111 }
1112
1113 static void dmfe_ethtool_get_wol(struct net_device *dev,
1114 struct ethtool_wolinfo *wolinfo)
1115 {
1116 struct dmfe_board_info *db = netdev_priv(dev);
1117
1118 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1119 wolinfo->wolopts = db->wol_mode;
1120 }
1121
1122
1123 static const struct ethtool_ops netdev_ethtool_ops = {
1124 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1125 .get_link = ethtool_op_get_link,
1126 .set_wol = dmfe_ethtool_set_wol,
1127 .get_wol = dmfe_ethtool_get_wol,
1128 };
1129
1130 /*
1131 * A periodic timer routine
1132 * Dynamic media sense, allocate Rx buffer...
1133 */
1134
1135 static void dmfe_timer(unsigned long data)
1136 {
1137 struct net_device *dev = (struct net_device *)data;
1138 struct dmfe_board_info *db = netdev_priv(dev);
1139 void __iomem *ioaddr = db->ioaddr;
1140 u32 tmp_cr8;
1141 unsigned char tmp_cr12;
1142 unsigned long flags;
1143
1144 int link_ok, link_ok_phy;
1145
1146 DMFE_DBUG(0, "dmfe_timer()", 0);
1147 spin_lock_irqsave(&db->lock, flags);
1148
1149 /* Media mode process when Link OK before enter this route */
1150 if (db->first_in_callback == 0) {
1151 db->first_in_callback = 1;
1152 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1153 db->cr6_data &= ~0x40000;
1154 update_cr6(db->cr6_data, ioaddr);
1155 phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1156 db->cr6_data |= 0x40000;
1157 update_cr6(db->cr6_data, ioaddr);
1158 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1159 add_timer(&db->timer);
1160 spin_unlock_irqrestore(&db->lock, flags);
1161 return;
1162 }
1163 }
1164
1165
1166 /* Operating Mode Check */
1167 if ( (db->dm910x_chk_mode & 0x1) &&
1168 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1169 db->dm910x_chk_mode = 0x4;
1170
1171 /* Dynamic reset DM910X : system error or transmit time-out */
1172 tmp_cr8 = dr32(DCR8);
1173 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1174 db->reset_cr8++;
1175 db->wait_reset = 1;
1176 }
1177 db->interval_rx_cnt = 0;
1178
1179 /* TX polling kick monitor */
1180 if ( db->tx_packet_cnt &&
1181 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1182 dw32(DCR1, 0x1); /* Tx polling again */
1183
1184 /* TX Timeout */
1185 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1186 db->reset_TXtimeout++;
1187 db->wait_reset = 1;
1188 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1189 }
1190 }
1191
1192 if (db->wait_reset) {
1193 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1194 db->reset_count++;
1195 dmfe_dynamic_reset(dev);
1196 db->first_in_callback = 0;
1197 db->timer.expires = DMFE_TIMER_WUT;
1198 add_timer(&db->timer);
1199 spin_unlock_irqrestore(&db->lock, flags);
1200 return;
1201 }
1202
1203 /* Link status check, Dynamic media type change */
1204 if (db->chip_id == PCI_DM9132_ID)
1205 tmp_cr12 = dr8(DCR9 + 3); /* DM9132 */
1206 else
1207 tmp_cr12 = dr8(DCR12); /* DM9102/DM9102A */
1208
1209 if ( ((db->chip_id == PCI_DM9102_ID) &&
1210 (db->chip_revision == 0x30)) ||
1211 ((db->chip_id == PCI_DM9132_ID) &&
1212 (db->chip_revision == 0x10)) ) {
1213 /* DM9102A Chip */
1214 if (tmp_cr12 & 2)
1215 link_ok = 0;
1216 else
1217 link_ok = 1;
1218 }
1219 else
1220 /*0x43 is used instead of 0x3 because bit 6 should represent
1221 link status of external PHY */
1222 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1223
1224
1225 /* If chip reports that link is failed it could be because external
1226 PHY link status pin is not connected correctly to chip
1227 To be sure ask PHY too.
1228 */
1229
1230 /* need a dummy read because of PHY's register latch*/
1231 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1232 link_ok_phy = (phy_read (db->ioaddr,
1233 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1234
1235 if (link_ok_phy != link_ok) {
1236 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1237 link_ok = link_ok | link_ok_phy;
1238 }
1239
1240 if ( !link_ok && netif_carrier_ok(dev)) {
1241 /* Link Failed */
1242 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1243 netif_carrier_off(dev);
1244
1245 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1246 /* AUTO or force 1M Homerun/Longrun don't need */
1247 if ( !(db->media_mode & 0x38) )
1248 phy_write(db->ioaddr, db->phy_addr,
1249 0, 0x1000, db->chip_id);
1250
1251 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1252 if (db->media_mode & DMFE_AUTO) {
1253 /* 10/100M link failed, used 1M Home-Net */
1254 db->cr6_data|=0x00040000; /* bit18=1, MII */
1255 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1256 update_cr6(db->cr6_data, ioaddr);
1257 }
1258 } else if (!netif_carrier_ok(dev)) {
1259
1260 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1261
1262 /* Auto Sense Speed */
1263 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1264 netif_carrier_on(dev);
1265 SHOW_MEDIA_TYPE(db->op_mode);
1266 }
1267
1268 dmfe_process_mode(db);
1269 }
1270
1271 /* HPNA remote command check */
1272 if (db->HPNA_command & 0xf00) {
1273 db->HPNA_timer--;
1274 if (!db->HPNA_timer)
1275 dmfe_HPNA_remote_cmd_chk(db);
1276 }
1277
1278 /* Timer active again */
1279 db->timer.expires = DMFE_TIMER_WUT;
1280 add_timer(&db->timer);
1281 spin_unlock_irqrestore(&db->lock, flags);
1282 }
1283
1284
1285 /*
1286 * Dynamic reset the DM910X board
1287 * Stop DM910X board
1288 * Free Tx/Rx allocated memory
1289 * Reset DM910X board
1290 * Re-initialize DM910X board
1291 */
1292
1293 static void dmfe_dynamic_reset(struct net_device *dev)
1294 {
1295 struct dmfe_board_info *db = netdev_priv(dev);
1296 void __iomem *ioaddr = db->ioaddr;
1297
1298 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1299
1300 /* Sopt MAC controller */
1301 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1302 update_cr6(db->cr6_data, ioaddr);
1303 dw32(DCR7, 0); /* Disable Interrupt */
1304 dw32(DCR5, dr32(DCR5));
1305
1306 /* Disable upper layer interface */
1307 netif_stop_queue(dev);
1308
1309 /* Free Rx Allocate buffer */
1310 dmfe_free_rxbuffer(db);
1311
1312 /* system variable init */
1313 db->tx_packet_cnt = 0;
1314 db->tx_queue_cnt = 0;
1315 db->rx_avail_cnt = 0;
1316 netif_carrier_off(dev);
1317 db->wait_reset = 0;
1318
1319 /* Re-initialize DM910X board */
1320 dmfe_init_dm910x(dev);
1321
1322 /* Restart upper layer interface */
1323 netif_wake_queue(dev);
1324 }
1325
1326
1327 /*
1328 * free all allocated rx buffer
1329 */
1330
1331 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1332 {
1333 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1334
1335 /* free allocated rx buffer */
1336 while (db->rx_avail_cnt) {
1337 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1338 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1339 db->rx_avail_cnt--;
1340 }
1341 }
1342
1343
1344 /*
1345 * Reuse the SK buffer
1346 */
1347
1348 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1349 {
1350 struct rx_desc *rxptr = db->rx_insert_ptr;
1351
1352 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1353 rxptr->rx_skb_ptr = skb;
1354 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1355 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1356 wmb();
1357 rxptr->rdes0 = cpu_to_le32(0x80000000);
1358 db->rx_avail_cnt++;
1359 db->rx_insert_ptr = rxptr->next_rx_desc;
1360 } else
1361 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1362 }
1363
1364
1365 /*
1366 * Initialize transmit/Receive descriptor
1367 * Using Chain structure, and allocate Tx/Rx buffer
1368 */
1369
1370 static void dmfe_descriptor_init(struct net_device *dev)
1371 {
1372 struct dmfe_board_info *db = netdev_priv(dev);
1373 void __iomem *ioaddr = db->ioaddr;
1374 struct tx_desc *tmp_tx;
1375 struct rx_desc *tmp_rx;
1376 unsigned char *tmp_buf;
1377 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1378 dma_addr_t tmp_buf_dma;
1379 int i;
1380
1381 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1382
1383 /* tx descriptor start pointer */
1384 db->tx_insert_ptr = db->first_tx_desc;
1385 db->tx_remove_ptr = db->first_tx_desc;
1386 dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
1387
1388 /* rx descriptor start pointer */
1389 db->first_rx_desc = (void *)db->first_tx_desc +
1390 sizeof(struct tx_desc) * TX_DESC_CNT;
1391
1392 db->first_rx_desc_dma = db->first_tx_desc_dma +
1393 sizeof(struct tx_desc) * TX_DESC_CNT;
1394 db->rx_insert_ptr = db->first_rx_desc;
1395 db->rx_ready_ptr = db->first_rx_desc;
1396 dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
1397
1398 /* Init Transmit chain */
1399 tmp_buf = db->buf_pool_start;
1400 tmp_buf_dma = db->buf_pool_dma_start;
1401 tmp_tx_dma = db->first_tx_desc_dma;
1402 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1403 tmp_tx->tx_buf_ptr = tmp_buf;
1404 tmp_tx->tdes0 = cpu_to_le32(0);
1405 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1406 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1407 tmp_tx_dma += sizeof(struct tx_desc);
1408 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1409 tmp_tx->next_tx_desc = tmp_tx + 1;
1410 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1411 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1412 }
1413 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1414 tmp_tx->next_tx_desc = db->first_tx_desc;
1415
1416 /* Init Receive descriptor chain */
1417 tmp_rx_dma=db->first_rx_desc_dma;
1418 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1419 tmp_rx->rdes0 = cpu_to_le32(0);
1420 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1421 tmp_rx_dma += sizeof(struct rx_desc);
1422 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1423 tmp_rx->next_rx_desc = tmp_rx + 1;
1424 }
1425 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1426 tmp_rx->next_rx_desc = db->first_rx_desc;
1427
1428 /* pre-allocate Rx buffer */
1429 allocate_rx_buffer(dev);
1430 }
1431
1432
1433 /*
1434 * Update CR6 value
1435 * Firstly stop DM910X , then written value and start
1436 */
1437
1438 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1439 {
1440 u32 cr6_tmp;
1441
1442 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1443 dw32(DCR6, cr6_tmp);
1444 udelay(5);
1445 dw32(DCR6, cr6_data);
1446 udelay(5);
1447 }
1448
1449
1450 /*
1451 * Send a setup frame for DM9132
1452 * This setup frame initialize DM910X address filter mode
1453 */
1454
1455 static void dm9132_id_table(struct net_device *dev)
1456 {
1457 struct dmfe_board_info *db = netdev_priv(dev);
1458 void __iomem *ioaddr = db->ioaddr + 0xc0;
1459 u16 *addrptr = (u16 *)dev->dev_addr;
1460 struct netdev_hw_addr *ha;
1461 u16 i, hash_table[4];
1462
1463 /* Node address */
1464 for (i = 0; i < 3; i++) {
1465 dw16(0, addrptr[i]);
1466 ioaddr += 4;
1467 }
1468
1469 /* Clear Hash Table */
1470 memset(hash_table, 0, sizeof(hash_table));
1471
1472 /* broadcast address */
1473 hash_table[3] = 0x8000;
1474
1475 /* the multicast address in Hash Table : 64 bits */
1476 netdev_for_each_mc_addr(ha, dev) {
1477 u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f;
1478
1479 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1480 }
1481
1482 /* Write the hash table to MAC MD table */
1483 for (i = 0; i < 4; i++, ioaddr += 4)
1484 dw16(0, hash_table[i]);
1485 }
1486
1487
1488 /*
1489 * Send a setup frame for DM9102/DM9102A
1490 * This setup frame initialize DM910X address filter mode
1491 */
1492
1493 static void send_filter_frame(struct net_device *dev)
1494 {
1495 struct dmfe_board_info *db = netdev_priv(dev);
1496 struct netdev_hw_addr *ha;
1497 struct tx_desc *txptr;
1498 u16 * addrptr;
1499 u32 * suptr;
1500 int i;
1501
1502 DMFE_DBUG(0, "send_filter_frame()", 0);
1503
1504 txptr = db->tx_insert_ptr;
1505 suptr = (u32 *) txptr->tx_buf_ptr;
1506
1507 /* Node address */
1508 addrptr = (u16 *) dev->dev_addr;
1509 *suptr++ = addrptr[0];
1510 *suptr++ = addrptr[1];
1511 *suptr++ = addrptr[2];
1512
1513 /* broadcast address */
1514 *suptr++ = 0xffff;
1515 *suptr++ = 0xffff;
1516 *suptr++ = 0xffff;
1517
1518 /* fit the multicast address */
1519 netdev_for_each_mc_addr(ha, dev) {
1520 addrptr = (u16 *) ha->addr;
1521 *suptr++ = addrptr[0];
1522 *suptr++ = addrptr[1];
1523 *suptr++ = addrptr[2];
1524 }
1525
1526 for (i = netdev_mc_count(dev); i < 14; i++) {
1527 *suptr++ = 0xffff;
1528 *suptr++ = 0xffff;
1529 *suptr++ = 0xffff;
1530 }
1531
1532 /* prepare the setup frame */
1533 db->tx_insert_ptr = txptr->next_tx_desc;
1534 txptr->tdes1 = cpu_to_le32(0x890000c0);
1535
1536 /* Resource Check and Send the setup packet */
1537 if (!db->tx_packet_cnt) {
1538 void __iomem *ioaddr = db->ioaddr;
1539
1540 /* Resource Empty */
1541 db->tx_packet_cnt++;
1542 txptr->tdes0 = cpu_to_le32(0x80000000);
1543 update_cr6(db->cr6_data | 0x2000, ioaddr);
1544 dw32(DCR1, 0x1); /* Issue Tx polling */
1545 update_cr6(db->cr6_data, ioaddr);
1546 dev->trans_start = jiffies;
1547 } else
1548 db->tx_queue_cnt++; /* Put in TX queue */
1549 }
1550
1551
1552 /*
1553 * Allocate rx buffer,
1554 * As possible as allocate maxiumn Rx buffer
1555 */
1556
1557 static void allocate_rx_buffer(struct net_device *dev)
1558 {
1559 struct dmfe_board_info *db = netdev_priv(dev);
1560 struct rx_desc *rxptr;
1561 struct sk_buff *skb;
1562
1563 rxptr = db->rx_insert_ptr;
1564
1565 while(db->rx_avail_cnt < RX_DESC_CNT) {
1566 if ( ( skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE) ) == NULL )
1567 break;
1568 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1569 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1570 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1571 wmb();
1572 rxptr->rdes0 = cpu_to_le32(0x80000000);
1573 rxptr = rxptr->next_rx_desc;
1574 db->rx_avail_cnt++;
1575 }
1576
1577 db->rx_insert_ptr = rxptr;
1578 }
1579
1580 static void srom_clk_write(void __iomem *ioaddr, u32 data)
1581 {
1582 static const u32 cmd[] = {
1583 CR9_SROM_READ | CR9_SRCS,
1584 CR9_SROM_READ | CR9_SRCS | CR9_SRCLK,
1585 CR9_SROM_READ | CR9_SRCS
1586 };
1587 int i;
1588
1589 for (i = 0; i < ARRAY_SIZE(cmd); i++) {
1590 dw32(DCR9, data | cmd[i]);
1591 udelay(5);
1592 }
1593 }
1594
1595 /*
1596 * Read one word data from the serial ROM
1597 */
1598 static u16 read_srom_word(void __iomem *ioaddr, int offset)
1599 {
1600 u16 srom_data;
1601 int i;
1602
1603 dw32(DCR9, CR9_SROM_READ);
1604 udelay(5);
1605 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1606 udelay(5);
1607
1608 /* Send the Read Command 110b */
1609 srom_clk_write(ioaddr, SROM_DATA_1);
1610 srom_clk_write(ioaddr, SROM_DATA_1);
1611 srom_clk_write(ioaddr, SROM_DATA_0);
1612
1613 /* Send the offset */
1614 for (i = 5; i >= 0; i--) {
1615 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1616 srom_clk_write(ioaddr, srom_data);
1617 }
1618
1619 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1620 udelay(5);
1621
1622 for (i = 16; i > 0; i--) {
1623 dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1624 udelay(5);
1625 srom_data = (srom_data << 1) |
1626 ((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1627 dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1628 udelay(5);
1629 }
1630
1631 dw32(DCR9, CR9_SROM_READ);
1632 udelay(5);
1633 return srom_data;
1634 }
1635
1636
1637 /*
1638 * Auto sense the media mode
1639 */
1640
1641 static u8 dmfe_sense_speed(struct dmfe_board_info *db)
1642 {
1643 void __iomem *ioaddr = db->ioaddr;
1644 u8 ErrFlag = 0;
1645 u16 phy_mode;
1646
1647 /* CR6 bit18=0, select 10/100M */
1648 update_cr6(db->cr6_data & ~0x40000, ioaddr);
1649
1650 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1651 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1652
1653 if ( (phy_mode & 0x24) == 0x24 ) {
1654 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1655 phy_mode = phy_read(db->ioaddr,
1656 db->phy_addr, 7, db->chip_id) & 0xf000;
1657 else /* DM9102/DM9102A */
1658 phy_mode = phy_read(db->ioaddr,
1659 db->phy_addr, 17, db->chip_id) & 0xf000;
1660 switch (phy_mode) {
1661 case 0x1000: db->op_mode = DMFE_10MHF; break;
1662 case 0x2000: db->op_mode = DMFE_10MFD; break;
1663 case 0x4000: db->op_mode = DMFE_100MHF; break;
1664 case 0x8000: db->op_mode = DMFE_100MFD; break;
1665 default: db->op_mode = DMFE_10MHF;
1666 ErrFlag = 1;
1667 break;
1668 }
1669 } else {
1670 db->op_mode = DMFE_10MHF;
1671 DMFE_DBUG(0, "Link Failed :", phy_mode);
1672 ErrFlag = 1;
1673 }
1674
1675 return ErrFlag;
1676 }
1677
1678
1679 /*
1680 * Set 10/100 phyxcer capability
1681 * AUTO mode : phyxcer register4 is NIC capability
1682 * Force mode: phyxcer register4 is the force media
1683 */
1684
1685 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1686 {
1687 void __iomem *ioaddr = db->ioaddr;
1688 u16 phy_reg;
1689
1690 /* Select 10/100M phyxcer */
1691 db->cr6_data &= ~0x40000;
1692 update_cr6(db->cr6_data, ioaddr);
1693
1694 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1695 if (db->chip_id == PCI_DM9009_ID) {
1696 phy_reg = phy_read(db->ioaddr,
1697 db->phy_addr, 18, db->chip_id) & ~0x1000;
1698
1699 phy_write(db->ioaddr,
1700 db->phy_addr, 18, phy_reg, db->chip_id);
1701 }
1702
1703 /* Phyxcer capability setting */
1704 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1705
1706 if (db->media_mode & DMFE_AUTO) {
1707 /* AUTO Mode */
1708 phy_reg |= db->PHY_reg4;
1709 } else {
1710 /* Force Mode */
1711 switch(db->media_mode) {
1712 case DMFE_10MHF: phy_reg |= 0x20; break;
1713 case DMFE_10MFD: phy_reg |= 0x40; break;
1714 case DMFE_100MHF: phy_reg |= 0x80; break;
1715 case DMFE_100MFD: phy_reg |= 0x100; break;
1716 }
1717 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1718 }
1719
1720 /* Write new capability to Phyxcer Reg4 */
1721 if ( !(phy_reg & 0x01e0)) {
1722 phy_reg|=db->PHY_reg4;
1723 db->media_mode|=DMFE_AUTO;
1724 }
1725 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1726
1727 /* Restart Auto-Negotiation */
1728 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1729 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1730 if ( !db->chip_type )
1731 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1732 }
1733
1734
1735 /*
1736 * Process op-mode
1737 * AUTO mode : PHY controller in Auto-negotiation Mode
1738 * Force mode: PHY controller in force mode with HUB
1739 * N-way force capability with SWITCH
1740 */
1741
1742 static void dmfe_process_mode(struct dmfe_board_info *db)
1743 {
1744 u16 phy_reg;
1745
1746 /* Full Duplex Mode Check */
1747 if (db->op_mode & 0x4)
1748 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1749 else
1750 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1751
1752 /* Transciver Selection */
1753 if (db->op_mode & 0x10) /* 1M HomePNA */
1754 db->cr6_data |= 0x40000;/* External MII select */
1755 else
1756 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1757
1758 update_cr6(db->cr6_data, db->ioaddr);
1759
1760 /* 10/100M phyxcer force mode need */
1761 if ( !(db->media_mode & 0x18)) {
1762 /* Forece Mode */
1763 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1764 if ( !(phy_reg & 0x1) ) {
1765 /* parter without N-Way capability */
1766 phy_reg = 0x0;
1767 switch(db->op_mode) {
1768 case DMFE_10MHF: phy_reg = 0x0; break;
1769 case DMFE_10MFD: phy_reg = 0x100; break;
1770 case DMFE_100MHF: phy_reg = 0x2000; break;
1771 case DMFE_100MFD: phy_reg = 0x2100; break;
1772 }
1773 phy_write(db->ioaddr,
1774 db->phy_addr, 0, phy_reg, db->chip_id);
1775 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1776 mdelay(20);
1777 phy_write(db->ioaddr,
1778 db->phy_addr, 0, phy_reg, db->chip_id);
1779 }
1780 }
1781 }
1782
1783
1784 /*
1785 * Write a word to Phy register
1786 */
1787
1788 static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
1789 u16 phy_data, u32 chip_id)
1790 {
1791 u16 i;
1792
1793 if (chip_id == PCI_DM9132_ID) {
1794 dw16(0x80 + offset * 4, phy_data);
1795 } else {
1796 /* DM9102/DM9102A Chip */
1797
1798 /* Send 33 synchronization clock to Phy controller */
1799 for (i = 0; i < 35; i++)
1800 phy_write_1bit(ioaddr, PHY_DATA_1);
1801
1802 /* Send start command(01) to Phy */
1803 phy_write_1bit(ioaddr, PHY_DATA_0);
1804 phy_write_1bit(ioaddr, PHY_DATA_1);
1805
1806 /* Send write command(01) to Phy */
1807 phy_write_1bit(ioaddr, PHY_DATA_0);
1808 phy_write_1bit(ioaddr, PHY_DATA_1);
1809
1810 /* Send Phy address */
1811 for (i = 0x10; i > 0; i = i >> 1)
1812 phy_write_1bit(ioaddr,
1813 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1814
1815 /* Send register address */
1816 for (i = 0x10; i > 0; i = i >> 1)
1817 phy_write_1bit(ioaddr,
1818 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1819
1820 /* written trasnition */
1821 phy_write_1bit(ioaddr, PHY_DATA_1);
1822 phy_write_1bit(ioaddr, PHY_DATA_0);
1823
1824 /* Write a word data to PHY controller */
1825 for ( i = 0x8000; i > 0; i >>= 1)
1826 phy_write_1bit(ioaddr,
1827 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1828 }
1829 }
1830
1831
1832 /*
1833 * Read a word data from phy register
1834 */
1835
1836 static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
1837 {
1838 int i;
1839 u16 phy_data;
1840
1841 if (chip_id == PCI_DM9132_ID) {
1842 /* DM9132 Chip */
1843 phy_data = dr16(0x80 + offset * 4);
1844 } else {
1845 /* DM9102/DM9102A Chip */
1846
1847 /* Send 33 synchronization clock to Phy controller */
1848 for (i = 0; i < 35; i++)
1849 phy_write_1bit(ioaddr, PHY_DATA_1);
1850
1851 /* Send start command(01) to Phy */
1852 phy_write_1bit(ioaddr, PHY_DATA_0);
1853 phy_write_1bit(ioaddr, PHY_DATA_1);
1854
1855 /* Send read command(10) to Phy */
1856 phy_write_1bit(ioaddr, PHY_DATA_1);
1857 phy_write_1bit(ioaddr, PHY_DATA_0);
1858
1859 /* Send Phy address */
1860 for (i = 0x10; i > 0; i = i >> 1)
1861 phy_write_1bit(ioaddr,
1862 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1863
1864 /* Send register address */
1865 for (i = 0x10; i > 0; i = i >> 1)
1866 phy_write_1bit(ioaddr,
1867 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1868
1869 /* Skip transition state */
1870 phy_read_1bit(ioaddr);
1871
1872 /* read 16bit data */
1873 for (phy_data = 0, i = 0; i < 16; i++) {
1874 phy_data <<= 1;
1875 phy_data |= phy_read_1bit(ioaddr);
1876 }
1877 }
1878
1879 return phy_data;
1880 }
1881
1882
1883 /*
1884 * Write one bit data to Phy Controller
1885 */
1886
1887 static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
1888 {
1889 dw32(DCR9, phy_data); /* MII Clock Low */
1890 udelay(1);
1891 dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
1892 udelay(1);
1893 dw32(DCR9, phy_data); /* MII Clock Low */
1894 udelay(1);
1895 }
1896
1897
1898 /*
1899 * Read one bit phy data from PHY controller
1900 */
1901
1902 static u16 phy_read_1bit(void __iomem *ioaddr)
1903 {
1904 u16 phy_data;
1905
1906 dw32(DCR9, 0x50000);
1907 udelay(1);
1908 phy_data = (dr32(DCR9) >> 19) & 0x1;
1909 dw32(DCR9, 0x40000);
1910 udelay(1);
1911
1912 return phy_data;
1913 }
1914
1915
1916 /*
1917 * Parser SROM and media mode
1918 */
1919
1920 static void dmfe_parse_srom(struct dmfe_board_info * db)
1921 {
1922 char * srom = db->srom;
1923 int dmfe_mode, tmp_reg;
1924
1925 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1926
1927 /* Init CR15 */
1928 db->cr15_data = CR15_DEFAULT;
1929
1930 /* Check SROM Version */
1931 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1932 /* SROM V4.01 */
1933 /* Get NIC support media mode */
1934 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1935 db->PHY_reg4 = 0;
1936 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1937 switch( db->NIC_capability & tmp_reg ) {
1938 case 0x1: db->PHY_reg4 |= 0x0020; break;
1939 case 0x2: db->PHY_reg4 |= 0x0040; break;
1940 case 0x4: db->PHY_reg4 |= 0x0080; break;
1941 case 0x8: db->PHY_reg4 |= 0x0100; break;
1942 }
1943 }
1944
1945 /* Media Mode Force or not check */
1946 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1947 le32_to_cpup((__le32 *) (srom + 36)));
1948 switch(dmfe_mode) {
1949 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1950 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1951 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1952 case 0x100:
1953 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1954 }
1955
1956 /* Special Function setting */
1957 /* VLAN function */
1958 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1959 db->cr15_data |= 0x40;
1960
1961 /* Flow Control */
1962 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1963 db->cr15_data |= 0x400;
1964
1965 /* TX pause packet */
1966 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1967 db->cr15_data |= 0x9800;
1968 }
1969
1970 /* Parse HPNA parameter */
1971 db->HPNA_command = 1;
1972
1973 /* Accept remote command or not */
1974 if (HPNA_rx_cmd == 0)
1975 db->HPNA_command |= 0x8000;
1976
1977 /* Issue remote command & operation mode */
1978 if (HPNA_tx_cmd == 1)
1979 switch(HPNA_mode) { /* Issue Remote Command */
1980 case 0: db->HPNA_command |= 0x0904; break;
1981 case 1: db->HPNA_command |= 0x0a00; break;
1982 case 2: db->HPNA_command |= 0x0506; break;
1983 case 3: db->HPNA_command |= 0x0602; break;
1984 }
1985 else
1986 switch(HPNA_mode) { /* Don't Issue */
1987 case 0: db->HPNA_command |= 0x0004; break;
1988 case 1: db->HPNA_command |= 0x0000; break;
1989 case 2: db->HPNA_command |= 0x0006; break;
1990 case 3: db->HPNA_command |= 0x0002; break;
1991 }
1992
1993 /* Check DM9801 or DM9802 present or not */
1994 db->HPNA_present = 0;
1995 update_cr6(db->cr6_data | 0x40000, db->ioaddr);
1996 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1997 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1998 /* DM9801 or DM9802 present */
1999 db->HPNA_timer = 8;
2000 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
2001 /* DM9801 HomeRun */
2002 db->HPNA_present = 1;
2003 dmfe_program_DM9801(db, tmp_reg);
2004 } else {
2005 /* DM9802 LongRun */
2006 db->HPNA_present = 2;
2007 dmfe_program_DM9802(db);
2008 }
2009 }
2010
2011 }
2012
2013
2014 /*
2015 * Init HomeRun DM9801
2016 */
2017
2018 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2019 {
2020 uint reg17, reg25;
2021
2022 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2023 switch(HPNA_rev) {
2024 case 0xb900: /* DM9801 E3 */
2025 db->HPNA_command |= 0x1000;
2026 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2027 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2028 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2029 break;
2030 case 0xb901: /* DM9801 E4 */
2031 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2032 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2033 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2034 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2035 break;
2036 case 0xb902: /* DM9801 E5 */
2037 case 0xb903: /* DM9801 E6 */
2038 default:
2039 db->HPNA_command |= 0x1000;
2040 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2041 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2042 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2043 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2044 break;
2045 }
2046 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2047 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2048 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2049 }
2050
2051
2052 /*
2053 * Init HomeRun DM9802
2054 */
2055
2056 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2057 {
2058 uint phy_reg;
2059
2060 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2061 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2062 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2063 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2064 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2065 }
2066
2067
2068 /*
2069 * Check remote HPNA power and speed status. If not correct,
2070 * issue command again.
2071 */
2072
2073 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2074 {
2075 uint phy_reg;
2076
2077 /* Got remote device status */
2078 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2079 switch(phy_reg) {
2080 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2081 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2082 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2083 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2084 }
2085
2086 /* Check remote device status match our setting ot not */
2087 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2088 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2089 db->chip_id);
2090 db->HPNA_timer=8;
2091 } else
2092 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2093 }
2094
2095
2096
2097 static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
2098 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2099 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2100 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2101 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2102 { 0, }
2103 };
2104 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2105
2106
2107 #ifdef CONFIG_PM
2108 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2109 {
2110 struct net_device *dev = pci_get_drvdata(pci_dev);
2111 struct dmfe_board_info *db = netdev_priv(dev);
2112 void __iomem *ioaddr = db->ioaddr;
2113 u32 tmp;
2114
2115 /* Disable upper layer interface */
2116 netif_device_detach(dev);
2117
2118 /* Disable Tx/Rx */
2119 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2120 update_cr6(db->cr6_data, ioaddr);
2121
2122 /* Disable Interrupt */
2123 dw32(DCR7, 0);
2124 dw32(DCR5, dr32(DCR5));
2125
2126 /* Fre RX buffers */
2127 dmfe_free_rxbuffer(db);
2128
2129 /* Enable WOL */
2130 pci_read_config_dword(pci_dev, 0x40, &tmp);
2131 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2132
2133 if (db->wol_mode & WAKE_PHY)
2134 tmp |= DMFE_WOL_LINKCHANGE;
2135 if (db->wol_mode & WAKE_MAGIC)
2136 tmp |= DMFE_WOL_MAGICPACKET;
2137
2138 pci_write_config_dword(pci_dev, 0x40, tmp);
2139
2140 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2141 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2142
2143 /* Power down device*/
2144 pci_save_state(pci_dev);
2145 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2146
2147 return 0;
2148 }
2149
2150 static int dmfe_resume(struct pci_dev *pci_dev)
2151 {
2152 struct net_device *dev = pci_get_drvdata(pci_dev);
2153 u32 tmp;
2154
2155 pci_set_power_state(pci_dev, PCI_D0);
2156 pci_restore_state(pci_dev);
2157
2158 /* Re-initialize DM910X board */
2159 dmfe_init_dm910x(dev);
2160
2161 /* Disable WOL */
2162 pci_read_config_dword(pci_dev, 0x40, &tmp);
2163
2164 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2165 pci_write_config_dword(pci_dev, 0x40, tmp);
2166
2167 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2168 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2169
2170 /* Restart upper layer interface */
2171 netif_device_attach(dev);
2172
2173 return 0;
2174 }
2175 #else
2176 #define dmfe_suspend NULL
2177 #define dmfe_resume NULL
2178 #endif
2179
2180 static struct pci_driver dmfe_driver = {
2181 .name = "dmfe",
2182 .id_table = dmfe_pci_tbl,
2183 .probe = dmfe_init_one,
2184 .remove = __devexit_p(dmfe_remove_one),
2185 .suspend = dmfe_suspend,
2186 .resume = dmfe_resume
2187 };
2188
2189 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2190 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2191 MODULE_LICENSE("GPL");
2192 MODULE_VERSION(DRV_VERSION);
2193
2194 module_param(debug, int, 0);
2195 module_param(mode, byte, 0);
2196 module_param(cr6set, int, 0);
2197 module_param(chkmode, byte, 0);
2198 module_param(HPNA_mode, byte, 0);
2199 module_param(HPNA_rx_cmd, byte, 0);
2200 module_param(HPNA_tx_cmd, byte, 0);
2201 module_param(HPNA_NoiseFloor, byte, 0);
2202 module_param(SF_mode, byte, 0);
2203 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2204 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2205 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2206
2207 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2208 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2209
2210 /* Description:
2211 * when user used insmod to add module, system invoked init_module()
2212 * to initialize and register.
2213 */
2214
2215 static int __init dmfe_init_module(void)
2216 {
2217 int rc;
2218
2219 pr_info("%s\n", version);
2220 printed_version = 1;
2221
2222 DMFE_DBUG(0, "init_module() ", debug);
2223
2224 if (debug)
2225 dmfe_debug = debug; /* set debug flag */
2226 if (cr6set)
2227 dmfe_cr6_user_set = cr6set;
2228
2229 switch(mode) {
2230 case DMFE_10MHF:
2231 case DMFE_100MHF:
2232 case DMFE_10MFD:
2233 case DMFE_100MFD:
2234 case DMFE_1M_HPNA:
2235 dmfe_media_mode = mode;
2236 break;
2237 default:dmfe_media_mode = DMFE_AUTO;
2238 break;
2239 }
2240
2241 if (HPNA_mode > 4)
2242 HPNA_mode = 0; /* Default: LP/HS */
2243 if (HPNA_rx_cmd > 1)
2244 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2245 if (HPNA_tx_cmd > 1)
2246 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2247 if (HPNA_NoiseFloor > 15)
2248 HPNA_NoiseFloor = 0;
2249
2250 rc = pci_register_driver(&dmfe_driver);
2251 if (rc < 0)
2252 return rc;
2253
2254 return 0;
2255 }
2256
2257
2258 /*
2259 * Description:
2260 * when user used rmmod to delete module, system invoked clean_module()
2261 * to un-register all registered services.
2262 */
2263
2264 static void __exit dmfe_cleanup_module(void)
2265 {
2266 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2267 pci_unregister_driver(&dmfe_driver);
2268 }
2269
2270 module_init(dmfe_init_module);
2271 module_exit(dmfe_cleanup_module);
Linux ARM platform port for MOXA ART SoC