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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / ethernet / intel / e1000e / 80003es2lan.c
blob4dd18a1f45d27b7fd95ba6d486f509a7bce24a4d
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32 */
33
34 #include "e1000.h"
35
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
40
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
44
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
48
49 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
51
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
54
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
57
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
64
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
68
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
75
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
77
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
80 1 = 50-80M
81 2 = 80-110M
82 3 = 110-140M
83 4 = >140M */
84
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
87
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
90
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
94
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
97
98 /*
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at
101 * "index + 5".
102 */
103 static const u16 e1000_gg82563_cable_length_table[] = {
104 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
106 ARRAY_SIZE(e1000_gg82563_cable_length_table)
107
108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
116 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
117 u16 *data);
118 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
119 u16 data);
120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
121
122 /**
123 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
124 * @hw: pointer to the HW structure
125 **/
126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
127 {
128 struct e1000_phy_info *phy = &hw->phy;
129 s32 ret_val;
130
131 if (hw->phy.media_type != e1000_media_type_copper) {
132 phy->type = e1000_phy_none;
133 return 0;
134 } else {
135 phy->ops.power_up = e1000_power_up_phy_copper;
136 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
137 }
138
139 phy->addr = 1;
140 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
141 phy->reset_delay_us = 100;
142 phy->type = e1000_phy_gg82563;
143
144 /* This can only be done after all function pointers are setup. */
145 ret_val = e1000e_get_phy_id(hw);
146
147 /* Verify phy id */
148 if (phy->id != GG82563_E_PHY_ID)
149 return -E1000_ERR_PHY;
150
151 return ret_val;
152 }
153
154 /**
155 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
156 * @hw: pointer to the HW structure
157 **/
158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
159 {
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = er32(EECD);
162 u16 size;
163
164 nvm->opcode_bits = 8;
165 nvm->delay_usec = 1;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
168 nvm->page_size = 32;
169 nvm->address_bits = 16;
170 break;
171 case e1000_nvm_override_spi_small:
172 nvm->page_size = 8;
173 nvm->address_bits = 8;
174 break;
175 default:
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
178 break;
179 }
180
181 nvm->type = e1000_nvm_eeprom_spi;
182
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
185
186 /*
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
189 */
190 size += NVM_WORD_SIZE_BASE_SHIFT;
191
192 /* EEPROM access above 16k is unsupported */
193 if (size > 14)
194 size = 14;
195 nvm->word_size = 1 << size;
196
197 return 0;
198 }
199
200 /**
201 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
202 * @hw: pointer to the HW structure
203 **/
204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
205 {
206 struct e1000_mac_info *mac = &hw->mac;
207
208 /* Set media type and media-dependent function pointers */
209 switch (hw->adapter->pdev->device) {
210 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
211 hw->phy.media_type = e1000_media_type_internal_serdes;
212 mac->ops.check_for_link = e1000e_check_for_serdes_link;
213 mac->ops.setup_physical_interface =
214 e1000e_setup_fiber_serdes_link;
215 break;
216 default:
217 hw->phy.media_type = e1000_media_type_copper;
218 mac->ops.check_for_link = e1000e_check_for_copper_link;
219 mac->ops.setup_physical_interface =
220 e1000_setup_copper_link_80003es2lan;
221 break;
222 }
223
224 /* Set mta register count */
225 mac->mta_reg_count = 128;
226 /* Set rar entry count */
227 mac->rar_entry_count = E1000_RAR_ENTRIES;
228 /* FWSM register */
229 mac->has_fwsm = true;
230 /* ARC supported; valid only if manageability features are enabled. */
231 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
232 /* Adaptive IFS not supported */
233 mac->adaptive_ifs = false;
234
235 /* set lan id for port to determine which phy lock to use */
236 hw->mac.ops.set_lan_id(hw);
237
238 return 0;
239 }
240
241 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
242 {
243 struct e1000_hw *hw = &adapter->hw;
244 s32 rc;
245
246 rc = e1000_init_mac_params_80003es2lan(hw);
247 if (rc)
248 return rc;
249
250 rc = e1000_init_nvm_params_80003es2lan(hw);
251 if (rc)
252 return rc;
253
254 rc = e1000_init_phy_params_80003es2lan(hw);
255 if (rc)
256 return rc;
257
258 return 0;
259 }
260
261 /**
262 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
263 * @hw: pointer to the HW structure
264 *
265 * A wrapper to acquire access rights to the correct PHY.
266 **/
267 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
268 {
269 u16 mask;
270
271 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
272 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
273 }
274
275 /**
276 * e1000_release_phy_80003es2lan - Release rights to access PHY
277 * @hw: pointer to the HW structure
278 *
279 * A wrapper to release access rights to the correct PHY.
280 **/
281 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
282 {
283 u16 mask;
284
285 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
286 e1000_release_swfw_sync_80003es2lan(hw, mask);
287 }
288
289 /**
290 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
291 * @hw: pointer to the HW structure
292 *
293 * Acquire the semaphore to access the Kumeran interface.
294 *
295 **/
296 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
297 {
298 u16 mask;
299
300 mask = E1000_SWFW_CSR_SM;
301
302 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
303 }
304
305 /**
306 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
307 * @hw: pointer to the HW structure
308 *
309 * Release the semaphore used to access the Kumeran interface
310 **/
311 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
312 {
313 u16 mask;
314
315 mask = E1000_SWFW_CSR_SM;
316
317 e1000_release_swfw_sync_80003es2lan(hw, mask);
318 }
319
320 /**
321 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
322 * @hw: pointer to the HW structure
323 *
324 * Acquire the semaphore to access the EEPROM.
325 **/
326 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
327 {
328 s32 ret_val;
329
330 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
331 if (ret_val)
332 return ret_val;
333
334 ret_val = e1000e_acquire_nvm(hw);
335
336 if (ret_val)
337 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
338
339 return ret_val;
340 }
341
342 /**
343 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
344 * @hw: pointer to the HW structure
345 *
346 * Release the semaphore used to access the EEPROM.
347 **/
348 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
349 {
350 e1000e_release_nvm(hw);
351 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
352 }
353
354 /**
355 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
356 * @hw: pointer to the HW structure
357 * @mask: specifies which semaphore to acquire
358 *
359 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
360 * will also specify which port we're acquiring the lock for.
361 **/
362 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
363 {
364 u32 swfw_sync;
365 u32 swmask = mask;
366 u32 fwmask = mask << 16;
367 s32 i = 0;
368 s32 timeout = 50;
369
370 while (i < timeout) {
371 if (e1000e_get_hw_semaphore(hw))
372 return -E1000_ERR_SWFW_SYNC;
373
374 swfw_sync = er32(SW_FW_SYNC);
375 if (!(swfw_sync & (fwmask | swmask)))
376 break;
377
378 /*
379 * Firmware currently using resource (fwmask)
380 * or other software thread using resource (swmask)
381 */
382 e1000e_put_hw_semaphore(hw);
383 mdelay(5);
384 i++;
385 }
386
387 if (i == timeout) {
388 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
389 return -E1000_ERR_SWFW_SYNC;
390 }
391
392 swfw_sync |= swmask;
393 ew32(SW_FW_SYNC, swfw_sync);
394
395 e1000e_put_hw_semaphore(hw);
396
397 return 0;
398 }
399
400 /**
401 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
402 * @hw: pointer to the HW structure
403 * @mask: specifies which semaphore to acquire
404 *
405 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
406 * will also specify which port we're releasing the lock for.
407 **/
408 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
409 {
410 u32 swfw_sync;
411
412 while (e1000e_get_hw_semaphore(hw) != 0)
413 ; /* Empty */
414
415 swfw_sync = er32(SW_FW_SYNC);
416 swfw_sync &= ~mask;
417 ew32(SW_FW_SYNC, swfw_sync);
418
419 e1000e_put_hw_semaphore(hw);
420 }
421
422 /**
423 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
424 * @hw: pointer to the HW structure
425 * @offset: offset of the register to read
426 * @data: pointer to the data returned from the operation
427 *
428 * Read the GG82563 PHY register.
429 **/
430 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
431 u32 offset, u16 *data)
432 {
433 s32 ret_val;
434 u32 page_select;
435 u16 temp;
436
437 ret_val = e1000_acquire_phy_80003es2lan(hw);
438 if (ret_val)
439 return ret_val;
440
441 /* Select Configuration Page */
442 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
443 page_select = GG82563_PHY_PAGE_SELECT;
444 } else {
445 /*
446 * Use Alternative Page Select register to access
447 * registers 30 and 31
448 */
449 page_select = GG82563_PHY_PAGE_SELECT_ALT;
450 }
451
452 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
453 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
454 if (ret_val) {
455 e1000_release_phy_80003es2lan(hw);
456 return ret_val;
457 }
458
459 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
460 /*
461 * The "ready" bit in the MDIC register may be incorrectly set
462 * before the device has completed the "Page Select" MDI
463 * transaction. So we wait 200us after each MDI command...
464 */
465 udelay(200);
466
467 /* ...and verify the command was successful. */
468 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
469
470 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
471 e1000_release_phy_80003es2lan(hw);
472 return -E1000_ERR_PHY;
473 }
474
475 udelay(200);
476
477 ret_val = e1000e_read_phy_reg_mdic(hw,
478 MAX_PHY_REG_ADDRESS & offset,
479 data);
480
481 udelay(200);
482 } else {
483 ret_val = e1000e_read_phy_reg_mdic(hw,
484 MAX_PHY_REG_ADDRESS & offset,
485 data);
486 }
487
488 e1000_release_phy_80003es2lan(hw);
489
490 return ret_val;
491 }
492
493 /**
494 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
495 * @hw: pointer to the HW structure
496 * @offset: offset of the register to read
497 * @data: value to write to the register
498 *
499 * Write to the GG82563 PHY register.
500 **/
501 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
502 u32 offset, u16 data)
503 {
504 s32 ret_val;
505 u32 page_select;
506 u16 temp;
507
508 ret_val = e1000_acquire_phy_80003es2lan(hw);
509 if (ret_val)
510 return ret_val;
511
512 /* Select Configuration Page */
513 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
514 page_select = GG82563_PHY_PAGE_SELECT;
515 } else {
516 /*
517 * Use Alternative Page Select register to access
518 * registers 30 and 31
519 */
520 page_select = GG82563_PHY_PAGE_SELECT_ALT;
521 }
522
523 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
524 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
525 if (ret_val) {
526 e1000_release_phy_80003es2lan(hw);
527 return ret_val;
528 }
529
530 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
531 /*
532 * The "ready" bit in the MDIC register may be incorrectly set
533 * before the device has completed the "Page Select" MDI
534 * transaction. So we wait 200us after each MDI command...
535 */
536 udelay(200);
537
538 /* ...and verify the command was successful. */
539 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
540
541 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
542 e1000_release_phy_80003es2lan(hw);
543 return -E1000_ERR_PHY;
544 }
545
546 udelay(200);
547
548 ret_val = e1000e_write_phy_reg_mdic(hw,
549 MAX_PHY_REG_ADDRESS & offset,
550 data);
551
552 udelay(200);
553 } else {
554 ret_val = e1000e_write_phy_reg_mdic(hw,
555 MAX_PHY_REG_ADDRESS & offset,
556 data);
557 }
558
559 e1000_release_phy_80003es2lan(hw);
560
561 return ret_val;
562 }
563
564 /**
565 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
566 * @hw: pointer to the HW structure
567 * @offset: offset of the register to read
568 * @words: number of words to write
569 * @data: buffer of data to write to the NVM
570 *
571 * Write "words" of data to the ESB2 NVM.
572 **/
573 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
574 u16 words, u16 *data)
575 {
576 return e1000e_write_nvm_spi(hw, offset, words, data);
577 }
578
579 /**
580 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
581 * @hw: pointer to the HW structure
582 *
583 * Wait a specific amount of time for manageability processes to complete.
584 * This is a function pointer entry point called by the phy module.
585 **/
586 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
587 {
588 s32 timeout = PHY_CFG_TIMEOUT;
589 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
590
591 if (hw->bus.func == 1)
592 mask = E1000_NVM_CFG_DONE_PORT_1;
593
594 while (timeout) {
595 if (er32(EEMNGCTL) & mask)
596 break;
597 usleep_range(1000, 2000);
598 timeout--;
599 }
600 if (!timeout) {
601 e_dbg("MNG configuration cycle has not completed.\n");
602 return -E1000_ERR_RESET;
603 }
604
605 return 0;
606 }
607
608 /**
609 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
610 * @hw: pointer to the HW structure
611 *
612 * Force the speed and duplex settings onto the PHY. This is a
613 * function pointer entry point called by the phy module.
614 **/
615 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
616 {
617 s32 ret_val;
618 u16 phy_data;
619 bool link;
620
621 /*
622 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
623 * forced whenever speed and duplex are forced.
624 */
625 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
626 if (ret_val)
627 return ret_val;
628
629 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
630 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
631 if (ret_val)
632 return ret_val;
633
634 e_dbg("GG82563 PSCR: %X\n", phy_data);
635
636 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
637 if (ret_val)
638 return ret_val;
639
640 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
641
642 /* Reset the phy to commit changes. */
643 phy_data |= MII_CR_RESET;
644
645 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
646 if (ret_val)
647 return ret_val;
648
649 udelay(1);
650
651 if (hw->phy.autoneg_wait_to_complete) {
652 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
653
654 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
655 100000, &link);
656 if (ret_val)
657 return ret_val;
658
659 if (!link) {
660 /*
661 * We didn't get link.
662 * Reset the DSP and cross our fingers.
663 */
664 ret_val = e1000e_phy_reset_dsp(hw);
665 if (ret_val)
666 return ret_val;
667 }
668
669 /* Try once more */
670 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
671 100000, &link);
672 if (ret_val)
673 return ret_val;
674 }
675
676 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
677 if (ret_val)
678 return ret_val;
679
680 /*
681 * Resetting the phy means we need to verify the TX_CLK corresponds
682 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
683 */
684 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
685 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
686 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
687 else
688 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
689
690 /*
691 * In addition, we must re-enable CRS on Tx for both half and full
692 * duplex.
693 */
694 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
695 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
696
697 return ret_val;
698 }
699
700 /**
701 * e1000_get_cable_length_80003es2lan - Set approximate cable length
702 * @hw: pointer to the HW structure
703 *
704 * Find the approximate cable length as measured by the GG82563 PHY.
705 * This is a function pointer entry point called by the phy module.
706 **/
707 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
708 {
709 struct e1000_phy_info *phy = &hw->phy;
710 s32 ret_val = 0;
711 u16 phy_data, index;
712
713 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
714 if (ret_val)
715 return ret_val;
716
717 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
718
719 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
720 return -E1000_ERR_PHY;
721
722 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
723 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
724
725 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
726
727 return 0;
728 }
729
730 /**
731 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
732 * @hw: pointer to the HW structure
733 * @speed: pointer to speed buffer
734 * @duplex: pointer to duplex buffer
735 *
736 * Retrieve the current speed and duplex configuration.
737 **/
738 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
739 u16 *duplex)
740 {
741 s32 ret_val;
742
743 if (hw->phy.media_type == e1000_media_type_copper) {
744 ret_val = e1000e_get_speed_and_duplex_copper(hw,
745 speed,
746 duplex);
747 hw->phy.ops.cfg_on_link_up(hw);
748 } else {
749 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
750 speed,
751 duplex);
752 }
753
754 return ret_val;
755 }
756
757 /**
758 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
759 * @hw: pointer to the HW structure
760 *
761 * Perform a global reset to the ESB2 controller.
762 **/
763 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
764 {
765 u32 ctrl;
766 s32 ret_val;
767 u16 kum_reg_data;
768
769 /*
770 * Prevent the PCI-E bus from sticking if there is no TLP connection
771 * on the last TLP read/write transaction when MAC is reset.
772 */
773 ret_val = e1000e_disable_pcie_master(hw);
774 if (ret_val)
775 e_dbg("PCI-E Master disable polling has failed.\n");
776
777 e_dbg("Masking off all interrupts\n");
778 ew32(IMC, 0xffffffff);
779
780 ew32(RCTL, 0);
781 ew32(TCTL, E1000_TCTL_PSP);
782 e1e_flush();
783
784 usleep_range(10000, 20000);
785
786 ctrl = er32(CTRL);
787
788 ret_val = e1000_acquire_phy_80003es2lan(hw);
789 e_dbg("Issuing a global reset to MAC\n");
790 ew32(CTRL, ctrl | E1000_CTRL_RST);
791 e1000_release_phy_80003es2lan(hw);
792
793 /* Disable IBIST slave mode (far-end loopback) */
794 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
795 &kum_reg_data);
796 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
797 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
798 kum_reg_data);
799
800 ret_val = e1000e_get_auto_rd_done(hw);
801 if (ret_val)
802 /* We don't want to continue accessing MAC registers. */
803 return ret_val;
804
805 /* Clear any pending interrupt events. */
806 ew32(IMC, 0xffffffff);
807 er32(ICR);
808
809 return e1000_check_alt_mac_addr_generic(hw);
810 }
811
812 /**
813 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
814 * @hw: pointer to the HW structure
815 *
816 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
817 **/
818 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
819 {
820 struct e1000_mac_info *mac = &hw->mac;
821 u32 reg_data;
822 s32 ret_val;
823 u16 kum_reg_data;
824 u16 i;
825
826 e1000_initialize_hw_bits_80003es2lan(hw);
827
828 /* Initialize identification LED */
829 ret_val = mac->ops.id_led_init(hw);
830 if (ret_val)
831 e_dbg("Error initializing identification LED\n");
832 /* This is not fatal and we should not stop init due to this */
833
834 /* Disabling VLAN filtering */
835 e_dbg("Initializing the IEEE VLAN\n");
836 mac->ops.clear_vfta(hw);
837
838 /* Setup the receive address. */
839 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
840
841 /* Zero out the Multicast HASH table */
842 e_dbg("Zeroing the MTA\n");
843 for (i = 0; i < mac->mta_reg_count; i++)
844 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
845
846 /* Setup link and flow control */
847 ret_val = mac->ops.setup_link(hw);
848
849 /* Disable IBIST slave mode (far-end loopback) */
850 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
851 &kum_reg_data);
852 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
853 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
854 kum_reg_data);
855
856 /* Set the transmit descriptor write-back policy */
857 reg_data = er32(TXDCTL(0));
858 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
859 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
860 ew32(TXDCTL(0), reg_data);
861
862 /* ...for both queues. */
863 reg_data = er32(TXDCTL(1));
864 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
865 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
866 ew32(TXDCTL(1), reg_data);
867
868 /* Enable retransmit on late collisions */
869 reg_data = er32(TCTL);
870 reg_data |= E1000_TCTL_RTLC;
871 ew32(TCTL, reg_data);
872
873 /* Configure Gigabit Carry Extend Padding */
874 reg_data = er32(TCTL_EXT);
875 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
876 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
877 ew32(TCTL_EXT, reg_data);
878
879 /* Configure Transmit Inter-Packet Gap */
880 reg_data = er32(TIPG);
881 reg_data &= ~E1000_TIPG_IPGT_MASK;
882 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
883 ew32(TIPG, reg_data);
884
885 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
886 reg_data &= ~0x00100000;
887 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
888
889 /* default to true to enable the MDIC W/A */
890 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
891
892 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
893 E1000_KMRNCTRLSTA_OFFSET >>
894 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
895 &i);
896 if (!ret_val) {
897 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
898 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
899 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
900 }
901
902 /*
903 * Clear all of the statistics registers (clear on read). It is
904 * important that we do this after we have tried to establish link
905 * because the symbol error count will increment wildly if there
906 * is no link.
907 */
908 e1000_clear_hw_cntrs_80003es2lan(hw);
909
910 return ret_val;
911 }
912
913 /**
914 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
915 * @hw: pointer to the HW structure
916 *
917 * Initializes required hardware-dependent bits needed for normal operation.
918 **/
919 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
920 {
921 u32 reg;
922
923 /* Transmit Descriptor Control 0 */
924 reg = er32(TXDCTL(0));
925 reg |= (1 << 22);
926 ew32(TXDCTL(0), reg);
927
928 /* Transmit Descriptor Control 1 */
929 reg = er32(TXDCTL(1));
930 reg |= (1 << 22);
931 ew32(TXDCTL(1), reg);
932
933 /* Transmit Arbitration Control 0 */
934 reg = er32(TARC(0));
935 reg &= ~(0xF << 27); /* 30:27 */
936 if (hw->phy.media_type != e1000_media_type_copper)
937 reg &= ~(1 << 20);
938 ew32(TARC(0), reg);
939
940 /* Transmit Arbitration Control 1 */
941 reg = er32(TARC(1));
942 if (er32(TCTL) & E1000_TCTL_MULR)
943 reg &= ~(1 << 28);
944 else
945 reg |= (1 << 28);
946 ew32(TARC(1), reg);
947
948 /*
949 * Disable IPv6 extension header parsing because some malformed
950 * IPv6 headers can hang the Rx.
951 */
952 reg = er32(RFCTL);
953 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
954 ew32(RFCTL, reg);
955 }
956
957 /**
958 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
959 * @hw: pointer to the HW structure
960 *
961 * Setup some GG82563 PHY registers for obtaining link
962 **/
963 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
964 {
965 struct e1000_phy_info *phy = &hw->phy;
966 s32 ret_val;
967 u32 ctrl_ext;
968 u16 data;
969
970 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
971 if (ret_val)
972 return ret_val;
973
974 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
975 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
976 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
977
978 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
979 if (ret_val)
980 return ret_val;
981
982 /*
983 * Options:
984 * MDI/MDI-X = 0 (default)
985 * 0 - Auto for all speeds
986 * 1 - MDI mode
987 * 2 - MDI-X mode
988 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
989 */
990 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
991 if (ret_val)
992 return ret_val;
993
994 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
995
996 switch (phy->mdix) {
997 case 1:
998 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
999 break;
1000 case 2:
1001 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1002 break;
1003 case 0:
1004 default:
1005 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1006 break;
1007 }
1008
1009 /*
1010 * Options:
1011 * disable_polarity_correction = 0 (default)
1012 * Automatic Correction for Reversed Cable Polarity
1013 * 0 - Disabled
1014 * 1 - Enabled
1015 */
1016 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1017 if (phy->disable_polarity_correction)
1018 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1019
1020 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1021 if (ret_val)
1022 return ret_val;
1023
1024 /* SW Reset the PHY so all changes take effect */
1025 ret_val = e1000e_commit_phy(hw);
1026 if (ret_val) {
1027 e_dbg("Error Resetting the PHY\n");
1028 return ret_val;
1029 }
1030
1031 /* Bypass Rx and Tx FIFO's */
1032 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1033 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1034 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1035 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1036 if (ret_val)
1037 return ret_val;
1038
1039 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1040 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1041 &data);
1042 if (ret_val)
1043 return ret_val;
1044 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1045 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1046 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1047 data);
1048 if (ret_val)
1049 return ret_val;
1050
1051 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1052 if (ret_val)
1053 return ret_val;
1054
1055 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1056 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1057 if (ret_val)
1058 return ret_val;
1059
1060 ctrl_ext = er32(CTRL_EXT);
1061 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1062 ew32(CTRL_EXT, ctrl_ext);
1063
1064 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1065 if (ret_val)
1066 return ret_val;
1067
1068 /*
1069 * Do not init these registers when the HW is in IAMT mode, since the
1070 * firmware will have already initialized them. We only initialize
1071 * them if the HW is not in IAMT mode.
1072 */
1073 if (!hw->mac.ops.check_mng_mode(hw)) {
1074 /* Enable Electrical Idle on the PHY */
1075 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1076 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1077 if (ret_val)
1078 return ret_val;
1079
1080 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1081 if (ret_val)
1082 return ret_val;
1083
1084 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1085 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1086 if (ret_val)
1087 return ret_val;
1088 }
1089
1090 /*
1091 * Workaround: Disable padding in Kumeran interface in the MAC
1092 * and in the PHY to avoid CRC errors.
1093 */
1094 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1095 if (ret_val)
1096 return ret_val;
1097
1098 data |= GG82563_ICR_DIS_PADDING;
1099 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1100 if (ret_val)
1101 return ret_val;
1102
1103 return 0;
1104 }
1105
1106 /**
1107 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1108 * @hw: pointer to the HW structure
1109 *
1110 * Essentially a wrapper for setting up all things "copper" related.
1111 * This is a function pointer entry point called by the mac module.
1112 **/
1113 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1114 {
1115 u32 ctrl;
1116 s32 ret_val;
1117 u16 reg_data;
1118
1119 ctrl = er32(CTRL);
1120 ctrl |= E1000_CTRL_SLU;
1121 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1122 ew32(CTRL, ctrl);
1123
1124 /*
1125 * Set the mac to wait the maximum time between each
1126 * iteration and increase the max iterations when
1127 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1128 */
1129 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1130 0xFFFF);
1131 if (ret_val)
1132 return ret_val;
1133 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1134 &reg_data);
1135 if (ret_val)
1136 return ret_val;
1137 reg_data |= 0x3F;
1138 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1139 reg_data);
1140 if (ret_val)
1141 return ret_val;
1142 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1143 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1144 &reg_data);
1145 if (ret_val)
1146 return ret_val;
1147 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1148 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1149 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1150 reg_data);
1151 if (ret_val)
1152 return ret_val;
1153
1154 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1155 if (ret_val)
1156 return ret_val;
1157
1158 return e1000e_setup_copper_link(hw);
1159 }
1160
1161 /**
1162 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1163 * @hw: pointer to the HW structure
1164 * @duplex: current duplex setting
1165 *
1166 * Configure the KMRN interface by applying last minute quirks for
1167 * 10/100 operation.
1168 **/
1169 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1170 {
1171 s32 ret_val = 0;
1172 u16 speed;
1173 u16 duplex;
1174
1175 if (hw->phy.media_type == e1000_media_type_copper) {
1176 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1177 &duplex);
1178 if (ret_val)
1179 return ret_val;
1180
1181 if (speed == SPEED_1000)
1182 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1183 else
1184 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1185 }
1186
1187 return ret_val;
1188 }
1189
1190 /**
1191 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1192 * @hw: pointer to the HW structure
1193 * @duplex: current duplex setting
1194 *
1195 * Configure the KMRN interface by applying last minute quirks for
1196 * 10/100 operation.
1197 **/
1198 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1199 {
1200 s32 ret_val;
1201 u32 tipg;
1202 u32 i = 0;
1203 u16 reg_data, reg_data2;
1204
1205 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1206 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1207 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1208 reg_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212 /* Configure Transmit Inter-Packet Gap */
1213 tipg = er32(TIPG);
1214 tipg &= ~E1000_TIPG_IPGT_MASK;
1215 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1216 ew32(TIPG, tipg);
1217
1218 do {
1219 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1220 if (ret_val)
1221 return ret_val;
1222
1223 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1224 if (ret_val)
1225 return ret_val;
1226 i++;
1227 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1228
1229 if (duplex == HALF_DUPLEX)
1230 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1231 else
1232 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1233
1234 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1235 }
1236
1237 /**
1238 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1239 * @hw: pointer to the HW structure
1240 *
1241 * Configure the KMRN interface by applying last minute quirks for
1242 * gigabit operation.
1243 **/
1244 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1245 {
1246 s32 ret_val;
1247 u16 reg_data, reg_data2;
1248 u32 tipg;
1249 u32 i = 0;
1250
1251 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1252 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1253 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1254 reg_data);
1255 if (ret_val)
1256 return ret_val;
1257
1258 /* Configure Transmit Inter-Packet Gap */
1259 tipg = er32(TIPG);
1260 tipg &= ~E1000_TIPG_IPGT_MASK;
1261 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1262 ew32(TIPG, tipg);
1263
1264 do {
1265 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1266 if (ret_val)
1267 return ret_val;
1268
1269 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1270 if (ret_val)
1271 return ret_val;
1272 i++;
1273 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1274
1275 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1276
1277 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1278 }
1279
1280 /**
1281 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1282 * @hw: pointer to the HW structure
1283 * @offset: register offset to be read
1284 * @data: pointer to the read data
1285 *
1286 * Acquire semaphore, then read the PHY register at offset
1287 * using the kumeran interface. The information retrieved is stored in data.
1288 * Release the semaphore before exiting.
1289 **/
1290 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1291 u16 *data)
1292 {
1293 u32 kmrnctrlsta;
1294 s32 ret_val = 0;
1295
1296 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1297 if (ret_val)
1298 return ret_val;
1299
1300 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1301 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1302 ew32(KMRNCTRLSTA, kmrnctrlsta);
1303 e1e_flush();
1304
1305 udelay(2);
1306
1307 kmrnctrlsta = er32(KMRNCTRLSTA);
1308 *data = (u16)kmrnctrlsta;
1309
1310 e1000_release_mac_csr_80003es2lan(hw);
1311
1312 return ret_val;
1313 }
1314
1315 /**
1316 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1317 * @hw: pointer to the HW structure
1318 * @offset: register offset to write to
1319 * @data: data to write at register offset
1320 *
1321 * Acquire semaphore, then write the data to PHY register
1322 * at the offset using the kumeran interface. Release semaphore
1323 * before exiting.
1324 **/
1325 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1326 u16 data)
1327 {
1328 u32 kmrnctrlsta;
1329 s32 ret_val = 0;
1330
1331 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1332 if (ret_val)
1333 return ret_val;
1334
1335 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1336 E1000_KMRNCTRLSTA_OFFSET) | data;
1337 ew32(KMRNCTRLSTA, kmrnctrlsta);
1338 e1e_flush();
1339
1340 udelay(2);
1341
1342 e1000_release_mac_csr_80003es2lan(hw);
1343
1344 return ret_val;
1345 }
1346
1347 /**
1348 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1349 * @hw: pointer to the HW structure
1350 **/
1351 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1352 {
1353 s32 ret_val = 0;
1354
1355 /*
1356 * If there's an alternate MAC address place it in RAR0
1357 * so that it will override the Si installed default perm
1358 * address.
1359 */
1360 ret_val = e1000_check_alt_mac_addr_generic(hw);
1361 if (ret_val)
1362 return ret_val;
1363
1364 return e1000_read_mac_addr_generic(hw);
1365 }
1366
1367 /**
1368 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1369 * @hw: pointer to the HW structure
1370 *
1371 * In the case of a PHY power down to save power, or to turn off link during a
1372 * driver unload, or wake on lan is not enabled, remove the link.
1373 **/
1374 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1375 {
1376 /* If the management interface is not enabled, then power down */
1377 if (!(hw->mac.ops.check_mng_mode(hw) ||
1378 hw->phy.ops.check_reset_block(hw)))
1379 e1000_power_down_phy_copper(hw);
1380 }
1381
1382 /**
1383 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1384 * @hw: pointer to the HW structure
1385 *
1386 * Clears the hardware counters by reading the counter registers.
1387 **/
1388 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1389 {
1390 e1000e_clear_hw_cntrs_base(hw);
1391
1392 er32(PRC64);
1393 er32(PRC127);
1394 er32(PRC255);
1395 er32(PRC511);
1396 er32(PRC1023);
1397 er32(PRC1522);
1398 er32(PTC64);
1399 er32(PTC127);
1400 er32(PTC255);
1401 er32(PTC511);
1402 er32(PTC1023);
1403 er32(PTC1522);
1404
1405 er32(ALGNERRC);
1406 er32(RXERRC);
1407 er32(TNCRS);
1408 er32(CEXTERR);
1409 er32(TSCTC);
1410 er32(TSCTFC);
1411
1412 er32(MGTPRC);
1413 er32(MGTPDC);
1414 er32(MGTPTC);
1415
1416 er32(IAC);
1417 er32(ICRXOC);
1418
1419 er32(ICRXPTC);
1420 er32(ICRXATC);
1421 er32(ICTXPTC);
1422 er32(ICTXATC);
1423 er32(ICTXQEC);
1424 er32(ICTXQMTC);
1425 er32(ICRXDMTC);
1426 }
1427
1428 static const struct e1000_mac_operations es2_mac_ops = {
1429 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1430 .id_led_init = e1000e_id_led_init_generic,
1431 .blink_led = e1000e_blink_led_generic,
1432 .check_mng_mode = e1000e_check_mng_mode_generic,
1433 /* check_for_link dependent on media type */
1434 .cleanup_led = e1000e_cleanup_led_generic,
1435 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1436 .get_bus_info = e1000e_get_bus_info_pcie,
1437 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1438 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1439 .led_on = e1000e_led_on_generic,
1440 .led_off = e1000e_led_off_generic,
1441 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1442 .write_vfta = e1000_write_vfta_generic,
1443 .clear_vfta = e1000_clear_vfta_generic,
1444 .reset_hw = e1000_reset_hw_80003es2lan,
1445 .init_hw = e1000_init_hw_80003es2lan,
1446 .setup_link = e1000e_setup_link_generic,
1447 /* setup_physical_interface dependent on media type */
1448 .setup_led = e1000e_setup_led_generic,
1449 .config_collision_dist = e1000e_config_collision_dist_generic,
1450 .rar_set = e1000e_rar_set_generic,
1451 };
1452
1453 static const struct e1000_phy_operations es2_phy_ops = {
1454 .acquire = e1000_acquire_phy_80003es2lan,
1455 .check_polarity = e1000_check_polarity_m88,
1456 .check_reset_block = e1000e_check_reset_block_generic,
1457 .commit = e1000e_phy_sw_reset,
1458 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1459 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1460 .get_cable_length = e1000_get_cable_length_80003es2lan,
1461 .get_info = e1000e_get_phy_info_m88,
1462 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1463 .release = e1000_release_phy_80003es2lan,
1464 .reset = e1000e_phy_hw_reset_generic,
1465 .set_d0_lplu_state = NULL,
1466 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1467 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1468 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1469 };
1470
1471 static const struct e1000_nvm_operations es2_nvm_ops = {
1472 .acquire = e1000_acquire_nvm_80003es2lan,
1473 .read = e1000e_read_nvm_eerd,
1474 .release = e1000_release_nvm_80003es2lan,
1475 .reload = e1000e_reload_nvm_generic,
1476 .update = e1000e_update_nvm_checksum_generic,
1477 .valid_led_default = e1000e_valid_led_default,
1478 .validate = e1000e_validate_nvm_checksum_generic,
1479 .write = e1000_write_nvm_80003es2lan,
1480 };
1481
1482 const struct e1000_info e1000_es2_info = {
1483 .mac = e1000_80003es2lan,
1484 .flags = FLAG_HAS_HW_VLAN_FILTER
1485 | FLAG_HAS_JUMBO_FRAMES
1486 | FLAG_HAS_WOL
1487 | FLAG_APME_IN_CTRL3
1488 | FLAG_HAS_CTRLEXT_ON_LOAD
1489 | FLAG_RX_NEEDS_RESTART /* errata */
1490 | FLAG_TARC_SET_BIT_ZERO /* errata */
1491 | FLAG_APME_CHECK_PORT_B
1492 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1493 .flags2 = FLAG2_DMA_BURST,
1494 .pba = 38,
1495 .max_hw_frame_size = DEFAULT_JUMBO,
1496 .get_variants = e1000_get_variants_80003es2lan,
1497 .mac_ops = &es2_mac_ops,
1498 .phy_ops = &es2_phy_ops,
1499 .nvm_ops = &es2_nvm_ops,
1500 };
1501
Linux ARM platform port for MOXA ART SoC