drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/driver.h>
  49 #include <linux/mlx4/doorbell.h>
  50 #include <linux/mlx4/cmd.h>
  51
  52 #define DRV_NAME        "mlx4_core"
  53 #define PFX             DRV_NAME ": "
  54 #define DRV_VERSION     "1.1"
  55 #define DRV_RELDATE     "Dec, 2011"
  56
  57 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  58 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  59 #define MLX4_FS_NUM_OF_L2_ADDR          8
  60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  61 #define MLX4_FS_NUM_MCG                 (1 << 17)
  62
  63 enum {
  64         MLX4_FS_L2_HASH = 0,
  65         MLX4_FS_L2_L3_L4_HASH,
  66 };
  67
  68 #define MLX4_NUM_UP             8
  69 #define MLX4_NUM_TC             8
  70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
  71 #define MLX4_RATELIMIT_DEFAULT 0xffff
  72
  73 struct mlx4_set_port_prio2tc_context {
  74         u8 prio2tc[4];
  75 };
  76
  77 struct mlx4_port_scheduler_tc_cfg_be {
  78         __be16 pg;
  79         __be16 bw_precentage;
  80         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  81         __be16 max_bw_value;
  82 };
  83
  84 struct mlx4_set_port_scheduler_context {
  85         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  86 };
  87
  88 enum {
  89         MLX4_HCR_BASE           = 0x80680,
  90         MLX4_HCR_SIZE           = 0x0001c,
  91         MLX4_CLR_INT_SIZE       = 0x00008,
  92         MLX4_SLAVE_COMM_BASE    = 0x0,
  93         MLX4_COMM_PAGESIZE      = 0x1000
  94 };
  95
  96 enum {
  97         MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
  98         MLX4_MAX_QP_PER_MGM     = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
  99         MLX4_MTT_ENTRY_PER_SEG  = 8,
 100 };
 101
 102 enum {
 103         MLX4_NUM_PDS            = 1 << 15
 104 };
 105
 106 enum {
 107         MLX4_CMPT_TYPE_QP       = 0,
 108         MLX4_CMPT_TYPE_SRQ      = 1,
 109         MLX4_CMPT_TYPE_CQ       = 2,
 110         MLX4_CMPT_TYPE_EQ       = 3,
 111         MLX4_CMPT_NUM_TYPE
 112 };
 113
 114 enum {
 115         MLX4_CMPT_SHIFT         = 24,
 116         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 117 };
 118
 119 enum mlx4_mr_state {
 120         MLX4_MR_DISABLED = 0,
 121         MLX4_MR_EN_HW,
 122         MLX4_MR_EN_SW
 123 };
 124
 125 #define MLX4_COMM_TIME          10000
 126 enum {
 127         MLX4_COMM_CMD_RESET,
 128         MLX4_COMM_CMD_VHCR0,
 129         MLX4_COMM_CMD_VHCR1,
 130         MLX4_COMM_CMD_VHCR2,
 131         MLX4_COMM_CMD_VHCR_EN,
 132         MLX4_COMM_CMD_VHCR_POST,
 133         MLX4_COMM_CMD_FLR = 254
 134 };
 135
 136 /*The flag indicates that the slave should delay the RESET cmd*/
 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 138 /*indicates how many retries will be done if we are in the middle of FLR*/
 139 #define NUM_OF_RESET_RETRIES    10
 140 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 141 enum mlx4_resource {
 142         RES_QP,
 143         RES_CQ,
 144         RES_SRQ,
 145         RES_XRCD,
 146         RES_MPT,
 147         RES_MTT,
 148         RES_MAC,
 149         RES_VLAN,
 150         RES_EQ,
 151         RES_COUNTER,
 152         RES_FS_RULE,
 153         MLX4_NUM_OF_RESOURCE_TYPE
 154 };
 155
 156 enum mlx4_alloc_mode {
 157         RES_OP_RESERVE,
 158         RES_OP_RESERVE_AND_MAP,
 159         RES_OP_MAP_ICM,
 160 };
 161
 162 enum mlx4_res_tracker_free_type {
 163         RES_TR_FREE_ALL,
 164         RES_TR_FREE_SLAVES_ONLY,
 165         RES_TR_FREE_STRUCTS_ONLY,
 166 };
 167
 168 /*
 169  *Virtual HCR structures.
 170  * mlx4_vhcr is the sw representation, in machine endianess
 171  *
 172  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 173  * to FW to go through communication channel.
 174  * It is big endian, and has the same structure as the physical HCR
 175  * used by command interface
 176  */
 177 struct mlx4_vhcr {
 178         u64     in_param;
 179         u64     out_param;
 180         u32     in_modifier;
 181         u32     errno;
 182         u16     op;
 183         u16     token;
 184         u8      op_modifier;
 185         u8      e_bit;
 186 };
 187
 188 struct mlx4_vhcr_cmd {
 189         __be64 in_param;
 190         __be32 in_modifier;
 191         __be64 out_param;
 192         __be16 token;
 193         u16 reserved;
 194         u8 status;
 195         u8 flags;
 196         __be16 opcode;
 197 };
 198
 199 struct mlx4_cmd_info {
 200         u16 opcode;
 201         bool has_inbox;
 202         bool has_outbox;
 203         bool out_is_imm;
 204         bool encode_slave_id;
 205         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 206                       struct mlx4_cmd_mailbox *inbox);
 207         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 208                        struct mlx4_cmd_mailbox *inbox,
 209                        struct mlx4_cmd_mailbox *outbox,
 210                        struct mlx4_cmd_info *cmd);
 211 };
 212
 213 #ifdef CONFIG_MLX4_DEBUG
 214 extern int mlx4_debug_level;
 215 #else /* CONFIG_MLX4_DEBUG */
 216 #define mlx4_debug_level        (0)
 217 #endif /* CONFIG_MLX4_DEBUG */
 218
 219 #define mlx4_dbg(mdev, format, arg...)                                  \
 220 do {                                                                    \
 221         if (mlx4_debug_level)                                           \
 222                 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
 223 } while (0)
 224
 225 #define mlx4_err(mdev, format, arg...) \
 226         dev_err(&mdev->pdev->dev, format, ##arg)
 227 #define mlx4_info(mdev, format, arg...) \
 228         dev_info(&mdev->pdev->dev, format, ##arg)
 229 #define mlx4_warn(mdev, format, arg...) \
 230         dev_warn(&mdev->pdev->dev, format, ##arg)
 231
 232 extern int mlx4_log_num_mgm_entry_size;
 233 extern int log_mtts_per_seg;
 234
 235 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 236 #define ALL_SLAVES 0xff
 237
 238 struct mlx4_bitmap {
 239         u32                     last;
 240         u32                     top;
 241         u32                     max;
 242         u32                     reserved_top;
 243         u32                     mask;
 244         u32                     avail;
 245         spinlock_t              lock;
 246         unsigned long          *table;
 247 };
 248
 249 struct mlx4_buddy {
 250         unsigned long         **bits;
 251         unsigned int           *num_free;
 252         u32                     max_order;
 253         spinlock_t              lock;
 254 };
 255
 256 struct mlx4_icm;
 257
 258 struct mlx4_icm_table {
 259         u64                     virt;
 260         int                     num_icm;
 261         u32                     num_obj;
 262         int                     obj_size;
 263         int                     lowmem;
 264         int                     coherent;
 265         struct mutex            mutex;
 266         struct mlx4_icm       **icm;
 267 };
 268
 269 /*
 270  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 271  */
 272 struct mlx4_mpt_entry {
 273         __be32 flags;
 274         __be32 qpn;
 275         __be32 key;
 276         __be32 pd_flags;
 277         __be64 start;
 278         __be64 length;
 279         __be32 lkey;
 280         __be32 win_cnt;
 281         u8      reserved1[3];
 282         u8      mtt_rep;
 283         __be64 mtt_addr;
 284         __be32 mtt_sz;
 285         __be32 entity_size;
 286         __be32 first_byte_offset;
 287 } __packed;
 288
 289 /*
 290  * Must be packed because start is 64 bits but only aligned to 32 bits.
 291  */
 292 struct mlx4_eq_context {
 293         __be32                  flags;
 294         u16                     reserved1[3];
 295         __be16                  page_offset;
 296         u8                      log_eq_size;
 297         u8                      reserved2[4];
 298         u8                      eq_period;
 299         u8                      reserved3;
 300         u8                      eq_max_count;
 301         u8                      reserved4[3];
 302         u8                      intr;
 303         u8                      log_page_size;
 304         u8                      reserved5[2];
 305         u8                      mtt_base_addr_h;
 306         __be32                  mtt_base_addr_l;
 307         u32                     reserved6[2];
 308         __be32                  consumer_index;
 309         __be32                  producer_index;
 310         u32                     reserved7[4];
 311 };
 312
 313 struct mlx4_cq_context {
 314         __be32                  flags;
 315         u16                     reserved1[3];
 316         __be16                  page_offset;
 317         __be32                  logsize_usrpage;
 318         __be16                  cq_period;
 319         __be16                  cq_max_count;
 320         u8                      reserved2[3];
 321         u8                      comp_eqn;
 322         u8                      log_page_size;
 323         u8                      reserved3[2];
 324         u8                      mtt_base_addr_h;
 325         __be32                  mtt_base_addr_l;
 326         __be32                  last_notified_index;
 327         __be32                  solicit_producer_index;
 328         __be32                  consumer_index;
 329         __be32                  producer_index;
 330         u32                     reserved4[2];
 331         __be64                  db_rec_addr;
 332 };
 333
 334 struct mlx4_srq_context {
 335         __be32                  state_logsize_srqn;
 336         u8                      logstride;
 337         u8                      reserved1;
 338         __be16                  xrcd;
 339         __be32                  pg_offset_cqn;
 340         u32                     reserved2;
 341         u8                      log_page_size;
 342         u8                      reserved3[2];
 343         u8                      mtt_base_addr_h;
 344         __be32                  mtt_base_addr_l;
 345         __be32                  pd;
 346         __be16                  limit_watermark;
 347         __be16                  wqe_cnt;
 348         u16                     reserved4;
 349         __be16                  wqe_counter;
 350         u32                     reserved5;
 351         __be64                  db_rec_addr;
 352 };
 353
 354 struct mlx4_eq {
 355         struct mlx4_dev        *dev;
 356         void __iomem           *doorbell;
 357         int                     eqn;
 358         u32                     cons_index;
 359         u16                     irq;
 360         u16                     have_irq;
 361         int                     nent;
 362         struct mlx4_buf_list   *page_list;
 363         struct mlx4_mtt         mtt;
 364 };
 365
 366 struct mlx4_slave_eqe {
 367         u8 type;
 368         u8 port;
 369         u32 param;
 370 };
 371
 372 struct mlx4_slave_event_eq_info {
 373         int eqn;
 374         u16 token;
 375 };
 376
 377 struct mlx4_profile {
 378         int                     num_qp;
 379         int                     rdmarc_per_qp;
 380         int                     num_srq;
 381         int                     num_cq;
 382         int                     num_mcg;
 383         int                     num_mpt;
 384         unsigned                num_mtt;
 385 };
 386
 387 struct mlx4_fw {
 388         u64                     clr_int_base;
 389         u64                     catas_offset;
 390         u64                     comm_base;
 391         struct mlx4_icm        *fw_icm;
 392         struct mlx4_icm        *aux_icm;
 393         u32                     catas_size;
 394         u16                     fw_pages;
 395         u8                      clr_int_bar;
 396         u8                      catas_bar;
 397         u8                      comm_bar;
 398 };
 399
 400 struct mlx4_comm {
 401         u32                     slave_write;
 402         u32                     slave_read;
 403 };
 404
 405 enum {
 406         MLX4_MCAST_CONFIG       = 0,
 407         MLX4_MCAST_DISABLE      = 1,
 408         MLX4_MCAST_ENABLE       = 2,
 409 };
 410
 411 #define VLAN_FLTR_SIZE  128
 412
 413 struct mlx4_vlan_fltr {
 414         __be32 entry[VLAN_FLTR_SIZE];
 415 };
 416
 417 struct mlx4_mcast_entry {
 418         struct list_head list;
 419         u64 addr;
 420 };
 421
 422 struct mlx4_promisc_qp {
 423         struct list_head list;
 424         u32 qpn;
 425 };
 426
 427 struct mlx4_steer_index {
 428         struct list_head list;
 429         unsigned int index;
 430         struct list_head duplicates;
 431 };
 432
 433 #define MLX4_EVENT_TYPES_NUM 64
 434
 435 struct mlx4_slave_state {
 436         u8 comm_toggle;
 437         u8 last_cmd;
 438         u8 init_port_mask;
 439         bool active;
 440         u8 function;
 441         dma_addr_t vhcr_dma;
 442         u16 mtu[MLX4_MAX_PORTS + 1];
 443         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 444         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 445         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 446         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 447         /* event type to eq number lookup */
 448         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 449         u16 eq_pi;
 450         u16 eq_ci;
 451         spinlock_t lock;
 452         /*initialized via the kzalloc*/
 453         u8 is_slave_going_down;
 454         u32 cookie;
 455 };
 456
 457 struct slave_list {
 458         struct mutex mutex;
 459         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 460 };
 461
 462 struct mlx4_resource_tracker {
 463         spinlock_t lock;
 464         /* tree for each resources */
 465         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 466         /* num_of_slave's lists, one per slave */
 467         struct slave_list *slave_list;
 468 };
 469
 470 #define SLAVE_EVENT_EQ_SIZE     128
 471 struct mlx4_slave_event_eq {
 472         u32 eqn;
 473         u32 cons;
 474         u32 prod;
 475         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 476 };
 477
 478 struct mlx4_master_qp0_state {
 479         int proxy_qp0_active;
 480         int qp0_active;
 481         int port_active;
 482 };
 483
 484 struct mlx4_mfunc_master_ctx {
 485         struct mlx4_slave_state *slave_state;
 486         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 487         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 488         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 489         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 490         struct mlx4_resource_tracker res_tracker;
 491         struct workqueue_struct *comm_wq;
 492         struct work_struct      comm_work;
 493         struct work_struct      slave_event_work;
 494         struct work_struct      slave_flr_event_work;
 495         spinlock_t              slave_state_lock;
 496         __be32                  comm_arm_bit_vector[4];
 497         struct mlx4_eqe         cmd_eqe;
 498         struct mlx4_slave_event_eq slave_eq;
 499         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 500 };
 501
 502 struct mlx4_mfunc {
 503         struct mlx4_comm __iomem       *comm;
 504         struct mlx4_vhcr_cmd           *vhcr;
 505         dma_addr_t                      vhcr_dma;
 506
 507         struct mlx4_mfunc_master_ctx    master;
 508 };
 509
 510 struct mlx4_cmd {
 511         struct pci_pool        *pool;
 512         void __iomem           *hcr;
 513         struct mutex            hcr_mutex;
 514         struct semaphore        poll_sem;
 515         struct semaphore        event_sem;
 516         struct semaphore        slave_sem;
 517         int                     max_cmds;
 518         spinlock_t              context_lock;
 519         int                     free_head;
 520         struct mlx4_cmd_context *context;
 521         u16                     token_mask;
 522         u8                      use_events;
 523         u8                      toggle;
 524         u8                      comm_toggle;
 525 };
 526
 527 struct mlx4_uar_table {
 528         struct mlx4_bitmap      bitmap;
 529 };
 530
 531 struct mlx4_mr_table {
 532         struct mlx4_bitmap      mpt_bitmap;
 533         struct mlx4_buddy       mtt_buddy;
 534         u64                     mtt_base;
 535         u64                     mpt_base;
 536         struct mlx4_icm_table   mtt_table;
 537         struct mlx4_icm_table   dmpt_table;
 538 };
 539
 540 struct mlx4_cq_table {
 541         struct mlx4_bitmap      bitmap;
 542         spinlock_t              lock;
 543         struct radix_tree_root  tree;
 544         struct mlx4_icm_table   table;
 545         struct mlx4_icm_table   cmpt_table;
 546 };
 547
 548 struct mlx4_eq_table {
 549         struct mlx4_bitmap      bitmap;
 550         char                   *irq_names;
 551         void __iomem           *clr_int;
 552         void __iomem          **uar_map;
 553         u32                     clr_mask;
 554         struct mlx4_eq         *eq;
 555         struct mlx4_icm_table   table;
 556         struct mlx4_icm_table   cmpt_table;
 557         int                     have_irq;
 558         u8                      inta_pin;
 559 };
 560
 561 struct mlx4_srq_table {
 562         struct mlx4_bitmap      bitmap;
 563         spinlock_t              lock;
 564         struct radix_tree_root  tree;
 565         struct mlx4_icm_table   table;
 566         struct mlx4_icm_table   cmpt_table;
 567 };
 568
 569 struct mlx4_qp_table {
 570         struct mlx4_bitmap      bitmap;
 571         u32                     rdmarc_base;
 572         int                     rdmarc_shift;
 573         spinlock_t              lock;
 574         struct mlx4_icm_table   qp_table;
 575         struct mlx4_icm_table   auxc_table;
 576         struct mlx4_icm_table   altc_table;
 577         struct mlx4_icm_table   rdmarc_table;
 578         struct mlx4_icm_table   cmpt_table;
 579 };
 580
 581 struct mlx4_mcg_table {
 582         struct mutex            mutex;
 583         struct mlx4_bitmap      bitmap;
 584         struct mlx4_icm_table   table;
 585 };
 586
 587 struct mlx4_catas_err {
 588         u32 __iomem            *map;
 589         struct timer_list       timer;
 590         struct list_head        list;
 591 };
 592
 593 #define MLX4_MAX_MAC_NUM        128
 594 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 595
 596 struct mlx4_mac_table {
 597         __be64                  entries[MLX4_MAX_MAC_NUM];
 598         int                     refs[MLX4_MAX_MAC_NUM];
 599         struct mutex            mutex;
 600         int                     total;
 601         int                     max;
 602 };
 603
 604 #define MLX4_MAX_VLAN_NUM       128
 605 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 606
 607 struct mlx4_vlan_table {
 608         __be32                  entries[MLX4_MAX_VLAN_NUM];
 609         int                     refs[MLX4_MAX_VLAN_NUM];
 610         struct mutex            mutex;
 611         int                     total;
 612         int                     max;
 613 };
 614
 615 #define SET_PORT_GEN_ALL_VALID          0x7
 616 #define SET_PORT_PROMISC_SHIFT          31
 617 #define SET_PORT_MC_PROMISC_SHIFT       30
 618
 619 enum {
 620         MCAST_DIRECT_ONLY       = 0,
 621         MCAST_DIRECT            = 1,
 622         MCAST_DEFAULT           = 2
 623 };
 624
 625
 626 struct mlx4_set_port_general_context {
 627         u8 reserved[3];
 628         u8 flags;
 629         u16 reserved2;
 630         __be16 mtu;
 631         u8 pptx;
 632         u8 pfctx;
 633         u16 reserved3;
 634         u8 pprx;
 635         u8 pfcrx;
 636         u16 reserved4;
 637 };
 638
 639 struct mlx4_set_port_rqp_calc_context {
 640         __be32 base_qpn;
 641         u8 rererved;
 642         u8 n_mac;
 643         u8 n_vlan;
 644         u8 n_prio;
 645         u8 reserved2[3];
 646         u8 mac_miss;
 647         u8 intra_no_vlan;
 648         u8 no_vlan;
 649         u8 intra_vlan_miss;
 650         u8 vlan_miss;
 651         u8 reserved3[3];
 652         u8 no_vlan_prio;
 653         __be32 promisc;
 654         __be32 mcast;
 655 };
 656
 657 struct mlx4_mac_entry {
 658         u64 mac;
 659         u64 reg_id;
 660 };
 661
 662 struct mlx4_port_info {
 663         struct mlx4_dev        *dev;
 664         int                     port;
 665         char                    dev_name[16];
 666         struct device_attribute port_attr;
 667         enum mlx4_port_type     tmp_type;
 668         char                    dev_mtu_name[16];
 669         struct device_attribute port_mtu_attr;
 670         struct mlx4_mac_table   mac_table;
 671         struct radix_tree_root  mac_tree;
 672         struct mlx4_vlan_table  vlan_table;
 673         int                     base_qpn;
 674 };
 675
 676 struct mlx4_sense {
 677         struct mlx4_dev         *dev;
 678         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 679         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 680         struct delayed_work     sense_poll;
 681 };
 682
 683 struct mlx4_msix_ctl {
 684         u64             pool_bm;
 685         struct mutex    pool_lock;
 686 };
 687
 688 struct mlx4_steer {
 689         struct list_head promisc_qps[MLX4_NUM_STEERS];
 690         struct list_head steer_entries[MLX4_NUM_STEERS];
 691 };
 692
 693 struct mlx4_net_trans_rule_hw_ctrl {
 694         __be32 ctrl;
 695         __be32 vf_vep_port;
 696         __be32 qpn;
 697         __be32 reserved;
 698 };
 699
 700 struct mlx4_net_trans_rule_hw_ib {
 701         u8 size;
 702         u8 rsvd1;
 703         __be16 id;
 704         u32 rsvd2;
 705         __be32 qpn;
 706         __be32 qpn_mask;
 707         u8 dst_gid[16];
 708         u8 dst_gid_msk[16];
 709 } __packed;
 710
 711 struct mlx4_net_trans_rule_hw_eth {
 712         u8      size;
 713         u8      rsvd;
 714         __be16  id;
 715         u8      rsvd1[6];
 716         u8      dst_mac[6];
 717         u16     rsvd2;
 718         u8      dst_mac_msk[6];
 719         u16     rsvd3;
 720         u8      src_mac[6];
 721         u16     rsvd4;
 722         u8      src_mac_msk[6];
 723         u8      rsvd5;
 724         u8      ether_type_enable;
 725         __be16  ether_type;
 726         __be16  vlan_id_msk;
 727         __be16  vlan_id;
 728 } __packed;
 729
 730 struct mlx4_net_trans_rule_hw_tcp_udp {
 731         u8      size;
 732         u8      rsvd;
 733         __be16  id;
 734         __be16  rsvd1[3];
 735         __be16  dst_port;
 736         __be16  rsvd2;
 737         __be16  dst_port_msk;
 738         __be16  rsvd3;
 739         __be16  src_port;
 740         __be16  rsvd4;
 741         __be16  src_port_msk;
 742 } __packed;
 743
 744 struct mlx4_net_trans_rule_hw_ipv4 {
 745         u8      size;
 746         u8      rsvd;
 747         __be16  id;
 748         __be32  rsvd1;
 749         __be32  dst_ip;
 750         __be32  dst_ip_msk;
 751         __be32  src_ip;
 752         __be32  src_ip_msk;
 753 } __packed;
 754
 755 struct _rule_hw {
 756         union {
 757                 struct {
 758                         u8 size;
 759                         u8 rsvd;
 760                         __be16 id;
 761                 };
 762                 struct mlx4_net_trans_rule_hw_eth eth;
 763                 struct mlx4_net_trans_rule_hw_ib ib;
 764                 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
 765                 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
 766         };
 767 };
 768
 769 struct mlx4_priv {
 770         struct mlx4_dev         dev;
 771
 772         struct list_head        dev_list;
 773         struct list_head        ctx_list;
 774         spinlock_t              ctx_lock;
 775
 776         struct list_head        pgdir_list;
 777         struct mutex            pgdir_mutex;
 778
 779         struct mlx4_fw          fw;
 780         struct mlx4_cmd         cmd;
 781         struct mlx4_mfunc       mfunc;
 782
 783         struct mlx4_bitmap      pd_bitmap;
 784         struct mlx4_bitmap      xrcd_bitmap;
 785         struct mlx4_uar_table   uar_table;
 786         struct mlx4_mr_table    mr_table;
 787         struct mlx4_cq_table    cq_table;
 788         struct mlx4_eq_table    eq_table;
 789         struct mlx4_srq_table   srq_table;
 790         struct mlx4_qp_table    qp_table;
 791         struct mlx4_mcg_table   mcg_table;
 792         struct mlx4_bitmap      counters_bitmap;
 793
 794         struct mlx4_catas_err   catas_err;
 795
 796         void __iomem           *clr_base;
 797
 798         struct mlx4_uar         driver_uar;
 799         void __iomem           *kar;
 800         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 801         struct mlx4_sense       sense;
 802         struct mutex            port_mutex;
 803         struct mlx4_msix_ctl    msix_ctl;
 804         struct mlx4_steer       *steer;
 805         struct list_head        bf_list;
 806         struct mutex            bf_mutex;
 807         struct io_mapping       *bf_mapping;
 808         int                     reserved_mtts;
 809         int                     fs_hash_mode;
 810 };
 811
 812 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 813 {
 814         return container_of(dev, struct mlx4_priv, dev);
 815 }
 816
 817 #define MLX4_SENSE_RANGE        (HZ * 3)
 818
 819 extern struct workqueue_struct *mlx4_wq;
 820
 821 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 822 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
 823 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
 824 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
 825 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 826 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 827                      u32 reserved_bot, u32 resetrved_top);
 828 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 829
 830 int mlx4_reset(struct mlx4_dev *dev);
 831
 832 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 833 void mlx4_free_eq_table(struct mlx4_dev *dev);
 834
 835 int mlx4_init_pd_table(struct mlx4_dev *dev);
 836 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 837 int mlx4_init_uar_table(struct mlx4_dev *dev);
 838 int mlx4_init_mr_table(struct mlx4_dev *dev);
 839 int mlx4_init_eq_table(struct mlx4_dev *dev);
 840 int mlx4_init_cq_table(struct mlx4_dev *dev);
 841 int mlx4_init_qp_table(struct mlx4_dev *dev);
 842 int mlx4_init_srq_table(struct mlx4_dev *dev);
 843 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 844
 845 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 846 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 847 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 848 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 849 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 850 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 851 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 852 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 853 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 854 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
 855 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 856 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 857 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 858 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 859 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 860 int __mlx4_mr_reserve(struct mlx4_dev *dev);
 861 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
 862 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
 863 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
 864 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 865 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 866
 867 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 868                            struct mlx4_vhcr *vhcr,
 869                            struct mlx4_cmd_mailbox *inbox,
 870                            struct mlx4_cmd_mailbox *outbox,
 871                            struct mlx4_cmd_info *cmd);
 872 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 873                            struct mlx4_vhcr *vhcr,
 874                            struct mlx4_cmd_mailbox *inbox,
 875                            struct mlx4_cmd_mailbox *outbox,
 876                            struct mlx4_cmd_info *cmd);
 877 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 878                            struct mlx4_vhcr *vhcr,
 879                            struct mlx4_cmd_mailbox *inbox,
 880                            struct mlx4_cmd_mailbox *outbox,
 881                            struct mlx4_cmd_info *cmd);
 882 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 883                            struct mlx4_vhcr *vhcr,
 884                            struct mlx4_cmd_mailbox *inbox,
 885                            struct mlx4_cmd_mailbox *outbox,
 886                            struct mlx4_cmd_info *cmd);
 887 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 888                            struct mlx4_vhcr *vhcr,
 889                            struct mlx4_cmd_mailbox *inbox,
 890                            struct mlx4_cmd_mailbox *outbox,
 891                            struct mlx4_cmd_info *cmd);
 892 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 893                           struct mlx4_vhcr *vhcr,
 894                           struct mlx4_cmd_mailbox *inbox,
 895                           struct mlx4_cmd_mailbox *outbox,
 896                           struct mlx4_cmd_info *cmd);
 897 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 898                      struct mlx4_vhcr *vhcr,
 899                      struct mlx4_cmd_mailbox *inbox,
 900                      struct mlx4_cmd_mailbox *outbox,
 901                      struct mlx4_cmd_info *cmd);
 902 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 903                             int *base);
 904 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 905 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 906 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 907 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
 908 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 909                      int start_index, int npages, u64 *page_list);
 910 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 911 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 912 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
 913 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
 914
 915 void mlx4_start_catas_poll(struct mlx4_dev *dev);
 916 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
 917 void mlx4_catas_init(void);
 918 int mlx4_restart_one(struct pci_dev *pdev);
 919 int mlx4_register_device(struct mlx4_dev *dev);
 920 void mlx4_unregister_device(struct mlx4_dev *dev);
 921 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
 922                          unsigned long param);
 923
 924 struct mlx4_dev_cap;
 925 struct mlx4_init_hca_param;
 926
 927 u64 mlx4_make_profile(struct mlx4_dev *dev,
 928                       struct mlx4_profile *request,
 929                       struct mlx4_dev_cap *dev_cap,
 930                       struct mlx4_init_hca_param *init_hca);
 931 void mlx4_master_comm_channel(struct work_struct *work);
 932 void mlx4_gen_slave_eqe(struct work_struct *work);
 933 void mlx4_master_handle_slave_flr(struct work_struct *work);
 934
 935 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
 936                            struct mlx4_vhcr *vhcr,
 937                            struct mlx4_cmd_mailbox *inbox,
 938                            struct mlx4_cmd_mailbox *outbox,
 939                            struct mlx4_cmd_info *cmd);
 940 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
 941                           struct mlx4_vhcr *vhcr,
 942                           struct mlx4_cmd_mailbox *inbox,
 943                           struct mlx4_cmd_mailbox *outbox,
 944                           struct mlx4_cmd_info *cmd);
 945 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 946                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
 947                         struct mlx4_cmd_mailbox *outbox,
 948                         struct mlx4_cmd_info *cmd);
 949 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
 950                           struct mlx4_vhcr *vhcr,
 951                           struct mlx4_cmd_mailbox *inbox,
 952                           struct mlx4_cmd_mailbox *outbox,
 953                           struct mlx4_cmd_info *cmd);
 954 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 955                             struct mlx4_vhcr *vhcr,
 956                             struct mlx4_cmd_mailbox *inbox,
 957                             struct mlx4_cmd_mailbox *outbox,
 958                           struct mlx4_cmd_info *cmd);
 959 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
 960                           struct mlx4_vhcr *vhcr,
 961                           struct mlx4_cmd_mailbox *inbox,
 962                           struct mlx4_cmd_mailbox *outbox,
 963                           struct mlx4_cmd_info *cmd);
 964 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 965                           struct mlx4_vhcr *vhcr,
 966                           struct mlx4_cmd_mailbox *inbox,
 967                           struct mlx4_cmd_mailbox *outbox,
 968                           struct mlx4_cmd_info *cmd);
 969 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 970                           struct mlx4_vhcr *vhcr,
 971                           struct mlx4_cmd_mailbox *inbox,
 972                           struct mlx4_cmd_mailbox *outbox,
 973                           struct mlx4_cmd_info *cmd);
 974 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 975                           struct mlx4_vhcr *vhcr,
 976                           struct mlx4_cmd_mailbox *inbox,
 977                           struct mlx4_cmd_mailbox *outbox,
 978                           struct mlx4_cmd_info *cmd);
 979 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 980                           struct mlx4_vhcr *vhcr,
 981                           struct mlx4_cmd_mailbox *inbox,
 982                           struct mlx4_cmd_mailbox *outbox,
 983                            struct mlx4_cmd_info *cmd);
 984 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 985                            struct mlx4_vhcr *vhcr,
 986                            struct mlx4_cmd_mailbox *inbox,
 987                            struct mlx4_cmd_mailbox *outbox,
 988                            struct mlx4_cmd_info *cmd);
 989 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 990                            struct mlx4_vhcr *vhcr,
 991                            struct mlx4_cmd_mailbox *inbox,
 992                            struct mlx4_cmd_mailbox *outbox,
 993                            struct mlx4_cmd_info *cmd);
 994 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 995                            struct mlx4_vhcr *vhcr,
 996                            struct mlx4_cmd_mailbox *inbox,
 997                            struct mlx4_cmd_mailbox *outbox,
 998                            struct mlx4_cmd_info *cmd);
 999 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1000                          struct mlx4_vhcr *vhcr,
1001                          struct mlx4_cmd_mailbox *inbox,
1002                          struct mlx4_cmd_mailbox *outbox,
1003                          struct mlx4_cmd_info *cmd);
1004 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1005                         struct mlx4_vhcr *vhcr,
1006                         struct mlx4_cmd_mailbox *inbox,
1007                         struct mlx4_cmd_mailbox *outbox,
1008                         struct mlx4_cmd_info *cmd);
1009 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1010                              struct mlx4_vhcr *vhcr,
1011                              struct mlx4_cmd_mailbox *inbox,
1012                              struct mlx4_cmd_mailbox *outbox,
1013                              struct mlx4_cmd_info *cmd);
1014 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1015                              struct mlx4_vhcr *vhcr,
1016                              struct mlx4_cmd_mailbox *inbox,
1017                              struct mlx4_cmd_mailbox *outbox,
1018                              struct mlx4_cmd_info *cmd);
1019 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1020                          struct mlx4_vhcr *vhcr,
1021                          struct mlx4_cmd_mailbox *inbox,
1022                          struct mlx4_cmd_mailbox *outbox,
1023                          struct mlx4_cmd_info *cmd);
1024
1025 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1026
1027 int mlx4_cmd_init(struct mlx4_dev *dev);
1028 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1029 int mlx4_multi_func_init(struct mlx4_dev *dev);
1030 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1031 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1032 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1033 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1034
1035 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1036                   unsigned long timeout);
1037
1038 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1039 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1040
1041 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1042
1043 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1044
1045 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1046
1047 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1048                     enum mlx4_port_type *type);
1049 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1050                          enum mlx4_port_type *stype,
1051                          enum mlx4_port_type *defaults);
1052 void mlx4_start_sense(struct mlx4_dev *dev);
1053 void mlx4_stop_sense(struct mlx4_dev *dev);
1054 void mlx4_sense_init(struct mlx4_dev *dev);
1055 int mlx4_check_port_params(struct mlx4_dev *dev,
1056                            enum mlx4_port_type *port_type);
1057 int mlx4_change_port_types(struct mlx4_dev *dev,
1058                            enum mlx4_port_type *port_types);
1059
1060 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1061 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1062
1063 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1064 /* resource tracker functions*/
1065 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1066                                     enum mlx4_resource resource_type,
1067                                     u64 resource_id, int *slave);
1068 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1069 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1070
1071 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1072                                 enum mlx4_res_tracker_free_type type);
1073
1074 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1075                           struct mlx4_vhcr *vhcr,
1076                           struct mlx4_cmd_mailbox *inbox,
1077                           struct mlx4_cmd_mailbox *outbox,
1078                           struct mlx4_cmd_info *cmd);
1079 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1080                           struct mlx4_vhcr *vhcr,
1081                           struct mlx4_cmd_mailbox *inbox,
1082                           struct mlx4_cmd_mailbox *outbox,
1083                           struct mlx4_cmd_info *cmd);
1084 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1085                            struct mlx4_vhcr *vhcr,
1086                            struct mlx4_cmd_mailbox *inbox,
1087                            struct mlx4_cmd_mailbox *outbox,
1088                            struct mlx4_cmd_info *cmd);
1089 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1090                             struct mlx4_vhcr *vhcr,
1091                             struct mlx4_cmd_mailbox *inbox,
1092                             struct mlx4_cmd_mailbox *outbox,
1093                             struct mlx4_cmd_info *cmd);
1094 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1095                                struct mlx4_vhcr *vhcr,
1096                                struct mlx4_cmd_mailbox *inbox,
1097                                struct mlx4_cmd_mailbox *outbox,
1098                                struct mlx4_cmd_info *cmd);
1099 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1100                             struct mlx4_vhcr *vhcr,
1101                             struct mlx4_cmd_mailbox *inbox,
1102                             struct mlx4_cmd_mailbox *outbox,
1103                             struct mlx4_cmd_info *cmd);
1104 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1105
1106 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1107                                     int *gid_tbl_len, int *pkey_tbl_len);
1108
1109 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1110                            struct mlx4_vhcr *vhcr,
1111                            struct mlx4_cmd_mailbox *inbox,
1112                            struct mlx4_cmd_mailbox *outbox,
1113                            struct mlx4_cmd_info *cmd);
1114
1115 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1116                          struct mlx4_vhcr *vhcr,
1117                          struct mlx4_cmd_mailbox *inbox,
1118                          struct mlx4_cmd_mailbox *outbox,
1119                          struct mlx4_cmd_info *cmd);
1120 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1121                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1122 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1123                           int block_mcast_loopback, enum mlx4_protocol prot,
1124                           enum mlx4_steer_type steer);
1125 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1126                                 struct mlx4_vhcr *vhcr,
1127                                 struct mlx4_cmd_mailbox *inbox,
1128                                 struct mlx4_cmd_mailbox *outbox,
1129                                 struct mlx4_cmd_info *cmd);
1130 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1131                                struct mlx4_vhcr *vhcr,
1132                                struct mlx4_cmd_mailbox *inbox,
1133                                struct mlx4_cmd_mailbox *outbox,
1134                                struct mlx4_cmd_info *cmd);
1135 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1136                                      int port, void *buf);
1137 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1138                                 struct mlx4_cmd_mailbox *outbox);
1139 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1140                                    struct mlx4_vhcr *vhcr,
1141                                    struct mlx4_cmd_mailbox *inbox,
1142                                    struct mlx4_cmd_mailbox *outbox,
1143                                 struct mlx4_cmd_info *cmd);
1144 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1145                             struct mlx4_vhcr *vhcr,
1146                             struct mlx4_cmd_mailbox *inbox,
1147                             struct mlx4_cmd_mailbox *outbox,
1148                             struct mlx4_cmd_info *cmd);
1149 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1150                                struct mlx4_vhcr *vhcr,
1151                                struct mlx4_cmd_mailbox *inbox,
1152                                struct mlx4_cmd_mailbox *outbox,
1153                                struct mlx4_cmd_info *cmd);
1154 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1155                                          struct mlx4_vhcr *vhcr,
1156                                          struct mlx4_cmd_mailbox *inbox,
1157                                          struct mlx4_cmd_mailbox *outbox,
1158                                          struct mlx4_cmd_info *cmd);
1159 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1160                                          struct mlx4_vhcr *vhcr,
1161                                          struct mlx4_cmd_mailbox *inbox,
1162                                          struct mlx4_cmd_mailbox *outbox,
1163                                          struct mlx4_cmd_info *cmd);
1164
1165 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1166 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1167
1168 static inline void set_param_l(u64 *arg, u32 val)
1169 {
1170         *((u32 *)arg) = val;
1171 }
1172
1173 static inline void set_param_h(u64 *arg, u32 val)
1174 {
1175         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1176 }
1177
1178 static inline u32 get_param_l(u64 *arg)
1179 {
1180         return (u32) (*arg & 0xffffffff);
1181 }
1182
1183 static inline u32 get_param_h(u64 *arg)
1184 {
1185         return (u32)(*arg >> 32);
1186 }
1187
1188 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1189 {
1190         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1191 }
1192
1193 #define NOT_MASKED_PD_BITS 17
1194
1195 #endif /* MLX4_H */