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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / ethernet / realtek / 8139too.c
blob1d83565cc6af6dca0e61360c1c60394e1fb5682d
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/rtnetlink.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/completion.h>
111 #include <linux/crc32.h>
112 #include <linux/io.h>
113 #include <linux/uaccess.h>
114 #include <linux/gfp.h>
115 #include <asm/irq.h>
116
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* define to 1, 2 or 3 to enable copious debugging info */
126 #define RTL8139_DEBUG 0
127
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
130
131
132 #ifdef RTL8139_NDEBUG
133 # define assert(expr) do {} while (0)
134 #else
135 # define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
139 }
140 #endif
141
142
143 /* A few user-configurable values. */
144 /* media options */
145 #define MAX_UNITS 8
146 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
148
149 /* Whether to use MMIO or PIO. Default to MMIO. */
150 #ifdef CONFIG_8139TOO_PIO
151 static bool use_io = true;
152 #else
153 static bool use_io = false;
154 #endif
155
156 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
158 static int multicast_filter_limit = 32;
159
160 /* bitmapped message enable number */
161 static int debug = -1;
162
163 /*
164 * Receive ring size
165 * Warning: 64K ring has hardware issues and may lock up.
166 */
167 #if defined(CONFIG_SH_DREAMCAST)
168 #define RX_BUF_IDX 0 /* 8K ring */
169 #else
170 #define RX_BUF_IDX 2 /* 32K ring */
171 #endif
172 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
173 #define RX_BUF_PAD 16
174 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
175
176 #if RX_BUF_LEN == 65536
177 #define RX_BUF_TOT_LEN RX_BUF_LEN
178 #else
179 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
180 #endif
181
182 /* Number of Tx descriptor registers. */
183 #define NUM_TX_DESC 4
184
185 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
186 #define MAX_ETH_FRAME_SIZE 1536
187
188 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
189 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
190 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
191
192 /* PCI Tuning Parameters
193 Threshold is bytes transferred to chip before transmission starts. */
194 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
195
196 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
197 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
198 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
200 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
201
202 /* Operational parameters that usually are not changed. */
203 /* Time in jiffies before concluding the transmitter is hung. */
204 #define TX_TIMEOUT (6*HZ)
205
206
207 enum {
208 HAS_MII_XCVR = 0x010000,
209 HAS_CHIP_XCVR = 0x020000,
210 HAS_LNK_CHNG = 0x040000,
211 };
212
213 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
214 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
215 #define RTL_MIN_IO_SIZE 0x80
216 #define RTL8139B_IO_SIZE 256
217
218 #define RTL8129_CAPS HAS_MII_XCVR
219 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
220
221 typedef enum {
222 RTL8139 = 0,
223 RTL8129,
224 } board_t;
225
226
227 /* indexed by board_t, above */
228 static const struct {
229 const char *name;
230 u32 hw_flags;
231 } board_info[] __devinitdata = {
232 { "RealTek RTL8139", RTL8139_CAPS },
233 { "RealTek RTL8129", RTL8129_CAPS },
234 };
235
236
237 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257
258 #ifdef CONFIG_SH_SECUREEDGE5410
259 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 #endif
262 #ifdef CONFIG_8139TOO_8129
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
264 #endif
265
266 /* some crazy cards report invalid vendor ids like
267 * 0x0001 here. The other ids are valid and constant,
268 * so we simply don't match on the main vendor id.
269 */
270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
273
274 {0,}
275 };
276 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
277
278 static struct {
279 const char str[ETH_GSTRING_LEN];
280 } ethtool_stats_keys[] = {
281 { "early_rx" },
282 { "tx_buf_mapped" },
283 { "tx_timeouts" },
284 { "rx_lost_in_ring" },
285 };
286
287 /* The rest of these values should never change. */
288
289 /* Symbolic offsets to registers. */
290 enum RTL8139_registers {
291 MAC0 = 0, /* Ethernet hardware address. */
292 MAR0 = 8, /* Multicast filter. */
293 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
294 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
295 RxBuf = 0x30,
296 ChipCmd = 0x37,
297 RxBufPtr = 0x38,
298 RxBufAddr = 0x3A,
299 IntrMask = 0x3C,
300 IntrStatus = 0x3E,
301 TxConfig = 0x40,
302 RxConfig = 0x44,
303 Timer = 0x48, /* A general-purpose counter. */
304 RxMissed = 0x4C, /* 24 bits valid, write clears. */
305 Cfg9346 = 0x50,
306 Config0 = 0x51,
307 Config1 = 0x52,
308 TimerInt = 0x54,
309 MediaStatus = 0x58,
310 Config3 = 0x59,
311 Config4 = 0x5A, /* absent on RTL-8139A */
312 HltClk = 0x5B,
313 MultiIntr = 0x5C,
314 TxSummary = 0x60,
315 BasicModeCtrl = 0x62,
316 BasicModeStatus = 0x64,
317 NWayAdvert = 0x66,
318 NWayLPAR = 0x68,
319 NWayExpansion = 0x6A,
320 /* Undocumented registers, but required for proper operation. */
321 FIFOTMS = 0x70, /* FIFO Control and test. */
322 CSCR = 0x74, /* Chip Status and Configuration Register. */
323 PARA78 = 0x78,
324 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
325 PARA7c = 0x7c, /* Magic transceiver parameter register. */
326 Config5 = 0xD8, /* absent on RTL-8139A */
327 };
328
329 enum ClearBitMasks {
330 MultiIntrClear = 0xF000,
331 ChipCmdClear = 0xE2,
332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
333 };
334
335 enum ChipCmdBits {
336 CmdReset = 0x10,
337 CmdRxEnb = 0x08,
338 CmdTxEnb = 0x04,
339 RxBufEmpty = 0x01,
340 };
341
342 /* Interrupt register bits, using my own meaningful names. */
343 enum IntrStatusBits {
344 PCIErr = 0x8000,
345 PCSTimeout = 0x4000,
346 RxFIFOOver = 0x40,
347 RxUnderrun = 0x20,
348 RxOverflow = 0x10,
349 TxErr = 0x08,
350 TxOK = 0x04,
351 RxErr = 0x02,
352 RxOK = 0x01,
353
354 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
355 };
356
357 enum TxStatusBits {
358 TxHostOwns = 0x2000,
359 TxUnderrun = 0x4000,
360 TxStatOK = 0x8000,
361 TxOutOfWindow = 0x20000000,
362 TxAborted = 0x40000000,
363 TxCarrierLost = 0x80000000,
364 };
365 enum RxStatusBits {
366 RxMulticast = 0x8000,
367 RxPhysical = 0x4000,
368 RxBroadcast = 0x2000,
369 RxBadSymbol = 0x0020,
370 RxRunt = 0x0010,
371 RxTooLong = 0x0008,
372 RxCRCErr = 0x0004,
373 RxBadAlign = 0x0002,
374 RxStatusOK = 0x0001,
375 };
376
377 /* Bits in RxConfig. */
378 enum rx_mode_bits {
379 AcceptErr = 0x20,
380 AcceptRunt = 0x10,
381 AcceptBroadcast = 0x08,
382 AcceptMulticast = 0x04,
383 AcceptMyPhys = 0x02,
384 AcceptAllPhys = 0x01,
385 };
386
387 /* Bits in TxConfig. */
388 enum tx_config_bits {
389 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
390 TxIFGShift = 24,
391 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
392 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
393 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
394 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
395
396 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
397 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
398 TxClearAbt = (1 << 0), /* Clear abort (WO) */
399 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
400 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
401
402 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
403 };
404
405 /* Bits in Config1 */
406 enum Config1Bits {
407 Cfg1_PM_Enable = 0x01,
408 Cfg1_VPD_Enable = 0x02,
409 Cfg1_PIO = 0x04,
410 Cfg1_MMIO = 0x08,
411 LWAKE = 0x10, /* not on 8139, 8139A */
412 Cfg1_Driver_Load = 0x20,
413 Cfg1_LED0 = 0x40,
414 Cfg1_LED1 = 0x80,
415 SLEEP = (1 << 1), /* only on 8139, 8139A */
416 PWRDN = (1 << 0), /* only on 8139, 8139A */
417 };
418
419 /* Bits in Config3 */
420 enum Config3Bits {
421 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
422 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
423 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
424 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
425 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
426 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
427 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
428 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
429 };
430
431 /* Bits in Config4 */
432 enum Config4Bits {
433 LWPTN = (1 << 2), /* not on 8139, 8139A */
434 };
435
436 /* Bits in Config5 */
437 enum Config5Bits {
438 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
439 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
440 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
441 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
442 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
443 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
444 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
445 };
446
447 enum RxConfigBits {
448 /* rx fifo threshold */
449 RxCfgFIFOShift = 13,
450 RxCfgFIFONone = (7 << RxCfgFIFOShift),
451
452 /* Max DMA burst */
453 RxCfgDMAShift = 8,
454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
455
456 /* rx ring buffer length */
457 RxCfgRcv8K = 0,
458 RxCfgRcv16K = (1 << 11),
459 RxCfgRcv32K = (1 << 12),
460 RxCfgRcv64K = (1 << 11) | (1 << 12),
461
462 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
463 RxNoWrap = (1 << 7),
464 };
465
466 /* Twister tuning parameters from RealTek.
467 Completely undocumented, but required to tune bad links on some boards. */
468 enum CSCRBits {
469 CSCR_LinkOKBit = 0x0400,
470 CSCR_LinkChangeBit = 0x0800,
471 CSCR_LinkStatusBits = 0x0f000,
472 CSCR_LinkDownOffCmd = 0x003c0,
473 CSCR_LinkDownCmd = 0x0f3c0,
474 };
475
476 enum Cfg9346Bits {
477 Cfg9346_Lock = 0x00,
478 Cfg9346_Unlock = 0xC0,
479 };
480
481 typedef enum {
482 CH_8139 = 0,
483 CH_8139_K,
484 CH_8139A,
485 CH_8139A_G,
486 CH_8139B,
487 CH_8130,
488 CH_8139C,
489 CH_8100,
490 CH_8100B_8139D,
491 CH_8101,
492 } chip_t;
493
494 enum chip_flags {
495 HasHltClk = (1 << 0),
496 HasLWake = (1 << 1),
497 };
498
499 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
501 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
502
503 /* directly indexed by chip_t, above */
504 static const struct {
505 const char *name;
506 u32 version; /* from RTL8139C/RTL8139D docs */
507 u32 flags;
508 } rtl_chip_info[] = {
509 { "RTL-8139",
510 HW_REVID(1, 0, 0, 0, 0, 0, 0),
511 HasHltClk,
512 },
513
514 { "RTL-8139 rev K",
515 HW_REVID(1, 1, 0, 0, 0, 0, 0),
516 HasHltClk,
517 },
518
519 { "RTL-8139A",
520 HW_REVID(1, 1, 1, 0, 0, 0, 0),
521 HasHltClk, /* XXX undocumented? */
522 },
523
524 { "RTL-8139A rev G",
525 HW_REVID(1, 1, 1, 0, 0, 1, 0),
526 HasHltClk, /* XXX undocumented? */
527 },
528
529 { "RTL-8139B",
530 HW_REVID(1, 1, 1, 1, 0, 0, 0),
531 HasLWake,
532 },
533
534 { "RTL-8130",
535 HW_REVID(1, 1, 1, 1, 1, 0, 0),
536 HasLWake,
537 },
538
539 { "RTL-8139C",
540 HW_REVID(1, 1, 1, 0, 1, 0, 0),
541 HasLWake,
542 },
543
544 { "RTL-8100",
545 HW_REVID(1, 1, 1, 1, 0, 1, 0),
546 HasLWake,
547 },
548
549 { "RTL-8100B/8139D",
550 HW_REVID(1, 1, 1, 0, 1, 0, 1),
551 HasHltClk /* XXX undocumented? */
552 | HasLWake,
553 },
554
555 { "RTL-8101",
556 HW_REVID(1, 1, 1, 0, 1, 1, 1),
557 HasLWake,
558 },
559 };
560
561 struct rtl_extra_stats {
562 unsigned long early_rx;
563 unsigned long tx_buf_mapped;
564 unsigned long tx_timeouts;
565 unsigned long rx_lost_in_ring;
566 };
567
568 struct rtl8139_stats {
569 u64 packets;
570 u64 bytes;
571 struct u64_stats_sync syncp;
572 };
573
574 struct rtl8139_private {
575 void __iomem *mmio_addr;
576 int drv_flags;
577 struct pci_dev *pci_dev;
578 u32 msg_enable;
579 struct napi_struct napi;
580 struct net_device *dev;
581
582 unsigned char *rx_ring;
583 unsigned int cur_rx; /* RX buf index of next pkt */
584 struct rtl8139_stats rx_stats;
585 dma_addr_t rx_ring_dma;
586
587 unsigned int tx_flag;
588 unsigned long cur_tx;
589 unsigned long dirty_tx;
590 struct rtl8139_stats tx_stats;
591 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
592 unsigned char *tx_bufs; /* Tx bounce buffer region. */
593 dma_addr_t tx_bufs_dma;
594
595 signed char phys[4]; /* MII device addresses. */
596
597 /* Twister tune state. */
598 char twistie, twist_row, twist_col;
599
600 unsigned int watchdog_fired : 1;
601 unsigned int default_port : 4; /* Last dev->if_port value. */
602 unsigned int have_thread : 1;
603
604 spinlock_t lock;
605 spinlock_t rx_lock;
606
607 chip_t chipset;
608 u32 rx_config;
609 struct rtl_extra_stats xstats;
610
611 struct delayed_work thread;
612
613 struct mii_if_info mii;
614 unsigned int regs_len;
615 unsigned long fifo_copy_timeout;
616 };
617
618 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
619 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
620 MODULE_LICENSE("GPL");
621 MODULE_VERSION(DRV_VERSION);
622
623 module_param(use_io, bool, 0);
624 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
625 module_param(multicast_filter_limit, int, 0);
626 module_param_array(media, int, NULL, 0);
627 module_param_array(full_duplex, int, NULL, 0);
628 module_param(debug, int, 0);
629 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
630 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
631 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
632 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
633
634 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
635 static int rtl8139_open (struct net_device *dev);
636 static int mdio_read (struct net_device *dev, int phy_id, int location);
637 static void mdio_write (struct net_device *dev, int phy_id, int location,
638 int val);
639 static void rtl8139_start_thread(struct rtl8139_private *tp);
640 static void rtl8139_tx_timeout (struct net_device *dev);
641 static void rtl8139_init_ring (struct net_device *dev);
642 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
643 struct net_device *dev);
644 #ifdef CONFIG_NET_POLL_CONTROLLER
645 static void rtl8139_poll_controller(struct net_device *dev);
646 #endif
647 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
648 static int rtl8139_poll(struct napi_struct *napi, int budget);
649 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
650 static int rtl8139_close (struct net_device *dev);
651 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
652 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
653 struct rtnl_link_stats64
654 *stats);
655 static void rtl8139_set_rx_mode (struct net_device *dev);
656 static void __set_rx_mode (struct net_device *dev);
657 static void rtl8139_hw_start (struct net_device *dev);
658 static void rtl8139_thread (struct work_struct *work);
659 static void rtl8139_tx_timeout_task(struct work_struct *work);
660 static const struct ethtool_ops rtl8139_ethtool_ops;
661
662 /* write MMIO register, with flush */
663 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
664 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
665 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
666 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
667
668 /* write MMIO register */
669 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
670 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
671 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
672
673 /* read MMIO register */
674 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
675 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
676 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
677
678
679 static const u16 rtl8139_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
681 TxErr | TxOK | RxErr | RxOK;
682
683 static const u16 rtl8139_norx_intr_mask =
684 PCIErr | PCSTimeout | RxUnderrun |
685 TxErr | TxOK | RxErr ;
686
687 #if RX_BUF_IDX == 0
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv8K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 1
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv16K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #elif RX_BUF_IDX == 2
698 static const unsigned int rtl8139_rx_config =
699 RxCfgRcv32K | RxNoWrap |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702 #elif RX_BUF_IDX == 3
703 static const unsigned int rtl8139_rx_config =
704 RxCfgRcv64K |
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
707 #else
708 #error "Invalid configuration for 8139_RXBUF_IDX"
709 #endif
710
711 static const unsigned int rtl8139_tx_config =
712 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
713
714 static void __rtl8139_cleanup_dev (struct net_device *dev)
715 {
716 struct rtl8139_private *tp = netdev_priv(dev);
717 struct pci_dev *pdev;
718
719 assert (dev != NULL);
720 assert (tp->pci_dev != NULL);
721 pdev = tp->pci_dev;
722
723 if (tp->mmio_addr)
724 pci_iounmap (pdev, tp->mmio_addr);
725
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
728
729 free_netdev(dev);
730 pci_set_drvdata (pdev, NULL);
731 }
732
733
734 static void rtl8139_chip_reset (void __iomem *ioaddr)
735 {
736 int i;
737
738 /* Soft reset the chip. */
739 RTL_W8 (ChipCmd, CmdReset);
740
741 /* Check that the chip has finished the reset. */
742 for (i = 1000; i > 0; i--) {
743 barrier();
744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
745 break;
746 udelay (10);
747 }
748 }
749
750
751 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
752 {
753 struct device *d = &pdev->dev;
754 void __iomem *ioaddr;
755 struct net_device *dev;
756 struct rtl8139_private *tp;
757 u8 tmp8;
758 int rc, disable_dev_on_err = 0;
759 unsigned int i, bar;
760 unsigned long io_len;
761 u32 version;
762 static const struct {
763 unsigned long mask;
764 char *type;
765 } res[] = {
766 { IORESOURCE_IO, "PIO" },
767 { IORESOURCE_MEM, "MMIO" }
768 };
769
770 assert (pdev != NULL);
771
772 /* dev and priv zeroed in alloc_etherdev */
773 dev = alloc_etherdev (sizeof (*tp));
774 if (dev == NULL)
775 return ERR_PTR(-ENOMEM);
776
777 SET_NETDEV_DEV(dev, &pdev->dev);
778
779 tp = netdev_priv(dev);
780 tp->pci_dev = pdev;
781
782 /* enable device (incl. PCI PM wakeup and hotplug setup) */
783 rc = pci_enable_device (pdev);
784 if (rc)
785 goto err_out;
786
787 rc = pci_request_regions (pdev, DRV_NAME);
788 if (rc)
789 goto err_out;
790 disable_dev_on_err = 1;
791
792 pci_set_master (pdev);
793
794 retry:
795 /* PIO bar register comes first. */
796 bar = !use_io;
797
798 io_len = pci_resource_len(pdev, bar);
799
800 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
801
802 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
803 dev_err(d, "region #%d not a %s resource, aborting\n", bar,
804 res[bar].type);
805 rc = -ENODEV;
806 goto err_out;
807 }
808 if (io_len < RTL_MIN_IO_SIZE) {
809 dev_err(d, "Invalid PCI %s region size(s), aborting\n",
810 res[bar].type);
811 rc = -ENODEV;
812 goto err_out;
813 }
814
815 ioaddr = pci_iomap(pdev, bar, 0);
816 if (!ioaddr) {
817 dev_err(d, "cannot map %s\n", res[bar].type);
818 if (!use_io) {
819 use_io = true;
820 goto retry;
821 }
822 rc = -ENODEV;
823 goto err_out;
824 }
825 tp->regs_len = io_len;
826 tp->mmio_addr = ioaddr;
827
828 /* Bring old chips out of low-power mode. */
829 RTL_W8 (HltClk, 'R');
830
831 /* check for missing/broken hardware */
832 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
833 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
834 rc = -EIO;
835 goto err_out;
836 }
837
838 /* identify chip attached to board */
839 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
840 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
841 if (version == rtl_chip_info[i].version) {
842 tp->chipset = i;
843 goto match;
844 }
845
846 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
847 i = 0;
848 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
849 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
850 tp->chipset = 0;
851
852 match:
853 pr_debug("chipset id (%d) == index %d, '%s'\n",
854 version, i, rtl_chip_info[i].name);
855
856 if (tp->chipset >= CH_8139B) {
857 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
858 pr_debug("PCI PM wakeup\n");
859 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
860 (tmp8 & LWAKE))
861 new_tmp8 &= ~LWAKE;
862 new_tmp8 |= Cfg1_PM_Enable;
863 if (new_tmp8 != tmp8) {
864 RTL_W8 (Cfg9346, Cfg9346_Unlock);
865 RTL_W8 (Config1, tmp8);
866 RTL_W8 (Cfg9346, Cfg9346_Lock);
867 }
868 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
869 tmp8 = RTL_R8 (Config4);
870 if (tmp8 & LWPTN) {
871 RTL_W8 (Cfg9346, Cfg9346_Unlock);
872 RTL_W8 (Config4, tmp8 & ~LWPTN);
873 RTL_W8 (Cfg9346, Cfg9346_Lock);
874 }
875 }
876 } else {
877 pr_debug("Old chip wakeup\n");
878 tmp8 = RTL_R8 (Config1);
879 tmp8 &= ~(SLEEP | PWRDN);
880 RTL_W8 (Config1, tmp8);
881 }
882
883 rtl8139_chip_reset (ioaddr);
884
885 return dev;
886
887 err_out:
888 __rtl8139_cleanup_dev (dev);
889 if (disable_dev_on_err)
890 pci_disable_device (pdev);
891 return ERR_PTR(rc);
892 }
893
894 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
895 {
896 struct rtl8139_private *tp = netdev_priv(dev);
897 unsigned long flags;
898 netdev_features_t changed = features ^ dev->features;
899 void __iomem *ioaddr = tp->mmio_addr;
900
901 if (!(changed & (NETIF_F_RXALL)))
902 return 0;
903
904 spin_lock_irqsave(&tp->lock, flags);
905
906 if (changed & NETIF_F_RXALL) {
907 int rx_mode = tp->rx_config;
908 if (features & NETIF_F_RXALL)
909 rx_mode |= (AcceptErr | AcceptRunt);
910 else
911 rx_mode &= ~(AcceptErr | AcceptRunt);
912 tp->rx_config = rtl8139_rx_config | rx_mode;
913 RTL_W32_F(RxConfig, tp->rx_config);
914 }
915
916 spin_unlock_irqrestore(&tp->lock, flags);
917
918 return 0;
919 }
920
921 static const struct net_device_ops rtl8139_netdev_ops = {
922 .ndo_open = rtl8139_open,
923 .ndo_stop = rtl8139_close,
924 .ndo_get_stats64 = rtl8139_get_stats64,
925 .ndo_change_mtu = eth_change_mtu,
926 .ndo_validate_addr = eth_validate_addr,
927 .ndo_set_mac_address = rtl8139_set_mac_address,
928 .ndo_start_xmit = rtl8139_start_xmit,
929 .ndo_set_rx_mode = rtl8139_set_rx_mode,
930 .ndo_do_ioctl = netdev_ioctl,
931 .ndo_tx_timeout = rtl8139_tx_timeout,
932 #ifdef CONFIG_NET_POLL_CONTROLLER
933 .ndo_poll_controller = rtl8139_poll_controller,
934 #endif
935 .ndo_set_features = rtl8139_set_features,
936 };
937
938 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
939 const struct pci_device_id *ent)
940 {
941 struct net_device *dev = NULL;
942 struct rtl8139_private *tp;
943 int i, addr_len, option;
944 void __iomem *ioaddr;
945 static int board_idx = -1;
946
947 assert (pdev != NULL);
948 assert (ent != NULL);
949
950 board_idx++;
951
952 /* when we're built into the kernel, the driver version message
953 * is only printed if at least one 8139 board has been found
954 */
955 #ifndef MODULE
956 {
957 static int printed_version;
958 if (!printed_version++)
959 pr_info(RTL8139_DRIVER_NAME "\n");
960 }
961 #endif
962
963 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
964 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
965 dev_info(&pdev->dev,
966 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
967 pdev->vendor, pdev->device, pdev->revision);
968 return -ENODEV;
969 }
970
971 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
972 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
973 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
974 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
975 pr_info("OQO Model 2 detected. Forcing PIO\n");
976 use_io = 1;
977 }
978
979 dev = rtl8139_init_board (pdev);
980 if (IS_ERR(dev))
981 return PTR_ERR(dev);
982
983 assert (dev != NULL);
984 tp = netdev_priv(dev);
985 tp->dev = dev;
986
987 ioaddr = tp->mmio_addr;
988 assert (ioaddr != NULL);
989
990 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
991 for (i = 0; i < 3; i++)
992 ((__le16 *) (dev->dev_addr))[i] =
993 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
994 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
995
996 /* The Rtl8139-specific entries in the device structure. */
997 dev->netdev_ops = &rtl8139_netdev_ops;
998 dev->ethtool_ops = &rtl8139_ethtool_ops;
999 dev->watchdog_timeo = TX_TIMEOUT;
1000 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1001
1002 /* note: the hardware is not capable of sg/csum/highdma, however
1003 * through the use of skb_copy_and_csum_dev we enable these
1004 * features
1005 */
1006 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1007 dev->vlan_features = dev->features;
1008
1009 dev->hw_features |= NETIF_F_RXALL;
1010 dev->hw_features |= NETIF_F_RXFCS;
1011
1012 /* tp zeroed and aligned in alloc_etherdev */
1013 tp = netdev_priv(dev);
1014
1015 /* note: tp->chipset set in rtl8139_init_board */
1016 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1017 tp->mmio_addr = ioaddr;
1018 tp->msg_enable =
1019 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1020 spin_lock_init (&tp->lock);
1021 spin_lock_init (&tp->rx_lock);
1022 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1023 tp->mii.dev = dev;
1024 tp->mii.mdio_read = mdio_read;
1025 tp->mii.mdio_write = mdio_write;
1026 tp->mii.phy_id_mask = 0x3f;
1027 tp->mii.reg_num_mask = 0x1f;
1028
1029 /* dev is fully set up and ready to use now */
1030 pr_debug("about to register device named %s (%p)...\n",
1031 dev->name, dev);
1032 i = register_netdev (dev);
1033 if (i) goto err_out;
1034
1035 pci_set_drvdata (pdev, dev);
1036
1037 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1038 board_info[ent->driver_data].name,
1039 ioaddr, dev->dev_addr, pdev->irq);
1040
1041 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1042 rtl_chip_info[tp->chipset].name);
1043
1044 /* Find the connected MII xcvrs.
1045 Doing this in open() would allow detecting external xcvrs later, but
1046 takes too much time. */
1047 #ifdef CONFIG_8139TOO_8129
1048 if (tp->drv_flags & HAS_MII_XCVR) {
1049 int phy, phy_idx = 0;
1050 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1051 int mii_status = mdio_read(dev, phy, 1);
1052 if (mii_status != 0xffff && mii_status != 0x0000) {
1053 u16 advertising = mdio_read(dev, phy, 4);
1054 tp->phys[phy_idx++] = phy;
1055 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1056 phy, mii_status, advertising);
1057 }
1058 }
1059 if (phy_idx == 0) {
1060 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1061 tp->phys[0] = 32;
1062 }
1063 } else
1064 #endif
1065 tp->phys[0] = 32;
1066 tp->mii.phy_id = tp->phys[0];
1067
1068 /* The lower four bits are the media type. */
1069 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1070 if (option > 0) {
1071 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1072 tp->default_port = option & 0xFF;
1073 if (tp->default_port)
1074 tp->mii.force_media = 1;
1075 }
1076 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1077 tp->mii.full_duplex = full_duplex[board_idx];
1078 if (tp->mii.full_duplex) {
1079 netdev_info(dev, "Media type forced to Full Duplex\n");
1080 /* Changing the MII-advertised media because might prevent
1081 re-connection. */
1082 tp->mii.force_media = 1;
1083 }
1084 if (tp->default_port) {
1085 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1086 (option & 0x20 ? 100 : 10),
1087 (option & 0x10 ? "full" : "half"));
1088 mdio_write(dev, tp->phys[0], 0,
1089 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1090 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1091 }
1092
1093 /* Put the chip into low-power mode. */
1094 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1095 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1096
1097 return 0;
1098
1099 err_out:
1100 __rtl8139_cleanup_dev (dev);
1101 pci_disable_device (pdev);
1102 return i;
1103 }
1104
1105
1106 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1107 {
1108 struct net_device *dev = pci_get_drvdata (pdev);
1109 struct rtl8139_private *tp = netdev_priv(dev);
1110
1111 assert (dev != NULL);
1112
1113 cancel_delayed_work_sync(&tp->thread);
1114
1115 unregister_netdev (dev);
1116
1117 __rtl8139_cleanup_dev (dev);
1118 pci_disable_device (pdev);
1119 }
1120
1121
1122 /* Serial EEPROM section. */
1123
1124 /* EEPROM_Ctrl bits. */
1125 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1126 #define EE_CS 0x08 /* EEPROM chip select. */
1127 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1128 #define EE_WRITE_0 0x00
1129 #define EE_WRITE_1 0x02
1130 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1131 #define EE_ENB (0x80 | EE_CS)
1132
1133 /* Delay between EEPROM clock transitions.
1134 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1135 */
1136
1137 #define eeprom_delay() (void)RTL_R8(Cfg9346)
1138
1139 /* The EEPROM commands include the alway-set leading bit. */
1140 #define EE_WRITE_CMD (5)
1141 #define EE_READ_CMD (6)
1142 #define EE_ERASE_CMD (7)
1143
1144 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1145 {
1146 int i;
1147 unsigned retval = 0;
1148 int read_cmd = location | (EE_READ_CMD << addr_len);
1149
1150 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1151 RTL_W8 (Cfg9346, EE_ENB);
1152 eeprom_delay ();
1153
1154 /* Shift the read command bits out. */
1155 for (i = 4 + addr_len; i >= 0; i--) {
1156 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1157 RTL_W8 (Cfg9346, EE_ENB | dataval);
1158 eeprom_delay ();
1159 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1160 eeprom_delay ();
1161 }
1162 RTL_W8 (Cfg9346, EE_ENB);
1163 eeprom_delay ();
1164
1165 for (i = 16; i > 0; i--) {
1166 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1167 eeprom_delay ();
1168 retval =
1169 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1170 0);
1171 RTL_W8 (Cfg9346, EE_ENB);
1172 eeprom_delay ();
1173 }
1174
1175 /* Terminate the EEPROM access. */
1176 RTL_W8(Cfg9346, 0);
1177 eeprom_delay ();
1178
1179 return retval;
1180 }
1181
1182 /* MII serial management: mostly bogus for now. */
1183 /* Read and write the MII management registers using software-generated
1184 serial MDIO protocol.
1185 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1186 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1187 "overclocking" issues. */
1188 #define MDIO_DIR 0x80
1189 #define MDIO_DATA_OUT 0x04
1190 #define MDIO_DATA_IN 0x02
1191 #define MDIO_CLK 0x01
1192 #define MDIO_WRITE0 (MDIO_DIR)
1193 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1194
1195 #define mdio_delay() RTL_R8(Config4)
1196
1197
1198 static const char mii_2_8139_map[8] = {
1199 BasicModeCtrl,
1200 BasicModeStatus,
1201 0,
1202 0,
1203 NWayAdvert,
1204 NWayLPAR,
1205 NWayExpansion,
1206 0
1207 };
1208
1209
1210 #ifdef CONFIG_8139TOO_8129
1211 /* Syncronize the MII management interface by shifting 32 one bits out. */
1212 static void mdio_sync (void __iomem *ioaddr)
1213 {
1214 int i;
1215
1216 for (i = 32; i >= 0; i--) {
1217 RTL_W8 (Config4, MDIO_WRITE1);
1218 mdio_delay ();
1219 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1220 mdio_delay ();
1221 }
1222 }
1223 #endif
1224
1225 static int mdio_read (struct net_device *dev, int phy_id, int location)
1226 {
1227 struct rtl8139_private *tp = netdev_priv(dev);
1228 int retval = 0;
1229 #ifdef CONFIG_8139TOO_8129
1230 void __iomem *ioaddr = tp->mmio_addr;
1231 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1232 int i;
1233 #endif
1234
1235 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1236 void __iomem *ioaddr = tp->mmio_addr;
1237 return location < 8 && mii_2_8139_map[location] ?
1238 RTL_R16 (mii_2_8139_map[location]) : 0;
1239 }
1240
1241 #ifdef CONFIG_8139TOO_8129
1242 mdio_sync (ioaddr);
1243 /* Shift the read command bits out. */
1244 for (i = 15; i >= 0; i--) {
1245 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1246
1247 RTL_W8 (Config4, MDIO_DIR | dataval);
1248 mdio_delay ();
1249 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1250 mdio_delay ();
1251 }
1252
1253 /* Read the two transition, 16 data, and wire-idle bits. */
1254 for (i = 19; i > 0; i--) {
1255 RTL_W8 (Config4, 0);
1256 mdio_delay ();
1257 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1258 RTL_W8 (Config4, MDIO_CLK);
1259 mdio_delay ();
1260 }
1261 #endif
1262
1263 return (retval >> 1) & 0xffff;
1264 }
1265
1266
1267 static void mdio_write (struct net_device *dev, int phy_id, int location,
1268 int value)
1269 {
1270 struct rtl8139_private *tp = netdev_priv(dev);
1271 #ifdef CONFIG_8139TOO_8129
1272 void __iomem *ioaddr = tp->mmio_addr;
1273 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1274 int i;
1275 #endif
1276
1277 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1278 void __iomem *ioaddr = tp->mmio_addr;
1279 if (location == 0) {
1280 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1281 RTL_W16 (BasicModeCtrl, value);
1282 RTL_W8 (Cfg9346, Cfg9346_Lock);
1283 } else if (location < 8 && mii_2_8139_map[location])
1284 RTL_W16 (mii_2_8139_map[location], value);
1285 return;
1286 }
1287
1288 #ifdef CONFIG_8139TOO_8129
1289 mdio_sync (ioaddr);
1290
1291 /* Shift the command bits out. */
1292 for (i = 31; i >= 0; i--) {
1293 int dataval =
1294 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1295 RTL_W8 (Config4, dataval);
1296 mdio_delay ();
1297 RTL_W8 (Config4, dataval | MDIO_CLK);
1298 mdio_delay ();
1299 }
1300 /* Clear out extra bits. */
1301 for (i = 2; i > 0; i--) {
1302 RTL_W8 (Config4, 0);
1303 mdio_delay ();
1304 RTL_W8 (Config4, MDIO_CLK);
1305 mdio_delay ();
1306 }
1307 #endif
1308 }
1309
1310
1311 static int rtl8139_open (struct net_device *dev)
1312 {
1313 struct rtl8139_private *tp = netdev_priv(dev);
1314 void __iomem *ioaddr = tp->mmio_addr;
1315 const int irq = tp->pci_dev->irq;
1316 int retval;
1317
1318 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1319 if (retval)
1320 return retval;
1321
1322 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1323 &tp->tx_bufs_dma, GFP_KERNEL);
1324 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1325 &tp->rx_ring_dma, GFP_KERNEL);
1326 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1327 free_irq(irq, dev);
1328
1329 if (tp->tx_bufs)
1330 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1331 tp->tx_bufs, tp->tx_bufs_dma);
1332 if (tp->rx_ring)
1333 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1334 tp->rx_ring, tp->rx_ring_dma);
1335
1336 return -ENOMEM;
1337
1338 }
1339
1340 napi_enable(&tp->napi);
1341
1342 tp->mii.full_duplex = tp->mii.force_media;
1343 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1344
1345 rtl8139_init_ring (dev);
1346 rtl8139_hw_start (dev);
1347 netif_start_queue (dev);
1348
1349 netif_dbg(tp, ifup, dev,
1350 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1351 __func__,
1352 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1353 irq, RTL_R8 (MediaStatus),
1354 tp->mii.full_duplex ? "full" : "half");
1355
1356 rtl8139_start_thread(tp);
1357
1358 return 0;
1359 }
1360
1361
1362 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1363 {
1364 struct rtl8139_private *tp = netdev_priv(dev);
1365
1366 if (tp->phys[0] >= 0) {
1367 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1368 }
1369 }
1370
1371 /* Start the hardware at open or resume. */
1372 static void rtl8139_hw_start (struct net_device *dev)
1373 {
1374 struct rtl8139_private *tp = netdev_priv(dev);
1375 void __iomem *ioaddr = tp->mmio_addr;
1376 u32 i;
1377 u8 tmp;
1378
1379 /* Bring old chips out of low-power mode. */
1380 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1381 RTL_W8 (HltClk, 'R');
1382
1383 rtl8139_chip_reset (ioaddr);
1384
1385 /* unlock Config[01234] and BMCR register writes */
1386 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1387 /* Restore our idea of the MAC address. */
1388 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1389 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1390
1391 tp->cur_rx = 0;
1392
1393 /* init Rx ring buffer DMA address */
1394 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1395
1396 /* Must enable Tx/Rx before setting transfer thresholds! */
1397 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1398
1399 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1400 RTL_W32 (RxConfig, tp->rx_config);
1401 RTL_W32 (TxConfig, rtl8139_tx_config);
1402
1403 rtl_check_media (dev, 1);
1404
1405 if (tp->chipset >= CH_8139B) {
1406 /* Disable magic packet scanning, which is enabled
1407 * when PM is enabled in Config1. It can be reenabled
1408 * via ETHTOOL_SWOL if desired. */
1409 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1410 }
1411
1412 netdev_dbg(dev, "init buffer addresses\n");
1413
1414 /* Lock Config[01234] and BMCR register writes */
1415 RTL_W8 (Cfg9346, Cfg9346_Lock);
1416
1417 /* init Tx buffer DMA addresses */
1418 for (i = 0; i < NUM_TX_DESC; i++)
1419 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1420
1421 RTL_W32 (RxMissed, 0);
1422
1423 rtl8139_set_rx_mode (dev);
1424
1425 /* no early-rx interrupts */
1426 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1427
1428 /* make sure RxTx has started */
1429 tmp = RTL_R8 (ChipCmd);
1430 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1431 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1432
1433 /* Enable all known interrupts by setting the interrupt mask. */
1434 RTL_W16 (IntrMask, rtl8139_intr_mask);
1435 }
1436
1437
1438 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1439 static void rtl8139_init_ring (struct net_device *dev)
1440 {
1441 struct rtl8139_private *tp = netdev_priv(dev);
1442 int i;
1443
1444 tp->cur_rx = 0;
1445 tp->cur_tx = 0;
1446 tp->dirty_tx = 0;
1447
1448 for (i = 0; i < NUM_TX_DESC; i++)
1449 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1450 }
1451
1452
1453 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1454 static int next_tick = 3 * HZ;
1455
1456 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1457 static inline void rtl8139_tune_twister (struct net_device *dev,
1458 struct rtl8139_private *tp) {}
1459 #else
1460 enum TwisterParamVals {
1461 PARA78_default = 0x78fa8388,
1462 PARA7c_default = 0xcb38de43, /* param[0][3] */
1463 PARA7c_xxx = 0xcb38de43,
1464 };
1465
1466 static const unsigned long param[4][4] = {
1467 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1468 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1469 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1470 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1471 };
1472
1473 static void rtl8139_tune_twister (struct net_device *dev,
1474 struct rtl8139_private *tp)
1475 {
1476 int linkcase;
1477 void __iomem *ioaddr = tp->mmio_addr;
1478
1479 /* This is a complicated state machine to configure the "twister" for
1480 impedance/echos based on the cable length.
1481 All of this is magic and undocumented.
1482 */
1483 switch (tp->twistie) {
1484 case 1:
1485 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1486 /* We have link beat, let us tune the twister. */
1487 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1488 tp->twistie = 2; /* Change to state 2. */
1489 next_tick = HZ / 10;
1490 } else {
1491 /* Just put in some reasonable defaults for when beat returns. */
1492 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1493 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1494 RTL_W32 (PARA78, PARA78_default);
1495 RTL_W32 (PARA7c, PARA7c_default);
1496 tp->twistie = 0; /* Bail from future actions. */
1497 }
1498 break;
1499 case 2:
1500 /* Read how long it took to hear the echo. */
1501 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1502 if (linkcase == 0x7000)
1503 tp->twist_row = 3;
1504 else if (linkcase == 0x3000)
1505 tp->twist_row = 2;
1506 else if (linkcase == 0x1000)
1507 tp->twist_row = 1;
1508 else
1509 tp->twist_row = 0;
1510 tp->twist_col = 0;
1511 tp->twistie = 3; /* Change to state 2. */
1512 next_tick = HZ / 10;
1513 break;
1514 case 3:
1515 /* Put out four tuning parameters, one per 100msec. */
1516 if (tp->twist_col == 0)
1517 RTL_W16 (FIFOTMS, 0);
1518 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1519 [(int) tp->twist_col]);
1520 next_tick = HZ / 10;
1521 if (++tp->twist_col >= 4) {
1522 /* For short cables we are done.
1523 For long cables (row == 3) check for mistune. */
1524 tp->twistie =
1525 (tp->twist_row == 3) ? 4 : 0;
1526 }
1527 break;
1528 case 4:
1529 /* Special case for long cables: check for mistune. */
1530 if ((RTL_R16 (CSCR) &
1531 CSCR_LinkStatusBits) == 0x7000) {
1532 tp->twistie = 0;
1533 break;
1534 } else {
1535 RTL_W32 (PARA7c, 0xfb38de03);
1536 tp->twistie = 5;
1537 next_tick = HZ / 10;
1538 }
1539 break;
1540 case 5:
1541 /* Retune for shorter cable (column 2). */
1542 RTL_W32 (FIFOTMS, 0x20);
1543 RTL_W32 (PARA78, PARA78_default);
1544 RTL_W32 (PARA7c, PARA7c_default);
1545 RTL_W32 (FIFOTMS, 0x00);
1546 tp->twist_row = 2;
1547 tp->twist_col = 0;
1548 tp->twistie = 3;
1549 next_tick = HZ / 10;
1550 break;
1551
1552 default:
1553 /* do nothing */
1554 break;
1555 }
1556 }
1557 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1558
1559 static inline void rtl8139_thread_iter (struct net_device *dev,
1560 struct rtl8139_private *tp,
1561 void __iomem *ioaddr)
1562 {
1563 int mii_lpa;
1564
1565 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1566
1567 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1568 int duplex = ((mii_lpa & LPA_100FULL) ||
1569 (mii_lpa & 0x01C0) == 0x0040);
1570 if (tp->mii.full_duplex != duplex) {
1571 tp->mii.full_duplex = duplex;
1572
1573 if (mii_lpa) {
1574 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1575 tp->mii.full_duplex ? "full" : "half",
1576 tp->phys[0], mii_lpa);
1577 } else {
1578 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1579 }
1580 #if 0
1581 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1582 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1583 RTL_W8 (Cfg9346, Cfg9346_Lock);
1584 #endif
1585 }
1586 }
1587
1588 next_tick = HZ * 60;
1589
1590 rtl8139_tune_twister (dev, tp);
1591
1592 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1593 RTL_R16(NWayLPAR));
1594 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1595 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1596 netdev_dbg(dev, "Chip config %02x %02x\n",
1597 RTL_R8(Config0), RTL_R8(Config1));
1598 }
1599
1600 static void rtl8139_thread (struct work_struct *work)
1601 {
1602 struct rtl8139_private *tp =
1603 container_of(work, struct rtl8139_private, thread.work);
1604 struct net_device *dev = tp->mii.dev;
1605 unsigned long thr_delay = next_tick;
1606
1607 rtnl_lock();
1608
1609 if (!netif_running(dev))
1610 goto out_unlock;
1611
1612 if (tp->watchdog_fired) {
1613 tp->watchdog_fired = 0;
1614 rtl8139_tx_timeout_task(work);
1615 } else
1616 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1617
1618 if (tp->have_thread)
1619 schedule_delayed_work(&tp->thread, thr_delay);
1620 out_unlock:
1621 rtnl_unlock ();
1622 }
1623
1624 static void rtl8139_start_thread(struct rtl8139_private *tp)
1625 {
1626 tp->twistie = 0;
1627 if (tp->chipset == CH_8139_K)
1628 tp->twistie = 1;
1629 else if (tp->drv_flags & HAS_LNK_CHNG)
1630 return;
1631
1632 tp->have_thread = 1;
1633 tp->watchdog_fired = 0;
1634
1635 schedule_delayed_work(&tp->thread, next_tick);
1636 }
1637
1638 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1639 {
1640 tp->cur_tx = 0;
1641 tp->dirty_tx = 0;
1642
1643 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1644 }
1645
1646 static void rtl8139_tx_timeout_task (struct work_struct *work)
1647 {
1648 struct rtl8139_private *tp =
1649 container_of(work, struct rtl8139_private, thread.work);
1650 struct net_device *dev = tp->mii.dev;
1651 void __iomem *ioaddr = tp->mmio_addr;
1652 int i;
1653 u8 tmp8;
1654
1655 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1656 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1657 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1658 /* Emit info to figure out what went wrong. */
1659 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1660 tp->cur_tx, tp->dirty_tx);
1661 for (i = 0; i < NUM_TX_DESC; i++)
1662 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1663 i, RTL_R32(TxStatus0 + (i * 4)),
1664 i == tp->dirty_tx % NUM_TX_DESC ?
1665 " (queue head)" : "");
1666
1667 tp->xstats.tx_timeouts++;
1668
1669 /* disable Tx ASAP, if not already */
1670 tmp8 = RTL_R8 (ChipCmd);
1671 if (tmp8 & CmdTxEnb)
1672 RTL_W8 (ChipCmd, CmdRxEnb);
1673
1674 spin_lock_bh(&tp->rx_lock);
1675 /* Disable interrupts by clearing the interrupt mask. */
1676 RTL_W16 (IntrMask, 0x0000);
1677
1678 /* Stop a shared interrupt from scavenging while we are. */
1679 spin_lock_irq(&tp->lock);
1680 rtl8139_tx_clear (tp);
1681 spin_unlock_irq(&tp->lock);
1682
1683 /* ...and finally, reset everything */
1684 if (netif_running(dev)) {
1685 rtl8139_hw_start (dev);
1686 netif_wake_queue (dev);
1687 }
1688 spin_unlock_bh(&tp->rx_lock);
1689 }
1690
1691 static void rtl8139_tx_timeout (struct net_device *dev)
1692 {
1693 struct rtl8139_private *tp = netdev_priv(dev);
1694
1695 tp->watchdog_fired = 1;
1696 if (!tp->have_thread) {
1697 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1698 schedule_delayed_work(&tp->thread, next_tick);
1699 }
1700 }
1701
1702 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1703 struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706 void __iomem *ioaddr = tp->mmio_addr;
1707 unsigned int entry;
1708 unsigned int len = skb->len;
1709 unsigned long flags;
1710
1711 /* Calculate the next Tx descriptor entry. */
1712 entry = tp->cur_tx % NUM_TX_DESC;
1713
1714 /* Note: the chip doesn't have auto-pad! */
1715 if (likely(len < TX_BUF_SIZE)) {
1716 if (len < ETH_ZLEN)
1717 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1718 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1719 dev_kfree_skb(skb);
1720 } else {
1721 dev_kfree_skb(skb);
1722 dev->stats.tx_dropped++;
1723 return NETDEV_TX_OK;
1724 }
1725
1726 spin_lock_irqsave(&tp->lock, flags);
1727 /*
1728 * Writing to TxStatus triggers a DMA transfer of the data
1729 * copied to tp->tx_buf[entry] above. Use a memory barrier
1730 * to make sure that the device sees the updated data.
1731 */
1732 wmb();
1733 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1734 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1735
1736 tp->cur_tx++;
1737
1738 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1739 netif_stop_queue (dev);
1740 spin_unlock_irqrestore(&tp->lock, flags);
1741
1742 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1743 len, entry);
1744
1745 return NETDEV_TX_OK;
1746 }
1747
1748
1749 static void rtl8139_tx_interrupt (struct net_device *dev,
1750 struct rtl8139_private *tp,
1751 void __iomem *ioaddr)
1752 {
1753 unsigned long dirty_tx, tx_left;
1754
1755 assert (dev != NULL);
1756 assert (ioaddr != NULL);
1757
1758 dirty_tx = tp->dirty_tx;
1759 tx_left = tp->cur_tx - dirty_tx;
1760 while (tx_left > 0) {
1761 int entry = dirty_tx % NUM_TX_DESC;
1762 int txstatus;
1763
1764 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1765
1766 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1767 break; /* It still hasn't been Txed */
1768
1769 /* Note: TxCarrierLost is always asserted at 100mbps. */
1770 if (txstatus & (TxOutOfWindow | TxAborted)) {
1771 /* There was an major error, log it. */
1772 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1773 txstatus);
1774 dev->stats.tx_errors++;
1775 if (txstatus & TxAborted) {
1776 dev->stats.tx_aborted_errors++;
1777 RTL_W32 (TxConfig, TxClearAbt);
1778 RTL_W16 (IntrStatus, TxErr);
1779 wmb();
1780 }
1781 if (txstatus & TxCarrierLost)
1782 dev->stats.tx_carrier_errors++;
1783 if (txstatus & TxOutOfWindow)
1784 dev->stats.tx_window_errors++;
1785 } else {
1786 if (txstatus & TxUnderrun) {
1787 /* Add 64 to the Tx FIFO threshold. */
1788 if (tp->tx_flag < 0x00300000)
1789 tp->tx_flag += 0x00020000;
1790 dev->stats.tx_fifo_errors++;
1791 }
1792 dev->stats.collisions += (txstatus >> 24) & 15;
1793 u64_stats_update_begin(&tp->tx_stats.syncp);
1794 tp->tx_stats.packets++;
1795 tp->tx_stats.bytes += txstatus & 0x7ff;
1796 u64_stats_update_end(&tp->tx_stats.syncp);
1797 }
1798
1799 dirty_tx++;
1800 tx_left--;
1801 }
1802
1803 #ifndef RTL8139_NDEBUG
1804 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1805 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1806 dirty_tx, tp->cur_tx);
1807 dirty_tx += NUM_TX_DESC;
1808 }
1809 #endif /* RTL8139_NDEBUG */
1810
1811 /* only wake the queue if we did work, and the queue is stopped */
1812 if (tp->dirty_tx != dirty_tx) {
1813 tp->dirty_tx = dirty_tx;
1814 mb();
1815 netif_wake_queue (dev);
1816 }
1817 }
1818
1819
1820 /* TODO: clean this up! Rx reset need not be this intensive */
1821 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1822 struct rtl8139_private *tp, void __iomem *ioaddr)
1823 {
1824 u8 tmp8;
1825 #ifdef CONFIG_8139_OLD_RX_RESET
1826 int tmp_work;
1827 #endif
1828
1829 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1830 rx_status);
1831 dev->stats.rx_errors++;
1832 if (!(rx_status & RxStatusOK)) {
1833 if (rx_status & RxTooLong) {
1834 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1835 rx_status);
1836 /* A.C.: The chip hangs here. */
1837 }
1838 if (rx_status & (RxBadSymbol | RxBadAlign))
1839 dev->stats.rx_frame_errors++;
1840 if (rx_status & (RxRunt | RxTooLong))
1841 dev->stats.rx_length_errors++;
1842 if (rx_status & RxCRCErr)
1843 dev->stats.rx_crc_errors++;
1844 } else {
1845 tp->xstats.rx_lost_in_ring++;
1846 }
1847
1848 #ifndef CONFIG_8139_OLD_RX_RESET
1849 tmp8 = RTL_R8 (ChipCmd);
1850 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1851 RTL_W8 (ChipCmd, tmp8);
1852 RTL_W32 (RxConfig, tp->rx_config);
1853 tp->cur_rx = 0;
1854 #else
1855 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1856
1857 /* disable receive */
1858 RTL_W8_F (ChipCmd, CmdTxEnb);
1859 tmp_work = 200;
1860 while (--tmp_work > 0) {
1861 udelay(1);
1862 tmp8 = RTL_R8 (ChipCmd);
1863 if (!(tmp8 & CmdRxEnb))
1864 break;
1865 }
1866 if (tmp_work <= 0)
1867 netdev_warn(dev, "rx stop wait too long\n");
1868 /* restart receive */
1869 tmp_work = 200;
1870 while (--tmp_work > 0) {
1871 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1872 udelay(1);
1873 tmp8 = RTL_R8 (ChipCmd);
1874 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1875 break;
1876 }
1877 if (tmp_work <= 0)
1878 netdev_warn(dev, "tx/rx enable wait too long\n");
1879
1880 /* and reinitialize all rx related registers */
1881 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1882 /* Must enable Tx/Rx before setting transfer thresholds! */
1883 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1884
1885 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1886 RTL_W32 (RxConfig, tp->rx_config);
1887 tp->cur_rx = 0;
1888
1889 netdev_dbg(dev, "init buffer addresses\n");
1890
1891 /* Lock Config[01234] and BMCR register writes */
1892 RTL_W8 (Cfg9346, Cfg9346_Lock);
1893
1894 /* init Rx ring buffer DMA address */
1895 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1896
1897 /* A.C.: Reset the multicast list. */
1898 __set_rx_mode (dev);
1899 #endif
1900 }
1901
1902 #if RX_BUF_IDX == 3
1903 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1904 u32 offset, unsigned int size)
1905 {
1906 u32 left = RX_BUF_LEN - offset;
1907
1908 if (size > left) {
1909 skb_copy_to_linear_data(skb, ring + offset, left);
1910 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1911 } else
1912 skb_copy_to_linear_data(skb, ring + offset, size);
1913 }
1914 #endif
1915
1916 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1917 {
1918 void __iomem *ioaddr = tp->mmio_addr;
1919 u16 status;
1920
1921 status = RTL_R16 (IntrStatus) & RxAckBits;
1922
1923 /* Clear out errors and receive interrupts */
1924 if (likely(status != 0)) {
1925 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1926 tp->dev->stats.rx_errors++;
1927 if (status & RxFIFOOver)
1928 tp->dev->stats.rx_fifo_errors++;
1929 }
1930 RTL_W16_F (IntrStatus, RxAckBits);
1931 }
1932 }
1933
1934 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1935 int budget)
1936 {
1937 void __iomem *ioaddr = tp->mmio_addr;
1938 int received = 0;
1939 unsigned char *rx_ring = tp->rx_ring;
1940 unsigned int cur_rx = tp->cur_rx;
1941 unsigned int rx_size = 0;
1942
1943 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1944 __func__, (u16)cur_rx,
1945 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1946
1947 while (netif_running(dev) && received < budget &&
1948 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1949 u32 ring_offset = cur_rx % RX_BUF_LEN;
1950 u32 rx_status;
1951 unsigned int pkt_size;
1952 struct sk_buff *skb;
1953
1954 rmb();
1955
1956 /* read size+status of next frame from DMA ring buffer */
1957 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1958 rx_size = rx_status >> 16;
1959 if (likely(!(dev->features & NETIF_F_RXFCS)))
1960 pkt_size = rx_size - 4;
1961 else
1962 pkt_size = rx_size;
1963
1964 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1965 __func__, rx_status, rx_size, cur_rx);
1966 #if RTL8139_DEBUG > 2
1967 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1968 DUMP_PREFIX_OFFSET, 16, 1,
1969 &rx_ring[ring_offset], 70, true);
1970 #endif
1971
1972 /* Packet copy from FIFO still in progress.
1973 * Theoretically, this should never happen
1974 * since EarlyRx is disabled.
1975 */
1976 if (unlikely(rx_size == 0xfff0)) {
1977 if (!tp->fifo_copy_timeout)
1978 tp->fifo_copy_timeout = jiffies + 2;
1979 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1980 netdev_dbg(dev, "hung FIFO. Reset\n");
1981 rx_size = 0;
1982 goto no_early_rx;
1983 }
1984 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1985 tp->xstats.early_rx++;
1986 break;
1987 }
1988
1989 no_early_rx:
1990 tp->fifo_copy_timeout = 0;
1991
1992 /* If Rx err or invalid rx_size/rx_status received
1993 * (which happens if we get lost in the ring),
1994 * Rx process gets reset, so we abort any further
1995 * Rx processing.
1996 */
1997 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1998 (rx_size < 8) ||
1999 (!(rx_status & RxStatusOK)))) {
2000 if ((dev->features & NETIF_F_RXALL) &&
2001 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2002 (rx_size >= 8) &&
2003 (!(rx_status & RxStatusOK))) {
2004 /* Length is at least mostly OK, but pkt has
2005 * error. I'm hoping we can handle some of these
2006 * errors without resetting the chip. --Ben
2007 */
2008 dev->stats.rx_errors++;
2009 if (rx_status & RxCRCErr) {
2010 dev->stats.rx_crc_errors++;
2011 goto keep_pkt;
2012 }
2013 if (rx_status & RxRunt) {
2014 dev->stats.rx_length_errors++;
2015 goto keep_pkt;
2016 }
2017 }
2018 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2019 received = -1;
2020 goto out;
2021 }
2022
2023 keep_pkt:
2024 /* Malloc up new buffer, compatible with net-2e. */
2025 /* Omit the four octet CRC from the length. */
2026
2027 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
2028 if (likely(skb)) {
2029 #if RX_BUF_IDX == 3
2030 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2031 #else
2032 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2033 #endif
2034 skb_put (skb, pkt_size);
2035
2036 skb->protocol = eth_type_trans (skb, dev);
2037
2038 u64_stats_update_begin(&tp->rx_stats.syncp);
2039 tp->rx_stats.packets++;
2040 tp->rx_stats.bytes += pkt_size;
2041 u64_stats_update_end(&tp->rx_stats.syncp);
2042
2043 netif_receive_skb (skb);
2044 } else {
2045 if (net_ratelimit())
2046 netdev_warn(dev, "Memory squeeze, dropping packet\n");
2047 dev->stats.rx_dropped++;
2048 }
2049 received++;
2050
2051 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2052 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2053
2054 rtl8139_isr_ack(tp);
2055 }
2056
2057 if (unlikely(!received || rx_size == 0xfff0))
2058 rtl8139_isr_ack(tp);
2059
2060 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2061 __func__, cur_rx,
2062 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2063
2064 tp->cur_rx = cur_rx;
2065
2066 /*
2067 * The receive buffer should be mostly empty.
2068 * Tell NAPI to reenable the Rx irq.
2069 */
2070 if (tp->fifo_copy_timeout)
2071 received = budget;
2072
2073 out:
2074 return received;
2075 }
2076
2077
2078 static void rtl8139_weird_interrupt (struct net_device *dev,
2079 struct rtl8139_private *tp,
2080 void __iomem *ioaddr,
2081 int status, int link_changed)
2082 {
2083 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2084
2085 assert (dev != NULL);
2086 assert (tp != NULL);
2087 assert (ioaddr != NULL);
2088
2089 /* Update the error count. */
2090 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2091 RTL_W32 (RxMissed, 0);
2092
2093 if ((status & RxUnderrun) && link_changed &&
2094 (tp->drv_flags & HAS_LNK_CHNG)) {
2095 rtl_check_media(dev, 0);
2096 status &= ~RxUnderrun;
2097 }
2098
2099 if (status & (RxUnderrun | RxErr))
2100 dev->stats.rx_errors++;
2101
2102 if (status & PCSTimeout)
2103 dev->stats.rx_length_errors++;
2104 if (status & RxUnderrun)
2105 dev->stats.rx_fifo_errors++;
2106 if (status & PCIErr) {
2107 u16 pci_cmd_status;
2108 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2109 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2110
2111 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2112 }
2113 }
2114
2115 static int rtl8139_poll(struct napi_struct *napi, int budget)
2116 {
2117 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2118 struct net_device *dev = tp->dev;
2119 void __iomem *ioaddr = tp->mmio_addr;
2120 int work_done;
2121
2122 spin_lock(&tp->rx_lock);
2123 work_done = 0;
2124 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2125 work_done += rtl8139_rx(dev, tp, budget);
2126
2127 if (work_done < budget) {
2128 unsigned long flags;
2129 /*
2130 * Order is important since data can get interrupted
2131 * again when we think we are done.
2132 */
2133 spin_lock_irqsave(&tp->lock, flags);
2134 __napi_complete(napi);
2135 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2136 spin_unlock_irqrestore(&tp->lock, flags);
2137 }
2138 spin_unlock(&tp->rx_lock);
2139
2140 return work_done;
2141 }
2142
2143 /* The interrupt handler does all of the Rx thread work and cleans up
2144 after the Tx thread. */
2145 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2146 {
2147 struct net_device *dev = (struct net_device *) dev_instance;
2148 struct rtl8139_private *tp = netdev_priv(dev);
2149 void __iomem *ioaddr = tp->mmio_addr;
2150 u16 status, ackstat;
2151 int link_changed = 0; /* avoid bogus "uninit" warning */
2152 int handled = 0;
2153
2154 spin_lock (&tp->lock);
2155 status = RTL_R16 (IntrStatus);
2156
2157 /* shared irq? */
2158 if (unlikely((status & rtl8139_intr_mask) == 0))
2159 goto out;
2160
2161 handled = 1;
2162
2163 /* h/w no longer present (hotplug?) or major error, bail */
2164 if (unlikely(status == 0xFFFF))
2165 goto out;
2166
2167 /* close possible race's with dev_close */
2168 if (unlikely(!netif_running(dev))) {
2169 RTL_W16 (IntrMask, 0);
2170 goto out;
2171 }
2172
2173 /* Acknowledge all of the current interrupt sources ASAP, but
2174 an first get an additional status bit from CSCR. */
2175 if (unlikely(status & RxUnderrun))
2176 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2177
2178 ackstat = status & ~(RxAckBits | TxErr);
2179 if (ackstat)
2180 RTL_W16 (IntrStatus, ackstat);
2181
2182 /* Receive packets are processed by poll routine.
2183 If not running start it now. */
2184 if (status & RxAckBits){
2185 if (napi_schedule_prep(&tp->napi)) {
2186 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2187 __napi_schedule(&tp->napi);
2188 }
2189 }
2190
2191 /* Check uncommon events with one test. */
2192 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2193 rtl8139_weird_interrupt (dev, tp, ioaddr,
2194 status, link_changed);
2195
2196 if (status & (TxOK | TxErr)) {
2197 rtl8139_tx_interrupt (dev, tp, ioaddr);
2198 if (status & TxErr)
2199 RTL_W16 (IntrStatus, TxErr);
2200 }
2201 out:
2202 spin_unlock (&tp->lock);
2203
2204 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2205 RTL_R16(IntrStatus));
2206 return IRQ_RETVAL(handled);
2207 }
2208
2209 #ifdef CONFIG_NET_POLL_CONTROLLER
2210 /*
2211 * Polling receive - used by netconsole and other diagnostic tools
2212 * to allow network i/o with interrupts disabled.
2213 */
2214 static void rtl8139_poll_controller(struct net_device *dev)
2215 {
2216 struct rtl8139_private *tp = netdev_priv(dev);
2217 const int irq = tp->pci_dev->irq;
2218
2219 disable_irq(irq);
2220 rtl8139_interrupt(irq, dev);
2221 enable_irq(irq);
2222 }
2223 #endif
2224
2225 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2226 {
2227 struct rtl8139_private *tp = netdev_priv(dev);
2228 void __iomem *ioaddr = tp->mmio_addr;
2229 struct sockaddr *addr = p;
2230
2231 if (!is_valid_ether_addr(addr->sa_data))
2232 return -EADDRNOTAVAIL;
2233
2234 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2235
2236 spin_lock_irq(&tp->lock);
2237
2238 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2239 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2240 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2241 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2242
2243 spin_unlock_irq(&tp->lock);
2244
2245 return 0;
2246 }
2247
2248 static int rtl8139_close (struct net_device *dev)
2249 {
2250 struct rtl8139_private *tp = netdev_priv(dev);
2251 void __iomem *ioaddr = tp->mmio_addr;
2252 unsigned long flags;
2253
2254 netif_stop_queue(dev);
2255 napi_disable(&tp->napi);
2256
2257 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2258 RTL_R16(IntrStatus));
2259
2260 spin_lock_irqsave (&tp->lock, flags);
2261
2262 /* Stop the chip's Tx and Rx DMA processes. */
2263 RTL_W8 (ChipCmd, 0);
2264
2265 /* Disable interrupts by clearing the interrupt mask. */
2266 RTL_W16 (IntrMask, 0);
2267
2268 /* Update the error counts. */
2269 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2270 RTL_W32 (RxMissed, 0);
2271
2272 spin_unlock_irqrestore (&tp->lock, flags);
2273
2274 free_irq(tp->pci_dev->irq, dev);
2275
2276 rtl8139_tx_clear (tp);
2277
2278 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2279 tp->rx_ring, tp->rx_ring_dma);
2280 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2281 tp->tx_bufs, tp->tx_bufs_dma);
2282 tp->rx_ring = NULL;
2283 tp->tx_bufs = NULL;
2284
2285 /* Green! Put the chip in low-power mode. */
2286 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2287
2288 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2289 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2290
2291 return 0;
2292 }
2293
2294
2295 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2296 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2297 other threads or interrupts aren't messing with the 8139. */
2298 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2299 {
2300 struct rtl8139_private *tp = netdev_priv(dev);
2301 void __iomem *ioaddr = tp->mmio_addr;
2302
2303 spin_lock_irq(&tp->lock);
2304 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2305 u8 cfg3 = RTL_R8 (Config3);
2306 u8 cfg5 = RTL_R8 (Config5);
2307
2308 wol->supported = WAKE_PHY | WAKE_MAGIC
2309 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2310
2311 wol->wolopts = 0;
2312 if (cfg3 & Cfg3_LinkUp)
2313 wol->wolopts |= WAKE_PHY;
2314 if (cfg3 & Cfg3_Magic)
2315 wol->wolopts |= WAKE_MAGIC;
2316 /* (KON)FIXME: See how netdev_set_wol() handles the
2317 following constants. */
2318 if (cfg5 & Cfg5_UWF)
2319 wol->wolopts |= WAKE_UCAST;
2320 if (cfg5 & Cfg5_MWF)
2321 wol->wolopts |= WAKE_MCAST;
2322 if (cfg5 & Cfg5_BWF)
2323 wol->wolopts |= WAKE_BCAST;
2324 }
2325 spin_unlock_irq(&tp->lock);
2326 }
2327
2328
2329 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2330 that wol points to kernel memory and other threads or interrupts
2331 aren't messing with the 8139. */
2332 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2333 {
2334 struct rtl8139_private *tp = netdev_priv(dev);
2335 void __iomem *ioaddr = tp->mmio_addr;
2336 u32 support;
2337 u8 cfg3, cfg5;
2338
2339 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2340 ? (WAKE_PHY | WAKE_MAGIC
2341 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2342 : 0);
2343 if (wol->wolopts & ~support)
2344 return -EINVAL;
2345
2346 spin_lock_irq(&tp->lock);
2347 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2348 if (wol->wolopts & WAKE_PHY)
2349 cfg3 |= Cfg3_LinkUp;
2350 if (wol->wolopts & WAKE_MAGIC)
2351 cfg3 |= Cfg3_Magic;
2352 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2353 RTL_W8 (Config3, cfg3);
2354 RTL_W8 (Cfg9346, Cfg9346_Lock);
2355
2356 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2357 /* (KON)FIXME: These are untested. We may have to set the
2358 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2359 documentation. */
2360 if (wol->wolopts & WAKE_UCAST)
2361 cfg5 |= Cfg5_UWF;
2362 if (wol->wolopts & WAKE_MCAST)
2363 cfg5 |= Cfg5_MWF;
2364 if (wol->wolopts & WAKE_BCAST)
2365 cfg5 |= Cfg5_BWF;
2366 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2367 spin_unlock_irq(&tp->lock);
2368
2369 return 0;
2370 }
2371
2372 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2373 {
2374 struct rtl8139_private *tp = netdev_priv(dev);
2375 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2376 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2377 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2378 info->regdump_len = tp->regs_len;
2379 }
2380
2381 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2382 {
2383 struct rtl8139_private *tp = netdev_priv(dev);
2384 spin_lock_irq(&tp->lock);
2385 mii_ethtool_gset(&tp->mii, cmd);
2386 spin_unlock_irq(&tp->lock);
2387 return 0;
2388 }
2389
2390 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2391 {
2392 struct rtl8139_private *tp = netdev_priv(dev);
2393 int rc;
2394 spin_lock_irq(&tp->lock);
2395 rc = mii_ethtool_sset(&tp->mii, cmd);
2396 spin_unlock_irq(&tp->lock);
2397 return rc;
2398 }
2399
2400 static int rtl8139_nway_reset(struct net_device *dev)
2401 {
2402 struct rtl8139_private *tp = netdev_priv(dev);
2403 return mii_nway_restart(&tp->mii);
2404 }
2405
2406 static u32 rtl8139_get_link(struct net_device *dev)
2407 {
2408 struct rtl8139_private *tp = netdev_priv(dev);
2409 return mii_link_ok(&tp->mii);
2410 }
2411
2412 static u32 rtl8139_get_msglevel(struct net_device *dev)
2413 {
2414 struct rtl8139_private *tp = netdev_priv(dev);
2415 return tp->msg_enable;
2416 }
2417
2418 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2419 {
2420 struct rtl8139_private *tp = netdev_priv(dev);
2421 tp->msg_enable = datum;
2422 }
2423
2424 static int rtl8139_get_regs_len(struct net_device *dev)
2425 {
2426 struct rtl8139_private *tp;
2427 /* TODO: we are too slack to do reg dumping for pio, for now */
2428 if (use_io)
2429 return 0;
2430 tp = netdev_priv(dev);
2431 return tp->regs_len;
2432 }
2433
2434 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2435 {
2436 struct rtl8139_private *tp;
2437
2438 /* TODO: we are too slack to do reg dumping for pio, for now */
2439 if (use_io)
2440 return;
2441 tp = netdev_priv(dev);
2442
2443 regs->version = RTL_REGS_VER;
2444
2445 spin_lock_irq(&tp->lock);
2446 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2447 spin_unlock_irq(&tp->lock);
2448 }
2449
2450 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2451 {
2452 switch (sset) {
2453 case ETH_SS_STATS:
2454 return RTL_NUM_STATS;
2455 default:
2456 return -EOPNOTSUPP;
2457 }
2458 }
2459
2460 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2461 {
2462 struct rtl8139_private *tp = netdev_priv(dev);
2463
2464 data[0] = tp->xstats.early_rx;
2465 data[1] = tp->xstats.tx_buf_mapped;
2466 data[2] = tp->xstats.tx_timeouts;
2467 data[3] = tp->xstats.rx_lost_in_ring;
2468 }
2469
2470 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2471 {
2472 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2473 }
2474
2475 static const struct ethtool_ops rtl8139_ethtool_ops = {
2476 .get_drvinfo = rtl8139_get_drvinfo,
2477 .get_settings = rtl8139_get_settings,
2478 .set_settings = rtl8139_set_settings,
2479 .get_regs_len = rtl8139_get_regs_len,
2480 .get_regs = rtl8139_get_regs,
2481 .nway_reset = rtl8139_nway_reset,
2482 .get_link = rtl8139_get_link,
2483 .get_msglevel = rtl8139_get_msglevel,
2484 .set_msglevel = rtl8139_set_msglevel,
2485 .get_wol = rtl8139_get_wol,
2486 .set_wol = rtl8139_set_wol,
2487 .get_strings = rtl8139_get_strings,
2488 .get_sset_count = rtl8139_get_sset_count,
2489 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2490 };
2491
2492 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2493 {
2494 struct rtl8139_private *tp = netdev_priv(dev);
2495 int rc;
2496
2497 if (!netif_running(dev))
2498 return -EINVAL;
2499
2500 spin_lock_irq(&tp->lock);
2501 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2502 spin_unlock_irq(&tp->lock);
2503
2504 return rc;
2505 }
2506
2507
2508 static struct rtnl_link_stats64 *
2509 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2510 {
2511 struct rtl8139_private *tp = netdev_priv(dev);
2512 void __iomem *ioaddr = tp->mmio_addr;
2513 unsigned long flags;
2514 unsigned int start;
2515
2516 if (netif_running(dev)) {
2517 spin_lock_irqsave (&tp->lock, flags);
2518 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2519 RTL_W32 (RxMissed, 0);
2520 spin_unlock_irqrestore (&tp->lock, flags);
2521 }
2522
2523 netdev_stats_to_stats64(stats, &dev->stats);
2524
2525 do {
2526 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
2527 stats->rx_packets = tp->rx_stats.packets;
2528 stats->rx_bytes = tp->rx_stats.bytes;
2529 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
2530
2531 do {
2532 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
2533 stats->tx_packets = tp->tx_stats.packets;
2534 stats->tx_bytes = tp->tx_stats.bytes;
2535 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
2536
2537 return stats;
2538 }
2539
2540 /* Set or clear the multicast filter for this adaptor.
2541 This routine is not state sensitive and need not be SMP locked. */
2542
2543 static void __set_rx_mode (struct net_device *dev)
2544 {
2545 struct rtl8139_private *tp = netdev_priv(dev);
2546 void __iomem *ioaddr = tp->mmio_addr;
2547 u32 mc_filter[2]; /* Multicast hash filter */
2548 int rx_mode;
2549 u32 tmp;
2550
2551 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2552 dev->flags, RTL_R32(RxConfig));
2553
2554 /* Note: do not reorder, GCC is clever about common statements. */
2555 if (dev->flags & IFF_PROMISC) {
2556 rx_mode =
2557 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2558 AcceptAllPhys;
2559 mc_filter[1] = mc_filter[0] = 0xffffffff;
2560 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2561 (dev->flags & IFF_ALLMULTI)) {
2562 /* Too many to filter perfectly -- accept all multicasts. */
2563 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2564 mc_filter[1] = mc_filter[0] = 0xffffffff;
2565 } else {
2566 struct netdev_hw_addr *ha;
2567 rx_mode = AcceptBroadcast | AcceptMyPhys;
2568 mc_filter[1] = mc_filter[0] = 0;
2569 netdev_for_each_mc_addr(ha, dev) {
2570 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2571
2572 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2573 rx_mode |= AcceptMulticast;
2574 }
2575 }
2576
2577 if (dev->features & NETIF_F_RXALL)
2578 rx_mode |= (AcceptErr | AcceptRunt);
2579
2580 /* We can safely update without stopping the chip. */
2581 tmp = rtl8139_rx_config | rx_mode;
2582 if (tp->rx_config != tmp) {
2583 RTL_W32_F (RxConfig, tmp);
2584 tp->rx_config = tmp;
2585 }
2586 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2587 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2588 }
2589
2590 static void rtl8139_set_rx_mode (struct net_device *dev)
2591 {
2592 unsigned long flags;
2593 struct rtl8139_private *tp = netdev_priv(dev);
2594
2595 spin_lock_irqsave (&tp->lock, flags);
2596 __set_rx_mode(dev);
2597 spin_unlock_irqrestore (&tp->lock, flags);
2598 }
2599
2600 #ifdef CONFIG_PM
2601
2602 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2603 {
2604 struct net_device *dev = pci_get_drvdata (pdev);
2605 struct rtl8139_private *tp = netdev_priv(dev);
2606 void __iomem *ioaddr = tp->mmio_addr;
2607 unsigned long flags;
2608
2609 pci_save_state (pdev);
2610
2611 if (!netif_running (dev))
2612 return 0;
2613
2614 netif_device_detach (dev);
2615
2616 spin_lock_irqsave (&tp->lock, flags);
2617
2618 /* Disable interrupts, stop Tx and Rx. */
2619 RTL_W16 (IntrMask, 0);
2620 RTL_W8 (ChipCmd, 0);
2621
2622 /* Update the error counts. */
2623 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2624 RTL_W32 (RxMissed, 0);
2625
2626 spin_unlock_irqrestore (&tp->lock, flags);
2627
2628 pci_set_power_state (pdev, PCI_D3hot);
2629
2630 return 0;
2631 }
2632
2633
2634 static int rtl8139_resume (struct pci_dev *pdev)
2635 {
2636 struct net_device *dev = pci_get_drvdata (pdev);
2637
2638 pci_restore_state (pdev);
2639 if (!netif_running (dev))
2640 return 0;
2641 pci_set_power_state (pdev, PCI_D0);
2642 rtl8139_init_ring (dev);
2643 rtl8139_hw_start (dev);
2644 netif_device_attach (dev);
2645 return 0;
2646 }
2647
2648 #endif /* CONFIG_PM */
2649
2650
2651 static struct pci_driver rtl8139_pci_driver = {
2652 .name = DRV_NAME,
2653 .id_table = rtl8139_pci_tbl,
2654 .probe = rtl8139_init_one,
2655 .remove = __devexit_p(rtl8139_remove_one),
2656 #ifdef CONFIG_PM
2657 .suspend = rtl8139_suspend,
2658 .resume = rtl8139_resume,
2659 #endif /* CONFIG_PM */
2660 };
2661
2662
2663 static int __init rtl8139_init_module (void)
2664 {
2665 /* when we're a module, we always print a version message,
2666 * even if no 8139 board is found.
2667 */
2668 #ifdef MODULE
2669 pr_info(RTL8139_DRIVER_NAME "\n");
2670 #endif
2671
2672 return pci_register_driver(&rtl8139_pci_driver);
2673 }
2674
2675
2676 static void __exit rtl8139_cleanup_module (void)
2677 {
2678 pci_unregister_driver (&rtl8139_pci_driver);
2679 }
2680
2681
2682 module_init(rtl8139_init_module);
2683 module_exit(rtl8139_cleanup_module);
Linux ARM platform port for MOXA ART SoC