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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_ethtool.c
blob76fd61aa005f18060806fd16430c56c869ac21dd
1 /*******************************************************************************
2 STMMAC Ethtool support
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <asm/io.h>
31
32 #include "stmmac.h"
33 #include "dwmac_dma.h"
34
35 #define REG_SPACE_SIZE 0x1054
36 #define MAC100_ETHTOOL_NAME "st_mac100"
37 #define GMAC_ETHTOOL_NAME "st_gmac"
38
39 struct stmmac_stats {
40 char stat_string[ETH_GSTRING_LEN];
41 int sizeof_stat;
42 int stat_offset;
43 };
44
45 #define STMMAC_STAT(m) \
46 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \
47 offsetof(struct stmmac_priv, xstats.m)}
48
49 static const struct stmmac_stats stmmac_gstrings_stats[] = {
50 /* Transmit errors */
51 STMMAC_STAT(tx_underflow),
52 STMMAC_STAT(tx_carrier),
53 STMMAC_STAT(tx_losscarrier),
54 STMMAC_STAT(vlan_tag),
55 STMMAC_STAT(tx_deferred),
56 STMMAC_STAT(tx_vlan),
57 STMMAC_STAT(tx_jabber),
58 STMMAC_STAT(tx_frame_flushed),
59 STMMAC_STAT(tx_payload_error),
60 STMMAC_STAT(tx_ip_header_error),
61 /* Receive errors */
62 STMMAC_STAT(rx_desc),
63 STMMAC_STAT(sa_filter_fail),
64 STMMAC_STAT(overflow_error),
65 STMMAC_STAT(ipc_csum_error),
66 STMMAC_STAT(rx_collision),
67 STMMAC_STAT(rx_crc),
68 STMMAC_STAT(dribbling_bit),
69 STMMAC_STAT(rx_length),
70 STMMAC_STAT(rx_mii),
71 STMMAC_STAT(rx_multicast),
72 STMMAC_STAT(rx_gmac_overflow),
73 STMMAC_STAT(rx_watchdog),
74 STMMAC_STAT(da_rx_filter_fail),
75 STMMAC_STAT(sa_rx_filter_fail),
76 STMMAC_STAT(rx_missed_cntr),
77 STMMAC_STAT(rx_overflow_cntr),
78 STMMAC_STAT(rx_vlan),
79 /* Tx/Rx IRQ errors */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Extra info */
90 STMMAC_STAT(threshold),
91 STMMAC_STAT(tx_pkt_n),
92 STMMAC_STAT(rx_pkt_n),
93 STMMAC_STAT(poll_n),
94 STMMAC_STAT(sched_timer_n),
95 STMMAC_STAT(normal_irq_n),
96 STMMAC_STAT(normal_irq_n),
97 STMMAC_STAT(mmc_tx_irq_n),
98 STMMAC_STAT(mmc_rx_irq_n),
99 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
100 STMMAC_STAT(irq_receive_pmt_irq_n),
101 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
102 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
103 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
104 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
105 STMMAC_STAT(phy_eee_wakeup_error_n),
106 };
107 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
108
109 /* HW MAC Management counters (if supported) */
110 #define STMMAC_MMC_STAT(m) \
111 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \
112 offsetof(struct stmmac_priv, mmc.m)}
113
114 static const struct stmmac_stats stmmac_mmc[] = {
115 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
116 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
117 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
118 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
119 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
120 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
121 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
122 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
123 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
124 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
125 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
126 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
127 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
128 STMMAC_MMC_STAT(mmc_tx_underflow_error),
129 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
130 STMMAC_MMC_STAT(mmc_tx_multicol_g),
131 STMMAC_MMC_STAT(mmc_tx_deferred),
132 STMMAC_MMC_STAT(mmc_tx_latecol),
133 STMMAC_MMC_STAT(mmc_tx_exesscol),
134 STMMAC_MMC_STAT(mmc_tx_carrier_error),
135 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
136 STMMAC_MMC_STAT(mmc_tx_framecount_g),
137 STMMAC_MMC_STAT(mmc_tx_excessdef),
138 STMMAC_MMC_STAT(mmc_tx_pause_frame),
139 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
140 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
141 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
142 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
143 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
144 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
145 STMMAC_MMC_STAT(mmc_rx_crc_errror),
146 STMMAC_MMC_STAT(mmc_rx_align_error),
147 STMMAC_MMC_STAT(mmc_rx_run_error),
148 STMMAC_MMC_STAT(mmc_rx_jabber_error),
149 STMMAC_MMC_STAT(mmc_rx_undersize_g),
150 STMMAC_MMC_STAT(mmc_rx_oversize_g),
151 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
152 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
153 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
154 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
155 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
156 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
157 STMMAC_MMC_STAT(mmc_rx_unicast_g),
158 STMMAC_MMC_STAT(mmc_rx_length_error),
159 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
160 STMMAC_MMC_STAT(mmc_rx_pause_frames),
161 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
162 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
163 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
164 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
165 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
166 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
167 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
168 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
169 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
170 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
171 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
172 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
173 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
174 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
175 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
176 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
177 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
178 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
179 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
180 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
181 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
182 STMMAC_MMC_STAT(mmc_rx_udp_gd),
183 STMMAC_MMC_STAT(mmc_rx_udp_err),
184 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
185 STMMAC_MMC_STAT(mmc_rx_tcp_err),
186 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
187 STMMAC_MMC_STAT(mmc_rx_icmp_err),
188 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
189 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
190 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
191 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
192 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
193 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
194 };
195 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
196
197 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
198 struct ethtool_drvinfo *info)
199 {
200 struct stmmac_priv *priv = netdev_priv(dev);
201
202 if (priv->plat->has_gmac)
203 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
204 else
205 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
206 sizeof(info->driver));
207
208 strcpy(info->version, DRV_MODULE_VERSION);
209 info->fw_version[0] = '\0';
210 }
211
212 static int stmmac_ethtool_getsettings(struct net_device *dev,
213 struct ethtool_cmd *cmd)
214 {
215 struct stmmac_priv *priv = netdev_priv(dev);
216 struct phy_device *phy = priv->phydev;
217 int rc;
218 if (phy == NULL) {
219 pr_err("%s: %s: PHY is not registered\n",
220 __func__, dev->name);
221 return -ENODEV;
222 }
223 if (!netif_running(dev)) {
224 pr_err("%s: interface is disabled: we cannot track "
225 "link speed / duplex setting\n", dev->name);
226 return -EBUSY;
227 }
228 cmd->transceiver = XCVR_INTERNAL;
229 spin_lock_irq(&priv->lock);
230 rc = phy_ethtool_gset(phy, cmd);
231 spin_unlock_irq(&priv->lock);
232 return rc;
233 }
234
235 static int stmmac_ethtool_setsettings(struct net_device *dev,
236 struct ethtool_cmd *cmd)
237 {
238 struct stmmac_priv *priv = netdev_priv(dev);
239 struct phy_device *phy = priv->phydev;
240 int rc;
241
242 spin_lock(&priv->lock);
243 rc = phy_ethtool_sset(phy, cmd);
244 spin_unlock(&priv->lock);
245
246 return rc;
247 }
248
249 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
250 {
251 struct stmmac_priv *priv = netdev_priv(dev);
252 return priv->msg_enable;
253 }
254
255 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
256 {
257 struct stmmac_priv *priv = netdev_priv(dev);
258 priv->msg_enable = level;
259
260 }
261
262 static int stmmac_check_if_running(struct net_device *dev)
263 {
264 if (!netif_running(dev))
265 return -EBUSY;
266 return 0;
267 }
268
269 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
270 {
271 return REG_SPACE_SIZE;
272 }
273
274 static void stmmac_ethtool_gregs(struct net_device *dev,
275 struct ethtool_regs *regs, void *space)
276 {
277 int i;
278 u32 *reg_space = (u32 *) space;
279
280 struct stmmac_priv *priv = netdev_priv(dev);
281
282 memset(reg_space, 0x0, REG_SPACE_SIZE);
283
284 if (!priv->plat->has_gmac) {
285 /* MAC registers */
286 for (i = 0; i < 12; i++)
287 reg_space[i] = readl(priv->ioaddr + (i * 4));
288 /* DMA registers */
289 for (i = 0; i < 9; i++)
290 reg_space[i + 12] =
291 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
292 reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR);
293 reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR);
294 } else {
295 /* MAC registers */
296 for (i = 0; i < 55; i++)
297 reg_space[i] = readl(priv->ioaddr + (i * 4));
298 /* DMA registers */
299 for (i = 0; i < 22; i++)
300 reg_space[i + 55] =
301 readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
302 }
303 }
304
305 static void
306 stmmac_get_pauseparam(struct net_device *netdev,
307 struct ethtool_pauseparam *pause)
308 {
309 struct stmmac_priv *priv = netdev_priv(netdev);
310
311 spin_lock(&priv->lock);
312
313 pause->rx_pause = 0;
314 pause->tx_pause = 0;
315 pause->autoneg = priv->phydev->autoneg;
316
317 if (priv->flow_ctrl & FLOW_RX)
318 pause->rx_pause = 1;
319 if (priv->flow_ctrl & FLOW_TX)
320 pause->tx_pause = 1;
321
322 spin_unlock(&priv->lock);
323 }
324
325 static int
326 stmmac_set_pauseparam(struct net_device *netdev,
327 struct ethtool_pauseparam *pause)
328 {
329 struct stmmac_priv *priv = netdev_priv(netdev);
330 struct phy_device *phy = priv->phydev;
331 int new_pause = FLOW_OFF;
332 int ret = 0;
333
334 spin_lock(&priv->lock);
335
336 if (pause->rx_pause)
337 new_pause |= FLOW_RX;
338 if (pause->tx_pause)
339 new_pause |= FLOW_TX;
340
341 priv->flow_ctrl = new_pause;
342 phy->autoneg = pause->autoneg;
343
344 if (phy->autoneg) {
345 if (netif_running(netdev))
346 ret = phy_start_aneg(phy);
347 } else
348 priv->hw->mac->flow_ctrl(priv->ioaddr, phy->duplex,
349 priv->flow_ctrl, priv->pause);
350 spin_unlock(&priv->lock);
351 return ret;
352 }
353
354 static void stmmac_get_ethtool_stats(struct net_device *dev,
355 struct ethtool_stats *dummy, u64 *data)
356 {
357 struct stmmac_priv *priv = netdev_priv(dev);
358 int i, j = 0;
359
360 /* Update the DMA HW counters for dwmac10/100 */
361 if (!priv->plat->has_gmac)
362 priv->hw->dma->dma_diagnostic_fr(&dev->stats,
363 (void *) &priv->xstats,
364 priv->ioaddr);
365 else {
366 /* If supported, for new GMAC chips expose the MMC counters */
367 if (priv->dma_cap.rmon) {
368 dwmac_mmc_read(priv->ioaddr, &priv->mmc);
369
370 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
371 char *p;
372 p = (char *)priv + stmmac_mmc[i].stat_offset;
373
374 data[j++] = (stmmac_mmc[i].sizeof_stat ==
375 sizeof(u64)) ? (*(u64 *)p) :
376 (*(u32 *)p);
377 }
378 }
379 if (priv->eee_enabled) {
380 int val = phy_get_eee_err(priv->phydev);
381 if (val)
382 priv->xstats.phy_eee_wakeup_error_n = val;
383 }
384 }
385 for (i = 0; i < STMMAC_STATS_LEN; i++) {
386 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
387 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
388 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
389 }
390 }
391
392 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
393 {
394 struct stmmac_priv *priv = netdev_priv(netdev);
395 int len;
396
397 switch (sset) {
398 case ETH_SS_STATS:
399 len = STMMAC_STATS_LEN;
400
401 if (priv->dma_cap.rmon)
402 len += STMMAC_MMC_STATS_LEN;
403
404 return len;
405 default:
406 return -EOPNOTSUPP;
407 }
408 }
409
410 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
411 {
412 int i;
413 u8 *p = data;
414 struct stmmac_priv *priv = netdev_priv(dev);
415
416 switch (stringset) {
417 case ETH_SS_STATS:
418 if (priv->dma_cap.rmon)
419 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
420 memcpy(p, stmmac_mmc[i].stat_string,
421 ETH_GSTRING_LEN);
422 p += ETH_GSTRING_LEN;
423 }
424 for (i = 0; i < STMMAC_STATS_LEN; i++) {
425 memcpy(p, stmmac_gstrings_stats[i].stat_string,
426 ETH_GSTRING_LEN);
427 p += ETH_GSTRING_LEN;
428 }
429 break;
430 default:
431 WARN_ON(1);
432 break;
433 }
434 }
435
436 /* Currently only support WOL through Magic packet. */
437 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
438 {
439 struct stmmac_priv *priv = netdev_priv(dev);
440
441 spin_lock_irq(&priv->lock);
442 if (device_can_wakeup(priv->device)) {
443 wol->supported = WAKE_MAGIC | WAKE_UCAST;
444 wol->wolopts = priv->wolopts;
445 }
446 spin_unlock_irq(&priv->lock);
447 }
448
449 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
450 {
451 struct stmmac_priv *priv = netdev_priv(dev);
452 u32 support = WAKE_MAGIC | WAKE_UCAST;
453
454 /* By default almost all GMAC devices support the WoL via
455 * magic frame but we can disable it if the HW capability
456 * register shows no support for pmt_magic_frame. */
457 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
458 wol->wolopts &= ~WAKE_MAGIC;
459
460 if (!device_can_wakeup(priv->device))
461 return -EINVAL;
462
463 if (wol->wolopts & ~support)
464 return -EINVAL;
465
466 if (wol->wolopts) {
467 pr_info("stmmac: wakeup enable\n");
468 device_set_wakeup_enable(priv->device, 1);
469 enable_irq_wake(priv->wol_irq);
470 } else {
471 device_set_wakeup_enable(priv->device, 0);
472 disable_irq_wake(priv->wol_irq);
473 }
474
475 spin_lock_irq(&priv->lock);
476 priv->wolopts = wol->wolopts;
477 spin_unlock_irq(&priv->lock);
478
479 return 0;
480 }
481
482 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
483 struct ethtool_eee *edata)
484 {
485 struct stmmac_priv *priv = netdev_priv(dev);
486
487 if (!priv->dma_cap.eee)
488 return -EOPNOTSUPP;
489
490 edata->eee_enabled = priv->eee_enabled;
491 edata->eee_active = priv->eee_active;
492 edata->tx_lpi_timer = priv->tx_lpi_timer;
493
494 return phy_ethtool_get_eee(priv->phydev, edata);
495 }
496
497 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
498 struct ethtool_eee *edata)
499 {
500 struct stmmac_priv *priv = netdev_priv(dev);
501
502 priv->eee_enabled = edata->eee_enabled;
503
504 if (!priv->eee_enabled)
505 stmmac_disable_eee_mode(priv);
506 else {
507 /* We are asking for enabling the EEE but it is safe
508 * to verify all by invoking the eee_init function.
509 * In case of failure it will return an error.
510 */
511 priv->eee_enabled = stmmac_eee_init(priv);
512 if (!priv->eee_enabled)
513 return -EOPNOTSUPP;
514
515 /* Do not change tx_lpi_timer in case of failure */
516 priv->tx_lpi_timer = edata->tx_lpi_timer;
517 }
518
519 return phy_ethtool_set_eee(priv->phydev, edata);
520 }
521
522 static const struct ethtool_ops stmmac_ethtool_ops = {
523 .begin = stmmac_check_if_running,
524 .get_drvinfo = stmmac_ethtool_getdrvinfo,
525 .get_settings = stmmac_ethtool_getsettings,
526 .set_settings = stmmac_ethtool_setsettings,
527 .get_msglevel = stmmac_ethtool_getmsglevel,
528 .set_msglevel = stmmac_ethtool_setmsglevel,
529 .get_regs = stmmac_ethtool_gregs,
530 .get_regs_len = stmmac_ethtool_get_regs_len,
531 .get_link = ethtool_op_get_link,
532 .get_pauseparam = stmmac_get_pauseparam,
533 .set_pauseparam = stmmac_set_pauseparam,
534 .get_ethtool_stats = stmmac_get_ethtool_stats,
535 .get_strings = stmmac_get_strings,
536 .get_wol = stmmac_get_wol,
537 .set_wol = stmmac_set_wol,
538 .get_eee = stmmac_ethtool_op_get_eee,
539 .set_eee = stmmac_ethtool_op_set_eee,
540 .get_sset_count = stmmac_get_sset_count,
541 .get_ts_info = ethtool_op_get_ts_info,
542 };
543
544 void stmmac_set_ethtool_ops(struct net_device *netdev)
545 {
546 SET_ETHTOOL_OPS(netdev, &stmmac_ethtool_ops);
547 }
Linux ARM platform port for MOXA ART SoC