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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
blobc6cdbc4eb05e613cd499cc35af4ee56300cafcf8
1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
34 #include <linux/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
41 #include <linux/if.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #ifdef CONFIG_STMMAC_DEBUG_FS
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #endif
50 #include "stmmac.h"
51
52 #undef STMMAC_DEBUG
53 /*#define STMMAC_DEBUG*/
54 #ifdef STMMAC_DEBUG
55 #define DBG(nlevel, klevel, fmt, args...) \
56 ((void)(netif_msg_##nlevel(priv) && \
57 printk(KERN_##klevel fmt, ## args)))
58 #else
59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
60 #endif
61
62 #undef STMMAC_RX_DEBUG
63 /*#define STMMAC_RX_DEBUG*/
64 #ifdef STMMAC_RX_DEBUG
65 #define RX_DBG(fmt, args...) printk(fmt, ## args)
66 #else
67 #define RX_DBG(fmt, args...) do { } while (0)
68 #endif
69
70 #undef STMMAC_XMIT_DEBUG
71 /*#define STMMAC_XMIT_DEBUG*/
72 #ifdef STMMAC_TX_DEBUG
73 #define TX_DBG(fmt, args...) printk(fmt, ## args)
74 #else
75 #define TX_DBG(fmt, args...) do { } while (0)
76 #endif
77
78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
79 #define JUMBO_LEN 9000
80
81 /* Module parameters */
82 #define TX_TIMEO 5000 /* default 5 seconds */
83 static int watchdog = TX_TIMEO;
84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
86
87 static int debug = -1; /* -1: default, 0: no output, 16: all */
88 module_param(debug, int, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
90
91 int phyaddr = -1;
92 module_param(phyaddr, int, S_IRUGO);
93 MODULE_PARM_DESC(phyaddr, "Physical device address");
94
95 #define DMA_TX_SIZE 256
96 static int dma_txsize = DMA_TX_SIZE;
97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
99
100 #define DMA_RX_SIZE 256
101 static int dma_rxsize = DMA_RX_SIZE;
102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
104
105 static int flow_ctrl = FLOW_OFF;
106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
108
109 static int pause = PAUSE_TIME;
110 module_param(pause, int, S_IRUGO | S_IWUSR);
111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
112
113 #define TC_DEFAULT 64
114 static int tc = TC_DEFAULT;
115 module_param(tc, int, S_IRUGO | S_IWUSR);
116 MODULE_PARM_DESC(tc, "DMA threshold control value");
117
118 /* Pay attention to tune this parameter; take care of both
119 * hardware capability and network stabitily/performance impact.
120 * Many tests showed that ~4ms latency seems to be good enough. */
121 #ifdef CONFIG_STMMAC_TIMER
122 #define DEFAULT_PERIODIC_RATE 256
123 static int tmrate = DEFAULT_PERIODIC_RATE;
124 module_param(tmrate, int, S_IRUGO | S_IWUSR);
125 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
126 #endif
127
128 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
129 static int buf_sz = DMA_BUFFER_SIZE;
130 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
131 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
132
133 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
134 NETIF_MSG_LINK | NETIF_MSG_IFUP |
135 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
136
137 #define STMMAC_DEFAULT_LPI_TIMER 1000
138 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
139 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
140 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
141 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
142
143 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
144
145 #ifdef CONFIG_STMMAC_DEBUG_FS
146 static int stmmac_init_fs(struct net_device *dev);
147 static void stmmac_exit_fs(void);
148 #endif
149
150 /**
151 * stmmac_verify_args - verify the driver parameters.
152 * Description: it verifies if some wrong parameter is passed to the driver.
153 * Note that wrong parameters are replaced with the default values.
154 */
155 static void stmmac_verify_args(void)
156 {
157 if (unlikely(watchdog < 0))
158 watchdog = TX_TIMEO;
159 if (unlikely(dma_rxsize < 0))
160 dma_rxsize = DMA_RX_SIZE;
161 if (unlikely(dma_txsize < 0))
162 dma_txsize = DMA_TX_SIZE;
163 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
164 buf_sz = DMA_BUFFER_SIZE;
165 if (unlikely(flow_ctrl > 1))
166 flow_ctrl = FLOW_AUTO;
167 else if (likely(flow_ctrl < 0))
168 flow_ctrl = FLOW_OFF;
169 if (unlikely((pause < 0) || (pause > 0xffff)))
170 pause = PAUSE_TIME;
171 if (eee_timer < 0)
172 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
173 }
174
175 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
176 {
177 u32 clk_rate;
178
179 clk_rate = clk_get_rate(priv->stmmac_clk);
180
181 /* Platform provided default clk_csr would be assumed valid
182 * for all other cases except for the below mentioned ones. */
183 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
184 if (clk_rate < CSR_F_35M)
185 priv->clk_csr = STMMAC_CSR_20_35M;
186 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
187 priv->clk_csr = STMMAC_CSR_35_60M;
188 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
189 priv->clk_csr = STMMAC_CSR_60_100M;
190 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
191 priv->clk_csr = STMMAC_CSR_100_150M;
192 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
193 priv->clk_csr = STMMAC_CSR_150_250M;
194 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
195 priv->clk_csr = STMMAC_CSR_250_300M;
196 } /* For values higher than the IEEE 802.3 specified frequency
197 * we can not estimate the proper divider as it is not known
198 * the frequency of clk_csr_i. So we do not change the default
199 * divider. */
200 }
201
202 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
203 static void print_pkt(unsigned char *buf, int len)
204 {
205 int j;
206 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
207 for (j = 0; j < len; j++) {
208 if ((j % 16) == 0)
209 pr_info("\n %03x:", j);
210 pr_info(" %02x", buf[j]);
211 }
212 pr_info("\n");
213 }
214 #endif
215
216 /* minimum number of free TX descriptors required to wake up TX process */
217 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
218
219 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
220 {
221 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
222 }
223
224 /* On some ST platforms, some HW system configuraton registers have to be
225 * set according to the link speed negotiated.
226 */
227 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
228 {
229 struct phy_device *phydev = priv->phydev;
230
231 if (likely(priv->plat->fix_mac_speed))
232 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
233 phydev->speed);
234 }
235
236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
237 {
238 /* Check and enter in LPI mode */
239 if ((priv->dirty_tx == priv->cur_tx) &&
240 (priv->tx_path_in_lpi_mode == false))
241 priv->hw->mac->set_eee_mode(priv->ioaddr);
242 }
243
244 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
245 {
246 /* Exit and disable EEE in case of we are are in LPI state. */
247 priv->hw->mac->reset_eee_mode(priv->ioaddr);
248 del_timer_sync(&priv->eee_ctrl_timer);
249 priv->tx_path_in_lpi_mode = false;
250 }
251
252 /**
253 * stmmac_eee_ctrl_timer
254 * @arg : data hook
255 * Description:
256 * If there is no data transfer and if we are not in LPI state,
257 * then MAC Transmitter can be moved to LPI state.
258 */
259 static void stmmac_eee_ctrl_timer(unsigned long arg)
260 {
261 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
262
263 stmmac_enable_eee_mode(priv);
264 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
265 }
266
267 /**
268 * stmmac_eee_init
269 * @priv: private device pointer
270 * Description:
271 * If the EEE support has been enabled while configuring the driver,
272 * if the GMAC actually supports the EEE (from the HW cap reg) and the
273 * phy can also manage EEE, so enable the LPI state and start the timer
274 * to verify if the tx path can enter in LPI state.
275 */
276 bool stmmac_eee_init(struct stmmac_priv *priv)
277 {
278 bool ret = false;
279
280 /* MAC core supports the EEE feature. */
281 if (priv->dma_cap.eee) {
282 /* Check if the PHY supports EEE */
283 if (phy_init_eee(priv->phydev, 1))
284 goto out;
285
286 priv->eee_active = 1;
287 init_timer(&priv->eee_ctrl_timer);
288 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
289 priv->eee_ctrl_timer.data = (unsigned long)priv;
290 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
291 add_timer(&priv->eee_ctrl_timer);
292
293 priv->hw->mac->set_eee_timer(priv->ioaddr,
294 STMMAC_DEFAULT_LIT_LS_TIMER,
295 priv->tx_lpi_timer);
296
297 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
298
299 ret = true;
300 }
301 out:
302 return ret;
303 }
304
305 static void stmmac_eee_adjust(struct stmmac_priv *priv)
306 {
307 /* When the EEE has been already initialised we have to
308 * modify the PLS bit in the LPI ctrl & status reg according
309 * to the PHY link status. For this reason.
310 */
311 if (priv->eee_enabled)
312 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
313 }
314
315 /**
316 * stmmac_adjust_link
317 * @dev: net device structure
318 * Description: it adjusts the link parameters.
319 */
320 static void stmmac_adjust_link(struct net_device *dev)
321 {
322 struct stmmac_priv *priv = netdev_priv(dev);
323 struct phy_device *phydev = priv->phydev;
324 unsigned long flags;
325 int new_state = 0;
326 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
327
328 if (phydev == NULL)
329 return;
330
331 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
332 phydev->addr, phydev->link);
333
334 spin_lock_irqsave(&priv->lock, flags);
335
336 if (phydev->link) {
337 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
338
339 /* Now we make sure that we can be in full duplex mode.
340 * If not, we operate in half-duplex mode. */
341 if (phydev->duplex != priv->oldduplex) {
342 new_state = 1;
343 if (!(phydev->duplex))
344 ctrl &= ~priv->hw->link.duplex;
345 else
346 ctrl |= priv->hw->link.duplex;
347 priv->oldduplex = phydev->duplex;
348 }
349 /* Flow Control operation */
350 if (phydev->pause)
351 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
352 fc, pause_time);
353
354 if (phydev->speed != priv->speed) {
355 new_state = 1;
356 switch (phydev->speed) {
357 case 1000:
358 if (likely(priv->plat->has_gmac))
359 ctrl &= ~priv->hw->link.port;
360 stmmac_hw_fix_mac_speed(priv);
361 break;
362 case 100:
363 case 10:
364 if (priv->plat->has_gmac) {
365 ctrl |= priv->hw->link.port;
366 if (phydev->speed == SPEED_100) {
367 ctrl |= priv->hw->link.speed;
368 } else {
369 ctrl &= ~(priv->hw->link.speed);
370 }
371 } else {
372 ctrl &= ~priv->hw->link.port;
373 }
374 stmmac_hw_fix_mac_speed(priv);
375 break;
376 default:
377 if (netif_msg_link(priv))
378 pr_warning("%s: Speed (%d) is not 10"
379 " or 100!\n", dev->name, phydev->speed);
380 break;
381 }
382
383 priv->speed = phydev->speed;
384 }
385
386 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
387
388 if (!priv->oldlink) {
389 new_state = 1;
390 priv->oldlink = 1;
391 }
392 } else if (priv->oldlink) {
393 new_state = 1;
394 priv->oldlink = 0;
395 priv->speed = 0;
396 priv->oldduplex = -1;
397 }
398
399 if (new_state && netif_msg_link(priv))
400 phy_print_status(phydev);
401
402 stmmac_eee_adjust(priv);
403
404 spin_unlock_irqrestore(&priv->lock, flags);
405
406 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
407 }
408
409 /**
410 * stmmac_init_phy - PHY initialization
411 * @dev: net device structure
412 * Description: it initializes the driver's PHY state, and attaches the PHY
413 * to the mac driver.
414 * Return value:
415 * 0 on success
416 */
417 static int stmmac_init_phy(struct net_device *dev)
418 {
419 struct stmmac_priv *priv = netdev_priv(dev);
420 struct phy_device *phydev;
421 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
422 char bus_id[MII_BUS_ID_SIZE];
423 int interface = priv->plat->interface;
424 priv->oldlink = 0;
425 priv->speed = 0;
426 priv->oldduplex = -1;
427
428 if (priv->plat->phy_bus_name)
429 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
430 priv->plat->phy_bus_name, priv->plat->bus_id);
431 else
432 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
433 priv->plat->bus_id);
434
435 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
436 priv->plat->phy_addr);
437 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
438
439 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 0,
440 interface);
441
442 if (IS_ERR(phydev)) {
443 pr_err("%s: Could not attach to PHY\n", dev->name);
444 return PTR_ERR(phydev);
445 }
446
447 /* Stop Advertising 1000BASE Capability if interface is not GMII */
448 if ((interface == PHY_INTERFACE_MODE_MII) ||
449 (interface == PHY_INTERFACE_MODE_RMII))
450 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
451 SUPPORTED_1000baseT_Full);
452
453 /*
454 * Broken HW is sometimes missing the pull-up resistor on the
455 * MDIO line, which results in reads to non-existent devices returning
456 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
457 * device as well.
458 * Note: phydev->phy_id is the result of reading the UID PHY registers.
459 */
460 if (phydev->phy_id == 0) {
461 phy_disconnect(phydev);
462 return -ENODEV;
463 }
464 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
465 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
466
467 priv->phydev = phydev;
468
469 return 0;
470 }
471
472 /**
473 * display_ring
474 * @p: pointer to the ring.
475 * @size: size of the ring.
476 * Description: display all the descriptors within the ring.
477 */
478 static void display_ring(struct dma_desc *p, int size)
479 {
480 struct tmp_s {
481 u64 a;
482 unsigned int b;
483 unsigned int c;
484 };
485 int i;
486 for (i = 0; i < size; i++) {
487 struct tmp_s *x = (struct tmp_s *)(p + i);
488 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
489 i, (unsigned int)virt_to_phys(&p[i]),
490 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
491 x->b, x->c);
492 pr_info("\n");
493 }
494 }
495
496 static int stmmac_set_bfsize(int mtu, int bufsize)
497 {
498 int ret = bufsize;
499
500 if (mtu >= BUF_SIZE_4KiB)
501 ret = BUF_SIZE_8KiB;
502 else if (mtu >= BUF_SIZE_2KiB)
503 ret = BUF_SIZE_4KiB;
504 else if (mtu >= DMA_BUFFER_SIZE)
505 ret = BUF_SIZE_2KiB;
506 else
507 ret = DMA_BUFFER_SIZE;
508
509 return ret;
510 }
511
512 /**
513 * init_dma_desc_rings - init the RX/TX descriptor rings
514 * @dev: net device structure
515 * Description: this function initializes the DMA RX/TX descriptors
516 * and allocates the socket buffers. It suppors the chained and ring
517 * modes.
518 */
519 static void init_dma_desc_rings(struct net_device *dev)
520 {
521 int i;
522 struct stmmac_priv *priv = netdev_priv(dev);
523 struct sk_buff *skb;
524 unsigned int txsize = priv->dma_tx_size;
525 unsigned int rxsize = priv->dma_rx_size;
526 unsigned int bfsize;
527 int dis_ic = 0;
528 int des3_as_data_buf = 0;
529
530 /* Set the max buffer size according to the DESC mode
531 * and the MTU. Note that RING mode allows 16KiB bsize. */
532 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
533
534 if (bfsize == BUF_SIZE_16KiB)
535 des3_as_data_buf = 1;
536 else
537 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
538
539 #ifdef CONFIG_STMMAC_TIMER
540 /* Disable interrupts on completion for the reception if timer is on */
541 if (likely(priv->tm->enable))
542 dis_ic = 1;
543 #endif
544
545 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
546 txsize, rxsize, bfsize);
547
548 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
549 priv->rx_skbuff =
550 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
551 priv->dma_rx =
552 (struct dma_desc *)dma_alloc_coherent(priv->device,
553 rxsize *
554 sizeof(struct dma_desc),
555 &priv->dma_rx_phy,
556 GFP_KERNEL);
557 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
558 GFP_KERNEL);
559 priv->dma_tx =
560 (struct dma_desc *)dma_alloc_coherent(priv->device,
561 txsize *
562 sizeof(struct dma_desc),
563 &priv->dma_tx_phy,
564 GFP_KERNEL);
565
566 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
567 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
568 return;
569 }
570
571 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
572 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
573 dev->name, priv->dma_rx, priv->dma_tx,
574 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
575
576 /* RX INITIALIZATION */
577 DBG(probe, INFO, "stmmac: SKB addresses:\n"
578 "skb\t\tskb data\tdma data\n");
579
580 for (i = 0; i < rxsize; i++) {
581 struct dma_desc *p = priv->dma_rx + i;
582
583 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
584 GFP_KERNEL);
585 if (unlikely(skb == NULL)) {
586 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
587 break;
588 }
589 skb_reserve(skb, NET_IP_ALIGN);
590 priv->rx_skbuff[i] = skb;
591 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
592 bfsize, DMA_FROM_DEVICE);
593
594 p->des2 = priv->rx_skbuff_dma[i];
595
596 priv->hw->ring->init_desc3(des3_as_data_buf, p);
597
598 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
599 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
600 }
601 priv->cur_rx = 0;
602 priv->dirty_rx = (unsigned int)(i - rxsize);
603 priv->dma_buf_sz = bfsize;
604 buf_sz = bfsize;
605
606 /* TX INITIALIZATION */
607 for (i = 0; i < txsize; i++) {
608 priv->tx_skbuff[i] = NULL;
609 priv->dma_tx[i].des2 = 0;
610 }
611
612 /* In case of Chained mode this sets the des3 to the next
613 * element in the chain */
614 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
615 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
616
617 priv->dirty_tx = 0;
618 priv->cur_tx = 0;
619
620 /* Clear the Rx/Tx descriptors */
621 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
622 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
623
624 if (netif_msg_hw(priv)) {
625 pr_info("RX descriptor ring:\n");
626 display_ring(priv->dma_rx, rxsize);
627 pr_info("TX descriptor ring:\n");
628 display_ring(priv->dma_tx, txsize);
629 }
630 }
631
632 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
633 {
634 int i;
635
636 for (i = 0; i < priv->dma_rx_size; i++) {
637 if (priv->rx_skbuff[i]) {
638 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
639 priv->dma_buf_sz, DMA_FROM_DEVICE);
640 dev_kfree_skb_any(priv->rx_skbuff[i]);
641 }
642 priv->rx_skbuff[i] = NULL;
643 }
644 }
645
646 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
647 {
648 int i;
649
650 for (i = 0; i < priv->dma_tx_size; i++) {
651 if (priv->tx_skbuff[i] != NULL) {
652 struct dma_desc *p = priv->dma_tx + i;
653 if (p->des2)
654 dma_unmap_single(priv->device, p->des2,
655 priv->hw->desc->get_tx_len(p),
656 DMA_TO_DEVICE);
657 dev_kfree_skb_any(priv->tx_skbuff[i]);
658 priv->tx_skbuff[i] = NULL;
659 }
660 }
661 }
662
663 static void free_dma_desc_resources(struct stmmac_priv *priv)
664 {
665 /* Release the DMA TX/RX socket buffers */
666 dma_free_rx_skbufs(priv);
667 dma_free_tx_skbufs(priv);
668
669 /* Free the region of consistent memory previously allocated for
670 * the DMA */
671 dma_free_coherent(priv->device,
672 priv->dma_tx_size * sizeof(struct dma_desc),
673 priv->dma_tx, priv->dma_tx_phy);
674 dma_free_coherent(priv->device,
675 priv->dma_rx_size * sizeof(struct dma_desc),
676 priv->dma_rx, priv->dma_rx_phy);
677 kfree(priv->rx_skbuff_dma);
678 kfree(priv->rx_skbuff);
679 kfree(priv->tx_skbuff);
680 }
681
682 /**
683 * stmmac_dma_operation_mode - HW DMA operation mode
684 * @priv : pointer to the private device structure.
685 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
686 * or Store-And-Forward capability.
687 */
688 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
689 {
690 if (likely(priv->plat->force_sf_dma_mode ||
691 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
692 /*
693 * In case of GMAC, SF mode can be enabled
694 * to perform the TX COE in HW. This depends on:
695 * 1) TX COE if actually supported
696 * 2) There is no bugged Jumbo frame support
697 * that needs to not insert csum in the TDES.
698 */
699 priv->hw->dma->dma_mode(priv->ioaddr,
700 SF_DMA_MODE, SF_DMA_MODE);
701 tc = SF_DMA_MODE;
702 } else
703 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
704 }
705
706 /**
707 * stmmac_tx:
708 * @priv: private driver structure
709 * Description: it reclaims resources after transmission completes.
710 */
711 static void stmmac_tx(struct stmmac_priv *priv)
712 {
713 unsigned int txsize = priv->dma_tx_size;
714
715 spin_lock(&priv->tx_lock);
716
717 while (priv->dirty_tx != priv->cur_tx) {
718 int last;
719 unsigned int entry = priv->dirty_tx % txsize;
720 struct sk_buff *skb = priv->tx_skbuff[entry];
721 struct dma_desc *p = priv->dma_tx + entry;
722
723 /* Check if the descriptor is owned by the DMA. */
724 if (priv->hw->desc->get_tx_owner(p))
725 break;
726
727 /* Verify tx error by looking at the last segment */
728 last = priv->hw->desc->get_tx_ls(p);
729 if (likely(last)) {
730 int tx_error =
731 priv->hw->desc->tx_status(&priv->dev->stats,
732 &priv->xstats, p,
733 priv->ioaddr);
734 if (likely(tx_error == 0)) {
735 priv->dev->stats.tx_packets++;
736 priv->xstats.tx_pkt_n++;
737 } else
738 priv->dev->stats.tx_errors++;
739 }
740 TX_DBG("%s: curr %d, dirty %d\n", __func__,
741 priv->cur_tx, priv->dirty_tx);
742
743 if (likely(p->des2))
744 dma_unmap_single(priv->device, p->des2,
745 priv->hw->desc->get_tx_len(p),
746 DMA_TO_DEVICE);
747 priv->hw->ring->clean_desc3(p);
748
749 if (likely(skb != NULL)) {
750 dev_kfree_skb(skb);
751 priv->tx_skbuff[entry] = NULL;
752 }
753
754 priv->hw->desc->release_tx_desc(p);
755
756 priv->dirty_tx++;
757 }
758 if (unlikely(netif_queue_stopped(priv->dev) &&
759 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
760 netif_tx_lock(priv->dev);
761 if (netif_queue_stopped(priv->dev) &&
762 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
763 TX_DBG("%s: restart transmit\n", __func__);
764 netif_wake_queue(priv->dev);
765 }
766 netif_tx_unlock(priv->dev);
767 }
768
769 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
770 stmmac_enable_eee_mode(priv);
771 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
772 }
773 spin_unlock(&priv->tx_lock);
774 }
775
776 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
777 {
778 #ifdef CONFIG_STMMAC_TIMER
779 if (likely(priv->tm->enable))
780 priv->tm->timer_start(tmrate);
781 else
782 #endif
783 priv->hw->dma->enable_dma_irq(priv->ioaddr);
784 }
785
786 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
787 {
788 #ifdef CONFIG_STMMAC_TIMER
789 if (likely(priv->tm->enable))
790 priv->tm->timer_stop();
791 else
792 #endif
793 priv->hw->dma->disable_dma_irq(priv->ioaddr);
794 }
795
796 static int stmmac_has_work(struct stmmac_priv *priv)
797 {
798 unsigned int has_work = 0;
799 int rxret, tx_work = 0;
800
801 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
802 (priv->cur_rx % priv->dma_rx_size));
803
804 if (priv->dirty_tx != priv->cur_tx)
805 tx_work = 1;
806
807 if (likely(!rxret || tx_work))
808 has_work = 1;
809
810 return has_work;
811 }
812
813 static inline void _stmmac_schedule(struct stmmac_priv *priv)
814 {
815 if (likely(stmmac_has_work(priv))) {
816 stmmac_disable_irq(priv);
817 napi_schedule(&priv->napi);
818 }
819 }
820
821 #ifdef CONFIG_STMMAC_TIMER
822 void stmmac_schedule(struct net_device *dev)
823 {
824 struct stmmac_priv *priv = netdev_priv(dev);
825
826 priv->xstats.sched_timer_n++;
827
828 _stmmac_schedule(priv);
829 }
830
831 static void stmmac_no_timer_started(unsigned int x)
832 {;
833 };
834
835 static void stmmac_no_timer_stopped(void)
836 {;
837 };
838 #endif
839
840 /**
841 * stmmac_tx_err:
842 * @priv: pointer to the private device structure
843 * Description: it cleans the descriptors and restarts the transmission
844 * in case of errors.
845 */
846 static void stmmac_tx_err(struct stmmac_priv *priv)
847 {
848 netif_stop_queue(priv->dev);
849
850 priv->hw->dma->stop_tx(priv->ioaddr);
851 dma_free_tx_skbufs(priv);
852 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
853 priv->dirty_tx = 0;
854 priv->cur_tx = 0;
855 priv->hw->dma->start_tx(priv->ioaddr);
856
857 priv->dev->stats.tx_errors++;
858 netif_wake_queue(priv->dev);
859 }
860
861
862 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
863 {
864 int status;
865
866 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
867 if (likely(status == handle_tx_rx))
868 _stmmac_schedule(priv);
869
870 else if (unlikely(status == tx_hard_error_bump_tc)) {
871 /* Try to bump up the dma threshold on this failure */
872 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
873 tc += 64;
874 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
875 priv->xstats.threshold = tc;
876 }
877 } else if (unlikely(status == tx_hard_error))
878 stmmac_tx_err(priv);
879 }
880
881 static void stmmac_mmc_setup(struct stmmac_priv *priv)
882 {
883 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
884 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
885
886 /* Mask MMC irq, counters are managed in SW and registers
887 * are cleared on each READ eventually. */
888 dwmac_mmc_intr_all_mask(priv->ioaddr);
889
890 if (priv->dma_cap.rmon) {
891 dwmac_mmc_ctrl(priv->ioaddr, mode);
892 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
893 } else
894 pr_info(" No MAC Management Counters available\n");
895 }
896
897 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
898 {
899 u32 hwid = priv->hw->synopsys_uid;
900
901 /* Only check valid Synopsys Id because old MAC chips
902 * have no HW registers where get the ID */
903 if (likely(hwid)) {
904 u32 uid = ((hwid & 0x0000ff00) >> 8);
905 u32 synid = (hwid & 0x000000ff);
906
907 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
908 uid, synid);
909
910 return synid;
911 }
912 return 0;
913 }
914
915 /**
916 * stmmac_selec_desc_mode
917 * @priv : private structure
918 * Description: select the Enhanced/Alternate or Normal descriptors
919 */
920 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
921 {
922 if (priv->plat->enh_desc) {
923 pr_info(" Enhanced/Alternate descriptors\n");
924 priv->hw->desc = &enh_desc_ops;
925 } else {
926 pr_info(" Normal descriptors\n");
927 priv->hw->desc = &ndesc_ops;
928 }
929 }
930
931 /**
932 * stmmac_get_hw_features
933 * @priv : private device pointer
934 * Description:
935 * new GMAC chip generations have a new register to indicate the
936 * presence of the optional feature/functions.
937 * This can be also used to override the value passed through the
938 * platform and necessary for old MAC10/100 and GMAC chips.
939 */
940 static int stmmac_get_hw_features(struct stmmac_priv *priv)
941 {
942 u32 hw_cap = 0;
943
944 if (priv->hw->dma->get_hw_feature) {
945 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
946
947 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
948 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
949 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
950 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
951 priv->dma_cap.multi_addr =
952 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
953 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
954 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
955 priv->dma_cap.pmt_remote_wake_up =
956 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
957 priv->dma_cap.pmt_magic_frame =
958 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
959 /* MMC */
960 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
961 /* IEEE 1588-2002*/
962 priv->dma_cap.time_stamp =
963 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
964 /* IEEE 1588-2008*/
965 priv->dma_cap.atime_stamp =
966 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
967 /* 802.3az - Energy-Efficient Ethernet (EEE) */
968 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
969 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
970 /* TX and RX csum */
971 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
972 priv->dma_cap.rx_coe_type1 =
973 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
974 priv->dma_cap.rx_coe_type2 =
975 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
976 priv->dma_cap.rxfifo_over_2048 =
977 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
978 /* TX and RX number of channels */
979 priv->dma_cap.number_rx_channel =
980 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
981 priv->dma_cap.number_tx_channel =
982 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
983 /* Alternate (enhanced) DESC mode*/
984 priv->dma_cap.enh_desc =
985 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
986
987 }
988
989 return hw_cap;
990 }
991
992 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
993 {
994 /* verify if the MAC address is valid, in case of failures it
995 * generates a random MAC address */
996 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
997 priv->hw->mac->get_umac_addr((void __iomem *)
998 priv->dev->base_addr,
999 priv->dev->dev_addr, 0);
1000 if (!is_valid_ether_addr(priv->dev->dev_addr))
1001 eth_hw_addr_random(priv->dev);
1002 }
1003 pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1004 priv->dev->dev_addr);
1005 }
1006
1007 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1008 {
1009 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1010 int mixed_burst = 0;
1011
1012 /* Some DMA parameters can be passed from the platform;
1013 * in case of these are not passed we keep a default
1014 * (good for all the chips) and init the DMA! */
1015 if (priv->plat->dma_cfg) {
1016 pbl = priv->plat->dma_cfg->pbl;
1017 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1018 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1019 burst_len = priv->plat->dma_cfg->burst_len;
1020 }
1021
1022 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1023 burst_len, priv->dma_tx_phy,
1024 priv->dma_rx_phy);
1025 }
1026
1027 /**
1028 * stmmac_open - open entry point of the driver
1029 * @dev : pointer to the device structure.
1030 * Description:
1031 * This function is the open entry point of the driver.
1032 * Return value:
1033 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1034 * file on failure.
1035 */
1036 static int stmmac_open(struct net_device *dev)
1037 {
1038 struct stmmac_priv *priv = netdev_priv(dev);
1039 int ret;
1040
1041 #ifdef CONFIG_STMMAC_TIMER
1042 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
1043 if (unlikely(priv->tm == NULL))
1044 return -ENOMEM;
1045
1046 priv->tm->freq = tmrate;
1047
1048 /* Test if the external timer can be actually used.
1049 * In case of failure continue without timer. */
1050 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
1051 pr_warning("stmmaceth: cannot attach the external timer.\n");
1052 priv->tm->freq = 0;
1053 priv->tm->timer_start = stmmac_no_timer_started;
1054 priv->tm->timer_stop = stmmac_no_timer_stopped;
1055 } else
1056 priv->tm->enable = 1;
1057 #endif
1058 clk_prepare_enable(priv->stmmac_clk);
1059
1060 stmmac_check_ether_addr(priv);
1061
1062 ret = stmmac_init_phy(dev);
1063 if (unlikely(ret)) {
1064 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1065 goto open_error;
1066 }
1067
1068 /* Create and initialize the TX/RX descriptors chains. */
1069 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1070 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1071 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1072 init_dma_desc_rings(dev);
1073
1074 /* DMA initialization and SW reset */
1075 ret = stmmac_init_dma_engine(priv);
1076 if (ret < 0) {
1077 pr_err("%s: DMA initialization failed\n", __func__);
1078 goto open_error;
1079 }
1080
1081 /* Copy the MAC addr into the HW */
1082 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1083
1084 /* If required, perform hw setup of the bus. */
1085 if (priv->plat->bus_setup)
1086 priv->plat->bus_setup(priv->ioaddr);
1087
1088 /* Initialize the MAC Core */
1089 priv->hw->mac->core_init(priv->ioaddr);
1090
1091 /* Request the IRQ lines */
1092 ret = request_irq(dev->irq, stmmac_interrupt,
1093 IRQF_SHARED, dev->name, dev);
1094 if (unlikely(ret < 0)) {
1095 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1096 __func__, dev->irq, ret);
1097 goto open_error;
1098 }
1099
1100 /* Request the Wake IRQ in case of another line is used for WoL */
1101 if (priv->wol_irq != dev->irq) {
1102 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1103 IRQF_SHARED, dev->name, dev);
1104 if (unlikely(ret < 0)) {
1105 pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1106 "(error: %d)\n", __func__, priv->wol_irq, ret);
1107 goto open_error_wolirq;
1108 }
1109 }
1110
1111 /* Request the IRQ lines */
1112 if (priv->lpi_irq != -ENXIO) {
1113 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1114 dev->name, dev);
1115 if (unlikely(ret < 0)) {
1116 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1117 __func__, priv->lpi_irq, ret);
1118 goto open_error_lpiirq;
1119 }
1120 }
1121
1122 /* Enable the MAC Rx/Tx */
1123 stmmac_set_mac(priv->ioaddr, true);
1124
1125 /* Set the HW DMA mode and the COE */
1126 stmmac_dma_operation_mode(priv);
1127
1128 /* Extra statistics */
1129 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1130 priv->xstats.threshold = tc;
1131
1132 stmmac_mmc_setup(priv);
1133
1134 #ifdef CONFIG_STMMAC_DEBUG_FS
1135 ret = stmmac_init_fs(dev);
1136 if (ret < 0)
1137 pr_warning("%s: failed debugFS registration\n", __func__);
1138 #endif
1139 /* Start the ball rolling... */
1140 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1141 priv->hw->dma->start_tx(priv->ioaddr);
1142 priv->hw->dma->start_rx(priv->ioaddr);
1143
1144 #ifdef CONFIG_STMMAC_TIMER
1145 priv->tm->timer_start(tmrate);
1146 #endif
1147
1148 /* Dump DMA/MAC registers */
1149 if (netif_msg_hw(priv)) {
1150 priv->hw->mac->dump_regs(priv->ioaddr);
1151 priv->hw->dma->dump_regs(priv->ioaddr);
1152 }
1153
1154 if (priv->phydev)
1155 phy_start(priv->phydev);
1156
1157 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1158 priv->eee_enabled = stmmac_eee_init(priv);
1159
1160 napi_enable(&priv->napi);
1161 netif_start_queue(dev);
1162
1163 return 0;
1164
1165 open_error_lpiirq:
1166 if (priv->wol_irq != dev->irq)
1167 free_irq(priv->wol_irq, dev);
1168
1169 open_error_wolirq:
1170 free_irq(dev->irq, dev);
1171
1172 open_error:
1173 #ifdef CONFIG_STMMAC_TIMER
1174 kfree(priv->tm);
1175 #endif
1176 if (priv->phydev)
1177 phy_disconnect(priv->phydev);
1178
1179 clk_disable_unprepare(priv->stmmac_clk);
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * stmmac_release - close entry point of the driver
1186 * @dev : device pointer.
1187 * Description:
1188 * This is the stop entry point of the driver.
1189 */
1190 static int stmmac_release(struct net_device *dev)
1191 {
1192 struct stmmac_priv *priv = netdev_priv(dev);
1193
1194 if (priv->eee_enabled)
1195 del_timer_sync(&priv->eee_ctrl_timer);
1196
1197 /* Stop and disconnect the PHY */
1198 if (priv->phydev) {
1199 phy_stop(priv->phydev);
1200 phy_disconnect(priv->phydev);
1201 priv->phydev = NULL;
1202 }
1203
1204 netif_stop_queue(dev);
1205
1206 #ifdef CONFIG_STMMAC_TIMER
1207 /* Stop and release the timer */
1208 stmmac_close_ext_timer();
1209 if (priv->tm != NULL)
1210 kfree(priv->tm);
1211 #endif
1212 napi_disable(&priv->napi);
1213
1214 /* Free the IRQ lines */
1215 free_irq(dev->irq, dev);
1216 if (priv->wol_irq != dev->irq)
1217 free_irq(priv->wol_irq, dev);
1218 if (priv->lpi_irq != -ENXIO)
1219 free_irq(priv->lpi_irq, dev);
1220
1221 /* Stop TX/RX DMA and clear the descriptors */
1222 priv->hw->dma->stop_tx(priv->ioaddr);
1223 priv->hw->dma->stop_rx(priv->ioaddr);
1224
1225 /* Release and free the Rx/Tx resources */
1226 free_dma_desc_resources(priv);
1227
1228 /* Disable the MAC Rx/Tx */
1229 stmmac_set_mac(priv->ioaddr, false);
1230
1231 netif_carrier_off(dev);
1232
1233 #ifdef CONFIG_STMMAC_DEBUG_FS
1234 stmmac_exit_fs();
1235 #endif
1236 clk_disable_unprepare(priv->stmmac_clk);
1237
1238 return 0;
1239 }
1240
1241 /**
1242 * stmmac_xmit:
1243 * @skb : the socket buffer
1244 * @dev : device pointer
1245 * Description : Tx entry point of the driver.
1246 */
1247 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1248 {
1249 struct stmmac_priv *priv = netdev_priv(dev);
1250 unsigned int txsize = priv->dma_tx_size;
1251 unsigned int entry;
1252 int i, csum_insertion = 0;
1253 int nfrags = skb_shinfo(skb)->nr_frags;
1254 struct dma_desc *desc, *first;
1255 unsigned int nopaged_len = skb_headlen(skb);
1256
1257 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1258 if (!netif_queue_stopped(dev)) {
1259 netif_stop_queue(dev);
1260 /* This is a hard error, log it. */
1261 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1262 __func__);
1263 }
1264 return NETDEV_TX_BUSY;
1265 }
1266
1267 spin_lock(&priv->tx_lock);
1268
1269 if (priv->tx_path_in_lpi_mode)
1270 stmmac_disable_eee_mode(priv);
1271
1272 entry = priv->cur_tx % txsize;
1273
1274 #ifdef STMMAC_XMIT_DEBUG
1275 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1276 pr_info("stmmac xmit:\n"
1277 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1278 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1279 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1280 !skb_is_gso(skb) ? "isn't" : "is");
1281 #endif
1282
1283 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1284
1285 desc = priv->dma_tx + entry;
1286 first = desc;
1287
1288 #ifdef STMMAC_XMIT_DEBUG
1289 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1290 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1291 "\t\tn_frags: %d, ip_summed: %d\n",
1292 skb->len, nopaged_len, nfrags, skb->ip_summed);
1293 #endif
1294 priv->tx_skbuff[entry] = skb;
1295
1296 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1297 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1298 desc = priv->dma_tx + entry;
1299 } else {
1300 desc->des2 = dma_map_single(priv->device, skb->data,
1301 nopaged_len, DMA_TO_DEVICE);
1302 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1303 csum_insertion);
1304 }
1305
1306 for (i = 0; i < nfrags; i++) {
1307 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1308 int len = skb_frag_size(frag);
1309
1310 entry = (++priv->cur_tx) % txsize;
1311 desc = priv->dma_tx + entry;
1312
1313 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1314 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1315 DMA_TO_DEVICE);
1316 priv->tx_skbuff[entry] = NULL;
1317 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1318 wmb();
1319 priv->hw->desc->set_tx_owner(desc);
1320 wmb();
1321 }
1322
1323 /* Interrupt on completition only for the latest segment */
1324 priv->hw->desc->close_tx_desc(desc);
1325
1326 #ifdef CONFIG_STMMAC_TIMER
1327 /* Clean IC while using timer */
1328 if (likely(priv->tm->enable))
1329 priv->hw->desc->clear_tx_ic(desc);
1330 #endif
1331
1332 wmb();
1333
1334 /* To avoid raise condition */
1335 priv->hw->desc->set_tx_owner(first);
1336 wmb();
1337
1338 priv->cur_tx++;
1339
1340 #ifdef STMMAC_XMIT_DEBUG
1341 if (netif_msg_pktdata(priv)) {
1342 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1343 "first=%p, nfrags=%d\n",
1344 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1345 entry, first, nfrags);
1346 display_ring(priv->dma_tx, txsize);
1347 pr_info(">>> frame to be transmitted: ");
1348 print_pkt(skb->data, skb->len);
1349 }
1350 #endif
1351 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1352 TX_DBG("%s: stop transmitted packets\n", __func__);
1353 netif_stop_queue(dev);
1354 }
1355
1356 dev->stats.tx_bytes += skb->len;
1357
1358 skb_tx_timestamp(skb);
1359
1360 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1361
1362 spin_unlock(&priv->tx_lock);
1363
1364 return NETDEV_TX_OK;
1365 }
1366
1367 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1368 {
1369 unsigned int rxsize = priv->dma_rx_size;
1370 int bfsize = priv->dma_buf_sz;
1371 struct dma_desc *p = priv->dma_rx;
1372
1373 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1374 unsigned int entry = priv->dirty_rx % rxsize;
1375 if (likely(priv->rx_skbuff[entry] == NULL)) {
1376 struct sk_buff *skb;
1377
1378 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1379
1380 if (unlikely(skb == NULL))
1381 break;
1382
1383 priv->rx_skbuff[entry] = skb;
1384 priv->rx_skbuff_dma[entry] =
1385 dma_map_single(priv->device, skb->data, bfsize,
1386 DMA_FROM_DEVICE);
1387
1388 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1389
1390 if (unlikely(priv->plat->has_gmac))
1391 priv->hw->ring->refill_desc3(bfsize, p + entry);
1392
1393 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1394 }
1395 wmb();
1396 priv->hw->desc->set_rx_owner(p + entry);
1397 wmb();
1398 }
1399 }
1400
1401 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1402 {
1403 unsigned int rxsize = priv->dma_rx_size;
1404 unsigned int entry = priv->cur_rx % rxsize;
1405 unsigned int next_entry;
1406 unsigned int count = 0;
1407 struct dma_desc *p = priv->dma_rx + entry;
1408 struct dma_desc *p_next;
1409
1410 #ifdef STMMAC_RX_DEBUG
1411 if (netif_msg_hw(priv)) {
1412 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1413 display_ring(priv->dma_rx, rxsize);
1414 }
1415 #endif
1416 while (!priv->hw->desc->get_rx_owner(p)) {
1417 int status;
1418
1419 if (count >= limit)
1420 break;
1421
1422 count++;
1423
1424 next_entry = (++priv->cur_rx) % rxsize;
1425 p_next = priv->dma_rx + next_entry;
1426 prefetch(p_next);
1427
1428 /* read the status of the incoming frame */
1429 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1430 &priv->xstats, p));
1431 if (unlikely(status == discard_frame))
1432 priv->dev->stats.rx_errors++;
1433 else {
1434 struct sk_buff *skb;
1435 int frame_len;
1436
1437 frame_len = priv->hw->desc->get_rx_frame_len(p,
1438 priv->plat->rx_coe);
1439 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1440 * Type frames (LLC/LLC-SNAP) */
1441 if (unlikely(status != llc_snap))
1442 frame_len -= ETH_FCS_LEN;
1443 #ifdef STMMAC_RX_DEBUG
1444 if (frame_len > ETH_FRAME_LEN)
1445 pr_debug("\tRX frame size %d, COE status: %d\n",
1446 frame_len, status);
1447
1448 if (netif_msg_hw(priv))
1449 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1450 p, entry, p->des2);
1451 #endif
1452 skb = priv->rx_skbuff[entry];
1453 if (unlikely(!skb)) {
1454 pr_err("%s: Inconsistent Rx descriptor chain\n",
1455 priv->dev->name);
1456 priv->dev->stats.rx_dropped++;
1457 break;
1458 }
1459 prefetch(skb->data - NET_IP_ALIGN);
1460 priv->rx_skbuff[entry] = NULL;
1461
1462 skb_put(skb, frame_len);
1463 dma_unmap_single(priv->device,
1464 priv->rx_skbuff_dma[entry],
1465 priv->dma_buf_sz, DMA_FROM_DEVICE);
1466 #ifdef STMMAC_RX_DEBUG
1467 if (netif_msg_pktdata(priv)) {
1468 pr_info(" frame received (%dbytes)", frame_len);
1469 print_pkt(skb->data, frame_len);
1470 }
1471 #endif
1472 skb->protocol = eth_type_trans(skb, priv->dev);
1473
1474 if (unlikely(!priv->plat->rx_coe)) {
1475 /* No RX COE for old mac10/100 devices */
1476 skb_checksum_none_assert(skb);
1477 netif_receive_skb(skb);
1478 } else {
1479 skb->ip_summed = CHECKSUM_UNNECESSARY;
1480 napi_gro_receive(&priv->napi, skb);
1481 }
1482
1483 priv->dev->stats.rx_packets++;
1484 priv->dev->stats.rx_bytes += frame_len;
1485 }
1486 entry = next_entry;
1487 p = p_next; /* use prefetched values */
1488 }
1489
1490 stmmac_rx_refill(priv);
1491
1492 priv->xstats.rx_pkt_n += count;
1493
1494 return count;
1495 }
1496
1497 /**
1498 * stmmac_poll - stmmac poll method (NAPI)
1499 * @napi : pointer to the napi structure.
1500 * @budget : maximum number of packets that the current CPU can receive from
1501 * all interfaces.
1502 * Description :
1503 * This function implements the the reception process.
1504 * Also it runs the TX completion thread
1505 */
1506 static int stmmac_poll(struct napi_struct *napi, int budget)
1507 {
1508 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1509 int work_done = 0;
1510
1511 priv->xstats.poll_n++;
1512 stmmac_tx(priv);
1513 work_done = stmmac_rx(priv, budget);
1514
1515 if (work_done < budget) {
1516 napi_complete(napi);
1517 stmmac_enable_irq(priv);
1518 }
1519 return work_done;
1520 }
1521
1522 /**
1523 * stmmac_tx_timeout
1524 * @dev : Pointer to net device structure
1525 * Description: this function is called when a packet transmission fails to
1526 * complete within a reasonable tmrate. The driver will mark the error in the
1527 * netdev structure and arrange for the device to be reset to a sane state
1528 * in order to transmit a new packet.
1529 */
1530 static void stmmac_tx_timeout(struct net_device *dev)
1531 {
1532 struct stmmac_priv *priv = netdev_priv(dev);
1533
1534 /* Clear Tx resources and restart transmitting again */
1535 stmmac_tx_err(priv);
1536 }
1537
1538 /* Configuration changes (passed on by ifconfig) */
1539 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1540 {
1541 if (dev->flags & IFF_UP) /* can't act on a running interface */
1542 return -EBUSY;
1543
1544 /* Don't allow changing the I/O address */
1545 if (map->base_addr != dev->base_addr) {
1546 pr_warning("%s: can't change I/O address\n", dev->name);
1547 return -EOPNOTSUPP;
1548 }
1549
1550 /* Don't allow changing the IRQ */
1551 if (map->irq != dev->irq) {
1552 pr_warning("%s: can't change IRQ number %d\n",
1553 dev->name, dev->irq);
1554 return -EOPNOTSUPP;
1555 }
1556
1557 /* ignore other fields */
1558 return 0;
1559 }
1560
1561 /**
1562 * stmmac_set_rx_mode - entry point for multicast addressing
1563 * @dev : pointer to the device structure
1564 * Description:
1565 * This function is a driver entry point which gets called by the kernel
1566 * whenever multicast addresses must be enabled/disabled.
1567 * Return value:
1568 * void.
1569 */
1570 static void stmmac_set_rx_mode(struct net_device *dev)
1571 {
1572 struct stmmac_priv *priv = netdev_priv(dev);
1573
1574 spin_lock(&priv->lock);
1575 priv->hw->mac->set_filter(dev, priv->synopsys_id);
1576 spin_unlock(&priv->lock);
1577 }
1578
1579 /**
1580 * stmmac_change_mtu - entry point to change MTU size for the device.
1581 * @dev : device pointer.
1582 * @new_mtu : the new MTU size for the device.
1583 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1584 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1585 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1586 * Return value:
1587 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1588 * file on failure.
1589 */
1590 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1591 {
1592 struct stmmac_priv *priv = netdev_priv(dev);
1593 int max_mtu;
1594
1595 if (netif_running(dev)) {
1596 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1597 return -EBUSY;
1598 }
1599
1600 if (priv->plat->enh_desc)
1601 max_mtu = JUMBO_LEN;
1602 else
1603 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1604
1605 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1606 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1607 return -EINVAL;
1608 }
1609
1610 dev->mtu = new_mtu;
1611 netdev_update_features(dev);
1612
1613 return 0;
1614 }
1615
1616 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1617 netdev_features_t features)
1618 {
1619 struct stmmac_priv *priv = netdev_priv(dev);
1620
1621 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1622 features &= ~NETIF_F_RXCSUM;
1623 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1624 features &= ~NETIF_F_IPV6_CSUM;
1625 if (!priv->plat->tx_coe)
1626 features &= ~NETIF_F_ALL_CSUM;
1627
1628 /* Some GMAC devices have a bugged Jumbo frame support that
1629 * needs to have the Tx COE disabled for oversized frames
1630 * (due to limited buffer sizes). In this case we disable
1631 * the TX csum insertionin the TDES and not use SF. */
1632 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1633 features &= ~NETIF_F_ALL_CSUM;
1634
1635 return features;
1636 }
1637
1638 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1639 {
1640 struct net_device *dev = (struct net_device *)dev_id;
1641 struct stmmac_priv *priv = netdev_priv(dev);
1642
1643 if (unlikely(!dev)) {
1644 pr_err("%s: invalid dev pointer\n", __func__);
1645 return IRQ_NONE;
1646 }
1647
1648 /* To handle GMAC own interrupts */
1649 if (priv->plat->has_gmac) {
1650 int status = priv->hw->mac->host_irq_status((void __iomem *)
1651 dev->base_addr);
1652 if (unlikely(status)) {
1653 if (status & core_mmc_tx_irq)
1654 priv->xstats.mmc_tx_irq_n++;
1655 if (status & core_mmc_rx_irq)
1656 priv->xstats.mmc_rx_irq_n++;
1657 if (status & core_mmc_rx_csum_offload_irq)
1658 priv->xstats.mmc_rx_csum_offload_irq_n++;
1659 if (status & core_irq_receive_pmt_irq)
1660 priv->xstats.irq_receive_pmt_irq_n++;
1661
1662 /* For LPI we need to save the tx status */
1663 if (status & core_irq_tx_path_in_lpi_mode) {
1664 priv->xstats.irq_tx_path_in_lpi_mode_n++;
1665 priv->tx_path_in_lpi_mode = true;
1666 }
1667 if (status & core_irq_tx_path_exit_lpi_mode) {
1668 priv->xstats.irq_tx_path_exit_lpi_mode_n++;
1669 priv->tx_path_in_lpi_mode = false;
1670 }
1671 if (status & core_irq_rx_path_in_lpi_mode)
1672 priv->xstats.irq_rx_path_in_lpi_mode_n++;
1673 if (status & core_irq_rx_path_exit_lpi_mode)
1674 priv->xstats.irq_rx_path_exit_lpi_mode_n++;
1675 }
1676 }
1677
1678 /* To handle DMA interrupts */
1679 stmmac_dma_interrupt(priv);
1680
1681 return IRQ_HANDLED;
1682 }
1683
1684 #ifdef CONFIG_NET_POLL_CONTROLLER
1685 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1686 * to allow network I/O with interrupts disabled. */
1687 static void stmmac_poll_controller(struct net_device *dev)
1688 {
1689 disable_irq(dev->irq);
1690 stmmac_interrupt(dev->irq, dev);
1691 enable_irq(dev->irq);
1692 }
1693 #endif
1694
1695 /**
1696 * stmmac_ioctl - Entry point for the Ioctl
1697 * @dev: Device pointer.
1698 * @rq: An IOCTL specefic structure, that can contain a pointer to
1699 * a proprietary structure used to pass information to the driver.
1700 * @cmd: IOCTL command
1701 * Description:
1702 * Currently there are no special functionality supported in IOCTL, just the
1703 * phy_mii_ioctl(...) can be invoked.
1704 */
1705 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1706 {
1707 struct stmmac_priv *priv = netdev_priv(dev);
1708 int ret;
1709
1710 if (!netif_running(dev))
1711 return -EINVAL;
1712
1713 if (!priv->phydev)
1714 return -EINVAL;
1715
1716 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1717
1718 return ret;
1719 }
1720
1721 #ifdef CONFIG_STMMAC_DEBUG_FS
1722 static struct dentry *stmmac_fs_dir;
1723 static struct dentry *stmmac_rings_status;
1724 static struct dentry *stmmac_dma_cap;
1725
1726 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1727 {
1728 struct tmp_s {
1729 u64 a;
1730 unsigned int b;
1731 unsigned int c;
1732 };
1733 int i;
1734 struct net_device *dev = seq->private;
1735 struct stmmac_priv *priv = netdev_priv(dev);
1736
1737 seq_printf(seq, "=======================\n");
1738 seq_printf(seq, " RX descriptor ring\n");
1739 seq_printf(seq, "=======================\n");
1740
1741 for (i = 0; i < priv->dma_rx_size; i++) {
1742 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1743 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1744 i, (unsigned int)(x->a),
1745 (unsigned int)((x->a) >> 32), x->b, x->c);
1746 seq_printf(seq, "\n");
1747 }
1748
1749 seq_printf(seq, "\n");
1750 seq_printf(seq, "=======================\n");
1751 seq_printf(seq, " TX descriptor ring\n");
1752 seq_printf(seq, "=======================\n");
1753
1754 for (i = 0; i < priv->dma_tx_size; i++) {
1755 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1756 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1757 i, (unsigned int)(x->a),
1758 (unsigned int)((x->a) >> 32), x->b, x->c);
1759 seq_printf(seq, "\n");
1760 }
1761
1762 return 0;
1763 }
1764
1765 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1766 {
1767 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1768 }
1769
1770 static const struct file_operations stmmac_rings_status_fops = {
1771 .owner = THIS_MODULE,
1772 .open = stmmac_sysfs_ring_open,
1773 .read = seq_read,
1774 .llseek = seq_lseek,
1775 .release = single_release,
1776 };
1777
1778 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1779 {
1780 struct net_device *dev = seq->private;
1781 struct stmmac_priv *priv = netdev_priv(dev);
1782
1783 if (!priv->hw_cap_support) {
1784 seq_printf(seq, "DMA HW features not supported\n");
1785 return 0;
1786 }
1787
1788 seq_printf(seq, "==============================\n");
1789 seq_printf(seq, "\tDMA HW features\n");
1790 seq_printf(seq, "==============================\n");
1791
1792 seq_printf(seq, "\t10/100 Mbps %s\n",
1793 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1794 seq_printf(seq, "\t1000 Mbps %s\n",
1795 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1796 seq_printf(seq, "\tHalf duple %s\n",
1797 (priv->dma_cap.half_duplex) ? "Y" : "N");
1798 seq_printf(seq, "\tHash Filter: %s\n",
1799 (priv->dma_cap.hash_filter) ? "Y" : "N");
1800 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1801 (priv->dma_cap.multi_addr) ? "Y" : "N");
1802 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1803 (priv->dma_cap.pcs) ? "Y" : "N");
1804 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1805 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1806 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1807 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1808 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1809 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1810 seq_printf(seq, "\tRMON module: %s\n",
1811 (priv->dma_cap.rmon) ? "Y" : "N");
1812 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1813 (priv->dma_cap.time_stamp) ? "Y" : "N");
1814 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1815 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1816 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1817 (priv->dma_cap.eee) ? "Y" : "N");
1818 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1819 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1820 (priv->dma_cap.tx_coe) ? "Y" : "N");
1821 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1822 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1823 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1824 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1825 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1826 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1827 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1828 priv->dma_cap.number_rx_channel);
1829 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1830 priv->dma_cap.number_tx_channel);
1831 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1832 (priv->dma_cap.enh_desc) ? "Y" : "N");
1833
1834 return 0;
1835 }
1836
1837 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1838 {
1839 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1840 }
1841
1842 static const struct file_operations stmmac_dma_cap_fops = {
1843 .owner = THIS_MODULE,
1844 .open = stmmac_sysfs_dma_cap_open,
1845 .read = seq_read,
1846 .llseek = seq_lseek,
1847 .release = single_release,
1848 };
1849
1850 static int stmmac_init_fs(struct net_device *dev)
1851 {
1852 /* Create debugfs entries */
1853 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1854
1855 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1856 pr_err("ERROR %s, debugfs create directory failed\n",
1857 STMMAC_RESOURCE_NAME);
1858
1859 return -ENOMEM;
1860 }
1861
1862 /* Entry to report DMA RX/TX rings */
1863 stmmac_rings_status = debugfs_create_file("descriptors_status",
1864 S_IRUGO, stmmac_fs_dir, dev,
1865 &stmmac_rings_status_fops);
1866
1867 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1868 pr_info("ERROR creating stmmac ring debugfs file\n");
1869 debugfs_remove(stmmac_fs_dir);
1870
1871 return -ENOMEM;
1872 }
1873
1874 /* Entry to report the DMA HW features */
1875 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1876 dev, &stmmac_dma_cap_fops);
1877
1878 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1879 pr_info("ERROR creating stmmac MMC debugfs file\n");
1880 debugfs_remove(stmmac_rings_status);
1881 debugfs_remove(stmmac_fs_dir);
1882
1883 return -ENOMEM;
1884 }
1885
1886 return 0;
1887 }
1888
1889 static void stmmac_exit_fs(void)
1890 {
1891 debugfs_remove(stmmac_rings_status);
1892 debugfs_remove(stmmac_dma_cap);
1893 debugfs_remove(stmmac_fs_dir);
1894 }
1895 #endif /* CONFIG_STMMAC_DEBUG_FS */
1896
1897 static const struct net_device_ops stmmac_netdev_ops = {
1898 .ndo_open = stmmac_open,
1899 .ndo_start_xmit = stmmac_xmit,
1900 .ndo_stop = stmmac_release,
1901 .ndo_change_mtu = stmmac_change_mtu,
1902 .ndo_fix_features = stmmac_fix_features,
1903 .ndo_set_rx_mode = stmmac_set_rx_mode,
1904 .ndo_tx_timeout = stmmac_tx_timeout,
1905 .ndo_do_ioctl = stmmac_ioctl,
1906 .ndo_set_config = stmmac_config,
1907 #ifdef CONFIG_NET_POLL_CONTROLLER
1908 .ndo_poll_controller = stmmac_poll_controller,
1909 #endif
1910 .ndo_set_mac_address = eth_mac_addr,
1911 };
1912
1913 /**
1914 * stmmac_hw_init - Init the MAC device
1915 * @priv : pointer to the private device structure.
1916 * Description: this function detects which MAC device
1917 * (GMAC/MAC10-100) has to attached, checks the HW capability
1918 * (if supported) and sets the driver's features (for example
1919 * to use the ring or chaine mode or support the normal/enh
1920 * descriptor structure).
1921 */
1922 static int stmmac_hw_init(struct stmmac_priv *priv)
1923 {
1924 int ret = 0;
1925 struct mac_device_info *mac;
1926
1927 /* Identify the MAC HW device */
1928 if (priv->plat->has_gmac) {
1929 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1930 mac = dwmac1000_setup(priv->ioaddr);
1931 } else {
1932 mac = dwmac100_setup(priv->ioaddr);
1933 }
1934 if (!mac)
1935 return -ENOMEM;
1936
1937 priv->hw = mac;
1938
1939 /* To use the chained or ring mode */
1940 priv->hw->ring = &ring_mode_ops;
1941
1942 /* Get and dump the chip ID */
1943 priv->synopsys_id = stmmac_get_synopsys_id(priv);
1944
1945 /* Get the HW capability (new GMAC newer than 3.50a) */
1946 priv->hw_cap_support = stmmac_get_hw_features(priv);
1947 if (priv->hw_cap_support) {
1948 pr_info(" DMA HW capability register supported");
1949
1950 /* We can override some gmac/dma configuration fields: e.g.
1951 * enh_desc, tx_coe (e.g. that are passed through the
1952 * platform) with the values from the HW capability
1953 * register (if supported).
1954 */
1955 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1956 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1957
1958 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1959
1960 if (priv->dma_cap.rx_coe_type2)
1961 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1962 else if (priv->dma_cap.rx_coe_type1)
1963 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1964
1965 } else
1966 pr_info(" No HW DMA feature register supported");
1967
1968 /* Select the enhnaced/normal descriptor structures */
1969 stmmac_selec_desc_mode(priv);
1970
1971 /* Enable the IPC (Checksum Offload) and check if the feature has been
1972 * enabled during the core configuration. */
1973 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1974 if (!ret) {
1975 pr_warning(" RX IPC Checksum Offload not configured.\n");
1976 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1977 }
1978
1979 if (priv->plat->rx_coe)
1980 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1981 priv->plat->rx_coe);
1982 if (priv->plat->tx_coe)
1983 pr_info(" TX Checksum insertion supported\n");
1984
1985 if (priv->plat->pmt) {
1986 pr_info(" Wake-Up On Lan supported\n");
1987 device_set_wakeup_capable(priv->device, 1);
1988 }
1989
1990 return ret;
1991 }
1992
1993 /**
1994 * stmmac_dvr_probe
1995 * @device: device pointer
1996 * @plat_dat: platform data pointer
1997 * @addr: iobase memory address
1998 * Description: this is the main probe function used to
1999 * call the alloc_etherdev, allocate the priv structure.
2000 */
2001 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2002 struct plat_stmmacenet_data *plat_dat,
2003 void __iomem *addr)
2004 {
2005 int ret = 0;
2006 struct net_device *ndev = NULL;
2007 struct stmmac_priv *priv;
2008
2009 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2010 if (!ndev)
2011 return NULL;
2012
2013 SET_NETDEV_DEV(ndev, device);
2014
2015 priv = netdev_priv(ndev);
2016 priv->device = device;
2017 priv->dev = ndev;
2018
2019 ether_setup(ndev);
2020
2021 stmmac_set_ethtool_ops(ndev);
2022 priv->pause = pause;
2023 priv->plat = plat_dat;
2024 priv->ioaddr = addr;
2025 priv->dev->base_addr = (unsigned long)addr;
2026
2027 /* Verify driver arguments */
2028 stmmac_verify_args();
2029
2030 /* Override with kernel parameters if supplied XXX CRS XXX
2031 * this needs to have multiple instances */
2032 if ((phyaddr >= 0) && (phyaddr <= 31))
2033 priv->plat->phy_addr = phyaddr;
2034
2035 /* Init MAC and get the capabilities */
2036 stmmac_hw_init(priv);
2037
2038 ndev->netdev_ops = &stmmac_netdev_ops;
2039
2040 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2041 NETIF_F_RXCSUM;
2042 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2043 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2044 #ifdef STMMAC_VLAN_TAG_USED
2045 /* Both mac100 and gmac support receive VLAN tag detection */
2046 ndev->features |= NETIF_F_HW_VLAN_RX;
2047 #endif
2048 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2049
2050 if (flow_ctrl)
2051 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2052
2053 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2054
2055 spin_lock_init(&priv->lock);
2056 spin_lock_init(&priv->tx_lock);
2057
2058 ret = register_netdev(ndev);
2059 if (ret) {
2060 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2061 goto error_netdev_register;
2062 }
2063
2064 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2065 if (IS_ERR(priv->stmmac_clk)) {
2066 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2067 goto error_clk_get;
2068 }
2069
2070 /* If a specific clk_csr value is passed from the platform
2071 * this means that the CSR Clock Range selection cannot be
2072 * changed at run-time and it is fixed. Viceversa the driver'll try to
2073 * set the MDC clock dynamically according to the csr actual
2074 * clock input.
2075 */
2076 if (!priv->plat->clk_csr)
2077 stmmac_clk_csr_set(priv);
2078 else
2079 priv->clk_csr = priv->plat->clk_csr;
2080
2081 /* MDIO bus Registration */
2082 ret = stmmac_mdio_register(ndev);
2083 if (ret < 0) {
2084 pr_debug("%s: MDIO bus (id: %d) registration failed",
2085 __func__, priv->plat->bus_id);
2086 goto error_mdio_register;
2087 }
2088
2089 return priv;
2090
2091 error_mdio_register:
2092 clk_put(priv->stmmac_clk);
2093 error_clk_get:
2094 unregister_netdev(ndev);
2095 error_netdev_register:
2096 netif_napi_del(&priv->napi);
2097 free_netdev(ndev);
2098
2099 return NULL;
2100 }
2101
2102 /**
2103 * stmmac_dvr_remove
2104 * @ndev: net device pointer
2105 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2106 * changes the link status, releases the DMA descriptor rings.
2107 */
2108 int stmmac_dvr_remove(struct net_device *ndev)
2109 {
2110 struct stmmac_priv *priv = netdev_priv(ndev);
2111
2112 pr_info("%s:\n\tremoving driver", __func__);
2113
2114 priv->hw->dma->stop_rx(priv->ioaddr);
2115 priv->hw->dma->stop_tx(priv->ioaddr);
2116
2117 stmmac_set_mac(priv->ioaddr, false);
2118 stmmac_mdio_unregister(ndev);
2119 netif_carrier_off(ndev);
2120 unregister_netdev(ndev);
2121 free_netdev(ndev);
2122
2123 return 0;
2124 }
2125
2126 #ifdef CONFIG_PM
2127 int stmmac_suspend(struct net_device *ndev)
2128 {
2129 struct stmmac_priv *priv = netdev_priv(ndev);
2130 int dis_ic = 0;
2131 unsigned long flags;
2132
2133 if (!ndev || !netif_running(ndev))
2134 return 0;
2135
2136 if (priv->phydev)
2137 phy_stop(priv->phydev);
2138
2139 spin_lock_irqsave(&priv->lock, flags);
2140
2141 netif_device_detach(ndev);
2142 netif_stop_queue(ndev);
2143
2144 #ifdef CONFIG_STMMAC_TIMER
2145 priv->tm->timer_stop();
2146 if (likely(priv->tm->enable))
2147 dis_ic = 1;
2148 #endif
2149 napi_disable(&priv->napi);
2150
2151 /* Stop TX/RX DMA */
2152 priv->hw->dma->stop_tx(priv->ioaddr);
2153 priv->hw->dma->stop_rx(priv->ioaddr);
2154 /* Clear the Rx/Tx descriptors */
2155 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2156 dis_ic);
2157 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2158
2159 /* Enable Power down mode by programming the PMT regs */
2160 if (device_may_wakeup(priv->device))
2161 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2162 else {
2163 stmmac_set_mac(priv->ioaddr, false);
2164 /* Disable clock in case of PWM is off */
2165 clk_disable_unprepare(priv->stmmac_clk);
2166 }
2167 spin_unlock_irqrestore(&priv->lock, flags);
2168 return 0;
2169 }
2170
2171 int stmmac_resume(struct net_device *ndev)
2172 {
2173 struct stmmac_priv *priv = netdev_priv(ndev);
2174 unsigned long flags;
2175
2176 if (!netif_running(ndev))
2177 return 0;
2178
2179 spin_lock_irqsave(&priv->lock, flags);
2180
2181 /* Power Down bit, into the PM register, is cleared
2182 * automatically as soon as a magic packet or a Wake-up frame
2183 * is received. Anyway, it's better to manually clear
2184 * this bit because it can generate problems while resuming
2185 * from another devices (e.g. serial console). */
2186 if (device_may_wakeup(priv->device))
2187 priv->hw->mac->pmt(priv->ioaddr, 0);
2188 else
2189 /* enable the clk prevously disabled */
2190 clk_prepare_enable(priv->stmmac_clk);
2191
2192 netif_device_attach(ndev);
2193
2194 /* Enable the MAC and DMA */
2195 stmmac_set_mac(priv->ioaddr, true);
2196 priv->hw->dma->start_tx(priv->ioaddr);
2197 priv->hw->dma->start_rx(priv->ioaddr);
2198
2199 #ifdef CONFIG_STMMAC_TIMER
2200 if (likely(priv->tm->enable))
2201 priv->tm->timer_start(tmrate);
2202 #endif
2203 napi_enable(&priv->napi);
2204
2205 netif_start_queue(ndev);
2206
2207 spin_unlock_irqrestore(&priv->lock, flags);
2208
2209 if (priv->phydev)
2210 phy_start(priv->phydev);
2211
2212 return 0;
2213 }
2214
2215 int stmmac_freeze(struct net_device *ndev)
2216 {
2217 if (!ndev || !netif_running(ndev))
2218 return 0;
2219
2220 return stmmac_release(ndev);
2221 }
2222
2223 int stmmac_restore(struct net_device *ndev)
2224 {
2225 if (!ndev || !netif_running(ndev))
2226 return 0;
2227
2228 return stmmac_open(ndev);
2229 }
2230 #endif /* CONFIG_PM */
2231
2232 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2233 * depending on the configuration selected.
2234 */
2235 static int __init stmmac_init(void)
2236 {
2237 int err_plt = 0;
2238 int err_pci = 0;
2239
2240 err_plt = stmmac_register_platform();
2241 err_pci = stmmac_register_pci();
2242
2243 if ((err_pci) && (err_plt)) {
2244 pr_err("stmmac: driver registration failed\n");
2245 return -EINVAL;
2246 }
2247
2248 return 0;
2249 }
2250
2251 static void __exit stmmac_exit(void)
2252 {
2253 stmmac_unregister_platform();
2254 stmmac_unregister_pci();
2255 }
2256
2257 module_init(stmmac_init);
2258 module_exit(stmmac_exit);
2259
2260 #ifndef MODULE
2261 static int __init stmmac_cmdline_opt(char *str)
2262 {
2263 char *opt;
2264
2265 if (!str || !*str)
2266 return -EINVAL;
2267 while ((opt = strsep(&str, ",")) != NULL) {
2268 if (!strncmp(opt, "debug:", 6)) {
2269 if (kstrtoint(opt + 6, 0, &debug))
2270 goto err;
2271 } else if (!strncmp(opt, "phyaddr:", 8)) {
2272 if (kstrtoint(opt + 8, 0, &phyaddr))
2273 goto err;
2274 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2275 if (kstrtoint(opt + 11, 0, &dma_txsize))
2276 goto err;
2277 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2278 if (kstrtoint(opt + 11, 0, &dma_rxsize))
2279 goto err;
2280 } else if (!strncmp(opt, "buf_sz:", 7)) {
2281 if (kstrtoint(opt + 7, 0, &buf_sz))
2282 goto err;
2283 } else if (!strncmp(opt, "tc:", 3)) {
2284 if (kstrtoint(opt + 3, 0, &tc))
2285 goto err;
2286 } else if (!strncmp(opt, "watchdog:", 9)) {
2287 if (kstrtoint(opt + 9, 0, &watchdog))
2288 goto err;
2289 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2290 if (kstrtoint(opt + 10, 0, &flow_ctrl))
2291 goto err;
2292 } else if (!strncmp(opt, "pause:", 6)) {
2293 if (kstrtoint(opt + 6, 0, &pause))
2294 goto err;
2295 } else if (!strncmp(opt, "eee_timer:", 6)) {
2296 if (kstrtoint(opt + 10, 0, &eee_timer))
2297 goto err;
2298 #ifdef CONFIG_STMMAC_TIMER
2299 } else if (!strncmp(opt, "tmrate:", 7)) {
2300 if (kstrtoint(opt + 7, 0, &tmrate))
2301 goto err;
2302 #endif
2303 }
2304 }
2305 return 0;
2306
2307 err:
2308 pr_err("%s: ERROR broken module parameter conversion", __func__);
2309 return -EINVAL;
2310 }
2311
2312 __setup("stmmaceth=", stmmac_cmdline_opt);
2313 #endif
2314
2315 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2316 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2317 MODULE_LICENSE("GPL");
Linux ARM platform port for MOXA ART SoC