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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / net / wireless / ath / ath9k / ar9003_mac.c
blob78816b8b2173cf8e238d56e1fcf981bf027ff009
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <linux/export.h>
17 #include "hw.h"
18 #include "ar9003_mac.h"
19 #include "ar9003_mci.h"
20
21 static void ar9003_hw_rx_enable(struct ath_hw *hw)
22 {
23 REG_WRITE(hw, AR_CR, 0);
24 }
25
26 static void
27 ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
28 {
29 struct ar9003_txc *ads = ds;
30 int checksum = 0;
31 u32 val, ctl12, ctl17;
32 u8 desc_len;
33
34 desc_len = (AR_SREV_9462(ah) ? 0x18 : 0x17);
35
36 val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
37 (1 << AR_TxRxDesc_S) |
38 (1 << AR_CtrlStat_S) |
39 (i->qcu << AR_TxQcuNum_S) | desc_len;
40
41 checksum += val;
42 ACCESS_ONCE(ads->info) = val;
43
44 checksum += i->link;
45 ACCESS_ONCE(ads->link) = i->link;
46
47 checksum += i->buf_addr[0];
48 ACCESS_ONCE(ads->data0) = i->buf_addr[0];
49 checksum += i->buf_addr[1];
50 ACCESS_ONCE(ads->data1) = i->buf_addr[1];
51 checksum += i->buf_addr[2];
52 ACCESS_ONCE(ads->data2) = i->buf_addr[2];
53 checksum += i->buf_addr[3];
54 ACCESS_ONCE(ads->data3) = i->buf_addr[3];
55
56 checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen);
57 ACCESS_ONCE(ads->ctl3) = val;
58 checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen);
59 ACCESS_ONCE(ads->ctl5) = val;
60 checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen);
61 ACCESS_ONCE(ads->ctl7) = val;
62 checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen);
63 ACCESS_ONCE(ads->ctl9) = val;
64
65 checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff);
66 ACCESS_ONCE(ads->ctl10) = checksum;
67
68 if (i->is_first || i->is_last) {
69 ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0)
70 | set11nTries(i->rates, 1)
71 | set11nTries(i->rates, 2)
72 | set11nTries(i->rates, 3)
73 | (i->dur_update ? AR_DurUpdateEna : 0)
74 | SM(0, AR_BurstDur);
75
76 ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0)
77 | set11nRate(i->rates, 1)
78 | set11nRate(i->rates, 2)
79 | set11nRate(i->rates, 3);
80 } else {
81 ACCESS_ONCE(ads->ctl13) = 0;
82 ACCESS_ONCE(ads->ctl14) = 0;
83 }
84
85 ads->ctl20 = 0;
86 ads->ctl21 = 0;
87 ads->ctl22 = 0;
88 ads->ctl23 = 0;
89
90 ctl17 = SM(i->keytype, AR_EncrType);
91 if (!i->is_first) {
92 ACCESS_ONCE(ads->ctl11) = 0;
93 ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore;
94 ACCESS_ONCE(ads->ctl15) = 0;
95 ACCESS_ONCE(ads->ctl16) = 0;
96 ACCESS_ONCE(ads->ctl17) = ctl17;
97 ACCESS_ONCE(ads->ctl18) = 0;
98 ACCESS_ONCE(ads->ctl19) = 0;
99 return;
100 }
101
102 ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen)
103 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
104 | SM(i->txpower, AR_XmitPower)
105 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
106 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
107 | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0)
108 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
109 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
110 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
111
112 ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ?
113 SM(i->keyix, AR_DestIdx) : 0)
114 | SM(i->type, AR_FrameType)
115 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
116 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
117 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
118
119 ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
120 switch (i->aggr) {
121 case AGGR_BUF_FIRST:
122 ctl17 |= SM(i->aggr_len, AR_AggrLen);
123 /* fall through */
124 case AGGR_BUF_MIDDLE:
125 ctl12 |= AR_IsAggr | AR_MoreAggr;
126 ctl17 |= SM(i->ndelim, AR_PadDelim);
127 break;
128 case AGGR_BUF_LAST:
129 ctl12 |= AR_IsAggr;
130 break;
131 case AGGR_BUF_NONE:
132 break;
133 }
134
135 val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S;
136 ctl12 |= SM(val, AR_PAPRDChainMask);
137
138 ACCESS_ONCE(ads->ctl12) = ctl12;
139 ACCESS_ONCE(ads->ctl17) = ctl17;
140
141 ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0)
142 | set11nPktDurRTSCTS(i->rates, 1);
143
144 ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2)
145 | set11nPktDurRTSCTS(i->rates, 3);
146
147 ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0)
148 | set11nRateFlags(i->rates, 1)
149 | set11nRateFlags(i->rates, 2)
150 | set11nRateFlags(i->rates, 3)
151 | SM(i->rtscts_rate, AR_RTSCTSRate);
152
153 ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding;
154 }
155
156 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
157 {
158 int checksum;
159
160 checksum = ads->info + ads->link
161 + ads->data0 + ads->ctl3
162 + ads->data1 + ads->ctl5
163 + ads->data2 + ads->ctl7
164 + ads->data3 + ads->ctl9;
165
166 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
167 }
168
169 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
170 {
171 struct ar9003_txc *ads = ds;
172
173 ads->link = ds_link;
174 ads->ctl10 &= ~AR_TxPtrChkSum;
175 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
176 }
177
178 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
179 {
180 u32 isr = 0;
181 u32 mask2 = 0;
182 struct ath9k_hw_capabilities *pCap = &ah->caps;
183 struct ath_common *common = ath9k_hw_common(ah);
184 u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;
185
186 if (ath9k_hw_mci_is_enabled(ah))
187 async_mask |= AR_INTR_ASYNC_MASK_MCI;
188
189 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
190
191 if (async_cause & async_mask) {
192 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
193 == AR_RTC_STATUS_ON)
194 isr = REG_READ(ah, AR_ISR);
195 }
196
197
198 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
199
200 *masked = 0;
201
202 if (!isr && !sync_cause && !async_cause)
203 return false;
204
205 if (isr) {
206 if (isr & AR_ISR_BCNMISC) {
207 u32 isr2;
208 isr2 = REG_READ(ah, AR_ISR_S2);
209
210 mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
211 MAP_ISR_S2_TIM);
212 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
213 MAP_ISR_S2_DTIM);
214 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
215 MAP_ISR_S2_DTIMSYNC);
216 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
217 MAP_ISR_S2_CABEND);
218 mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
219 MAP_ISR_S2_GTT);
220 mask2 |= ((isr2 & AR_ISR_S2_CST) <<
221 MAP_ISR_S2_CST);
222 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
223 MAP_ISR_S2_TSFOOR);
224 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
225 MAP_ISR_S2_BB_WATCHDOG);
226
227 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
228 REG_WRITE(ah, AR_ISR_S2, isr2);
229 isr &= ~AR_ISR_BCNMISC;
230 }
231 }
232
233 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
234 isr = REG_READ(ah, AR_ISR_RAC);
235
236 if (isr == 0xffffffff) {
237 *masked = 0;
238 return false;
239 }
240
241 *masked = isr & ATH9K_INT_COMMON;
242
243 if (ah->config.rx_intr_mitigation)
244 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
245 *masked |= ATH9K_INT_RXLP;
246
247 if (ah->config.tx_intr_mitigation)
248 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
249 *masked |= ATH9K_INT_TX;
250
251 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
252 *masked |= ATH9K_INT_RXLP;
253
254 if (isr & AR_ISR_HP_RXOK)
255 *masked |= ATH9K_INT_RXHP;
256
257 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
258 *masked |= ATH9K_INT_TX;
259
260 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
261 u32 s0, s1;
262 s0 = REG_READ(ah, AR_ISR_S0);
263 REG_WRITE(ah, AR_ISR_S0, s0);
264 s1 = REG_READ(ah, AR_ISR_S1);
265 REG_WRITE(ah, AR_ISR_S1, s1);
266
267 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
268 AR_ISR_TXEOL);
269 }
270 }
271
272 if (isr & AR_ISR_GENTMR) {
273 u32 s5;
274
275 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
276 s5 = REG_READ(ah, AR_ISR_S5_S);
277 else
278 s5 = REG_READ(ah, AR_ISR_S5);
279
280 ah->intr_gen_timer_trigger =
281 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
282
283 ah->intr_gen_timer_thresh =
284 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
285
286 if (ah->intr_gen_timer_trigger)
287 *masked |= ATH9K_INT_GENTIMER;
288
289 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
290 REG_WRITE(ah, AR_ISR_S5, s5);
291 isr &= ~AR_ISR_GENTMR;
292 }
293
294 }
295
296 *masked |= mask2;
297
298 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
299 REG_WRITE(ah, AR_ISR, isr);
300
301 (void) REG_READ(ah, AR_ISR);
302 }
303
304 if (*masked & ATH9K_INT_BB_WATCHDOG)
305 ar9003_hw_bb_watchdog_read(ah);
306 }
307
308 if (async_cause & AR_INTR_ASYNC_MASK_MCI)
309 ar9003_mci_get_isr(ah, masked);
310
311 if (sync_cause) {
312 ath9k_debug_sync_cause(common, sync_cause);
313
314 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
315 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
316 REG_WRITE(ah, AR_RC, 0);
317 *masked |= ATH9K_INT_FATAL;
318 }
319
320 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
321 ath_dbg(common, INTERRUPT,
322 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
323
324 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
325 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
326
327 }
328 return true;
329 }
330
331 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
332 struct ath_tx_status *ts)
333 {
334 struct ar9003_txs *ads;
335 u32 status;
336
337 ads = &ah->ts_ring[ah->ts_tail];
338
339 status = ACCESS_ONCE(ads->status8);
340 if ((status & AR_TxDone) == 0)
341 return -EINPROGRESS;
342
343 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
344
345 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
346 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
347 ath_dbg(ath9k_hw_common(ah), XMIT,
348 "Tx Descriptor error %x\n", ads->ds_info);
349 memset(ads, 0, sizeof(*ads));
350 return -EIO;
351 }
352
353 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
354 ts->ts_seqnum = MS(status, AR_SeqNum);
355 ts->tid = MS(status, AR_TxTid);
356
357 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
358 ts->desc_id = MS(ads->status1, AR_TxDescId);
359 ts->ts_tstamp = ads->status4;
360 ts->ts_status = 0;
361 ts->ts_flags = 0;
362
363 if (status & AR_TxOpExceeded)
364 ts->ts_status |= ATH9K_TXERR_XTXOP;
365 status = ACCESS_ONCE(ads->status2);
366 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
367 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
368 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
369 if (status & AR_TxBaStatus) {
370 ts->ts_flags |= ATH9K_TX_BA;
371 ts->ba_low = ads->status5;
372 ts->ba_high = ads->status6;
373 }
374
375 status = ACCESS_ONCE(ads->status3);
376 if (status & AR_ExcessiveRetries)
377 ts->ts_status |= ATH9K_TXERR_XRETRY;
378 if (status & AR_Filtered)
379 ts->ts_status |= ATH9K_TXERR_FILT;
380 if (status & AR_FIFOUnderrun) {
381 ts->ts_status |= ATH9K_TXERR_FIFO;
382 ath9k_hw_updatetxtriglevel(ah, true);
383 }
384 if (status & AR_TxTimerExpired)
385 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
386 if (status & AR_DescCfgErr)
387 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
388 if (status & AR_TxDataUnderrun) {
389 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
390 ath9k_hw_updatetxtriglevel(ah, true);
391 }
392 if (status & AR_TxDelimUnderrun) {
393 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
394 ath9k_hw_updatetxtriglevel(ah, true);
395 }
396 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
397 ts->ts_longretry = MS(status, AR_DataFailCnt);
398 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
399
400 status = ACCESS_ONCE(ads->status7);
401 ts->ts_rssi = MS(status, AR_TxRSSICombined);
402 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
403 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
404 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
405
406 memset(ads, 0, sizeof(*ads));
407
408 return 0;
409 }
410
411 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
412 {
413 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
414
415 ops->rx_enable = ar9003_hw_rx_enable;
416 ops->set_desc_link = ar9003_hw_set_desc_link;
417 ops->get_isr = ar9003_hw_get_isr;
418 ops->set_txdesc = ar9003_set_txdesc;
419 ops->proc_txdesc = ar9003_hw_proc_txdesc;
420 }
421
422 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
423 {
424 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
425 }
426 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
427
428 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
429 enum ath9k_rx_qtype qtype)
430 {
431 if (qtype == ATH9K_RX_QUEUE_HP)
432 REG_WRITE(ah, AR_HP_RXDP, rxdp);
433 else
434 REG_WRITE(ah, AR_LP_RXDP, rxdp);
435 }
436 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
437
438 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
439 void *buf_addr)
440 {
441 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
442 unsigned int phyerr;
443
444 if ((rxsp->status11 & AR_RxDone) == 0)
445 return -EINPROGRESS;
446
447 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
448 return -EINVAL;
449
450 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
451 return -EINPROGRESS;
452
453 rxs->rs_status = 0;
454 rxs->rs_flags = 0;
455
456 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
457 rxs->rs_tstamp = rxsp->status3;
458
459 /* XXX: Keycache */
460 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
461 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
462 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
463 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
464 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
465 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
466 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
467
468 if (rxsp->status11 & AR_RxKeyIdxValid)
469 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
470 else
471 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
472
473 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
474 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
475
476 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
477 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
478 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
479 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
480 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
481
482 rxs->evm0 = rxsp->status6;
483 rxs->evm1 = rxsp->status7;
484 rxs->evm2 = rxsp->status8;
485 rxs->evm3 = rxsp->status9;
486 rxs->evm4 = (rxsp->status10 & 0xffff);
487
488 if (rxsp->status11 & AR_PreDelimCRCErr)
489 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
490
491 if (rxsp->status11 & AR_PostDelimCRCErr)
492 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
493
494 if (rxsp->status11 & AR_DecryptBusyErr)
495 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
496
497 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
498 /*
499 * AR_CRCErr will bet set to true if we're on the last
500 * subframe and the AR_PostDelimCRCErr is caught.
501 * In a way this also gives us a guarantee that when
502 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
503 * possibly be reviewing the last subframe. AR_CRCErr
504 * is the CRC of the actual data.
505 */
506 if (rxsp->status11 & AR_CRCErr)
507 rxs->rs_status |= ATH9K_RXERR_CRC;
508 else if (rxsp->status11 & AR_DecryptCRCErr)
509 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
510 else if (rxsp->status11 & AR_MichaelErr)
511 rxs->rs_status |= ATH9K_RXERR_MIC;
512 if (rxsp->status11 & AR_PHYErr) {
513 phyerr = MS(rxsp->status11, AR_PHYErrCode);
514 /*
515 * If we reach a point here where AR_PostDelimCRCErr is
516 * true it implies we're *not* on the last subframe. In
517 * in that case that we know already that the CRC of
518 * the frame was OK, and MAC would send an ACK for that
519 * subframe, even if we did get a phy error of type
520 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
521 * to frame that are prior to the last subframe.
522 * The AR_PostDelimCRCErr is the CRC for the MPDU
523 * delimiter, which contains the 4 reserved bits,
524 * the MPDU length (12 bits), and follows the MPDU
525 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
526 */
527 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
528 (rxsp->status11 & AR_PostDelimCRCErr)) {
529 rxs->rs_phyerr = 0;
530 } else {
531 rxs->rs_status |= ATH9K_RXERR_PHY;
532 rxs->rs_phyerr = phyerr;
533 }
534 };
535 }
536
537 if (rxsp->status11 & AR_KeyMiss)
538 rxs->rs_status |= ATH9K_RXERR_KEYMISS;
539
540 return 0;
541 }
542 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
543
544 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
545 {
546 ah->ts_tail = 0;
547
548 memset((void *) ah->ts_ring, 0,
549 ah->ts_size * sizeof(struct ar9003_txs));
550
551 ath_dbg(ath9k_hw_common(ah), XMIT,
552 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
553 ah->ts_paddr_start, ah->ts_paddr_end,
554 ah->ts_ring, ah->ts_size);
555
556 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
557 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
558 }
559
560 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
561 u32 ts_paddr_start,
562 u16 size)
563 {
564
565 ah->ts_paddr_start = ts_paddr_start;
566 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
567 ah->ts_size = size;
568 ah->ts_ring = (struct ar9003_txs *) ts_start;
569
570 ath9k_hw_reset_txstatus_ring(ah);
571 }
572 EXPORT_SYMBOL(ath9k_hw_setup_statusring);
Linux ARM platform port for MOXA ART SoC