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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / scsi / qla2xxx / qla_dbg.c
blobfdee5611f3e2afce938c7f7ad559ce5d8eecffe9
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8 /*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x0122 | 0x4b,0xba,0xfa |
15 * | Mailbox commands | 0x1140 | 0x111a-0x111b |
16 * | | | 0x112c-0x112e |
17 * | | | 0x113a |
18 * | Device Discovery | 0x2086 | 0x2020-0x2022 |
19 * | Queue Command and IO tracing | 0x3030 | 0x3006,0x3008 |
20 * | | | 0x302d-0x302e |
21 * | DPC Thread | 0x401c | 0x4002,0x4013 |
22 * | Async Events | 0x505f | 0x502b-0x502f |
23 * | | | 0x5047,0x5052 |
24 * | Timer Routines | 0x6011 | |
25 * | User Space Interactions | 0x709f | 0x7018,0x702e, |
26 * | | | 0x7039,0x7045, |
27 * | | | 0x7073-0x7075, |
28 * | | | 0x708c |
29 * | Task Management | 0x803c | 0x8025-0x8026 |
30 * | | | 0x800b,0x8039 |
31 * | AER/EEH | 0x9011 | |
32 * | Virtual Port | 0xa007 | |
33 * | ISP82XX Specific | 0xb054 | 0xb024 |
34 * | MultiQ | 0xc00c | |
35 * | Misc | 0xd010 | |
36 * | Target Mode | 0xe06f | |
37 * | Target Mode Management | 0xf071 | |
38 * | Target Mode Task Management | 0x1000b | |
39 * ----------------------------------------------------------------------
40 */
41
42 #include "qla_def.h"
43
44 #include <linux/delay.h>
45
46 static uint32_t ql_dbg_offset = 0x800;
47
48 static inline void
49 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
50 {
51 fw_dump->fw_major_version = htonl(ha->fw_major_version);
52 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
53 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
54 fw_dump->fw_attributes = htonl(ha->fw_attributes);
55
56 fw_dump->vendor = htonl(ha->pdev->vendor);
57 fw_dump->device = htonl(ha->pdev->device);
58 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
59 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
60 }
61
62 static inline void *
63 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
64 {
65 struct req_que *req = ha->req_q_map[0];
66 struct rsp_que *rsp = ha->rsp_q_map[0];
67 /* Request queue. */
68 memcpy(ptr, req->ring, req->length *
69 sizeof(request_t));
70
71 /* Response queue. */
72 ptr += req->length * sizeof(request_t);
73 memcpy(ptr, rsp->ring, rsp->length *
74 sizeof(response_t));
75
76 return ptr + (rsp->length * sizeof(response_t));
77 }
78
79 static int
80 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
81 uint32_t ram_dwords, void **nxt)
82 {
83 int rval;
84 uint32_t cnt, stat, timer, dwords, idx;
85 uint16_t mb0;
86 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
87 dma_addr_t dump_dma = ha->gid_list_dma;
88 uint32_t *dump = (uint32_t *)ha->gid_list;
89
90 rval = QLA_SUCCESS;
91 mb0 = 0;
92
93 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
94 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
95
96 dwords = qla2x00_gid_list_size(ha) / 4;
97 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
98 cnt += dwords, addr += dwords) {
99 if (cnt + dwords > ram_dwords)
100 dwords = ram_dwords - cnt;
101
102 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
103 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
104
105 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
106 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
107 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
108 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
109
110 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
111 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
112 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
113
114 for (timer = 6000000; timer; timer--) {
115 /* Check for pending interrupts. */
116 stat = RD_REG_DWORD(&reg->host_status);
117 if (stat & HSRX_RISC_INT) {
118 stat &= 0xff;
119
120 if (stat == 0x1 || stat == 0x2 ||
121 stat == 0x10 || stat == 0x11) {
122 set_bit(MBX_INTERRUPT,
123 &ha->mbx_cmd_flags);
124
125 mb0 = RD_REG_WORD(&reg->mailbox0);
126
127 WRT_REG_DWORD(&reg->hccr,
128 HCCRX_CLR_RISC_INT);
129 RD_REG_DWORD(&reg->hccr);
130 break;
131 }
132
133 /* Clear this intr; it wasn't a mailbox intr */
134 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
135 RD_REG_DWORD(&reg->hccr);
136 }
137 udelay(5);
138 }
139
140 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
141 rval = mb0 & MBS_MASK;
142 for (idx = 0; idx < dwords; idx++)
143 ram[cnt + idx] = swab32(dump[idx]);
144 } else {
145 rval = QLA_FUNCTION_FAILED;
146 }
147 }
148
149 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
150 return rval;
151 }
152
153 static int
154 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
155 uint32_t cram_size, void **nxt)
156 {
157 int rval;
158
159 /* Code RAM. */
160 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
161 if (rval != QLA_SUCCESS)
162 return rval;
163
164 /* External Memory. */
165 return qla24xx_dump_ram(ha, 0x100000, *nxt,
166 ha->fw_memory_size - 0x100000 + 1, nxt);
167 }
168
169 static uint32_t *
170 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
171 uint32_t count, uint32_t *buf)
172 {
173 uint32_t __iomem *dmp_reg;
174
175 WRT_REG_DWORD(&reg->iobase_addr, iobase);
176 dmp_reg = &reg->iobase_window;
177 while (count--)
178 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
179
180 return buf;
181 }
182
183 static inline int
184 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
185 {
186 int rval = QLA_SUCCESS;
187 uint32_t cnt;
188
189 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
190 for (cnt = 30000;
191 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
192 rval == QLA_SUCCESS; cnt--) {
193 if (cnt)
194 udelay(100);
195 else
196 rval = QLA_FUNCTION_TIMEOUT;
197 }
198
199 return rval;
200 }
201
202 static int
203 qla24xx_soft_reset(struct qla_hw_data *ha)
204 {
205 int rval = QLA_SUCCESS;
206 uint32_t cnt;
207 uint16_t mb0, wd;
208 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
209
210 /* Reset RISC. */
211 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
212 for (cnt = 0; cnt < 30000; cnt++) {
213 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
214 break;
215
216 udelay(10);
217 }
218
219 WRT_REG_DWORD(&reg->ctrl_status,
220 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
221 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
222
223 udelay(100);
224 /* Wait for firmware to complete NVRAM accesses. */
225 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
226 for (cnt = 10000 ; cnt && mb0; cnt--) {
227 udelay(5);
228 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
229 barrier();
230 }
231
232 /* Wait for soft-reset to complete. */
233 for (cnt = 0; cnt < 30000; cnt++) {
234 if ((RD_REG_DWORD(&reg->ctrl_status) &
235 CSRX_ISP_SOFT_RESET) == 0)
236 break;
237
238 udelay(10);
239 }
240 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
241 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
242
243 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
244 rval == QLA_SUCCESS; cnt--) {
245 if (cnt)
246 udelay(100);
247 else
248 rval = QLA_FUNCTION_TIMEOUT;
249 }
250
251 return rval;
252 }
253
254 static int
255 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
256 uint32_t ram_words, void **nxt)
257 {
258 int rval;
259 uint32_t cnt, stat, timer, words, idx;
260 uint16_t mb0;
261 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
262 dma_addr_t dump_dma = ha->gid_list_dma;
263 uint16_t *dump = (uint16_t *)ha->gid_list;
264
265 rval = QLA_SUCCESS;
266 mb0 = 0;
267
268 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
269 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
270
271 words = qla2x00_gid_list_size(ha) / 2;
272 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
273 cnt += words, addr += words) {
274 if (cnt + words > ram_words)
275 words = ram_words - cnt;
276
277 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
278 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
279
280 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
281 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
282 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
283 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
284
285 WRT_MAILBOX_REG(ha, reg, 4, words);
286 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
287
288 for (timer = 6000000; timer; timer--) {
289 /* Check for pending interrupts. */
290 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
291 if (stat & HSR_RISC_INT) {
292 stat &= 0xff;
293
294 if (stat == 0x1 || stat == 0x2) {
295 set_bit(MBX_INTERRUPT,
296 &ha->mbx_cmd_flags);
297
298 mb0 = RD_MAILBOX_REG(ha, reg, 0);
299
300 /* Release mailbox registers. */
301 WRT_REG_WORD(&reg->semaphore, 0);
302 WRT_REG_WORD(&reg->hccr,
303 HCCR_CLR_RISC_INT);
304 RD_REG_WORD(&reg->hccr);
305 break;
306 } else if (stat == 0x10 || stat == 0x11) {
307 set_bit(MBX_INTERRUPT,
308 &ha->mbx_cmd_flags);
309
310 mb0 = RD_MAILBOX_REG(ha, reg, 0);
311
312 WRT_REG_WORD(&reg->hccr,
313 HCCR_CLR_RISC_INT);
314 RD_REG_WORD(&reg->hccr);
315 break;
316 }
317
318 /* clear this intr; it wasn't a mailbox intr */
319 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
320 RD_REG_WORD(&reg->hccr);
321 }
322 udelay(5);
323 }
324
325 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
326 rval = mb0 & MBS_MASK;
327 for (idx = 0; idx < words; idx++)
328 ram[cnt + idx] = swab16(dump[idx]);
329 } else {
330 rval = QLA_FUNCTION_FAILED;
331 }
332 }
333
334 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
335 return rval;
336 }
337
338 static inline void
339 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
340 uint16_t *buf)
341 {
342 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
343
344 while (count--)
345 *buf++ = htons(RD_REG_WORD(dmp_reg++));
346 }
347
348 static inline void *
349 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
350 {
351 if (!ha->eft)
352 return ptr;
353
354 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
355 return ptr + ntohl(ha->fw_dump->eft_size);
356 }
357
358 static inline void *
359 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
360 {
361 uint32_t cnt;
362 uint32_t *iter_reg;
363 struct qla2xxx_fce_chain *fcec = ptr;
364
365 if (!ha->fce)
366 return ptr;
367
368 *last_chain = &fcec->type;
369 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
370 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
371 fce_calc_size(ha->fce_bufs));
372 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
373 fcec->addr_l = htonl(LSD(ha->fce_dma));
374 fcec->addr_h = htonl(MSD(ha->fce_dma));
375
376 iter_reg = fcec->eregs;
377 for (cnt = 0; cnt < 8; cnt++)
378 *iter_reg++ = htonl(ha->fce_mb[cnt]);
379
380 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
381
382 return (char *)iter_reg + ntohl(fcec->size);
383 }
384
385 static inline void *
386 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
387 uint32_t **last_chain)
388 {
389 struct qla2xxx_mqueue_chain *q;
390 struct qla2xxx_mqueue_header *qh;
391 uint32_t num_queues;
392 int que;
393 struct {
394 int length;
395 void *ring;
396 } aq, *aqp;
397
398 if (!ha->tgt.atio_q_length)
399 return ptr;
400
401 num_queues = 1;
402 aqp = &aq;
403 aqp->length = ha->tgt.atio_q_length;
404 aqp->ring = ha->tgt.atio_ring;
405
406 for (que = 0; que < num_queues; que++) {
407 /* aqp = ha->atio_q_map[que]; */
408 q = ptr;
409 *last_chain = &q->type;
410 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
411 q->chain_size = htonl(
412 sizeof(struct qla2xxx_mqueue_chain) +
413 sizeof(struct qla2xxx_mqueue_header) +
414 (aqp->length * sizeof(request_t)));
415 ptr += sizeof(struct qla2xxx_mqueue_chain);
416
417 /* Add header. */
418 qh = ptr;
419 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
420 qh->number = htonl(que);
421 qh->size = htonl(aqp->length * sizeof(request_t));
422 ptr += sizeof(struct qla2xxx_mqueue_header);
423
424 /* Add data. */
425 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
426
427 ptr += aqp->length * sizeof(request_t);
428 }
429
430 return ptr;
431 }
432
433 static inline void *
434 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
435 {
436 struct qla2xxx_mqueue_chain *q;
437 struct qla2xxx_mqueue_header *qh;
438 struct req_que *req;
439 struct rsp_que *rsp;
440 int que;
441
442 if (!ha->mqenable)
443 return ptr;
444
445 /* Request queues */
446 for (que = 1; que < ha->max_req_queues; que++) {
447 req = ha->req_q_map[que];
448 if (!req)
449 break;
450
451 /* Add chain. */
452 q = ptr;
453 *last_chain = &q->type;
454 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
455 q->chain_size = htonl(
456 sizeof(struct qla2xxx_mqueue_chain) +
457 sizeof(struct qla2xxx_mqueue_header) +
458 (req->length * sizeof(request_t)));
459 ptr += sizeof(struct qla2xxx_mqueue_chain);
460
461 /* Add header. */
462 qh = ptr;
463 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
464 qh->number = htonl(que);
465 qh->size = htonl(req->length * sizeof(request_t));
466 ptr += sizeof(struct qla2xxx_mqueue_header);
467
468 /* Add data. */
469 memcpy(ptr, req->ring, req->length * sizeof(request_t));
470 ptr += req->length * sizeof(request_t);
471 }
472
473 /* Response queues */
474 for (que = 1; que < ha->max_rsp_queues; que++) {
475 rsp = ha->rsp_q_map[que];
476 if (!rsp)
477 break;
478
479 /* Add chain. */
480 q = ptr;
481 *last_chain = &q->type;
482 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
483 q->chain_size = htonl(
484 sizeof(struct qla2xxx_mqueue_chain) +
485 sizeof(struct qla2xxx_mqueue_header) +
486 (rsp->length * sizeof(response_t)));
487 ptr += sizeof(struct qla2xxx_mqueue_chain);
488
489 /* Add header. */
490 qh = ptr;
491 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
492 qh->number = htonl(que);
493 qh->size = htonl(rsp->length * sizeof(response_t));
494 ptr += sizeof(struct qla2xxx_mqueue_header);
495
496 /* Add data. */
497 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
498 ptr += rsp->length * sizeof(response_t);
499 }
500
501 return ptr;
502 }
503
504 static inline void *
505 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
506 {
507 uint32_t cnt, que_idx;
508 uint8_t que_cnt;
509 struct qla2xxx_mq_chain *mq = ptr;
510 struct device_reg_25xxmq __iomem *reg;
511
512 if (!ha->mqenable || IS_QLA83XX(ha))
513 return ptr;
514
515 mq = ptr;
516 *last_chain = &mq->type;
517 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
518 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
519
520 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
521 ha->max_req_queues : ha->max_rsp_queues;
522 mq->count = htonl(que_cnt);
523 for (cnt = 0; cnt < que_cnt; cnt++) {
524 reg = (struct device_reg_25xxmq *) ((void *)
525 ha->mqiobase + cnt * QLA_QUE_PAGE);
526 que_idx = cnt * 4;
527 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
528 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
529 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
530 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
531 }
532
533 return ptr + sizeof(struct qla2xxx_mq_chain);
534 }
535
536 void
537 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
538 {
539 struct qla_hw_data *ha = vha->hw;
540
541 if (rval != QLA_SUCCESS) {
542 ql_log(ql_log_warn, vha, 0xd000,
543 "Failed to dump firmware (%x).\n", rval);
544 ha->fw_dumped = 0;
545 } else {
546 ql_log(ql_log_info, vha, 0xd001,
547 "Firmware dump saved to temp buffer (%ld/%p).\n",
548 vha->host_no, ha->fw_dump);
549 ha->fw_dumped = 1;
550 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
551 }
552 }
553
554 /**
555 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
556 * @ha: HA context
557 * @hardware_locked: Called with the hardware_lock
558 */
559 void
560 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
561 {
562 int rval;
563 uint32_t cnt;
564 struct qla_hw_data *ha = vha->hw;
565 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
566 uint16_t __iomem *dmp_reg;
567 unsigned long flags;
568 struct qla2300_fw_dump *fw;
569 void *nxt;
570 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
571
572 flags = 0;
573
574 if (!hardware_locked)
575 spin_lock_irqsave(&ha->hardware_lock, flags);
576
577 if (!ha->fw_dump) {
578 ql_log(ql_log_warn, vha, 0xd002,
579 "No buffer available for dump.\n");
580 goto qla2300_fw_dump_failed;
581 }
582
583 if (ha->fw_dumped) {
584 ql_log(ql_log_warn, vha, 0xd003,
585 "Firmware has been previously dumped (%p) "
586 "-- ignoring request.\n",
587 ha->fw_dump);
588 goto qla2300_fw_dump_failed;
589 }
590 fw = &ha->fw_dump->isp.isp23;
591 qla2xxx_prep_dump(ha, ha->fw_dump);
592
593 rval = QLA_SUCCESS;
594 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
595
596 /* Pause RISC. */
597 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
598 if (IS_QLA2300(ha)) {
599 for (cnt = 30000;
600 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
601 rval == QLA_SUCCESS; cnt--) {
602 if (cnt)
603 udelay(100);
604 else
605 rval = QLA_FUNCTION_TIMEOUT;
606 }
607 } else {
608 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
609 udelay(10);
610 }
611
612 if (rval == QLA_SUCCESS) {
613 dmp_reg = &reg->flash_address;
614 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
615 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
616
617 dmp_reg = &reg->u.isp2300.req_q_in;
618 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
619 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
620
621 dmp_reg = &reg->u.isp2300.mailbox0;
622 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
623 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
624
625 WRT_REG_WORD(&reg->ctrl_status, 0x40);
626 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
627
628 WRT_REG_WORD(&reg->ctrl_status, 0x50);
629 qla2xxx_read_window(reg, 48, fw->dma_reg);
630
631 WRT_REG_WORD(&reg->ctrl_status, 0x00);
632 dmp_reg = &reg->risc_hw;
633 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
634 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
635
636 WRT_REG_WORD(&reg->pcr, 0x2000);
637 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
638
639 WRT_REG_WORD(&reg->pcr, 0x2200);
640 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
641
642 WRT_REG_WORD(&reg->pcr, 0x2400);
643 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
644
645 WRT_REG_WORD(&reg->pcr, 0x2600);
646 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
647
648 WRT_REG_WORD(&reg->pcr, 0x2800);
649 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
650
651 WRT_REG_WORD(&reg->pcr, 0x2A00);
652 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
653
654 WRT_REG_WORD(&reg->pcr, 0x2C00);
655 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
656
657 WRT_REG_WORD(&reg->pcr, 0x2E00);
658 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
659
660 WRT_REG_WORD(&reg->ctrl_status, 0x10);
661 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
662
663 WRT_REG_WORD(&reg->ctrl_status, 0x20);
664 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
665
666 WRT_REG_WORD(&reg->ctrl_status, 0x30);
667 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
668
669 /* Reset RISC. */
670 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
671 for (cnt = 0; cnt < 30000; cnt++) {
672 if ((RD_REG_WORD(&reg->ctrl_status) &
673 CSR_ISP_SOFT_RESET) == 0)
674 break;
675
676 udelay(10);
677 }
678 }
679
680 if (!IS_QLA2300(ha)) {
681 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
682 rval == QLA_SUCCESS; cnt--) {
683 if (cnt)
684 udelay(100);
685 else
686 rval = QLA_FUNCTION_TIMEOUT;
687 }
688 }
689
690 /* Get RISC SRAM. */
691 if (rval == QLA_SUCCESS)
692 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
693 sizeof(fw->risc_ram) / 2, &nxt);
694
695 /* Get stack SRAM. */
696 if (rval == QLA_SUCCESS)
697 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
698 sizeof(fw->stack_ram) / 2, &nxt);
699
700 /* Get data SRAM. */
701 if (rval == QLA_SUCCESS)
702 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
703 ha->fw_memory_size - 0x11000 + 1, &nxt);
704
705 if (rval == QLA_SUCCESS)
706 qla2xxx_copy_queues(ha, nxt);
707
708 qla2xxx_dump_post_process(base_vha, rval);
709
710 qla2300_fw_dump_failed:
711 if (!hardware_locked)
712 spin_unlock_irqrestore(&ha->hardware_lock, flags);
713 }
714
715 /**
716 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
717 * @ha: HA context
718 * @hardware_locked: Called with the hardware_lock
719 */
720 void
721 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
722 {
723 int rval;
724 uint32_t cnt, timer;
725 uint16_t risc_address;
726 uint16_t mb0, mb2;
727 struct qla_hw_data *ha = vha->hw;
728 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
729 uint16_t __iomem *dmp_reg;
730 unsigned long flags;
731 struct qla2100_fw_dump *fw;
732 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
733
734 risc_address = 0;
735 mb0 = mb2 = 0;
736 flags = 0;
737
738 if (!hardware_locked)
739 spin_lock_irqsave(&ha->hardware_lock, flags);
740
741 if (!ha->fw_dump) {
742 ql_log(ql_log_warn, vha, 0xd004,
743 "No buffer available for dump.\n");
744 goto qla2100_fw_dump_failed;
745 }
746
747 if (ha->fw_dumped) {
748 ql_log(ql_log_warn, vha, 0xd005,
749 "Firmware has been previously dumped (%p) "
750 "-- ignoring request.\n",
751 ha->fw_dump);
752 goto qla2100_fw_dump_failed;
753 }
754 fw = &ha->fw_dump->isp.isp21;
755 qla2xxx_prep_dump(ha, ha->fw_dump);
756
757 rval = QLA_SUCCESS;
758 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
759
760 /* Pause RISC. */
761 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
762 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
763 rval == QLA_SUCCESS; cnt--) {
764 if (cnt)
765 udelay(100);
766 else
767 rval = QLA_FUNCTION_TIMEOUT;
768 }
769 if (rval == QLA_SUCCESS) {
770 dmp_reg = &reg->flash_address;
771 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
772 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
773
774 dmp_reg = &reg->u.isp2100.mailbox0;
775 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
776 if (cnt == 8)
777 dmp_reg = &reg->u_end.isp2200.mailbox8;
778
779 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
780 }
781
782 dmp_reg = &reg->u.isp2100.unused_2[0];
783 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
784 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
785
786 WRT_REG_WORD(&reg->ctrl_status, 0x00);
787 dmp_reg = &reg->risc_hw;
788 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
789 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
790
791 WRT_REG_WORD(&reg->pcr, 0x2000);
792 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
793
794 WRT_REG_WORD(&reg->pcr, 0x2100);
795 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
796
797 WRT_REG_WORD(&reg->pcr, 0x2200);
798 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
799
800 WRT_REG_WORD(&reg->pcr, 0x2300);
801 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
802
803 WRT_REG_WORD(&reg->pcr, 0x2400);
804 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
805
806 WRT_REG_WORD(&reg->pcr, 0x2500);
807 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
808
809 WRT_REG_WORD(&reg->pcr, 0x2600);
810 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
811
812 WRT_REG_WORD(&reg->pcr, 0x2700);
813 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
814
815 WRT_REG_WORD(&reg->ctrl_status, 0x10);
816 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
817
818 WRT_REG_WORD(&reg->ctrl_status, 0x20);
819 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
820
821 WRT_REG_WORD(&reg->ctrl_status, 0x30);
822 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
823
824 /* Reset the ISP. */
825 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
826 }
827
828 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
829 rval == QLA_SUCCESS; cnt--) {
830 if (cnt)
831 udelay(100);
832 else
833 rval = QLA_FUNCTION_TIMEOUT;
834 }
835
836 /* Pause RISC. */
837 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
838 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
839
840 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
841 for (cnt = 30000;
842 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
843 rval == QLA_SUCCESS; cnt--) {
844 if (cnt)
845 udelay(100);
846 else
847 rval = QLA_FUNCTION_TIMEOUT;
848 }
849 if (rval == QLA_SUCCESS) {
850 /* Set memory configuration and timing. */
851 if (IS_QLA2100(ha))
852 WRT_REG_WORD(&reg->mctr, 0xf1);
853 else
854 WRT_REG_WORD(&reg->mctr, 0xf2);
855 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
856
857 /* Release RISC. */
858 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
859 }
860 }
861
862 if (rval == QLA_SUCCESS) {
863 /* Get RISC SRAM. */
864 risc_address = 0x1000;
865 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
866 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
867 }
868 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
869 cnt++, risc_address++) {
870 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
871 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
872
873 for (timer = 6000000; timer != 0; timer--) {
874 /* Check for pending interrupts. */
875 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
876 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
877 set_bit(MBX_INTERRUPT,
878 &ha->mbx_cmd_flags);
879
880 mb0 = RD_MAILBOX_REG(ha, reg, 0);
881 mb2 = RD_MAILBOX_REG(ha, reg, 2);
882
883 WRT_REG_WORD(&reg->semaphore, 0);
884 WRT_REG_WORD(&reg->hccr,
885 HCCR_CLR_RISC_INT);
886 RD_REG_WORD(&reg->hccr);
887 break;
888 }
889 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
890 RD_REG_WORD(&reg->hccr);
891 }
892 udelay(5);
893 }
894
895 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
896 rval = mb0 & MBS_MASK;
897 fw->risc_ram[cnt] = htons(mb2);
898 } else {
899 rval = QLA_FUNCTION_FAILED;
900 }
901 }
902
903 if (rval == QLA_SUCCESS)
904 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
905
906 qla2xxx_dump_post_process(base_vha, rval);
907
908 qla2100_fw_dump_failed:
909 if (!hardware_locked)
910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
911 }
912
913 void
914 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
915 {
916 int rval;
917 uint32_t cnt;
918 uint32_t risc_address;
919 struct qla_hw_data *ha = vha->hw;
920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
921 uint32_t __iomem *dmp_reg;
922 uint32_t *iter_reg;
923 uint16_t __iomem *mbx_reg;
924 unsigned long flags;
925 struct qla24xx_fw_dump *fw;
926 uint32_t ext_mem_cnt;
927 void *nxt;
928 void *nxt_chain;
929 uint32_t *last_chain = NULL;
930 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
931
932 if (IS_QLA82XX(ha))
933 return;
934
935 risc_address = ext_mem_cnt = 0;
936 flags = 0;
937
938 if (!hardware_locked)
939 spin_lock_irqsave(&ha->hardware_lock, flags);
940
941 if (!ha->fw_dump) {
942 ql_log(ql_log_warn, vha, 0xd006,
943 "No buffer available for dump.\n");
944 goto qla24xx_fw_dump_failed;
945 }
946
947 if (ha->fw_dumped) {
948 ql_log(ql_log_warn, vha, 0xd007,
949 "Firmware has been previously dumped (%p) "
950 "-- ignoring request.\n",
951 ha->fw_dump);
952 goto qla24xx_fw_dump_failed;
953 }
954 fw = &ha->fw_dump->isp.isp24;
955 qla2xxx_prep_dump(ha, ha->fw_dump);
956
957 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
958
959 /* Pause RISC. */
960 rval = qla24xx_pause_risc(reg);
961 if (rval != QLA_SUCCESS)
962 goto qla24xx_fw_dump_failed_0;
963
964 /* Host interface registers. */
965 dmp_reg = &reg->flash_addr;
966 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
967 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
968
969 /* Disable interrupts. */
970 WRT_REG_DWORD(&reg->ictrl, 0);
971 RD_REG_DWORD(&reg->ictrl);
972
973 /* Shadow registers. */
974 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
975 RD_REG_DWORD(&reg->iobase_addr);
976 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
977 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
978
979 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
980 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
981
982 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
983 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
984
985 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
986 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
987
988 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
989 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
990
991 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
992 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
993
994 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
995 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
996
997 /* Mailbox registers. */
998 mbx_reg = &reg->mailbox0;
999 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1000 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1001
1002 /* Transfer sequence registers. */
1003 iter_reg = fw->xseq_gp_reg;
1004 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1005 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1006 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1007 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1008 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1009 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1010 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1011 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1012
1013 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1014 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1015
1016 /* Receive sequence registers. */
1017 iter_reg = fw->rseq_gp_reg;
1018 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1019 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1020 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1021 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1022 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1023 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1024 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1025 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1026
1027 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1028 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1029 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1030
1031 /* Command DMA registers. */
1032 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1033
1034 /* Queues. */
1035 iter_reg = fw->req0_dma_reg;
1036 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1037 dmp_reg = &reg->iobase_q;
1038 for (cnt = 0; cnt < 7; cnt++)
1039 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1040
1041 iter_reg = fw->resp0_dma_reg;
1042 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1043 dmp_reg = &reg->iobase_q;
1044 for (cnt = 0; cnt < 7; cnt++)
1045 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1046
1047 iter_reg = fw->req1_dma_reg;
1048 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1049 dmp_reg = &reg->iobase_q;
1050 for (cnt = 0; cnt < 7; cnt++)
1051 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1052
1053 /* Transmit DMA registers. */
1054 iter_reg = fw->xmt0_dma_reg;
1055 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1056 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1057
1058 iter_reg = fw->xmt1_dma_reg;
1059 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1060 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1061
1062 iter_reg = fw->xmt2_dma_reg;
1063 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1064 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1065
1066 iter_reg = fw->xmt3_dma_reg;
1067 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1068 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1069
1070 iter_reg = fw->xmt4_dma_reg;
1071 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1072 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1073
1074 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1075
1076 /* Receive DMA registers. */
1077 iter_reg = fw->rcvt0_data_dma_reg;
1078 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1079 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1080
1081 iter_reg = fw->rcvt1_data_dma_reg;
1082 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1083 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1084
1085 /* RISC registers. */
1086 iter_reg = fw->risc_gp_reg;
1087 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1088 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1089 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1090 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1091 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1092 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1093 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1094 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1095
1096 /* Local memory controller registers. */
1097 iter_reg = fw->lmc_reg;
1098 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1099 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1100 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1101 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1102 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1103 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1104 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1105
1106 /* Fibre Protocol Module registers. */
1107 iter_reg = fw->fpm_hdw_reg;
1108 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1109 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1110 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1111 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1112 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1113 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1114 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1115 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1116 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1117 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1118 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1119 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1120
1121 /* Frame Buffer registers. */
1122 iter_reg = fw->fb_hdw_reg;
1123 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1130 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1131 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1132 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1133 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1134
1135 rval = qla24xx_soft_reset(ha);
1136 if (rval != QLA_SUCCESS)
1137 goto qla24xx_fw_dump_failed_0;
1138
1139 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1140 &nxt);
1141 if (rval != QLA_SUCCESS)
1142 goto qla24xx_fw_dump_failed_0;
1143
1144 nxt = qla2xxx_copy_queues(ha, nxt);
1145
1146 qla24xx_copy_eft(ha, nxt);
1147
1148 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1149 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1150 if (last_chain) {
1151 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1152 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1153 }
1154
1155 /* Adjust valid length. */
1156 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1157
1158 qla24xx_fw_dump_failed_0:
1159 qla2xxx_dump_post_process(base_vha, rval);
1160
1161 qla24xx_fw_dump_failed:
1162 if (!hardware_locked)
1163 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1164 }
1165
1166 void
1167 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1168 {
1169 int rval;
1170 uint32_t cnt;
1171 uint32_t risc_address;
1172 struct qla_hw_data *ha = vha->hw;
1173 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1174 uint32_t __iomem *dmp_reg;
1175 uint32_t *iter_reg;
1176 uint16_t __iomem *mbx_reg;
1177 unsigned long flags;
1178 struct qla25xx_fw_dump *fw;
1179 uint32_t ext_mem_cnt;
1180 void *nxt, *nxt_chain;
1181 uint32_t *last_chain = NULL;
1182 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1183
1184 risc_address = ext_mem_cnt = 0;
1185 flags = 0;
1186
1187 if (!hardware_locked)
1188 spin_lock_irqsave(&ha->hardware_lock, flags);
1189
1190 if (!ha->fw_dump) {
1191 ql_log(ql_log_warn, vha, 0xd008,
1192 "No buffer available for dump.\n");
1193 goto qla25xx_fw_dump_failed;
1194 }
1195
1196 if (ha->fw_dumped) {
1197 ql_log(ql_log_warn, vha, 0xd009,
1198 "Firmware has been previously dumped (%p) "
1199 "-- ignoring request.\n",
1200 ha->fw_dump);
1201 goto qla25xx_fw_dump_failed;
1202 }
1203 fw = &ha->fw_dump->isp.isp25;
1204 qla2xxx_prep_dump(ha, ha->fw_dump);
1205 ha->fw_dump->version = __constant_htonl(2);
1206
1207 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1208
1209 /* Pause RISC. */
1210 rval = qla24xx_pause_risc(reg);
1211 if (rval != QLA_SUCCESS)
1212 goto qla25xx_fw_dump_failed_0;
1213
1214 /* Host/Risc registers. */
1215 iter_reg = fw->host_risc_reg;
1216 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1217 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1218
1219 /* PCIe registers. */
1220 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1221 RD_REG_DWORD(&reg->iobase_addr);
1222 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1223 dmp_reg = &reg->iobase_c4;
1224 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1225 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1226 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1227 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1228
1229 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1230 RD_REG_DWORD(&reg->iobase_window);
1231
1232 /* Host interface registers. */
1233 dmp_reg = &reg->flash_addr;
1234 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1235 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1236
1237 /* Disable interrupts. */
1238 WRT_REG_DWORD(&reg->ictrl, 0);
1239 RD_REG_DWORD(&reg->ictrl);
1240
1241 /* Shadow registers. */
1242 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1243 RD_REG_DWORD(&reg->iobase_addr);
1244 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1245 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1246
1247 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1248 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1249
1250 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1251 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1252
1253 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1254 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1255
1256 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1257 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1258
1259 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1260 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1261
1262 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1263 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1264
1265 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1266 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1267
1268 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1269 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1270
1271 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1272 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1273
1274 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1275 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1276
1277 /* RISC I/O register. */
1278 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1279 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1280
1281 /* Mailbox registers. */
1282 mbx_reg = &reg->mailbox0;
1283 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1284 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1285
1286 /* Transfer sequence registers. */
1287 iter_reg = fw->xseq_gp_reg;
1288 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1289 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1290 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1291 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1292 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1293 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1294 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1295 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1296
1297 iter_reg = fw->xseq_0_reg;
1298 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1299 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1300 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1301
1302 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1303
1304 /* Receive sequence registers. */
1305 iter_reg = fw->rseq_gp_reg;
1306 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1307 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1308 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1309 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1310 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1311 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1312 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1313 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1314
1315 iter_reg = fw->rseq_0_reg;
1316 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1317 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1318
1319 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1320 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1321
1322 /* Auxiliary sequence registers. */
1323 iter_reg = fw->aseq_gp_reg;
1324 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1325 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1326 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1327 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1328 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1329 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1330 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1331 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1332
1333 iter_reg = fw->aseq_0_reg;
1334 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1335 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1336
1337 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1338 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1339
1340 /* Command DMA registers. */
1341 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1342
1343 /* Queues. */
1344 iter_reg = fw->req0_dma_reg;
1345 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1346 dmp_reg = &reg->iobase_q;
1347 for (cnt = 0; cnt < 7; cnt++)
1348 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1349
1350 iter_reg = fw->resp0_dma_reg;
1351 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1352 dmp_reg = &reg->iobase_q;
1353 for (cnt = 0; cnt < 7; cnt++)
1354 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1355
1356 iter_reg = fw->req1_dma_reg;
1357 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1358 dmp_reg = &reg->iobase_q;
1359 for (cnt = 0; cnt < 7; cnt++)
1360 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1361
1362 /* Transmit DMA registers. */
1363 iter_reg = fw->xmt0_dma_reg;
1364 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1365 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1366
1367 iter_reg = fw->xmt1_dma_reg;
1368 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1369 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1370
1371 iter_reg = fw->xmt2_dma_reg;
1372 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1373 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1374
1375 iter_reg = fw->xmt3_dma_reg;
1376 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1377 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1378
1379 iter_reg = fw->xmt4_dma_reg;
1380 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1381 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1382
1383 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1384
1385 /* Receive DMA registers. */
1386 iter_reg = fw->rcvt0_data_dma_reg;
1387 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1388 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1389
1390 iter_reg = fw->rcvt1_data_dma_reg;
1391 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1392 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1393
1394 /* RISC registers. */
1395 iter_reg = fw->risc_gp_reg;
1396 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1397 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1398 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1399 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1400 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1401 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1402 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1403 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1404
1405 /* Local memory controller registers. */
1406 iter_reg = fw->lmc_reg;
1407 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1409 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1410 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1411 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1412 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1413 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1414 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1415
1416 /* Fibre Protocol Module registers. */
1417 iter_reg = fw->fpm_hdw_reg;
1418 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1420 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1421 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1422 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1423 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1424 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1425 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1426 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1427 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1428 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1429 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1430
1431 /* Frame Buffer registers. */
1432 iter_reg = fw->fb_hdw_reg;
1433 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1438 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1439 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1440 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1441 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1442 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1443 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1444 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1445
1446 /* Multi queue registers */
1447 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1448 &last_chain);
1449
1450 rval = qla24xx_soft_reset(ha);
1451 if (rval != QLA_SUCCESS)
1452 goto qla25xx_fw_dump_failed_0;
1453
1454 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1455 &nxt);
1456 if (rval != QLA_SUCCESS)
1457 goto qla25xx_fw_dump_failed_0;
1458
1459 nxt = qla2xxx_copy_queues(ha, nxt);
1460
1461 nxt = qla24xx_copy_eft(ha, nxt);
1462
1463 /* Chain entries -- started with MQ. */
1464 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1465 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1466 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1467 if (last_chain) {
1468 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1469 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1470 }
1471
1472 /* Adjust valid length. */
1473 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1474
1475 qla25xx_fw_dump_failed_0:
1476 qla2xxx_dump_post_process(base_vha, rval);
1477
1478 qla25xx_fw_dump_failed:
1479 if (!hardware_locked)
1480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1481 }
1482
1483 void
1484 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1485 {
1486 int rval;
1487 uint32_t cnt;
1488 uint32_t risc_address;
1489 struct qla_hw_data *ha = vha->hw;
1490 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1491 uint32_t __iomem *dmp_reg;
1492 uint32_t *iter_reg;
1493 uint16_t __iomem *mbx_reg;
1494 unsigned long flags;
1495 struct qla81xx_fw_dump *fw;
1496 uint32_t ext_mem_cnt;
1497 void *nxt, *nxt_chain;
1498 uint32_t *last_chain = NULL;
1499 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1500
1501 risc_address = ext_mem_cnt = 0;
1502 flags = 0;
1503
1504 if (!hardware_locked)
1505 spin_lock_irqsave(&ha->hardware_lock, flags);
1506
1507 if (!ha->fw_dump) {
1508 ql_log(ql_log_warn, vha, 0xd00a,
1509 "No buffer available for dump.\n");
1510 goto qla81xx_fw_dump_failed;
1511 }
1512
1513 if (ha->fw_dumped) {
1514 ql_log(ql_log_warn, vha, 0xd00b,
1515 "Firmware has been previously dumped (%p) "
1516 "-- ignoring request.\n",
1517 ha->fw_dump);
1518 goto qla81xx_fw_dump_failed;
1519 }
1520 fw = &ha->fw_dump->isp.isp81;
1521 qla2xxx_prep_dump(ha, ha->fw_dump);
1522
1523 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1524
1525 /* Pause RISC. */
1526 rval = qla24xx_pause_risc(reg);
1527 if (rval != QLA_SUCCESS)
1528 goto qla81xx_fw_dump_failed_0;
1529
1530 /* Host/Risc registers. */
1531 iter_reg = fw->host_risc_reg;
1532 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1533 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1534
1535 /* PCIe registers. */
1536 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1537 RD_REG_DWORD(&reg->iobase_addr);
1538 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1539 dmp_reg = &reg->iobase_c4;
1540 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1541 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1542 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1543 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1544
1545 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1546 RD_REG_DWORD(&reg->iobase_window);
1547
1548 /* Host interface registers. */
1549 dmp_reg = &reg->flash_addr;
1550 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1551 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1552
1553 /* Disable interrupts. */
1554 WRT_REG_DWORD(&reg->ictrl, 0);
1555 RD_REG_DWORD(&reg->ictrl);
1556
1557 /* Shadow registers. */
1558 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1559 RD_REG_DWORD(&reg->iobase_addr);
1560 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1561 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1562
1563 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1564 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1565
1566 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1567 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1568
1569 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1570 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1571
1572 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1573 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1574
1575 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1576 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1577
1578 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1579 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1580
1581 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1582 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1583
1584 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1585 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1586
1587 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1588 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1589
1590 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1591 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1592
1593 /* RISC I/O register. */
1594 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1595 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1596
1597 /* Mailbox registers. */
1598 mbx_reg = &reg->mailbox0;
1599 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1600 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1601
1602 /* Transfer sequence registers. */
1603 iter_reg = fw->xseq_gp_reg;
1604 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1605 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1606 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1607 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1608 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1609 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1610 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1611 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1612
1613 iter_reg = fw->xseq_0_reg;
1614 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1615 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1616 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1617
1618 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1619
1620 /* Receive sequence registers. */
1621 iter_reg = fw->rseq_gp_reg;
1622 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1623 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1624 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1625 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1626 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1627 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1628 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1629 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1630
1631 iter_reg = fw->rseq_0_reg;
1632 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1633 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1634
1635 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1636 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1637
1638 /* Auxiliary sequence registers. */
1639 iter_reg = fw->aseq_gp_reg;
1640 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1641 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1642 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1643 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1644 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1645 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1646 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1647 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1648
1649 iter_reg = fw->aseq_0_reg;
1650 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1651 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1652
1653 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1654 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1655
1656 /* Command DMA registers. */
1657 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1658
1659 /* Queues. */
1660 iter_reg = fw->req0_dma_reg;
1661 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1662 dmp_reg = &reg->iobase_q;
1663 for (cnt = 0; cnt < 7; cnt++)
1664 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1665
1666 iter_reg = fw->resp0_dma_reg;
1667 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1668 dmp_reg = &reg->iobase_q;
1669 for (cnt = 0; cnt < 7; cnt++)
1670 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1671
1672 iter_reg = fw->req1_dma_reg;
1673 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1674 dmp_reg = &reg->iobase_q;
1675 for (cnt = 0; cnt < 7; cnt++)
1676 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1677
1678 /* Transmit DMA registers. */
1679 iter_reg = fw->xmt0_dma_reg;
1680 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1681 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1682
1683 iter_reg = fw->xmt1_dma_reg;
1684 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1685 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1686
1687 iter_reg = fw->xmt2_dma_reg;
1688 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1689 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1690
1691 iter_reg = fw->xmt3_dma_reg;
1692 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1693 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1694
1695 iter_reg = fw->xmt4_dma_reg;
1696 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1697 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1698
1699 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1700
1701 /* Receive DMA registers. */
1702 iter_reg = fw->rcvt0_data_dma_reg;
1703 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1704 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1705
1706 iter_reg = fw->rcvt1_data_dma_reg;
1707 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1708 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1709
1710 /* RISC registers. */
1711 iter_reg = fw->risc_gp_reg;
1712 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1713 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1714 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1715 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1716 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1717 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1718 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1719 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1720
1721 /* Local memory controller registers. */
1722 iter_reg = fw->lmc_reg;
1723 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1725 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1726 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1727 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1728 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1729 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1730 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1731
1732 /* Fibre Protocol Module registers. */
1733 iter_reg = fw->fpm_hdw_reg;
1734 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1736 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1737 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1738 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1740 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1741 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1742 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1743 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1744 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1745 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1747 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1748
1749 /* Frame Buffer registers. */
1750 iter_reg = fw->fb_hdw_reg;
1751 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1754 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1755 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1756 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1757 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1758 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1759 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1760 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1761 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1763 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1764
1765 /* Multi queue registers */
1766 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1767 &last_chain);
1768
1769 rval = qla24xx_soft_reset(ha);
1770 if (rval != QLA_SUCCESS)
1771 goto qla81xx_fw_dump_failed_0;
1772
1773 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1774 &nxt);
1775 if (rval != QLA_SUCCESS)
1776 goto qla81xx_fw_dump_failed_0;
1777
1778 nxt = qla2xxx_copy_queues(ha, nxt);
1779
1780 nxt = qla24xx_copy_eft(ha, nxt);
1781
1782 /* Chain entries -- started with MQ. */
1783 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1784 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1785 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1786 if (last_chain) {
1787 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1788 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1789 }
1790
1791 /* Adjust valid length. */
1792 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1793
1794 qla81xx_fw_dump_failed_0:
1795 qla2xxx_dump_post_process(base_vha, rval);
1796
1797 qla81xx_fw_dump_failed:
1798 if (!hardware_locked)
1799 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1800 }
1801
1802 void
1803 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1804 {
1805 int rval;
1806 uint32_t cnt, reg_data;
1807 uint32_t risc_address;
1808 struct qla_hw_data *ha = vha->hw;
1809 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1810 uint32_t __iomem *dmp_reg;
1811 uint32_t *iter_reg;
1812 uint16_t __iomem *mbx_reg;
1813 unsigned long flags;
1814 struct qla83xx_fw_dump *fw;
1815 uint32_t ext_mem_cnt;
1816 void *nxt, *nxt_chain;
1817 uint32_t *last_chain = NULL;
1818 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1819
1820 risc_address = ext_mem_cnt = 0;
1821 flags = 0;
1822
1823 if (!hardware_locked)
1824 spin_lock_irqsave(&ha->hardware_lock, flags);
1825
1826 if (!ha->fw_dump) {
1827 ql_log(ql_log_warn, vha, 0xd00c,
1828 "No buffer available for dump!!!\n");
1829 goto qla83xx_fw_dump_failed;
1830 }
1831
1832 if (ha->fw_dumped) {
1833 ql_log(ql_log_warn, vha, 0xd00d,
1834 "Firmware has been previously dumped (%p) -- ignoring "
1835 "request...\n", ha->fw_dump);
1836 goto qla83xx_fw_dump_failed;
1837 }
1838 fw = &ha->fw_dump->isp.isp83;
1839 qla2xxx_prep_dump(ha, ha->fw_dump);
1840
1841 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1842
1843 /* Pause RISC. */
1844 rval = qla24xx_pause_risc(reg);
1845 if (rval != QLA_SUCCESS)
1846 goto qla83xx_fw_dump_failed_0;
1847
1848 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1849 dmp_reg = &reg->iobase_window;
1850 reg_data = RD_REG_DWORD(dmp_reg);
1851 WRT_REG_DWORD(dmp_reg, 0);
1852
1853 dmp_reg = &reg->unused_4_1[0];
1854 reg_data = RD_REG_DWORD(dmp_reg);
1855 WRT_REG_DWORD(dmp_reg, 0);
1856
1857 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1858 dmp_reg = &reg->unused_4_1[2];
1859 reg_data = RD_REG_DWORD(dmp_reg);
1860 WRT_REG_DWORD(dmp_reg, 0);
1861
1862 /* select PCR and disable ecc checking and correction */
1863 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1864 RD_REG_DWORD(&reg->iobase_addr);
1865 WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
1866
1867 /* Host/Risc registers. */
1868 iter_reg = fw->host_risc_reg;
1869 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1870 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1871 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1872
1873 /* PCIe registers. */
1874 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1875 RD_REG_DWORD(&reg->iobase_addr);
1876 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1877 dmp_reg = &reg->iobase_c4;
1878 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1879 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1880 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1881 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1882
1883 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1884 RD_REG_DWORD(&reg->iobase_window);
1885
1886 /* Host interface registers. */
1887 dmp_reg = &reg->flash_addr;
1888 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1889 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1890
1891 /* Disable interrupts. */
1892 WRT_REG_DWORD(&reg->ictrl, 0);
1893 RD_REG_DWORD(&reg->ictrl);
1894
1895 /* Shadow registers. */
1896 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1897 RD_REG_DWORD(&reg->iobase_addr);
1898 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1899 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1900
1901 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1902 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1903
1904 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1905 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1906
1907 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1908 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1909
1910 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1911 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1912
1913 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1914 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1915
1916 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1917 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1918
1919 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1920 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1921
1922 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1923 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1924
1925 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1926 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1927
1928 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1929 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1930
1931 /* RISC I/O register. */
1932 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1933 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1934
1935 /* Mailbox registers. */
1936 mbx_reg = &reg->mailbox0;
1937 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1938 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1939
1940 /* Transfer sequence registers. */
1941 iter_reg = fw->xseq_gp_reg;
1942 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1943 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1944 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1945 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1946 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1947 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1948 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1949 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1950 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1951 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1952 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1953 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1954 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1957 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1958
1959 iter_reg = fw->xseq_0_reg;
1960 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1961 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1962 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1963
1964 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1965
1966 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1967
1968 /* Receive sequence registers. */
1969 iter_reg = fw->rseq_gp_reg;
1970 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1971 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1972 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1973 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1974 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1975 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1976 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1977 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1978 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1979 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1980 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1981 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1983 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1984 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1985 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1986
1987 iter_reg = fw->rseq_0_reg;
1988 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1989 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1990
1991 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1992 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1993 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
1994
1995 /* Auxiliary sequence registers. */
1996 iter_reg = fw->aseq_gp_reg;
1997 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1998 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1999 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2000 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2001 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2002 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2003 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2004 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2005 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2006 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2007 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2011 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2012 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2013
2014 iter_reg = fw->aseq_0_reg;
2015 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2016 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2017
2018 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2019 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2020 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2021
2022 /* Command DMA registers. */
2023 iter_reg = fw->cmd_dma_reg;
2024 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2025 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2026 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2027 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2028
2029 /* Queues. */
2030 iter_reg = fw->req0_dma_reg;
2031 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2032 dmp_reg = &reg->iobase_q;
2033 for (cnt = 0; cnt < 7; cnt++)
2034 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2035
2036 iter_reg = fw->resp0_dma_reg;
2037 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2038 dmp_reg = &reg->iobase_q;
2039 for (cnt = 0; cnt < 7; cnt++)
2040 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2041
2042 iter_reg = fw->req1_dma_reg;
2043 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2044 dmp_reg = &reg->iobase_q;
2045 for (cnt = 0; cnt < 7; cnt++)
2046 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2047
2048 /* Transmit DMA registers. */
2049 iter_reg = fw->xmt0_dma_reg;
2050 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2051 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2052
2053 iter_reg = fw->xmt1_dma_reg;
2054 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2055 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2056
2057 iter_reg = fw->xmt2_dma_reg;
2058 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2059 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2060
2061 iter_reg = fw->xmt3_dma_reg;
2062 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2063 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2064
2065 iter_reg = fw->xmt4_dma_reg;
2066 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2067 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2068
2069 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2070
2071 /* Receive DMA registers. */
2072 iter_reg = fw->rcvt0_data_dma_reg;
2073 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2074 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2075
2076 iter_reg = fw->rcvt1_data_dma_reg;
2077 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2078 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2079
2080 /* RISC registers. */
2081 iter_reg = fw->risc_gp_reg;
2082 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2083 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2084 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2085 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2086 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2087 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2088 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2089 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2090
2091 /* Local memory controller registers. */
2092 iter_reg = fw->lmc_reg;
2093 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2096 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2097 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2098 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2099 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2100 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2101
2102 /* Fibre Protocol Module registers. */
2103 iter_reg = fw->fpm_hdw_reg;
2104 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2106 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2107 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2108 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2110 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2111 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2112 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2113 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2114 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2119 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2120
2121 /* RQ0 Array registers. */
2122 iter_reg = fw->rq0_array_reg;
2123 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2126 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2127 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2128 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2129 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2130 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2131 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2132 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2133 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2138 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2139
2140 /* RQ1 Array registers. */
2141 iter_reg = fw->rq1_array_reg;
2142 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2145 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2146 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2147 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2148 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2149 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2150 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2151 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2152 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2157 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2158
2159 /* RP0 Array registers. */
2160 iter_reg = fw->rp0_array_reg;
2161 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2164 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2165 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2166 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2167 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2168 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2169 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2170 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2171 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2176 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2177
2178 /* RP1 Array registers. */
2179 iter_reg = fw->rp1_array_reg;
2180 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2182 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2183 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2184 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2185 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2186 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2187 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2188 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2189 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2190 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2195 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2196
2197 iter_reg = fw->at0_array_reg;
2198 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2202 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2203 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2204 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2205 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2206
2207 /* I/O Queue Control registers. */
2208 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2209
2210 /* Frame Buffer registers. */
2211 iter_reg = fw->fb_hdw_reg;
2212 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2215 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2216 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2217 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2218 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2219 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2220 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2221 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2222 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2238 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2239
2240 /* Multi queue registers */
2241 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2242 &last_chain);
2243
2244 rval = qla24xx_soft_reset(ha);
2245 if (rval != QLA_SUCCESS) {
2246 ql_log(ql_log_warn, vha, 0xd00e,
2247 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2248 rval = QLA_SUCCESS;
2249
2250 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2251
2252 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2253 RD_REG_DWORD(&reg->hccr);
2254
2255 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2256 RD_REG_DWORD(&reg->hccr);
2257
2258 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2259 RD_REG_DWORD(&reg->hccr);
2260
2261 for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
2262 udelay(5);
2263
2264 if (!cnt) {
2265 nxt = fw->code_ram;
2266 nxt += sizeof(fw->code_ram),
2267 nxt += (ha->fw_memory_size - 0x100000 + 1);
2268 goto copy_queue;
2269 } else
2270 ql_log(ql_log_warn, vha, 0xd010,
2271 "bigger hammer success?\n");
2272 }
2273
2274 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2275 &nxt);
2276 if (rval != QLA_SUCCESS)
2277 goto qla83xx_fw_dump_failed_0;
2278
2279 copy_queue:
2280 nxt = qla2xxx_copy_queues(ha, nxt);
2281
2282 nxt = qla24xx_copy_eft(ha, nxt);
2283
2284 /* Chain entries -- started with MQ. */
2285 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2286 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2287 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2288 if (last_chain) {
2289 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2290 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2291 }
2292
2293 /* Adjust valid length. */
2294 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2295
2296 qla83xx_fw_dump_failed_0:
2297 qla2xxx_dump_post_process(base_vha, rval);
2298
2299 qla83xx_fw_dump_failed:
2300 if (!hardware_locked)
2301 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2302 }
2303
2304 /****************************************************************************/
2305 /* Driver Debug Functions. */
2306 /****************************************************************************/
2307
2308 static inline int
2309 ql_mask_match(uint32_t level)
2310 {
2311 if (ql2xextended_error_logging == 1)
2312 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2313 return (level & ql2xextended_error_logging) == level;
2314 }
2315
2316 /*
2317 * This function is for formatting and logging debug information.
2318 * It is to be used when vha is available. It formats the message
2319 * and logs it to the messages file.
2320 * parameters:
2321 * level: The level of the debug messages to be printed.
2322 * If ql2xextended_error_logging value is correctly set,
2323 * this message will appear in the messages file.
2324 * vha: Pointer to the scsi_qla_host_t.
2325 * id: This is a unique identifier for the level. It identifies the
2326 * part of the code from where the message originated.
2327 * msg: The message to be displayed.
2328 */
2329 void
2330 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2331 {
2332 va_list va;
2333 struct va_format vaf;
2334
2335 if (!ql_mask_match(level))
2336 return;
2337
2338 va_start(va, fmt);
2339
2340 vaf.fmt = fmt;
2341 vaf.va = &va;
2342
2343 if (vha != NULL) {
2344 const struct pci_dev *pdev = vha->hw->pdev;
2345 /* <module-name> <pci-name> <msg-id>:<host> Message */
2346 pr_warn("%s [%s]-%04x:%ld: %pV",
2347 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2348 vha->host_no, &vaf);
2349 } else {
2350 pr_warn("%s [%s]-%04x: : %pV",
2351 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2352 }
2353
2354 va_end(va);
2355
2356 }
2357
2358 /*
2359 * This function is for formatting and logging debug information.
2360 * It is to be used when vha is not available and pci is availble,
2361 * i.e., before host allocation. It formats the message and logs it
2362 * to the messages file.
2363 * parameters:
2364 * level: The level of the debug messages to be printed.
2365 * If ql2xextended_error_logging value is correctly set,
2366 * this message will appear in the messages file.
2367 * pdev: Pointer to the struct pci_dev.
2368 * id: This is a unique id for the level. It identifies the part
2369 * of the code from where the message originated.
2370 * msg: The message to be displayed.
2371 */
2372 void
2373 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2374 const char *fmt, ...)
2375 {
2376 va_list va;
2377 struct va_format vaf;
2378
2379 if (pdev == NULL)
2380 return;
2381 if (!ql_mask_match(level))
2382 return;
2383
2384 va_start(va, fmt);
2385
2386 vaf.fmt = fmt;
2387 vaf.va = &va;
2388
2389 /* <module-name> <dev-name>:<msg-id> Message */
2390 pr_warn("%s [%s]-%04x: : %pV",
2391 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2392
2393 va_end(va);
2394 }
2395
2396 /*
2397 * This function is for formatting and logging log messages.
2398 * It is to be used when vha is available. It formats the message
2399 * and logs it to the messages file. All the messages will be logged
2400 * irrespective of value of ql2xextended_error_logging.
2401 * parameters:
2402 * level: The level of the log messages to be printed in the
2403 * messages file.
2404 * vha: Pointer to the scsi_qla_host_t
2405 * id: This is a unique id for the level. It identifies the
2406 * part of the code from where the message originated.
2407 * msg: The message to be displayed.
2408 */
2409 void
2410 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2411 {
2412 va_list va;
2413 struct va_format vaf;
2414 char pbuf[128];
2415
2416 if (level > ql_errlev)
2417 return;
2418
2419 if (vha != NULL) {
2420 const struct pci_dev *pdev = vha->hw->pdev;
2421 /* <module-name> <msg-id>:<host> Message */
2422 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2423 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2424 } else {
2425 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2426 QL_MSGHDR, "0000:00:00.0", id);
2427 }
2428 pbuf[sizeof(pbuf) - 1] = 0;
2429
2430 va_start(va, fmt);
2431
2432 vaf.fmt = fmt;
2433 vaf.va = &va;
2434
2435 switch (level) {
2436 case ql_log_fatal: /* FATAL LOG */
2437 pr_crit("%s%pV", pbuf, &vaf);
2438 break;
2439 case ql_log_warn:
2440 pr_err("%s%pV", pbuf, &vaf);
2441 break;
2442 case ql_log_info:
2443 pr_warn("%s%pV", pbuf, &vaf);
2444 break;
2445 default:
2446 pr_info("%s%pV", pbuf, &vaf);
2447 break;
2448 }
2449
2450 va_end(va);
2451 }
2452
2453 /*
2454 * This function is for formatting and logging log messages.
2455 * It is to be used when vha is not available and pci is availble,
2456 * i.e., before host allocation. It formats the message and logs
2457 * it to the messages file. All the messages are logged irrespective
2458 * of the value of ql2xextended_error_logging.
2459 * parameters:
2460 * level: The level of the log messages to be printed in the
2461 * messages file.
2462 * pdev: Pointer to the struct pci_dev.
2463 * id: This is a unique id for the level. It identifies the
2464 * part of the code from where the message originated.
2465 * msg: The message to be displayed.
2466 */
2467 void
2468 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2469 const char *fmt, ...)
2470 {
2471 va_list va;
2472 struct va_format vaf;
2473 char pbuf[128];
2474
2475 if (pdev == NULL)
2476 return;
2477 if (level > ql_errlev)
2478 return;
2479
2480 /* <module-name> <dev-name>:<msg-id> Message */
2481 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2482 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2483 pbuf[sizeof(pbuf) - 1] = 0;
2484
2485 va_start(va, fmt);
2486
2487 vaf.fmt = fmt;
2488 vaf.va = &va;
2489
2490 switch (level) {
2491 case ql_log_fatal: /* FATAL LOG */
2492 pr_crit("%s%pV", pbuf, &vaf);
2493 break;
2494 case ql_log_warn:
2495 pr_err("%s%pV", pbuf, &vaf);
2496 break;
2497 case ql_log_info:
2498 pr_warn("%s%pV", pbuf, &vaf);
2499 break;
2500 default:
2501 pr_info("%s%pV", pbuf, &vaf);
2502 break;
2503 }
2504
2505 va_end(va);
2506 }
2507
2508 void
2509 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2510 {
2511 int i;
2512 struct qla_hw_data *ha = vha->hw;
2513 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2514 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2515 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2516 uint16_t __iomem *mbx_reg;
2517
2518 if (!ql_mask_match(level))
2519 return;
2520
2521 if (IS_QLA82XX(ha))
2522 mbx_reg = &reg82->mailbox_in[0];
2523 else if (IS_FWI2_CAPABLE(ha))
2524 mbx_reg = &reg24->mailbox0;
2525 else
2526 mbx_reg = MAILBOX_REG(ha, reg, 0);
2527
2528 ql_dbg(level, vha, id, "Mailbox registers:\n");
2529 for (i = 0; i < 6; i++)
2530 ql_dbg(level, vha, id,
2531 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2532 }
2533
2534
2535 void
2536 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2537 uint8_t *b, uint32_t size)
2538 {
2539 uint32_t cnt;
2540 uint8_t c;
2541
2542 if (!ql_mask_match(level))
2543 return;
2544
2545 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2546 "9 Ah Bh Ch Dh Eh Fh\n");
2547 ql_dbg(level, vha, id, "----------------------------------"
2548 "----------------------------\n");
2549
2550 ql_dbg(level, vha, id, " ");
2551 for (cnt = 0; cnt < size;) {
2552 c = *b++;
2553 printk("%02x", (uint32_t) c);
2554 cnt++;
2555 if (!(cnt % 16))
2556 printk("\n");
2557 else
2558 printk(" ");
2559 }
2560 if (cnt % 16)
2561 ql_dbg(level, vha, id, "\n");
2562 }
Linux ARM platform port for MOXA ART SoC