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Adding support for MOXA ART SoC. Testing port of linux-2.6.32.60-moxart.
[linux-3.6.7-moxart.git] / drivers / staging / sm7xxfb / sm7xxfb.c
blob1c1780c70fbb2374abdb834a49813d92691f45b4
1 /*
2 * Silicon Motion SM7XX frame buffer device
3 *
4 * Copyright (C) 2006 Silicon Motion Technology Corp.
5 * Authors: Ge Wang, gewang@siliconmotion.com
6 * Boyod boyod.yang@siliconmotion.com.cn
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 *
11 * Copyright (C) 2011 Igalia, S.L.
12 * Author: Javier M. Mellid <jmunhoz@igalia.com>
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file COPYING in the main directory of this archive for
16 * more details.
17 *
18 * Framebuffer driver for Silicon Motion SM710, SM712, SM721 and SM722 chips
19 */
20
21 #include <linux/io.h>
22 #include <linux/fb.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/slab.h>
26 #include <linux/uaccess.h>
27 #include <linux/module.h>
28 #include <linux/console.h>
29 #include <linux/screen_info.h>
30
31 #ifdef CONFIG_PM
32 #include <linux/pm.h>
33 #endif
34
35 #include "sm7xx.h"
36
37 /*
38 * Private structure
39 */
40 struct smtcfb_info {
41 struct pci_dev *pdev;
42 struct fb_info fb;
43 u16 chip_id;
44 u8 chip_rev_id;
45
46 unsigned char __iomem *m_pMMIO;
47 char __iomem *m_pLFB;
48 char *m_pDPR;
49 char *m_pVPR;
50 char *m_pCPR;
51
52 u_int width;
53 u_int height;
54 u_int hz;
55
56 u32 colreg[17];
57 };
58
59 char __iomem *smtc_RegBaseAddress; /* Memory Map IO starting address */
60 char __iomem *smtc_VRAMBaseAddress; /* video memory starting address */
61
62 static struct fb_var_screeninfo smtcfb_var = {
63 .xres = 1024,
64 .yres = 600,
65 .xres_virtual = 1024,
66 .yres_virtual = 600,
67 .bits_per_pixel = 16,
68 .red = {16, 8, 0},
69 .green = {8, 8, 0},
70 .blue = {0, 8, 0},
71 .activate = FB_ACTIVATE_NOW,
72 .height = -1,
73 .width = -1,
74 .vmode = FB_VMODE_NONINTERLACED,
75 };
76
77 static struct fb_fix_screeninfo smtcfb_fix = {
78 .id = "sm712fb",
79 .type = FB_TYPE_PACKED_PIXELS,
80 .visual = FB_VISUAL_TRUECOLOR,
81 .line_length = 800 * 3,
82 .accel = FB_ACCEL_SMI_LYNX,
83 };
84
85 struct vesa_mode {
86 char index[6];
87 u16 lfb_width;
88 u16 lfb_height;
89 u16 lfb_depth;
90 };
91
92 static struct vesa_mode vesa_mode_table[] = {
93 {"0x301", 640, 480, 8},
94 {"0x303", 800, 600, 8},
95 {"0x305", 1024, 768, 8},
96 {"0x307", 1280, 1024, 8},
97
98 {"0x311", 640, 480, 16},
99 {"0x314", 800, 600, 16},
100 {"0x317", 1024, 768, 16},
101 {"0x31A", 1280, 1024, 16},
102
103 {"0x312", 640, 480, 24},
104 {"0x315", 800, 600, 24},
105 {"0x318", 1024, 768, 24},
106 {"0x31B", 1280, 1024, 24},
107 };
108
109 struct screen_info smtc_scr_info;
110
111 /* process command line options, get vga parameter */
112 static int __init sm7xx_vga_setup(char *options)
113 {
114 int i;
115
116 if (!options || !*options)
117 return -EINVAL;
118
119 smtc_scr_info.lfb_width = 0;
120 smtc_scr_info.lfb_height = 0;
121 smtc_scr_info.lfb_depth = 0;
122
123 pr_debug("sm7xx_vga_setup = %s\n", options);
124
125 for (i = 0; i < ARRAY_SIZE(vesa_mode_table); i++) {
126 if (strstr(options, vesa_mode_table[i].index)) {
127 smtc_scr_info.lfb_width = vesa_mode_table[i].lfb_width;
128 smtc_scr_info.lfb_height = vesa_mode_table[i].lfb_height;
129 smtc_scr_info.lfb_depth = vesa_mode_table[i].lfb_depth;
130 return 0;
131 }
132 }
133
134 return -1;
135 }
136 __setup("vga=", sm7xx_vga_setup);
137
138 static void sm712_setpalette(int regno, unsigned red, unsigned green,
139 unsigned blue, struct fb_info *info)
140 {
141 /* set bit 5:4 = 01 (write LCD RAM only) */
142 smtc_seqw(0x66, (smtc_seqr(0x66) & 0xC3) | 0x10);
143
144 smtc_mmiowb(regno, dac_reg);
145 smtc_mmiowb(red >> 10, dac_val);
146 smtc_mmiowb(green >> 10, dac_val);
147 smtc_mmiowb(blue >> 10, dac_val);
148 }
149
150 /* chan_to_field
151 *
152 * convert a colour value into a field position
153 *
154 * from pxafb.c
155 */
156
157 static inline unsigned int chan_to_field(unsigned int chan,
158 struct fb_bitfield *bf)
159 {
160 chan &= 0xffff;
161 chan >>= 16 - bf->length;
162 return chan << bf->offset;
163 }
164
165 static int smtc_blank(int blank_mode, struct fb_info *info)
166 {
167 /* clear DPMS setting */
168 switch (blank_mode) {
169 case FB_BLANK_UNBLANK:
170 /* Screen On: HSync: On, VSync : On */
171 smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
172 smtc_seqw(0x6a, 0x16);
173 smtc_seqw(0x6b, 0x02);
174 smtc_seqw(0x21, (smtc_seqr(0x21) & 0x77));
175 smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
176 smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
177 smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
178 smtc_seqw(0x31, (smtc_seqr(0x31) | 0x03));
179 break;
180 case FB_BLANK_NORMAL:
181 /* Screen Off: HSync: On, VSync : On Soft blank */
182 smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
183 smtc_seqw(0x6a, 0x16);
184 smtc_seqw(0x6b, 0x02);
185 smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
186 smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
187 smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
188 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
189 break;
190 case FB_BLANK_VSYNC_SUSPEND:
191 /* Screen On: HSync: On, VSync : Off */
192 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
193 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
194 smtc_seqw(0x6a, 0x0c);
195 smtc_seqw(0x6b, 0x02);
196 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
197 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x20));
198 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0x20));
199 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
200 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
201 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
202 break;
203 case FB_BLANK_HSYNC_SUSPEND:
204 /* Screen On: HSync: Off, VSync : On */
205 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
206 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
207 smtc_seqw(0x6a, 0x0c);
208 smtc_seqw(0x6b, 0x02);
209 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
210 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x10));
211 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
212 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
213 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
214 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
215 break;
216 case FB_BLANK_POWERDOWN:
217 /* Screen On: HSync: Off, VSync : Off */
218 smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
219 smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
220 smtc_seqw(0x6a, 0x0c);
221 smtc_seqw(0x6b, 0x02);
222 smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
223 smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x30));
224 smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
225 smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
226 smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
227 smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
228 break;
229 default:
230 return -EINVAL;
231 }
232
233 return 0;
234 }
235
236 static int smtc_setcolreg(unsigned regno, unsigned red, unsigned green,
237 unsigned blue, unsigned trans, struct fb_info *info)
238 {
239 struct smtcfb_info *sfb;
240 u32 val;
241
242 sfb = info->par;
243
244 if (regno > 255)
245 return 1;
246
247 switch (sfb->fb.fix.visual) {
248 case FB_VISUAL_DIRECTCOLOR:
249 case FB_VISUAL_TRUECOLOR:
250 /*
251 * 16/32 bit true-colour, use pseudo-palette for 16 base color
252 */
253 if (regno < 16) {
254 if (sfb->fb.var.bits_per_pixel == 16) {
255 u32 *pal = sfb->fb.pseudo_palette;
256 val = chan_to_field(red, &sfb->fb.var.red);
257 val |= chan_to_field(green, \
258 &sfb->fb.var.green);
259 val |= chan_to_field(blue, &sfb->fb.var.blue);
260 #ifdef __BIG_ENDIAN
261 pal[regno] =
262 ((red & 0xf800) >> 8) |
263 ((green & 0xe000) >> 13) |
264 ((green & 0x1c00) << 3) |
265 ((blue & 0xf800) >> 3);
266 #else
267 pal[regno] = val;
268 #endif
269 } else {
270 u32 *pal = sfb->fb.pseudo_palette;
271 val = chan_to_field(red, &sfb->fb.var.red);
272 val |= chan_to_field(green, \
273 &sfb->fb.var.green);
274 val |= chan_to_field(blue, &sfb->fb.var.blue);
275 #ifdef __BIG_ENDIAN
276 val =
277 (val & 0xff00ff00 >> 8) |
278 (val & 0x00ff00ff << 8);
279 #endif
280 pal[regno] = val;
281 }
282 }
283 break;
284
285 case FB_VISUAL_PSEUDOCOLOR:
286 /* color depth 8 bit */
287 sm712_setpalette(regno, red, green, blue, info);
288 break;
289
290 default:
291 return 1; /* unknown type */
292 }
293
294 return 0;
295
296 }
297
298 #ifdef __BIG_ENDIAN
299 static ssize_t smtcfb_read(struct fb_info *info, char __user *buf, size_t
300 count, loff_t *ppos)
301 {
302 unsigned long p = *ppos;
303
304 u32 *buffer, *dst;
305 u32 __iomem *src;
306 int c, i, cnt = 0, err = 0;
307 unsigned long total_size;
308
309 if (!info || !info->screen_base)
310 return -ENODEV;
311
312 if (info->state != FBINFO_STATE_RUNNING)
313 return -EPERM;
314
315 total_size = info->screen_size;
316
317 if (total_size == 0)
318 total_size = info->fix.smem_len;
319
320 if (p >= total_size)
321 return 0;
322
323 if (count >= total_size)
324 count = total_size;
325
326 if (count + p > total_size)
327 count = total_size - p;
328
329 buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL);
330 if (!buffer)
331 return -ENOMEM;
332
333 src = (u32 __iomem *) (info->screen_base + p);
334
335 if (info->fbops->fb_sync)
336 info->fbops->fb_sync(info);
337
338 while (count) {
339 c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
340 dst = buffer;
341 for (i = c >> 2; i--;) {
342 *dst = fb_readl(src++);
343 *dst =
344 (*dst & 0xff00ff00 >> 8) |
345 (*dst & 0x00ff00ff << 8);
346 dst++;
347 }
348 if (c & 3) {
349 u8 *dst8 = (u8 *) dst;
350 u8 __iomem *src8 = (u8 __iomem *) src;
351
352 for (i = c & 3; i--;) {
353 if (i & 1) {
354 *dst8++ = fb_readb(++src8);
355 } else {
356 *dst8++ = fb_readb(--src8);
357 src8 += 2;
358 }
359 }
360 src = (u32 __iomem *) src8;
361 }
362
363 if (copy_to_user(buf, buffer, c)) {
364 err = -EFAULT;
365 break;
366 }
367 *ppos += c;
368 buf += c;
369 cnt += c;
370 count -= c;
371 }
372
373 kfree(buffer);
374
375 return (err) ? err : cnt;
376 }
377
378 static ssize_t
379 smtcfb_write(struct fb_info *info, const char __user *buf, size_t count,
380 loff_t *ppos)
381 {
382 unsigned long p = *ppos;
383
384 u32 *buffer, *src;
385 u32 __iomem *dst;
386 int c, i, cnt = 0, err = 0;
387 unsigned long total_size;
388
389 if (!info || !info->screen_base)
390 return -ENODEV;
391
392 if (info->state != FBINFO_STATE_RUNNING)
393 return -EPERM;
394
395 total_size = info->screen_size;
396
397 if (total_size == 0)
398 total_size = info->fix.smem_len;
399
400 if (p > total_size)
401 return -EFBIG;
402
403 if (count > total_size) {
404 err = -EFBIG;
405 count = total_size;
406 }
407
408 if (count + p > total_size) {
409 if (!err)
410 err = -ENOSPC;
411
412 count = total_size - p;
413 }
414
415 buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count, GFP_KERNEL);
416 if (!buffer)
417 return -ENOMEM;
418
419 dst = (u32 __iomem *) (info->screen_base + p);
420
421 if (info->fbops->fb_sync)
422 info->fbops->fb_sync(info);
423
424 while (count) {
425 c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
426 src = buffer;
427
428 if (copy_from_user(src, buf, c)) {
429 err = -EFAULT;
430 break;
431 }
432
433 for (i = c >> 2; i--;) {
434 fb_writel((*src & 0xff00ff00 >> 8) |
435 (*src & 0x00ff00ff << 8), dst++);
436 src++;
437 }
438 if (c & 3) {
439 u8 *src8 = (u8 *) src;
440 u8 __iomem *dst8 = (u8 __iomem *) dst;
441
442 for (i = c & 3; i--;) {
443 if (i & 1) {
444 fb_writeb(*src8++, ++dst8);
445 } else {
446 fb_writeb(*src8++, --dst8);
447 dst8 += 2;
448 }
449 }
450 dst = (u32 __iomem *) dst8;
451 }
452
453 *ppos += c;
454 buf += c;
455 cnt += c;
456 count -= c;
457 }
458
459 kfree(buffer);
460
461 return (cnt) ? cnt : err;
462 }
463 #endif /* ! __BIG_ENDIAN */
464
465 static void sm7xx_set_timing(struct smtcfb_info *sfb)
466 {
467 int i = 0, j = 0;
468 u32 m_nScreenStride;
469
470 dev_dbg(&sfb->pdev->dev,
471 "sfb->width=%d sfb->height=%d "
472 "sfb->fb.var.bits_per_pixel=%d sfb->hz=%d\n",
473 sfb->width, sfb->height, sfb->fb.var.bits_per_pixel, sfb->hz);
474
475 for (j = 0; j < numVGAModes; j++) {
476 if (VGAMode[j].mmSizeX == sfb->width &&
477 VGAMode[j].mmSizeY == sfb->height &&
478 VGAMode[j].bpp == sfb->fb.var.bits_per_pixel &&
479 VGAMode[j].hz == sfb->hz) {
480
481 dev_dbg(&sfb->pdev->dev,
482 "VGAMode[j].mmSizeX=%d VGAMode[j].mmSizeY=%d "
483 "VGAMode[j].bpp=%d VGAMode[j].hz=%d\n",
484 VGAMode[j].mmSizeX, VGAMode[j].mmSizeY,
485 VGAMode[j].bpp, VGAMode[j].hz);
486
487 dev_dbg(&sfb->pdev->dev, "VGAMode index=%d\n", j);
488
489 smtc_mmiowb(0x0, 0x3c6);
490
491 smtc_seqw(0, 0x1);
492
493 smtc_mmiowb(VGAMode[j].Init_MISC, 0x3c2);
494
495 /* init SEQ register SR00 - SR04 */
496 for (i = 0; i < SIZE_SR00_SR04; i++)
497 smtc_seqw(i, VGAMode[j].Init_SR00_SR04[i]);
498
499 /* init SEQ register SR10 - SR24 */
500 for (i = 0; i < SIZE_SR10_SR24; i++)
501 smtc_seqw(i + 0x10,
502 VGAMode[j].Init_SR10_SR24[i]);
503
504 /* init SEQ register SR30 - SR75 */
505 for (i = 0; i < SIZE_SR30_SR75; i++)
506 if (((i + 0x30) != 0x62) \
507 && ((i + 0x30) != 0x6a) \
508 && ((i + 0x30) != 0x6b))
509 smtc_seqw(i + 0x30,
510 VGAMode[j].Init_SR30_SR75[i]);
511
512 /* init SEQ register SR80 - SR93 */
513 for (i = 0; i < SIZE_SR80_SR93; i++)
514 smtc_seqw(i + 0x80,
515 VGAMode[j].Init_SR80_SR93[i]);
516
517 /* init SEQ register SRA0 - SRAF */
518 for (i = 0; i < SIZE_SRA0_SRAF; i++)
519 smtc_seqw(i + 0xa0,
520 VGAMode[j].Init_SRA0_SRAF[i]);
521
522 /* init Graphic register GR00 - GR08 */
523 for (i = 0; i < SIZE_GR00_GR08; i++)
524 smtc_grphw(i, VGAMode[j].Init_GR00_GR08[i]);
525
526 /* init Attribute register AR00 - AR14 */
527 for (i = 0; i < SIZE_AR00_AR14; i++)
528 smtc_attrw(i, VGAMode[j].Init_AR00_AR14[i]);
529
530 /* init CRTC register CR00 - CR18 */
531 for (i = 0; i < SIZE_CR00_CR18; i++)
532 smtc_crtcw(i, VGAMode[j].Init_CR00_CR18[i]);
533
534 /* init CRTC register CR30 - CR4D */
535 for (i = 0; i < SIZE_CR30_CR4D; i++)
536 smtc_crtcw(i + 0x30,
537 VGAMode[j].Init_CR30_CR4D[i]);
538
539 /* init CRTC register CR90 - CRA7 */
540 for (i = 0; i < SIZE_CR90_CRA7; i++)
541 smtc_crtcw(i + 0x90,
542 VGAMode[j].Init_CR90_CRA7[i]);
543 }
544 }
545 smtc_mmiowb(0x67, 0x3c2);
546
547 /* set VPR registers */
548 writel(0x0, sfb->m_pVPR + 0x0C);
549 writel(0x0, sfb->m_pVPR + 0x40);
550
551 /* set data width */
552 m_nScreenStride =
553 (sfb->width * sfb->fb.var.bits_per_pixel) / 64;
554 switch (sfb->fb.var.bits_per_pixel) {
555 case 8:
556 writel(0x0, sfb->m_pVPR + 0x0);
557 break;
558 case 16:
559 writel(0x00020000, sfb->m_pVPR + 0x0);
560 break;
561 case 24:
562 writel(0x00040000, sfb->m_pVPR + 0x0);
563 break;
564 case 32:
565 writel(0x00030000, sfb->m_pVPR + 0x0);
566 break;
567 }
568 writel((u32) (((m_nScreenStride + 2) << 16) | m_nScreenStride),
569 sfb->m_pVPR + 0x10);
570
571 }
572
573 static void smtc_set_timing(struct smtcfb_info *sfb)
574 {
575 switch (sfb->chip_id) {
576 case 0x710:
577 case 0x712:
578 case 0x720:
579 sm7xx_set_timing(sfb);
580 break;
581 }
582 }
583
584 void smtcfb_setmode(struct smtcfb_info *sfb)
585 {
586 switch (sfb->fb.var.bits_per_pixel) {
587 case 32:
588 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
589 sfb->fb.fix.line_length = sfb->fb.var.xres * 4;
590 sfb->fb.var.red.length = 8;
591 sfb->fb.var.green.length = 8;
592 sfb->fb.var.blue.length = 8;
593 sfb->fb.var.red.offset = 16;
594 sfb->fb.var.green.offset = 8;
595 sfb->fb.var.blue.offset = 0;
596 break;
597 case 24:
598 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
599 sfb->fb.fix.line_length = sfb->fb.var.xres * 3;
600 sfb->fb.var.red.length = 8;
601 sfb->fb.var.green.length = 8;
602 sfb->fb.var.blue.length = 8;
603 sfb->fb.var.red.offset = 16;
604 sfb->fb.var.green.offset = 8;
605 sfb->fb.var.blue.offset = 0;
606 break;
607 case 8:
608 sfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
609 sfb->fb.fix.line_length = sfb->fb.var.xres;
610 sfb->fb.var.red.length = 3;
611 sfb->fb.var.green.length = 3;
612 sfb->fb.var.blue.length = 2;
613 sfb->fb.var.red.offset = 5;
614 sfb->fb.var.green.offset = 2;
615 sfb->fb.var.blue.offset = 0;
616 break;
617 case 16:
618 default:
619 sfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
620 sfb->fb.fix.line_length = sfb->fb.var.xres * 2;
621 sfb->fb.var.red.length = 5;
622 sfb->fb.var.green.length = 6;
623 sfb->fb.var.blue.length = 5;
624 sfb->fb.var.red.offset = 11;
625 sfb->fb.var.green.offset = 5;
626 sfb->fb.var.blue.offset = 0;
627 break;
628 }
629
630 sfb->width = sfb->fb.var.xres;
631 sfb->height = sfb->fb.var.yres;
632 sfb->hz = 60;
633 smtc_set_timing(sfb);
634 }
635
636 static int smtc_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
637 {
638 /* sanity checks */
639 if (var->xres_virtual < var->xres)
640 var->xres_virtual = var->xres;
641
642 if (var->yres_virtual < var->yres)
643 var->yres_virtual = var->yres;
644
645 /* set valid default bpp */
646 if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16) &&
647 (var->bits_per_pixel != 24) && (var->bits_per_pixel != 32))
648 var->bits_per_pixel = 16;
649
650 return 0;
651 }
652
653 static int smtc_set_par(struct fb_info *info)
654 {
655 smtcfb_setmode(info->par);
656
657 return 0;
658 }
659
660 static struct fb_ops smtcfb_ops = {
661 .owner = THIS_MODULE,
662 .fb_check_var = smtc_check_var,
663 .fb_set_par = smtc_set_par,
664 .fb_setcolreg = smtc_setcolreg,
665 .fb_blank = smtc_blank,
666 .fb_fillrect = cfb_fillrect,
667 .fb_imageblit = cfb_imageblit,
668 .fb_copyarea = cfb_copyarea,
669 #ifdef __BIG_ENDIAN
670 .fb_read = smtcfb_read,
671 .fb_write = smtcfb_write,
672 #endif
673 };
674
675 /*
676 * alloc struct smtcfb_info and assign the default value
677 */
678 static struct smtcfb_info *smtc_alloc_fb_info(struct pci_dev *pdev, char *name)
679 {
680 struct smtcfb_info *sfb;
681
682 sfb = kzalloc(sizeof(*sfb), GFP_KERNEL);
683
684 if (!sfb)
685 return NULL;
686
687 sfb->pdev = pdev;
688
689 /* init sfb->fb with default value */
690
691 sfb->fb.flags = FBINFO_FLAG_DEFAULT;
692 sfb->fb.fbops = &smtcfb_ops;
693
694 sfb->fb.fix = smtcfb_fix;
695 strcpy(sfb->fb.fix.id, name);
696
697 sfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
698 sfb->fb.fix.type_aux = 0;
699 sfb->fb.fix.xpanstep = 0;
700 sfb->fb.fix.ypanstep = 0;
701 sfb->fb.fix.ywrapstep = 0;
702 sfb->fb.fix.accel = FB_ACCEL_SMI_LYNX;
703
704 sfb->fb.var = smtcfb_var;
705 sfb->fb.var.nonstd = 0;
706 sfb->fb.var.activate = FB_ACTIVATE_NOW;
707 sfb->fb.var.height = -1;
708 sfb->fb.var.width = -1;
709 sfb->fb.var.accel_flags = FB_ACCELF_TEXT;
710 sfb->fb.var.vmode = FB_VMODE_NONINTERLACED;
711
712 sfb->fb.pseudo_palette = sfb->colreg;
713
714 sfb->fb.par = sfb;
715
716 return sfb;
717 }
718
719 /*
720 * free struct smtcfb_info
721 */
722 static void smtc_free_fb_info(struct smtcfb_info *sfb)
723 {
724 kfree(sfb);
725 }
726
727 /*
728 * Unmap in the memory mapped IO registers
729 */
730
731 static void smtc_unmap_mmio(struct smtcfb_info *sfb)
732 {
733 if (sfb && smtc_RegBaseAddress)
734 smtc_RegBaseAddress = NULL;
735 }
736
737 /*
738 * Map in the screen memory
739 */
740
741 static int smtc_map_smem(struct smtcfb_info *sfb,
742 struct pci_dev *pdev, u_long smem_len)
743 {
744
745 sfb->fb.fix.smem_start = pci_resource_start(pdev, 0);
746
747 #ifdef __BIG_ENDIAN
748 if (sfb->fb.var.bits_per_pixel == 32)
749 sfb->fb.fix.smem_start += 0x800000;
750 #endif
751
752 sfb->fb.fix.smem_len = smem_len;
753
754 sfb->fb.screen_base = smtc_VRAMBaseAddress;
755
756 if (!sfb->fb.screen_base) {
757 dev_err(&pdev->dev,
758 "%s: unable to map screen memory\n", sfb->fb.fix.id);
759 return -ENOMEM;
760 }
761
762 return 0;
763 }
764
765 /*
766 * Unmap in the screen memory
767 *
768 */
769 static void smtc_unmap_smem(struct smtcfb_info *sfb)
770 {
771 if (sfb && sfb->fb.screen_base) {
772 iounmap(sfb->fb.screen_base);
773 sfb->fb.screen_base = NULL;
774 }
775 }
776
777 /*
778 * We need to wake up the device and make sure its in linear memory mode.
779 */
780 static inline void sm7xx_init_hw(void)
781 {
782 outb_p(0x18, 0x3c4);
783 outb_p(0x11, 0x3c5);
784 }
785
786 static int __devinit smtcfb_pci_probe(struct pci_dev *pdev,
787 const struct pci_device_id *ent)
788 {
789 struct smtcfb_info *sfb;
790 u_long smem_size = 0x00800000; /* default 8MB */
791 char name[16];
792 int err;
793 unsigned long pFramebufferPhysical;
794
795 dev_info(&pdev->dev, "Silicon Motion display driver.");
796
797 err = pci_enable_device(pdev); /* enable SMTC chip */
798 if (err)
799 return err;
800
801 sfb = smtc_alloc_fb_info(pdev, name);
802
803 if (!sfb) {
804 err = -ENOMEM;
805 goto failed_free;
806 }
807
808 sfb->chip_id = ent->device;
809 sprintf(name, "sm%Xfb", sfb->chip_id);
810
811 pci_set_drvdata(pdev, sfb);
812
813 sm7xx_init_hw();
814
815 /* get mode parameter from smtc_scr_info */
816 if (smtc_scr_info.lfb_width != 0) {
817 sfb->fb.var.xres = smtc_scr_info.lfb_width;
818 sfb->fb.var.yres = smtc_scr_info.lfb_height;
819 sfb->fb.var.bits_per_pixel = smtc_scr_info.lfb_depth;
820 } else {
821 /* default resolution 1024x600 16bit mode */
822 sfb->fb.var.xres = SCREEN_X_RES;
823 sfb->fb.var.yres = SCREEN_Y_RES;
824 sfb->fb.var.bits_per_pixel = SCREEN_BPP;
825 }
826
827 #ifdef __BIG_ENDIAN
828 if (sfb->fb.var.bits_per_pixel == 24)
829 sfb->fb.var.bits_per_pixel = (smtc_scr_info.lfb_depth = 32);
830 #endif
831 /* Map address and memory detection */
832 pFramebufferPhysical = pci_resource_start(pdev, 0);
833 pci_read_config_byte(pdev, PCI_REVISION_ID, &sfb->chip_rev_id);
834
835 switch (sfb->chip_id) {
836 case 0x710:
837 case 0x712:
838 sfb->fb.fix.mmio_start = pFramebufferPhysical + 0x00400000;
839 sfb->fb.fix.mmio_len = 0x00400000;
840 smem_size = SM712_VIDEOMEMORYSIZE;
841 #ifdef __BIG_ENDIAN
842 sfb->m_pLFB = (smtc_VRAMBaseAddress =
843 ioremap(pFramebufferPhysical, 0x00c00000));
844 #else
845 sfb->m_pLFB = (smtc_VRAMBaseAddress =
846 ioremap(pFramebufferPhysical, 0x00800000));
847 #endif
848 sfb->m_pMMIO = (smtc_RegBaseAddress =
849 smtc_VRAMBaseAddress + 0x00700000);
850 sfb->m_pDPR = smtc_VRAMBaseAddress + 0x00408000;
851 sfb->m_pVPR = sfb->m_pLFB + 0x0040c000;
852 #ifdef __BIG_ENDIAN
853 if (sfb->fb.var.bits_per_pixel == 32) {
854 smtc_VRAMBaseAddress += 0x800000;
855 sfb->m_pLFB += 0x800000;
856 dev_info(&pdev->dev,
857 "smtc_VRAMBaseAddress=%p sfb->m_pLFB=%p",
858 smtc_VRAMBaseAddress, sfb->m_pLFB);
859 }
860 #endif
861 if (!smtc_RegBaseAddress) {
862 dev_err(&pdev->dev,
863 "%s: unable to map memory mapped IO!",
864 sfb->fb.fix.id);
865 err = -ENOMEM;
866 goto failed_fb;
867 }
868
869 /* set MCLK = 14.31818 * (0x16 / 0x2) */
870 smtc_seqw(0x6a, 0x16);
871 smtc_seqw(0x6b, 0x02);
872 smtc_seqw(0x62, 0x3e);
873 /* enable PCI burst */
874 smtc_seqw(0x17, 0x20);
875 /* enable word swap */
876 #ifdef __BIG_ENDIAN
877 if (sfb->fb.var.bits_per_pixel == 32)
878 smtc_seqw(0x17, 0x30);
879 #endif
880 break;
881 case 0x720:
882 sfb->fb.fix.mmio_start = pFramebufferPhysical;
883 sfb->fb.fix.mmio_len = 0x00200000;
884 smem_size = SM722_VIDEOMEMORYSIZE;
885 sfb->m_pDPR = ioremap(pFramebufferPhysical, 0x00a00000);
886 sfb->m_pLFB = (smtc_VRAMBaseAddress =
887 sfb->m_pDPR + 0x00200000);
888 sfb->m_pMMIO = (smtc_RegBaseAddress =
889 sfb->m_pDPR + 0x000c0000);
890 sfb->m_pVPR = sfb->m_pDPR + 0x800;
891
892 smtc_seqw(0x62, 0xff);
893 smtc_seqw(0x6a, 0x0d);
894 smtc_seqw(0x6b, 0x02);
895 break;
896 default:
897 dev_err(&pdev->dev,
898 "No valid Silicon Motion display chip was detected!");
899
900 goto failed_fb;
901 }
902
903 /* can support 32 bpp */
904 if (15 == sfb->fb.var.bits_per_pixel)
905 sfb->fb.var.bits_per_pixel = 16;
906
907 sfb->fb.var.xres_virtual = sfb->fb.var.xres;
908 sfb->fb.var.yres_virtual = sfb->fb.var.yres;
909 err = smtc_map_smem(sfb, pdev, smem_size);
910 if (err)
911 goto failed;
912
913 smtcfb_setmode(sfb);
914
915 err = register_framebuffer(&sfb->fb);
916 if (err < 0)
917 goto failed;
918
919 dev_info(&pdev->dev,
920 "Silicon Motion SM%X Rev%X primary display mode %dx%d-%d Init Complete.",
921 sfb->chip_id, sfb->chip_rev_id, sfb->fb.var.xres,
922 sfb->fb.var.yres, sfb->fb.var.bits_per_pixel);
923
924 return 0;
925
926 failed:
927 dev_err(&pdev->dev, "Silicon Motion, Inc. primary display init fail.");
928
929 smtc_unmap_smem(sfb);
930 smtc_unmap_mmio(sfb);
931 failed_fb:
932 smtc_free_fb_info(sfb);
933
934 failed_free:
935 pci_disable_device(pdev);
936
937 return err;
938 }
939
940 /*
941 * 0x710 (LynxEM)
942 * 0x712 (LynxEM+)
943 * 0x720 (Lynx3DM, Lynx3DM+)
944 */
945 static DEFINE_PCI_DEVICE_TABLE(smtcfb_pci_table) = {
946 { PCI_DEVICE(0x126f, 0x710), },
947 { PCI_DEVICE(0x126f, 0x712), },
948 { PCI_DEVICE(0x126f, 0x720), },
949 {0,}
950 };
951
952 static void __devexit smtcfb_pci_remove(struct pci_dev *pdev)
953 {
954 struct smtcfb_info *sfb;
955
956 sfb = pci_get_drvdata(pdev);
957 pci_set_drvdata(pdev, NULL);
958 smtc_unmap_smem(sfb);
959 smtc_unmap_mmio(sfb);
960 unregister_framebuffer(&sfb->fb);
961 smtc_free_fb_info(sfb);
962 }
963
964 #ifdef CONFIG_PM
965 static int smtcfb_pci_suspend(struct device *device)
966 {
967 struct pci_dev *pdev = to_pci_dev(device);
968 struct smtcfb_info *sfb;
969
970 sfb = pci_get_drvdata(pdev);
971
972 /* set the hw in sleep mode use external clock and self memory refresh
973 * so that we can turn off internal PLLs later on
974 */
975 smtc_seqw(0x20, (smtc_seqr(0x20) | 0xc0));
976 smtc_seqw(0x69, (smtc_seqr(0x69) & 0xf7));
977
978 console_lock();
979 fb_set_suspend(&sfb->fb, 1);
980 console_unlock();
981
982 /* additionally turn off all function blocks including internal PLLs */
983 smtc_seqw(0x21, 0xff);
984
985 return 0;
986 }
987
988 static int smtcfb_pci_resume(struct device *device)
989 {
990 struct pci_dev *pdev = to_pci_dev(device);
991 struct smtcfb_info *sfb;
992
993 sfb = pci_get_drvdata(pdev);
994
995 /* reinit hardware */
996 sm7xx_init_hw();
997 switch (sfb->chip_id) {
998 case 0x710:
999 case 0x712:
1000 /* set MCLK = 14.31818 * (0x16 / 0x2) */
1001 smtc_seqw(0x6a, 0x16);
1002 smtc_seqw(0x6b, 0x02);
1003 smtc_seqw(0x62, 0x3e);
1004 /* enable PCI burst */
1005 smtc_seqw(0x17, 0x20);
1006 #ifdef __BIG_ENDIAN
1007 if (sfb->fb.var.bits_per_pixel == 32)
1008 smtc_seqw(0x17, 0x30);
1009 #endif
1010 break;
1011 case 0x720:
1012 smtc_seqw(0x62, 0xff);
1013 smtc_seqw(0x6a, 0x0d);
1014 smtc_seqw(0x6b, 0x02);
1015 break;
1016 }
1017
1018 smtc_seqw(0x34, (smtc_seqr(0x34) | 0xc0));
1019 smtc_seqw(0x33, ((smtc_seqr(0x33) | 0x08) & 0xfb));
1020
1021 smtcfb_setmode(sfb);
1022
1023 console_lock();
1024 fb_set_suspend(&sfb->fb, 0);
1025 console_unlock();
1026
1027 return 0;
1028 }
1029
1030 static const struct dev_pm_ops sm7xx_pm_ops = {
1031 .suspend = smtcfb_pci_suspend,
1032 .resume = smtcfb_pci_resume,
1033 .freeze = smtcfb_pci_suspend,
1034 .thaw = smtcfb_pci_resume,
1035 .poweroff = smtcfb_pci_suspend,
1036 .restore = smtcfb_pci_resume,
1037 };
1038
1039 #define SM7XX_PM_OPS (&sm7xx_pm_ops)
1040
1041 #else /* !CONFIG_PM */
1042
1043 #define SM7XX_PM_OPS NULL
1044
1045 #endif /* !CONFIG_PM */
1046
1047 static struct pci_driver smtcfb_driver = {
1048 .name = "smtcfb",
1049 .id_table = smtcfb_pci_table,
1050 .probe = smtcfb_pci_probe,
1051 .remove = __devexit_p(smtcfb_pci_remove),
1052 .driver.pm = SM7XX_PM_OPS,
1053 };
1054
1055 module_pci_driver(smtcfb_driver);
1056
1057 MODULE_AUTHOR("Siliconmotion ");
1058 MODULE_DESCRIPTION("Framebuffer driver for SMI Graphic Cards");
1059 MODULE_LICENSE("GPL");
Linux ARM platform port for MOXA ART SoC