drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           iaa;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 /*
  66  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  67  * controller may be doing DMA.  Lower values mean there's no DMA.
  68  */
  69 enum ehci_rh_state {
  70         EHCI_RH_HALTED,
  71         EHCI_RH_SUSPENDED,
  72         EHCI_RH_RUNNING,
  73         EHCI_RH_STOPPING
  74 };
  75
  76 /*
  77  * Timer events, ordered by increasing delay length.
  78  * Always update event_delays_ns[] and event_handlers[] (defined in
  79  * ehci-timer.c) in parallel with this list.
  80  */
  81 enum ehci_hrtimer_event {
  82         EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
  83         EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
  84         EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
  85         EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
  86         EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
  87         EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
  88         EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
  89         EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
  90         EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
  91         EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
  92         EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
  93 };
  94 #define EHCI_HRTIMER_NO_EVENT   99
  95
  96 struct ehci_hcd {                       /* one per controller */
  97         /* timing support */
  98         enum ehci_hrtimer_event next_hrtimer_event;
  99         unsigned                enabled_hrtimer_events;
 100         ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 101         struct hrtimer          hrtimer;
 102
 103         int                     PSS_poll_count;
 104         int                     ASS_poll_count;
 105         int                     died_poll_count;
 106
 107         /* glue to PCI and HCD framework */
 108         struct ehci_caps __iomem *caps;
 109         struct ehci_regs __iomem *regs;
 110         struct ehci_dbg_port __iomem *debug;
 111
 112         __u32                   hcs_params;     /* cached register copy */
 113         spinlock_t              lock;
 114         enum ehci_rh_state      rh_state;
 115
 116         /* general schedule support */
 117         bool                    scanning:1;
 118         bool                    need_rescan:1;
 119         bool                    intr_unlinking:1;
 120         bool                    async_unlinking:1;
 121         bool                    shutdown:1;
 122         struct ehci_qh          *qh_scan_next;
 123
 124         /* async schedule support */
 125         struct ehci_qh          *async;
 126         struct ehci_qh          *dummy;         /* For AMD quirk use */
 127         struct ehci_qh          *async_unlink;
 128         struct ehci_qh          *async_unlink_last;
 129         struct ehci_qh          *async_iaa;
 130         unsigned                async_unlink_cycle;
 131         unsigned                async_count;    /* async activity count */
 132
 133         /* periodic schedule support */
 134 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 135         unsigned                periodic_size;
 136         __hc32                  *periodic;      /* hw periodic table */
 137         dma_addr_t              periodic_dma;
 138         struct list_head        intr_qh_list;
 139         unsigned                i_thresh;       /* uframes HC might cache */
 140
 141         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 142         struct ehci_qh          *intr_unlink;
 143         struct ehci_qh          *intr_unlink_last;
 144         unsigned                intr_unlink_cycle;
 145         unsigned                now_frame;      /* frame from HC hardware */
 146         unsigned                next_frame;     /* scan periodic, start here */
 147         unsigned                intr_count;     /* intr activity count */
 148         unsigned                isoc_count;     /* isoc activity count */
 149         unsigned                periodic_count; /* periodic activity count */
 150         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 151
 152
 153         /* list of itds & sitds completed while now_frame was still active */
 154         struct list_head        cached_itd_list;
 155         struct ehci_itd         *last_itd_to_free;
 156         struct list_head        cached_sitd_list;
 157         struct ehci_sitd        *last_sitd_to_free;
 158
 159         /* per root hub port */
 160         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 161
 162         /* bit vectors (one bit per port) */
 163         unsigned long           bus_suspended;          /* which ports were
 164                         already suspended at the start of a bus suspend */
 165         unsigned long           companion_ports;        /* which ports are
 166                         dedicated to the companion controller */
 167         unsigned long           owned_ports;            /* which ports are
 168                         owned by the companion during a bus suspend */
 169         unsigned long           port_c_suspend;         /* which ports have
 170                         the change-suspend feature turned on */
 171         unsigned long           suspended_ports;        /* which ports are
 172                         suspended */
 173         unsigned long           resuming_ports;         /* which ports have
 174                         started to resume */
 175
 176         /* per-HC memory pools (could be per-bus, but ...) */
 177         struct dma_pool         *qh_pool;       /* qh per active urb */
 178         struct dma_pool         *qtd_pool;      /* one or more per qh */
 179         struct dma_pool         *itd_pool;      /* itd per iso urb */
 180         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 181
 182         unsigned                random_frame;
 183         unsigned long           next_statechange;
 184         ktime_t                 last_periodic_enable;
 185         u32                     command;
 186
 187         /* SILICON QUIRKS */
 188         unsigned                no_selective_suspend:1;
 189         unsigned                has_fsl_port_bug:1; /* FreeScale */
 190         unsigned                big_endian_mmio:1;
 191         unsigned                big_endian_desc:1;
 192         unsigned                big_endian_capbase:1;
 193         unsigned                has_amcc_usb23:1;
 194         unsigned                need_io_watchdog:1;
 195         unsigned                amd_pll_fix:1;
 196         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 197         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 198         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 199         unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 200
 201         /* required for usb32 quirk */
 202         #define OHCI_CTRL_HCFS          (3 << 6)
 203         #define OHCI_USB_OPER           (2 << 6)
 204         #define OHCI_USB_SUSPEND        (3 << 6)
 205
 206         #define OHCI_HCCTRL_OFFSET      0x4
 207         #define OHCI_HCCTRL_LEN         0x4
 208         __hc32                  *ohci_hcctrl_reg;
 209         unsigned                has_hostpc:1;
 210         unsigned                has_lpm:1;  /* support link power management */
 211         unsigned                has_ppcd:1; /* support per-port change bits */
 212         u8                      sbrn;           /* packed release number */
 213
 214         /* irq statistics */
 215 #ifdef EHCI_STATS
 216         struct ehci_stats       stats;
 217 #       define COUNT(x) do { (x)++; } while (0)
 218 #else
 219 #       define COUNT(x) do {} while (0)
 220 #endif
 221
 222         /* debug files */
 223 #ifdef DEBUG
 224         struct dentry           *debug_dir;
 225 #endif
 226 };
 227
 228 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 229 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 230 {
 231         return (struct ehci_hcd *) (hcd->hcd_priv);
 232 }
 233 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 234 {
 235         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 236 }
 237
 238 /*-------------------------------------------------------------------------*/
 239
 240 #include <linux/usb/ehci_def.h>
 241
 242 /*-------------------------------------------------------------------------*/
 243
 244 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 245
 246 /*
 247  * EHCI Specification 0.95 Section 3.5
 248  * QTD: describe data transfer components (buffer, direction, ...)
 249  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 250  *
 251  * These are associated only with "QH" (Queue Head) structures,
 252  * used with control, bulk, and interrupt transfers.
 253  */
 254 struct ehci_qtd {
 255         /* first part defined by EHCI spec */
 256         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 257         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 258         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 259 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 260 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 261 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 262 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 263 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 264 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 265 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 266 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 267 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 268 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 269 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 270 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 271 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 272
 273 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 274 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 275 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 276
 277         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 278         __hc32                  hw_buf_hi [5];        /* Appendix B */
 279
 280         /* the rest is HCD-private */
 281         dma_addr_t              qtd_dma;                /* qtd address */
 282         struct list_head        qtd_list;               /* sw qtd list */
 283         struct urb              *urb;                   /* qtd's urb */
 284         size_t                  length;                 /* length of buffer */
 285 } __attribute__ ((aligned (32)));
 286
 287 /* mask NakCnt+T in qh->hw_alt_next */
 288 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 289
 290 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 291
 292 /*-------------------------------------------------------------------------*/
 293
 294 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 295 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 296
 297 /*
 298  * Now the following defines are not converted using the
 299  * cpu_to_le32() macro anymore, since we have to support
 300  * "dynamic" switching between be and le support, so that the driver
 301  * can be used on one system with SoC EHCI controller using big-endian
 302  * descriptors as well as a normal little-endian PCI EHCI controller.
 303  */
 304 /* values for that type tag */
 305 #define Q_TYPE_ITD      (0 << 1)
 306 #define Q_TYPE_QH       (1 << 1)
 307 #define Q_TYPE_SITD     (2 << 1)
 308 #define Q_TYPE_FSTN     (3 << 1)
 309
 310 /* next async queue entry, or pointer to interrupt/periodic QH */
 311 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 312
 313 /* for periodic/async schedules and qtd lists, mark end of list */
 314 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 315
 316 /*
 317  * Entries in periodic shadow table are pointers to one of four kinds
 318  * of data structure.  That's dictated by the hardware; a type tag is
 319  * encoded in the low bits of the hardware's periodic schedule.  Use
 320  * Q_NEXT_TYPE to get the tag.
 321  *
 322  * For entries in the async schedule, the type tag always says "qh".
 323  */
 324 union ehci_shadow {
 325         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 326         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 327         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 328         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 329         __hc32                  *hw_next;       /* (all types) */
 330         void                    *ptr;
 331 };
 332
 333 /*-------------------------------------------------------------------------*/
 334
 335 /*
 336  * EHCI Specification 0.95 Section 3.6
 337  * QH: describes control/bulk/interrupt endpoints
 338  * See Fig 3-7 "Queue Head Structure Layout".
 339  *
 340  * These appear in both the async and (for interrupt) periodic schedules.
 341  */
 342
 343 /* first part defined by EHCI spec */
 344 struct ehci_qh_hw {
 345         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 346         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 347 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 348 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 349 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 350 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 351 #define QH_LOW_SPEED    (1 << 12)
 352 #define QH_FULL_SPEED   (0 << 12)
 353 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 354         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 355 #define QH_SMASK        0x000000ff
 356 #define QH_CMASK        0x0000ff00
 357 #define QH_HUBADDR      0x007f0000
 358 #define QH_HUBPORT      0x3f800000
 359 #define QH_MULT         0xc0000000
 360         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 361
 362         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 363         __hc32                  hw_qtd_next;
 364         __hc32                  hw_alt_next;
 365         __hc32                  hw_token;
 366         __hc32                  hw_buf [5];
 367         __hc32                  hw_buf_hi [5];
 368 } __attribute__ ((aligned(32)));
 369
 370 struct ehci_qh {
 371         struct ehci_qh_hw       *hw;            /* Must come first */
 372         /* the rest is HCD-private */
 373         dma_addr_t              qh_dma;         /* address of qh */
 374         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 375         struct list_head        qtd_list;       /* sw qtd list */
 376         struct list_head        intr_node;      /* list of intr QHs */
 377         struct ehci_qtd         *dummy;
 378         struct ehci_qh          *unlink_next;   /* next on unlink list */
 379
 380         unsigned                unlink_cycle;
 381
 382         u8                      needs_rescan;   /* Dequeue during giveback */
 383         u8                      qh_state;
 384 #define QH_STATE_LINKED         1               /* HC sees this */
 385 #define QH_STATE_UNLINK         2               /* HC may still see this */
 386 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 387 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 388 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 389
 390         u8                      xacterrs;       /* XactErr retry counter */
 391 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 392
 393         /* periodic schedule info */
 394         u8                      usecs;          /* intr bandwidth */
 395         u8                      gap_uf;         /* uframes split/csplit gap */
 396         u8                      c_usecs;        /* ... split completion bw */
 397         u16                     tt_usecs;       /* tt downstream bandwidth */
 398         unsigned short          period;         /* polling interval */
 399         unsigned short          start;          /* where polling starts */
 400 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 401
 402         struct usb_device       *dev;           /* access to TT */
 403         unsigned                is_out:1;       /* bulk or intr OUT */
 404         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 405 };
 406
 407 /*-------------------------------------------------------------------------*/
 408
 409 /* description of one iso transaction (up to 3 KB data if highspeed) */
 410 struct ehci_iso_packet {
 411         /* These will be copied to iTD when scheduling */
 412         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 413         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 414         u8                      cross;          /* buf crosses pages */
 415         /* for full speed OUT splits */
 416         u32                     buf1;
 417 };
 418
 419 /* temporary schedule data for packets from iso urbs (both speeds)
 420  * each packet is one logical usb transaction to the device (not TT),
 421  * beginning at stream->next_uframe
 422  */
 423 struct ehci_iso_sched {
 424         struct list_head        td_list;
 425         unsigned                span;
 426         struct ehci_iso_packet  packet [0];
 427 };
 428
 429 /*
 430  * ehci_iso_stream - groups all (s)itds for this endpoint.
 431  * acts like a qh would, if EHCI had them for ISO.
 432  */
 433 struct ehci_iso_stream {
 434         /* first field matches ehci_hq, but is NULL */
 435         struct ehci_qh_hw       *hw;
 436
 437         u8                      bEndpointAddress;
 438         u8                      highspeed;
 439         struct list_head        td_list;        /* queued itds/sitds */
 440         struct list_head        free_list;      /* list of unused itds/sitds */
 441         struct usb_device       *udev;
 442         struct usb_host_endpoint *ep;
 443
 444         /* output of (re)scheduling */
 445         int                     next_uframe;
 446         __hc32                  splits;
 447
 448         /* the rest is derived from the endpoint descriptor,
 449          * trusting urb->interval == f(epdesc->bInterval) and
 450          * including the extra info for hw_bufp[0..2]
 451          */
 452         u8                      usecs, c_usecs;
 453         u16                     interval;
 454         u16                     tt_usecs;
 455         u16                     maxp;
 456         u16                     raw_mask;
 457         unsigned                bandwidth;
 458
 459         /* This is used to initialize iTD's hw_bufp fields */
 460         __hc32                  buf0;
 461         __hc32                  buf1;
 462         __hc32                  buf2;
 463
 464         /* this is used to initialize sITD's tt info */
 465         __hc32                  address;
 466 };
 467
 468 /*-------------------------------------------------------------------------*/
 469
 470 /*
 471  * EHCI Specification 0.95 Section 3.3
 472  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 473  *
 474  * Schedule records for high speed iso xfers
 475  */
 476 struct ehci_itd {
 477         /* first part defined by EHCI spec */
 478         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 479         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 480 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 481 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 482 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 483 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 484 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 485 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 486
 487 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 488
 489         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 490         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 491
 492         /* the rest is HCD-private */
 493         dma_addr_t              itd_dma;        /* for this itd */
 494         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 495
 496         struct urb              *urb;
 497         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 498         struct list_head        itd_list;       /* list of stream's itds */
 499
 500         /* any/all hw_transactions here may be used by that urb */
 501         unsigned                frame;          /* where scheduled */
 502         unsigned                pg;
 503         unsigned                index[8];       /* in urb->iso_frame_desc */
 504 } __attribute__ ((aligned (32)));
 505
 506 /*-------------------------------------------------------------------------*/
 507
 508 /*
 509  * EHCI Specification 0.95 Section 3.4
 510  * siTD, aka split-transaction isochronous Transfer Descriptor
 511  *       ... describe full speed iso xfers through TT in hubs
 512  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 513  */
 514 struct ehci_sitd {
 515         /* first part defined by EHCI spec */
 516         __hc32                  hw_next;
 517 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 518         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 519         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 520         __hc32                  hw_results;             /* EHCI table 3-11 */
 521 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 522 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 523 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 524 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 525 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 526 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 527 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 528 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 529 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 530 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 531
 532 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 533
 534         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 535         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 536         __hc32                  hw_buf_hi [2];          /* Appendix B */
 537
 538         /* the rest is HCD-private */
 539         dma_addr_t              sitd_dma;
 540         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 541
 542         struct urb              *urb;
 543         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 544         struct list_head        sitd_list;      /* list of stream's sitds */
 545         unsigned                frame;
 546         unsigned                index;
 547 } __attribute__ ((aligned (32)));
 548
 549 /*-------------------------------------------------------------------------*/
 550
 551 /*
 552  * EHCI Specification 0.96 Section 3.7
 553  * Periodic Frame Span Traversal Node (FSTN)
 554  *
 555  * Manages split interrupt transactions (using TT) that span frame boundaries
 556  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 557  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 558  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 559  */
 560 struct ehci_fstn {
 561         __hc32                  hw_next;        /* any periodic q entry */
 562         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 563
 564         /* the rest is HCD-private */
 565         dma_addr_t              fstn_dma;
 566         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 567 } __attribute__ ((aligned (32)));
 568
 569 /*-------------------------------------------------------------------------*/
 570
 571 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 572
 573 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 574                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
 575
 576 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 577                 ehci_adjust_port_wakeup_flags(ehci, false, false);
 578
 579 /*-------------------------------------------------------------------------*/
 580
 581 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 582
 583 /*
 584  * Some EHCI controllers have a Transaction Translator built into the
 585  * root hub. This is a non-standard feature.  Each controller will need
 586  * to add code to the following inline functions, and call them as
 587  * needed (mostly in root hub code).
 588  */
 589
 590 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 591
 592 /* Returns the speed of a device attached to a port on the root hub. */
 593 static inline unsigned int
 594 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 595 {
 596         if (ehci_is_TDI(ehci)) {
 597                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 598                 case 0:
 599                         return 0;
 600                 case 1:
 601                         return USB_PORT_STAT_LOW_SPEED;
 602                 case 2:
 603                 default:
 604                         return USB_PORT_STAT_HIGH_SPEED;
 605                 }
 606         }
 607         return USB_PORT_STAT_HIGH_SPEED;
 608 }
 609
 610 #else
 611
 612 #define ehci_is_TDI(e)                  (0)
 613
 614 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 615 #endif
 616
 617 /*-------------------------------------------------------------------------*/
 618
 619 #ifdef CONFIG_PPC_83xx
 620 /* Some Freescale processors have an erratum in which the TT
 621  * port number in the queue head was 0..N-1 instead of 1..N.
 622  */
 623 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 624 #else
 625 #define ehci_has_fsl_portno_bug(e)              (0)
 626 #endif
 627
 628 /*
 629  * While most USB host controllers implement their registers in
 630  * little-endian format, a minority (celleb companion chip) implement
 631  * them in big endian format.
 632  *
 633  * This attempts to support either format at compile time without a
 634  * runtime penalty, or both formats with the additional overhead
 635  * of checking a flag bit.
 636  *
 637  * ehci_big_endian_capbase is a special quirk for controllers that
 638  * implement the HC capability registers as separate registers and not
 639  * as fields of a 32-bit register.
 640  */
 641
 642 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 643 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 644 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 645 #else
 646 #define ehci_big_endian_mmio(e)         0
 647 #define ehci_big_endian_capbase(e)      0
 648 #endif
 649
 650 /*
 651  * Big-endian read/write functions are arch-specific.
 652  * Other arches can be added if/when they're needed.
 653  */
 654 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 655 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 656 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 657 #endif
 658
 659 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 660                 __u32 __iomem * regs)
 661 {
 662 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 663         return ehci_big_endian_mmio(ehci) ?
 664                 readl_be(regs) :
 665                 readl(regs);
 666 #else
 667         return readl(regs);
 668 #endif
 669 }
 670
 671 static inline void ehci_writel(const struct ehci_hcd *ehci,
 672                 const unsigned int val, __u32 __iomem *regs)
 673 {
 674 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 675         ehci_big_endian_mmio(ehci) ?
 676                 writel_be(val, regs) :
 677                 writel(val, regs);
 678 #else
 679         writel(val, regs);
 680 #endif
 681 }
 682
 683 /*
 684  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 685  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 686  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 687  */
 688 #ifdef CONFIG_44x
 689 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 690 {
 691         u32 hc_control;
 692
 693         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 694         if (operational)
 695                 hc_control |= OHCI_USB_OPER;
 696         else
 697                 hc_control |= OHCI_USB_SUSPEND;
 698
 699         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 700         (void) readl_be(ehci->ohci_hcctrl_reg);
 701 }
 702 #else
 703 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 704 { }
 705 #endif
 706
 707 /*-------------------------------------------------------------------------*/
 708
 709 /*
 710  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 711  * format, but also its DMA data structures (descriptors).
 712  *
 713  * EHCI controllers accessed through PCI work normally (little-endian
 714  * everywhere), so we won't bother supporting a BE-only mode for now.
 715  */
 716 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 717 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 718
 719 /* cpu to ehci */
 720 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 721 {
 722         return ehci_big_endian_desc(ehci)
 723                 ? (__force __hc32)cpu_to_be32(x)
 724                 : (__force __hc32)cpu_to_le32(x);
 725 }
 726
 727 /* ehci to cpu */
 728 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 729 {
 730         return ehci_big_endian_desc(ehci)
 731                 ? be32_to_cpu((__force __be32)x)
 732                 : le32_to_cpu((__force __le32)x);
 733 }
 734
 735 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 736 {
 737         return ehci_big_endian_desc(ehci)
 738                 ? be32_to_cpup((__force __be32 *)x)
 739                 : le32_to_cpup((__force __le32 *)x);
 740 }
 741
 742 #else
 743
 744 /* cpu to ehci */
 745 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 746 {
 747         return cpu_to_le32(x);
 748 }
 749
 750 /* ehci to cpu */
 751 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 752 {
 753         return le32_to_cpu(x);
 754 }
 755
 756 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 757 {
 758         return le32_to_cpup(x);
 759 }
 760
 761 #endif
 762
 763 /*-------------------------------------------------------------------------*/
 764
 765 #ifdef CONFIG_PCI
 766
 767 /* For working around the MosChip frame-index-register bug */
 768 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
 769
 770 #else
 771
 772 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
 773 {
 774         return ehci_readl(ehci, &ehci->regs->frame_index);
 775 }
 776
 777 #endif
 778
 779 /*-------------------------------------------------------------------------*/
 780
 781 #ifndef DEBUG
 782 #define STUB_DEBUG_FILES
 783 #endif  /* DEBUG */
 784
 785 /*-------------------------------------------------------------------------*/
 786
 787 #endif /* __LINUX_EHCI_HCD_H */