include/linux/mtd/fsmc.h

   1 /*
   2  * incude/mtd/fsmc.h
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * platform data interface and header file
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #ifndef __MTD_FSMC_H
  17 #define __MTD_FSMC_H
  18
  19 #include <linux/io.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/types.h>
  23 #include <linux/mtd/partitions.h>
  24 #include <asm/param.h>
  25
  26 #define FSMC_NAND_BW8           1
  27 #define FSMC_NAND_BW16          2
  28
  29 #define FSMC_MAX_NOR_BANKS      4
  30 #define FSMC_MAX_NAND_BANKS     4
  31
  32 #define FSMC_FLASH_WIDTH8       1
  33 #define FSMC_FLASH_WIDTH16      2
  34
  35 /* fsmc controller registers for NOR flash */
  36 #define CTRL                    0x0
  37         /* ctrl register definitions */
  38         #define BANK_ENABLE             (1 << 0)
  39         #define MUXED                   (1 << 1)
  40         #define NOR_DEV                 (2 << 2)
  41         #define WIDTH_8                 (0 << 4)
  42         #define WIDTH_16                (1 << 4)
  43         #define RSTPWRDWN               (1 << 6)
  44         #define WPROT                   (1 << 7)
  45         #define WRT_ENABLE              (1 << 12)
  46         #define WAIT_ENB                (1 << 13)
  47
  48 #define CTRL_TIM                0x4
  49         /* ctrl_tim register definitions */
  50
  51 #define FSMC_NOR_BANK_SZ        0x8
  52 #define FSMC_NOR_REG_SIZE       0x40
  53
  54 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  55                                                 FSMC_NOR_BANK_SZ * (bank) + \
  56                                                 reg)
  57
  58 /* fsmc controller registers for NAND flash */
  59 #define PC                      0x00
  60         /* pc register definitions */
  61         #define FSMC_RESET              (1 << 0)
  62         #define FSMC_WAITON             (1 << 1)
  63         #define FSMC_ENABLE             (1 << 2)
  64         #define FSMC_DEVTYPE_NAND       (1 << 3)
  65         #define FSMC_DEVWID_8           (0 << 4)
  66         #define FSMC_DEVWID_16          (1 << 4)
  67         #define FSMC_ECCEN              (1 << 6)
  68         #define FSMC_ECCPLEN_512        (0 << 7)
  69         #define FSMC_ECCPLEN_256        (1 << 7)
  70         #define FSMC_TCLR_1             (1)
  71         #define FSMC_TCLR_SHIFT         (9)
  72         #define FSMC_TCLR_MASK          (0xF)
  73         #define FSMC_TAR_1              (1)
  74         #define FSMC_TAR_SHIFT          (13)
  75         #define FSMC_TAR_MASK           (0xF)
  76 #define STS                     0x04
  77         /* sts register definitions */
  78         #define FSMC_CODE_RDY           (1 << 15)
  79 #define COMM                    0x08
  80         /* comm register definitions */
  81         #define FSMC_TSET_0             0
  82         #define FSMC_TSET_SHIFT         0
  83         #define FSMC_TSET_MASK          0xFF
  84         #define FSMC_TWAIT_6            6
  85         #define FSMC_TWAIT_SHIFT        8
  86         #define FSMC_TWAIT_MASK         0xFF
  87         #define FSMC_THOLD_4            4
  88         #define FSMC_THOLD_SHIFT        16
  89         #define FSMC_THOLD_MASK         0xFF
  90         #define FSMC_THIZ_1             1
  91         #define FSMC_THIZ_SHIFT         24
  92         #define FSMC_THIZ_MASK          0xFF
  93 #define ATTRIB                  0x0C
  94 #define IOATA                   0x10
  95 #define ECC1                    0x14
  96 #define ECC2                    0x18
  97 #define ECC3                    0x1C
  98 #define FSMC_NAND_BANK_SZ       0x20
  99
 100 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 101                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 102                                                 reg)
 103
 104 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 105
 106 /*
 107  * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
 108  * and it has to be read consecutively and immediately after the 512
 109  * byte data block for hardware to generate the error bit offsets
 110  * Managing the ecc bytes in the following way is easier. This way is
 111  * similar to oobfree structure maintained already in u-boot nand driver
 112  */
 113 #define MAX_ECCPLACE_ENTRIES    32
 114
 115 struct fsmc_nand_eccplace {
 116         uint8_t offset;
 117         uint8_t length;
 118 };
 119
 120 struct fsmc_eccplace {
 121         struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
 122 };
 123
 124 struct fsmc_nand_timings {
 125         uint8_t tclr;
 126         uint8_t tar;
 127         uint8_t thiz;
 128         uint8_t thold;
 129         uint8_t twait;
 130         uint8_t tset;
 131 };
 132
 133 enum access_mode {
 134         USE_DMA_ACCESS = 1,
 135         USE_WORD_ACCESS,
 136 };
 137
 138 /**
 139  * fsmc_nand_platform_data - platform specific NAND controller config
 140  * @partitions: partition table for the platform, use a default fallback
 141  * if this is NULL
 142  * @nr_partitions: the number of partitions in the previous entry
 143  * @options: different options for the driver
 144  * @width: bus width
 145  * @bank: default bank
 146  * @select_bank: callback to select a certain bank, this is
 147  * platform-specific. If the controller only supports one bank
 148  * this may be set to NULL
 149  */
 150 struct fsmc_nand_platform_data {
 151         struct fsmc_nand_timings *nand_timings;
 152         struct mtd_partition    *partitions;
 153         unsigned int            nr_partitions;
 154         unsigned int            options;
 155         unsigned int            width;
 156         unsigned int            bank;
 157
 158         /* CLE, ALE offsets */
 159         unsigned int            cle_off;
 160         unsigned int            ale_off;
 161         enum access_mode        mode;
 162
 163         void                    (*select_bank)(uint32_t bank, uint32_t busw);
 164
 165         /* priv structures for dma accesses */
 166         void                    *read_dma_priv;
 167         void                    *write_dma_priv;
 168 };
 169
 170 extern int __init fsmc_nor_init(struct platform_device *pdev,
 171                 unsigned long base, uint32_t bank, uint32_t width);
 172 extern void __init fsmc_init_board_info(struct platform_device *pdev,
 173                 struct mtd_partition *partitions, unsigned int nr_partitions,
 174                 unsigned int width);
 175
 176 #endif /* __MTD_FSMC_H */